1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 13 #include "llvm/Target/TargetMachine.h" 14 #include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this. 15 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this. 16 17 namespace llvm { 18 19 class AMDGPUTargetMachine; 20 class FunctionPass; 21 class GCNTargetMachine; 22 class ModulePass; 23 class Pass; 24 class Target; 25 class TargetMachine; 26 class TargetOptions; 27 class PassRegistry; 28 class Module; 29 30 // GlobalISel passes 31 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &); 32 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone); 33 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &); 34 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone); 35 36 // R600 Passes 37 FunctionPass *createR600VectorRegMerger(); 38 FunctionPass *createR600ExpandSpecialInstrsPass(); 39 FunctionPass *createR600EmitClauseMarkers(); 40 FunctionPass *createR600ClauseMergePass(); 41 FunctionPass *createR600Packetizer(); 42 FunctionPass *createR600ControlFlowFinalizer(); 43 FunctionPass *createAMDGPUCFGStructurizerPass(); 44 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 45 46 // SI Passes 47 FunctionPass *createGCNDPPCombinePass(); 48 FunctionPass *createSIAnnotateControlFlowPass(); 49 FunctionPass *createSIFoldOperandsPass(); 50 FunctionPass *createSIPeepholeSDWAPass(); 51 FunctionPass *createSILowerI1CopiesPass(); 52 FunctionPass *createSIFixupVectorISelPass(); 53 FunctionPass *createSIAddIMGInitPass(); 54 FunctionPass *createSIShrinkInstructionsPass(); 55 FunctionPass *createSILoadStoreOptimizerPass(); 56 FunctionPass *createSIWholeQuadModePass(); 57 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 58 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 59 FunctionPass *createSIFixSGPRCopiesPass(); 60 FunctionPass *createSIMemoryLegalizerPass(); 61 FunctionPass *createSIInsertWaitcntsPass(); 62 FunctionPass *createSIPreAllocateWWMRegsPass(); 63 FunctionPass *createSIFormMemoryClausesPass(); 64 65 FunctionPass *createSIPostRABundlerPass(); 66 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *); 67 FunctionPass *createAMDGPUUseNativeCallsPass(); 68 FunctionPass *createAMDGPUCodeGenPreparePass(); 69 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 70 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *); 71 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *); 72 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 73 FunctionPass *createSIModeRegisterPass(); 74 75 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 76 77 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 78 extern char &AMDGPUMachineCFGStructurizerID; 79 80 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 81 82 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 83 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 84 extern char &AMDGPUAnnotateKernelFeaturesID; 85 86 FunctionPass *createAMDGPUAtomicOptimizerPass(); 87 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 88 extern char &AMDGPUAtomicOptimizerID; 89 90 ModulePass *createAMDGPULowerIntrinsicsPass(); 91 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 92 extern char &AMDGPULowerIntrinsicsID; 93 94 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 95 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 96 extern char &AMDGPUFixFunctionBitcastsID; 97 98 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 99 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 100 extern char &AMDGPULowerKernelArgumentsID; 101 102 ModulePass *createAMDGPULowerKernelAttributesPass(); 103 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 104 extern char &AMDGPULowerKernelAttributesID; 105 106 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &); 107 extern char &AMDGPUPropagateAttributesEarlyID; 108 109 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &); 110 extern char &AMDGPUPropagateAttributesLateID; 111 112 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 113 extern char &AMDGPURewriteOutArgumentsID; 114 115 void initializeGCNDPPCombinePass(PassRegistry &); 116 extern char &GCNDPPCombineID; 117 118 void initializeR600ClauseMergePassPass(PassRegistry &); 119 extern char &R600ClauseMergePassID; 120 121 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 122 extern char &R600ControlFlowFinalizerID; 123 124 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 125 extern char &R600ExpandSpecialInstrsPassID; 126 127 void initializeR600VectorRegMergerPass(PassRegistry &); 128 extern char &R600VectorRegMergerID; 129 130 void initializeR600PacketizerPass(PassRegistry &); 131 extern char &R600PacketizerID; 132 133 void initializeSIFoldOperandsPass(PassRegistry &); 134 extern char &SIFoldOperandsID; 135 136 void initializeSIPeepholeSDWAPass(PassRegistry &); 137 extern char &SIPeepholeSDWAID; 138 139 void initializeSIShrinkInstructionsPass(PassRegistry&); 140 extern char &SIShrinkInstructionsID; 141 142 void initializeSIFixSGPRCopiesPass(PassRegistry &); 143 extern char &SIFixSGPRCopiesID; 144 145 void initializeSIFixVGPRCopiesPass(PassRegistry &); 146 extern char &SIFixVGPRCopiesID; 147 148 void initializeSIFixupVectorISelPass(PassRegistry &); 149 extern char &SIFixupVectorISelID; 150 151 void initializeSILowerI1CopiesPass(PassRegistry &); 152 extern char &SILowerI1CopiesID; 153 154 void initializeSILowerSGPRSpillsPass(PassRegistry &); 155 extern char &SILowerSGPRSpillsID; 156 157 void initializeSILoadStoreOptimizerPass(PassRegistry &); 158 extern char &SILoadStoreOptimizerID; 159 160 void initializeSIWholeQuadModePass(PassRegistry &); 161 extern char &SIWholeQuadModeID; 162 163 void initializeSILowerControlFlowPass(PassRegistry &); 164 extern char &SILowerControlFlowID; 165 166 void initializeSIRemoveShortExecBranchesPass(PassRegistry &); 167 extern char &SIRemoveShortExecBranchesID; 168 169 void initializeSIPreEmitPeepholePass(PassRegistry &); 170 extern char &SIPreEmitPeepholeID; 171 172 void initializeSIInsertSkipsPass(PassRegistry &); 173 extern char &SIInsertSkipsPassID; 174 175 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 176 extern char &SIOptimizeExecMaskingID; 177 178 void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 179 extern char &SIPreAllocateWWMRegsID; 180 181 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 182 extern char &AMDGPUSimplifyLibCallsID; 183 184 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 185 extern char &AMDGPUUseNativeCallsID; 186 187 void initializeSIAddIMGInitPass(PassRegistry &); 188 extern char &SIAddIMGInitID; 189 190 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 191 extern char &AMDGPUPerfHintAnalysisID; 192 193 // Passes common to R600 and SI 194 FunctionPass *createAMDGPUPromoteAlloca(); 195 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 196 extern char &AMDGPUPromoteAllocaID; 197 198 Pass *createAMDGPUStructurizeCFGPass(); 199 FunctionPass *createAMDGPUISelDag( 200 TargetMachine *TM = nullptr, 201 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 202 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 203 ModulePass *createR600OpenCLImageTypeLoweringPass(); 204 FunctionPass *createAMDGPUAnnotateUniformValues(); 205 206 ModulePass *createAMDGPUPrintfRuntimeBinding(); 207 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&); 208 extern char &AMDGPUPrintfRuntimeBindingID; 209 210 ModulePass* createAMDGPUUnifyMetadataPass(); 211 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 212 extern char &AMDGPUUnifyMetadataID; 213 214 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 215 extern char &SIOptimizeExecMaskingPreRAID; 216 217 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 218 extern char &AMDGPUAnnotateUniformValuesPassID; 219 220 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 221 extern char &AMDGPUCodeGenPrepareID; 222 223 void initializeSIAnnotateControlFlowPass(PassRegistry&); 224 extern char &SIAnnotateControlFlowPassID; 225 226 void initializeSIMemoryLegalizerPass(PassRegistry&); 227 extern char &SIMemoryLegalizerID; 228 229 void initializeSIModeRegisterPass(PassRegistry&); 230 extern char &SIModeRegisterID; 231 232 void initializeSIInsertWaitcntsPass(PassRegistry&); 233 extern char &SIInsertWaitcntsID; 234 235 void initializeSIFormMemoryClausesPass(PassRegistry&); 236 extern char &SIFormMemoryClausesID; 237 238 void initializeSIPostRABundlerPass(PassRegistry&); 239 extern char &SIPostRABundlerID; 240 241 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 242 extern char &AMDGPUUnifyDivergentExitNodesID; 243 244 ImmutablePass *createAMDGPUAAWrapperPass(); 245 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 246 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 247 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 248 249 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 250 251 Pass *createAMDGPUFunctionInliningPass(); 252 void initializeAMDGPUInlinerPass(PassRegistry&); 253 254 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 255 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 256 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 257 258 void initializeGCNRegBankReassignPass(PassRegistry &); 259 extern char &GCNRegBankReassignID; 260 261 void initializeGCNNSAReassignPass(PassRegistry &); 262 extern char &GCNNSAReassignID; 263 264 namespace AMDGPU { 265 enum TargetIndex { 266 TI_CONSTDATA_START, 267 TI_SCRATCH_RSRC_DWORD0, 268 TI_SCRATCH_RSRC_DWORD1, 269 TI_SCRATCH_RSRC_DWORD2, 270 TI_SCRATCH_RSRC_DWORD3 271 }; 272 } 273 274 } // End namespace llvm 275 276 /// OpenCL uses address spaces to differentiate between 277 /// various memory regions on the hardware. On the CPU 278 /// all of the address spaces point to the same memory, 279 /// however on the GPU, each address space points to 280 /// a separate piece of memory that is unique from other 281 /// memory locations. 282 namespace AMDGPUAS { 283 enum : unsigned { 284 // The maximum value for flat, generic, local, private, constant and region. 285 MAX_AMDGPU_ADDRESS = 7, 286 287 FLAT_ADDRESS = 0, ///< Address space for flat memory. 288 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 289 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 290 291 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 292 LOCAL_ADDRESS = 3, ///< Address space for local memory. 293 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 294 295 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 296 297 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 298 299 /// Address space for direct addressible parameter memory (CONST0). 300 PARAM_D_ADDRESS = 6, 301 /// Address space for indirect addressible parameter memory (VTX1). 302 PARAM_I_ADDRESS = 7, 303 304 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 305 // this order to be able to dynamically index a constant buffer, for 306 // example: 307 // 308 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 309 310 CONSTANT_BUFFER_0 = 8, 311 CONSTANT_BUFFER_1 = 9, 312 CONSTANT_BUFFER_2 = 10, 313 CONSTANT_BUFFER_3 = 11, 314 CONSTANT_BUFFER_4 = 12, 315 CONSTANT_BUFFER_5 = 13, 316 CONSTANT_BUFFER_6 = 14, 317 CONSTANT_BUFFER_7 = 15, 318 CONSTANT_BUFFER_8 = 16, 319 CONSTANT_BUFFER_9 = 17, 320 CONSTANT_BUFFER_10 = 18, 321 CONSTANT_BUFFER_11 = 19, 322 CONSTANT_BUFFER_12 = 20, 323 CONSTANT_BUFFER_13 = 21, 324 CONSTANT_BUFFER_14 = 22, 325 CONSTANT_BUFFER_15 = 23, 326 327 // Some places use this if the address space can't be determined. 328 UNKNOWN_ADDRESS_SPACE = ~0u, 329 }; 330 } 331 332 #endif 333