1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AArch64 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64MCTargetDesc.h" 14 #include "AArch64ELFStreamer.h" 15 #include "AArch64MCAsmInfo.h" 16 #include "AArch64WinCOFFStreamer.h" 17 #include "MCTargetDesc/AArch64AddressingModes.h" 18 #include "MCTargetDesc/AArch64InstPrinter.h" 19 #include "TargetInfo/AArch64TargetInfo.h" 20 #include "llvm/DebugInfo/CodeView/CodeView.h" 21 #include "llvm/MC/MCAsmBackend.h" 22 #include "llvm/MC/MCCodeEmitter.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCObjectWriter.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCStreamer.h" 28 #include "llvm/MC/MCSubtargetInfo.h" 29 #include "llvm/MC/TargetRegistry.h" 30 #include "llvm/Support/Endian.h" 31 #include "llvm/Support/ErrorHandling.h" 32 33 using namespace llvm; 34 35 #define GET_INSTRINFO_MC_DESC 36 #define GET_INSTRINFO_MC_HELPERS 37 #include "AArch64GenInstrInfo.inc" 38 39 #define GET_SUBTARGETINFO_MC_DESC 40 #include "AArch64GenSubtargetInfo.inc" 41 42 #define GET_REGINFO_MC_DESC 43 #include "AArch64GenRegisterInfo.inc" 44 45 static MCInstrInfo *createAArch64MCInstrInfo() { 46 MCInstrInfo *X = new MCInstrInfo(); 47 InitAArch64MCInstrInfo(X); 48 return X; 49 } 50 51 static MCSubtargetInfo * 52 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 53 if (CPU.empty()) { 54 CPU = "generic"; 55 if (FS.empty()) 56 FS = "+v8a"; 57 58 if (TT.isArm64e()) 59 CPU = "apple-a12"; 60 } 61 62 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 63 } 64 65 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 66 // Mapping from CodeView to MC register id. 67 static const struct { 68 codeview::RegisterId CVReg; 69 MCPhysReg Reg; 70 } RegMap[] = { 71 {codeview::RegisterId::ARM64_W0, AArch64::W0}, 72 {codeview::RegisterId::ARM64_W1, AArch64::W1}, 73 {codeview::RegisterId::ARM64_W2, AArch64::W2}, 74 {codeview::RegisterId::ARM64_W3, AArch64::W3}, 75 {codeview::RegisterId::ARM64_W4, AArch64::W4}, 76 {codeview::RegisterId::ARM64_W5, AArch64::W5}, 77 {codeview::RegisterId::ARM64_W6, AArch64::W6}, 78 {codeview::RegisterId::ARM64_W7, AArch64::W7}, 79 {codeview::RegisterId::ARM64_W8, AArch64::W8}, 80 {codeview::RegisterId::ARM64_W9, AArch64::W9}, 81 {codeview::RegisterId::ARM64_W10, AArch64::W10}, 82 {codeview::RegisterId::ARM64_W11, AArch64::W11}, 83 {codeview::RegisterId::ARM64_W12, AArch64::W12}, 84 {codeview::RegisterId::ARM64_W13, AArch64::W13}, 85 {codeview::RegisterId::ARM64_W14, AArch64::W14}, 86 {codeview::RegisterId::ARM64_W15, AArch64::W15}, 87 {codeview::RegisterId::ARM64_W16, AArch64::W16}, 88 {codeview::RegisterId::ARM64_W17, AArch64::W17}, 89 {codeview::RegisterId::ARM64_W18, AArch64::W18}, 90 {codeview::RegisterId::ARM64_W19, AArch64::W19}, 91 {codeview::RegisterId::ARM64_W20, AArch64::W20}, 92 {codeview::RegisterId::ARM64_W21, AArch64::W21}, 93 {codeview::RegisterId::ARM64_W22, AArch64::W22}, 94 {codeview::RegisterId::ARM64_W23, AArch64::W23}, 95 {codeview::RegisterId::ARM64_W24, AArch64::W24}, 96 {codeview::RegisterId::ARM64_W25, AArch64::W25}, 97 {codeview::RegisterId::ARM64_W26, AArch64::W26}, 98 {codeview::RegisterId::ARM64_W27, AArch64::W27}, 99 {codeview::RegisterId::ARM64_W28, AArch64::W28}, 100 {codeview::RegisterId::ARM64_W29, AArch64::W29}, 101 {codeview::RegisterId::ARM64_W30, AArch64::W30}, 102 {codeview::RegisterId::ARM64_WZR, AArch64::WZR}, 103 {codeview::RegisterId::ARM64_X0, AArch64::X0}, 104 {codeview::RegisterId::ARM64_X1, AArch64::X1}, 105 {codeview::RegisterId::ARM64_X2, AArch64::X2}, 106 {codeview::RegisterId::ARM64_X3, AArch64::X3}, 107 {codeview::RegisterId::ARM64_X4, AArch64::X4}, 108 {codeview::RegisterId::ARM64_X5, AArch64::X5}, 109 {codeview::RegisterId::ARM64_X6, AArch64::X6}, 110 {codeview::RegisterId::ARM64_X7, AArch64::X7}, 111 {codeview::RegisterId::ARM64_X8, AArch64::X8}, 112 {codeview::RegisterId::ARM64_X9, AArch64::X9}, 113 {codeview::RegisterId::ARM64_X10, AArch64::X10}, 114 {codeview::RegisterId::ARM64_X11, AArch64::X11}, 115 {codeview::RegisterId::ARM64_X12, AArch64::X12}, 116 {codeview::RegisterId::ARM64_X13, AArch64::X13}, 117 {codeview::RegisterId::ARM64_X14, AArch64::X14}, 118 {codeview::RegisterId::ARM64_X15, AArch64::X15}, 119 {codeview::RegisterId::ARM64_X16, AArch64::X16}, 120 {codeview::RegisterId::ARM64_X17, AArch64::X17}, 121 {codeview::RegisterId::ARM64_X18, AArch64::X18}, 122 {codeview::RegisterId::ARM64_X19, AArch64::X19}, 123 {codeview::RegisterId::ARM64_X20, AArch64::X20}, 124 {codeview::RegisterId::ARM64_X21, AArch64::X21}, 125 {codeview::RegisterId::ARM64_X22, AArch64::X22}, 126 {codeview::RegisterId::ARM64_X23, AArch64::X23}, 127 {codeview::RegisterId::ARM64_X24, AArch64::X24}, 128 {codeview::RegisterId::ARM64_X25, AArch64::X25}, 129 {codeview::RegisterId::ARM64_X26, AArch64::X26}, 130 {codeview::RegisterId::ARM64_X27, AArch64::X27}, 131 {codeview::RegisterId::ARM64_X28, AArch64::X28}, 132 {codeview::RegisterId::ARM64_FP, AArch64::FP}, 133 {codeview::RegisterId::ARM64_LR, AArch64::LR}, 134 {codeview::RegisterId::ARM64_SP, AArch64::SP}, 135 {codeview::RegisterId::ARM64_ZR, AArch64::XZR}, 136 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV}, 137 {codeview::RegisterId::ARM64_S0, AArch64::S0}, 138 {codeview::RegisterId::ARM64_S1, AArch64::S1}, 139 {codeview::RegisterId::ARM64_S2, AArch64::S2}, 140 {codeview::RegisterId::ARM64_S3, AArch64::S3}, 141 {codeview::RegisterId::ARM64_S4, AArch64::S4}, 142 {codeview::RegisterId::ARM64_S5, AArch64::S5}, 143 {codeview::RegisterId::ARM64_S6, AArch64::S6}, 144 {codeview::RegisterId::ARM64_S7, AArch64::S7}, 145 {codeview::RegisterId::ARM64_S8, AArch64::S8}, 146 {codeview::RegisterId::ARM64_S9, AArch64::S9}, 147 {codeview::RegisterId::ARM64_S10, AArch64::S10}, 148 {codeview::RegisterId::ARM64_S11, AArch64::S11}, 149 {codeview::RegisterId::ARM64_S12, AArch64::S12}, 150 {codeview::RegisterId::ARM64_S13, AArch64::S13}, 151 {codeview::RegisterId::ARM64_S14, AArch64::S14}, 152 {codeview::RegisterId::ARM64_S15, AArch64::S15}, 153 {codeview::RegisterId::ARM64_S16, AArch64::S16}, 154 {codeview::RegisterId::ARM64_S17, AArch64::S17}, 155 {codeview::RegisterId::ARM64_S18, AArch64::S18}, 156 {codeview::RegisterId::ARM64_S19, AArch64::S19}, 157 {codeview::RegisterId::ARM64_S20, AArch64::S20}, 158 {codeview::RegisterId::ARM64_S21, AArch64::S21}, 159 {codeview::RegisterId::ARM64_S22, AArch64::S22}, 160 {codeview::RegisterId::ARM64_S23, AArch64::S23}, 161 {codeview::RegisterId::ARM64_S24, AArch64::S24}, 162 {codeview::RegisterId::ARM64_S25, AArch64::S25}, 163 {codeview::RegisterId::ARM64_S26, AArch64::S26}, 164 {codeview::RegisterId::ARM64_S27, AArch64::S27}, 165 {codeview::RegisterId::ARM64_S28, AArch64::S28}, 166 {codeview::RegisterId::ARM64_S29, AArch64::S29}, 167 {codeview::RegisterId::ARM64_S30, AArch64::S30}, 168 {codeview::RegisterId::ARM64_S31, AArch64::S31}, 169 {codeview::RegisterId::ARM64_D0, AArch64::D0}, 170 {codeview::RegisterId::ARM64_D1, AArch64::D1}, 171 {codeview::RegisterId::ARM64_D2, AArch64::D2}, 172 {codeview::RegisterId::ARM64_D3, AArch64::D3}, 173 {codeview::RegisterId::ARM64_D4, AArch64::D4}, 174 {codeview::RegisterId::ARM64_D5, AArch64::D5}, 175 {codeview::RegisterId::ARM64_D6, AArch64::D6}, 176 {codeview::RegisterId::ARM64_D7, AArch64::D7}, 177 {codeview::RegisterId::ARM64_D8, AArch64::D8}, 178 {codeview::RegisterId::ARM64_D9, AArch64::D9}, 179 {codeview::RegisterId::ARM64_D10, AArch64::D10}, 180 {codeview::RegisterId::ARM64_D11, AArch64::D11}, 181 {codeview::RegisterId::ARM64_D12, AArch64::D12}, 182 {codeview::RegisterId::ARM64_D13, AArch64::D13}, 183 {codeview::RegisterId::ARM64_D14, AArch64::D14}, 184 {codeview::RegisterId::ARM64_D15, AArch64::D15}, 185 {codeview::RegisterId::ARM64_D16, AArch64::D16}, 186 {codeview::RegisterId::ARM64_D17, AArch64::D17}, 187 {codeview::RegisterId::ARM64_D18, AArch64::D18}, 188 {codeview::RegisterId::ARM64_D19, AArch64::D19}, 189 {codeview::RegisterId::ARM64_D20, AArch64::D20}, 190 {codeview::RegisterId::ARM64_D21, AArch64::D21}, 191 {codeview::RegisterId::ARM64_D22, AArch64::D22}, 192 {codeview::RegisterId::ARM64_D23, AArch64::D23}, 193 {codeview::RegisterId::ARM64_D24, AArch64::D24}, 194 {codeview::RegisterId::ARM64_D25, AArch64::D25}, 195 {codeview::RegisterId::ARM64_D26, AArch64::D26}, 196 {codeview::RegisterId::ARM64_D27, AArch64::D27}, 197 {codeview::RegisterId::ARM64_D28, AArch64::D28}, 198 {codeview::RegisterId::ARM64_D29, AArch64::D29}, 199 {codeview::RegisterId::ARM64_D30, AArch64::D30}, 200 {codeview::RegisterId::ARM64_D31, AArch64::D31}, 201 {codeview::RegisterId::ARM64_Q0, AArch64::Q0}, 202 {codeview::RegisterId::ARM64_Q1, AArch64::Q1}, 203 {codeview::RegisterId::ARM64_Q2, AArch64::Q2}, 204 {codeview::RegisterId::ARM64_Q3, AArch64::Q3}, 205 {codeview::RegisterId::ARM64_Q4, AArch64::Q4}, 206 {codeview::RegisterId::ARM64_Q5, AArch64::Q5}, 207 {codeview::RegisterId::ARM64_Q6, AArch64::Q6}, 208 {codeview::RegisterId::ARM64_Q7, AArch64::Q7}, 209 {codeview::RegisterId::ARM64_Q8, AArch64::Q8}, 210 {codeview::RegisterId::ARM64_Q9, AArch64::Q9}, 211 {codeview::RegisterId::ARM64_Q10, AArch64::Q10}, 212 {codeview::RegisterId::ARM64_Q11, AArch64::Q11}, 213 {codeview::RegisterId::ARM64_Q12, AArch64::Q12}, 214 {codeview::RegisterId::ARM64_Q13, AArch64::Q13}, 215 {codeview::RegisterId::ARM64_Q14, AArch64::Q14}, 216 {codeview::RegisterId::ARM64_Q15, AArch64::Q15}, 217 {codeview::RegisterId::ARM64_Q16, AArch64::Q16}, 218 {codeview::RegisterId::ARM64_Q17, AArch64::Q17}, 219 {codeview::RegisterId::ARM64_Q18, AArch64::Q18}, 220 {codeview::RegisterId::ARM64_Q19, AArch64::Q19}, 221 {codeview::RegisterId::ARM64_Q20, AArch64::Q20}, 222 {codeview::RegisterId::ARM64_Q21, AArch64::Q21}, 223 {codeview::RegisterId::ARM64_Q22, AArch64::Q22}, 224 {codeview::RegisterId::ARM64_Q23, AArch64::Q23}, 225 {codeview::RegisterId::ARM64_Q24, AArch64::Q24}, 226 {codeview::RegisterId::ARM64_Q25, AArch64::Q25}, 227 {codeview::RegisterId::ARM64_Q26, AArch64::Q26}, 228 {codeview::RegisterId::ARM64_Q27, AArch64::Q27}, 229 {codeview::RegisterId::ARM64_Q28, AArch64::Q28}, 230 {codeview::RegisterId::ARM64_Q29, AArch64::Q29}, 231 {codeview::RegisterId::ARM64_Q30, AArch64::Q30}, 232 {codeview::RegisterId::ARM64_Q31, AArch64::Q31}, 233 234 }; 235 for (const auto &I : RegMap) 236 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 237 } 238 239 bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) { 240 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; 241 return llvm::any_of(MI, [&](const MCOperand &Op) { 242 return Op.isReg() && FPR128.contains(Op.getReg()); 243 }); 244 } 245 246 bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) { 247 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; 248 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID]; 249 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID]; 250 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID]; 251 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID]; 252 253 auto IsFPR = [&](const MCOperand &Op) { 254 if (!Op.isReg()) 255 return false; 256 auto Reg = Op.getReg(); 257 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || 258 FPR16.contains(Reg) || FPR8.contains(Reg); 259 }; 260 261 return llvm::any_of(MI, IsFPR); 262 } 263 264 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) { 265 MCRegisterInfo *X = new MCRegisterInfo(); 266 InitAArch64MCRegisterInfo(X, AArch64::LR); 267 AArch64_MC::initLLVMToCVRegMapping(X); 268 return X; 269 } 270 271 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, 272 const Triple &TheTriple, 273 const MCTargetOptions &Options) { 274 MCAsmInfo *MAI; 275 if (TheTriple.isOSBinFormatMachO()) 276 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32); 277 else if (TheTriple.isWindowsMSVCEnvironment()) 278 MAI = new AArch64MCAsmInfoMicrosoftCOFF(); 279 else if (TheTriple.isOSBinFormatCOFF()) 280 MAI = new AArch64MCAsmInfoGNUCOFF(); 281 else { 282 assert(TheTriple.isOSBinFormatELF() && "Invalid target"); 283 MAI = new AArch64MCAsmInfoELF(TheTriple); 284 } 285 286 // Initial state of the frame pointer is SP. 287 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); 288 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); 289 MAI->addInitialFrameState(Inst); 290 291 return MAI; 292 } 293 294 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, 295 unsigned SyntaxVariant, 296 const MCAsmInfo &MAI, 297 const MCInstrInfo &MII, 298 const MCRegisterInfo &MRI) { 299 if (SyntaxVariant == 0) 300 return new AArch64InstPrinter(MAI, MII, MRI); 301 if (SyntaxVariant == 1) 302 return new AArch64AppleInstPrinter(MAI, MII, MRI); 303 304 return nullptr; 305 } 306 307 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 308 std::unique_ptr<MCAsmBackend> &&TAB, 309 std::unique_ptr<MCObjectWriter> &&OW, 310 std::unique_ptr<MCCodeEmitter> &&Emitter, 311 bool RelaxAll) { 312 return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW), 313 std::move(Emitter), RelaxAll); 314 } 315 316 static MCStreamer *createMachOStreamer(MCContext &Ctx, 317 std::unique_ptr<MCAsmBackend> &&TAB, 318 std::unique_ptr<MCObjectWriter> &&OW, 319 std::unique_ptr<MCCodeEmitter> &&Emitter, 320 bool RelaxAll, 321 bool DWARFMustBeAtTheEnd) { 322 return createMachOStreamer(Ctx, std::move(TAB), std::move(OW), 323 std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd, 324 /*LabelSections*/ true); 325 } 326 327 static MCStreamer * 328 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB, 329 std::unique_ptr<MCObjectWriter> &&OW, 330 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll, 331 bool IncrementalLinkerCompatible) { 332 return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW), 333 std::move(Emitter), RelaxAll, 334 IncrementalLinkerCompatible); 335 } 336 337 namespace { 338 339 class AArch64MCInstrAnalysis : public MCInstrAnalysis { 340 public: 341 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 342 343 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 344 uint64_t &Target) const override { 345 // Search for a PC-relative argument. 346 // This will handle instructions like bcc (where the first argument is the 347 // condition code) and cbz (where it is a register). 348 const auto &Desc = Info->get(Inst.getOpcode()); 349 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) { 350 if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) { 351 int64_t Imm = Inst.getOperand(i).getImm() * 4; 352 Target = Addr + Imm; 353 return true; 354 } 355 } 356 return false; 357 } 358 359 std::vector<std::pair<uint64_t, uint64_t>> 360 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 361 uint64_t GotPltSectionVA, 362 const Triple &TargetTriple) const override { 363 // Do a lightweight parsing of PLT entries. 364 std::vector<std::pair<uint64_t, uint64_t>> Result; 365 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End; 366 Byte += 4) { 367 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); 368 uint64_t Off = 0; 369 // Check for optional bti c that prefixes adrp in BTI enabled entries 370 if (Insn == 0xd503245f) { 371 Off = 4; 372 Insn = support::endian::read32le(PltContents.data() + Byte + Off); 373 } 374 // Check for adrp. 375 if ((Insn & 0x9f000000) != 0x90000000) 376 continue; 377 Off += 4; 378 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) + 379 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14); 380 uint32_t Insn2 = 381 support::endian::read32le(PltContents.data() + Byte + Off); 382 // Check for: ldr Xt, [Xn, #pimm]. 383 if (Insn2 >> 22 == 0x3e5) { 384 Imm += ((Insn2 >> 10) & 0xfff) << 3; 385 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 386 Byte += 4; 387 } 388 } 389 return Result; 390 } 391 }; 392 393 } // end anonymous namespace 394 395 static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) { 396 return new AArch64MCInstrAnalysis(Info); 397 } 398 399 // Force static initialization. 400 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC() { 401 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(), 402 &getTheAArch64_32Target(), &getTheARM64Target(), 403 &getTheARM64_32Target()}) { 404 // Register the MC asm info. 405 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); 406 407 // Register the MC instruction info. 408 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); 409 410 // Register the MC register info. 411 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo); 412 413 // Register the MC subtarget info. 414 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo); 415 416 // Register the MC instruction analyzer. 417 TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis); 418 419 // Register the MC Code Emitter 420 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter); 421 422 // Register the obj streamers. 423 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 424 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer); 425 TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer); 426 427 // Register the obj target streamer. 428 TargetRegistry::RegisterObjectTargetStreamer( 429 *T, createAArch64ObjectTargetStreamer); 430 431 // Register the asm streamer. 432 TargetRegistry::RegisterAsmTargetStreamer(*T, 433 createAArch64AsmTargetStreamer); 434 // Register the MCInstPrinter. 435 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter); 436 } 437 438 // Register the asm backend. 439 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(), 440 &getTheARM64Target(), &getTheARM64_32Target()}) 441 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); 442 TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(), 443 createAArch64beAsmBackend); 444 } 445