1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AArch64 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64MCTargetDesc.h" 14 #include "AArch64ELFStreamer.h" 15 #include "AArch64MCAsmInfo.h" 16 #include "AArch64WinCOFFStreamer.h" 17 #include "MCTargetDesc/AArch64AddressingModes.h" 18 #include "MCTargetDesc/AArch64InstPrinter.h" 19 #include "TargetInfo/AArch64TargetInfo.h" 20 #include "llvm/DebugInfo/CodeView/CodeView.h" 21 #include "llvm/MC/MCAsmBackend.h" 22 #include "llvm/MC/MCCodeEmitter.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCObjectWriter.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCStreamer.h" 28 #include "llvm/MC/MCSubtargetInfo.h" 29 #include "llvm/MC/TargetRegistry.h" 30 #include "llvm/Support/Endian.h" 31 #include "llvm/Support/ErrorHandling.h" 32 33 using namespace llvm; 34 35 #define GET_INSTRINFO_MC_DESC 36 #define GET_INSTRINFO_MC_HELPERS 37 #include "AArch64GenInstrInfo.inc" 38 39 #define GET_SUBTARGETINFO_MC_DESC 40 #include "AArch64GenSubtargetInfo.inc" 41 42 #define GET_REGINFO_MC_DESC 43 #include "AArch64GenRegisterInfo.inc" 44 45 static MCInstrInfo *createAArch64MCInstrInfo() { 46 MCInstrInfo *X = new MCInstrInfo(); 47 InitAArch64MCInstrInfo(X); 48 return X; 49 } 50 51 static MCSubtargetInfo * 52 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 53 if (CPU.empty()) { 54 CPU = "generic"; 55 56 if (TT.isArm64e()) 57 CPU = "apple-a12"; 58 } 59 60 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 61 } 62 63 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 64 // Mapping from CodeView to MC register id. 65 static const struct { 66 codeview::RegisterId CVReg; 67 MCPhysReg Reg; 68 } RegMap[] = { 69 {codeview::RegisterId::ARM64_W0, AArch64::W0}, 70 {codeview::RegisterId::ARM64_W1, AArch64::W1}, 71 {codeview::RegisterId::ARM64_W2, AArch64::W2}, 72 {codeview::RegisterId::ARM64_W3, AArch64::W3}, 73 {codeview::RegisterId::ARM64_W4, AArch64::W4}, 74 {codeview::RegisterId::ARM64_W5, AArch64::W5}, 75 {codeview::RegisterId::ARM64_W6, AArch64::W6}, 76 {codeview::RegisterId::ARM64_W7, AArch64::W7}, 77 {codeview::RegisterId::ARM64_W8, AArch64::W8}, 78 {codeview::RegisterId::ARM64_W9, AArch64::W9}, 79 {codeview::RegisterId::ARM64_W10, AArch64::W10}, 80 {codeview::RegisterId::ARM64_W11, AArch64::W11}, 81 {codeview::RegisterId::ARM64_W12, AArch64::W12}, 82 {codeview::RegisterId::ARM64_W13, AArch64::W13}, 83 {codeview::RegisterId::ARM64_W14, AArch64::W14}, 84 {codeview::RegisterId::ARM64_W15, AArch64::W15}, 85 {codeview::RegisterId::ARM64_W16, AArch64::W16}, 86 {codeview::RegisterId::ARM64_W17, AArch64::W17}, 87 {codeview::RegisterId::ARM64_W18, AArch64::W18}, 88 {codeview::RegisterId::ARM64_W19, AArch64::W19}, 89 {codeview::RegisterId::ARM64_W20, AArch64::W20}, 90 {codeview::RegisterId::ARM64_W21, AArch64::W21}, 91 {codeview::RegisterId::ARM64_W22, AArch64::W22}, 92 {codeview::RegisterId::ARM64_W23, AArch64::W23}, 93 {codeview::RegisterId::ARM64_W24, AArch64::W24}, 94 {codeview::RegisterId::ARM64_W25, AArch64::W25}, 95 {codeview::RegisterId::ARM64_W26, AArch64::W26}, 96 {codeview::RegisterId::ARM64_W27, AArch64::W27}, 97 {codeview::RegisterId::ARM64_W28, AArch64::W28}, 98 {codeview::RegisterId::ARM64_W29, AArch64::W29}, 99 {codeview::RegisterId::ARM64_W30, AArch64::W30}, 100 {codeview::RegisterId::ARM64_WZR, AArch64::WZR}, 101 {codeview::RegisterId::ARM64_X0, AArch64::X0}, 102 {codeview::RegisterId::ARM64_X1, AArch64::X1}, 103 {codeview::RegisterId::ARM64_X2, AArch64::X2}, 104 {codeview::RegisterId::ARM64_X3, AArch64::X3}, 105 {codeview::RegisterId::ARM64_X4, AArch64::X4}, 106 {codeview::RegisterId::ARM64_X5, AArch64::X5}, 107 {codeview::RegisterId::ARM64_X6, AArch64::X6}, 108 {codeview::RegisterId::ARM64_X7, AArch64::X7}, 109 {codeview::RegisterId::ARM64_X8, AArch64::X8}, 110 {codeview::RegisterId::ARM64_X9, AArch64::X9}, 111 {codeview::RegisterId::ARM64_X10, AArch64::X10}, 112 {codeview::RegisterId::ARM64_X11, AArch64::X11}, 113 {codeview::RegisterId::ARM64_X12, AArch64::X12}, 114 {codeview::RegisterId::ARM64_X13, AArch64::X13}, 115 {codeview::RegisterId::ARM64_X14, AArch64::X14}, 116 {codeview::RegisterId::ARM64_X15, AArch64::X15}, 117 {codeview::RegisterId::ARM64_X16, AArch64::X16}, 118 {codeview::RegisterId::ARM64_X17, AArch64::X17}, 119 {codeview::RegisterId::ARM64_X18, AArch64::X18}, 120 {codeview::RegisterId::ARM64_X19, AArch64::X19}, 121 {codeview::RegisterId::ARM64_X20, AArch64::X20}, 122 {codeview::RegisterId::ARM64_X21, AArch64::X21}, 123 {codeview::RegisterId::ARM64_X22, AArch64::X22}, 124 {codeview::RegisterId::ARM64_X23, AArch64::X23}, 125 {codeview::RegisterId::ARM64_X24, AArch64::X24}, 126 {codeview::RegisterId::ARM64_X25, AArch64::X25}, 127 {codeview::RegisterId::ARM64_X26, AArch64::X26}, 128 {codeview::RegisterId::ARM64_X27, AArch64::X27}, 129 {codeview::RegisterId::ARM64_X28, AArch64::X28}, 130 {codeview::RegisterId::ARM64_FP, AArch64::FP}, 131 {codeview::RegisterId::ARM64_LR, AArch64::LR}, 132 {codeview::RegisterId::ARM64_SP, AArch64::SP}, 133 {codeview::RegisterId::ARM64_ZR, AArch64::XZR}, 134 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV}, 135 {codeview::RegisterId::ARM64_S0, AArch64::S0}, 136 {codeview::RegisterId::ARM64_S1, AArch64::S1}, 137 {codeview::RegisterId::ARM64_S2, AArch64::S2}, 138 {codeview::RegisterId::ARM64_S3, AArch64::S3}, 139 {codeview::RegisterId::ARM64_S4, AArch64::S4}, 140 {codeview::RegisterId::ARM64_S5, AArch64::S5}, 141 {codeview::RegisterId::ARM64_S6, AArch64::S6}, 142 {codeview::RegisterId::ARM64_S7, AArch64::S7}, 143 {codeview::RegisterId::ARM64_S8, AArch64::S8}, 144 {codeview::RegisterId::ARM64_S9, AArch64::S9}, 145 {codeview::RegisterId::ARM64_S10, AArch64::S10}, 146 {codeview::RegisterId::ARM64_S11, AArch64::S11}, 147 {codeview::RegisterId::ARM64_S12, AArch64::S12}, 148 {codeview::RegisterId::ARM64_S13, AArch64::S13}, 149 {codeview::RegisterId::ARM64_S14, AArch64::S14}, 150 {codeview::RegisterId::ARM64_S15, AArch64::S15}, 151 {codeview::RegisterId::ARM64_S16, AArch64::S16}, 152 {codeview::RegisterId::ARM64_S17, AArch64::S17}, 153 {codeview::RegisterId::ARM64_S18, AArch64::S18}, 154 {codeview::RegisterId::ARM64_S19, AArch64::S19}, 155 {codeview::RegisterId::ARM64_S20, AArch64::S20}, 156 {codeview::RegisterId::ARM64_S21, AArch64::S21}, 157 {codeview::RegisterId::ARM64_S22, AArch64::S22}, 158 {codeview::RegisterId::ARM64_S23, AArch64::S23}, 159 {codeview::RegisterId::ARM64_S24, AArch64::S24}, 160 {codeview::RegisterId::ARM64_S25, AArch64::S25}, 161 {codeview::RegisterId::ARM64_S26, AArch64::S26}, 162 {codeview::RegisterId::ARM64_S27, AArch64::S27}, 163 {codeview::RegisterId::ARM64_S28, AArch64::S28}, 164 {codeview::RegisterId::ARM64_S29, AArch64::S29}, 165 {codeview::RegisterId::ARM64_S30, AArch64::S30}, 166 {codeview::RegisterId::ARM64_S31, AArch64::S31}, 167 {codeview::RegisterId::ARM64_D0, AArch64::D0}, 168 {codeview::RegisterId::ARM64_D1, AArch64::D1}, 169 {codeview::RegisterId::ARM64_D2, AArch64::D2}, 170 {codeview::RegisterId::ARM64_D3, AArch64::D3}, 171 {codeview::RegisterId::ARM64_D4, AArch64::D4}, 172 {codeview::RegisterId::ARM64_D5, AArch64::D5}, 173 {codeview::RegisterId::ARM64_D6, AArch64::D6}, 174 {codeview::RegisterId::ARM64_D7, AArch64::D7}, 175 {codeview::RegisterId::ARM64_D8, AArch64::D8}, 176 {codeview::RegisterId::ARM64_D9, AArch64::D9}, 177 {codeview::RegisterId::ARM64_D10, AArch64::D10}, 178 {codeview::RegisterId::ARM64_D11, AArch64::D11}, 179 {codeview::RegisterId::ARM64_D12, AArch64::D12}, 180 {codeview::RegisterId::ARM64_D13, AArch64::D13}, 181 {codeview::RegisterId::ARM64_D14, AArch64::D14}, 182 {codeview::RegisterId::ARM64_D15, AArch64::D15}, 183 {codeview::RegisterId::ARM64_D16, AArch64::D16}, 184 {codeview::RegisterId::ARM64_D17, AArch64::D17}, 185 {codeview::RegisterId::ARM64_D18, AArch64::D18}, 186 {codeview::RegisterId::ARM64_D19, AArch64::D19}, 187 {codeview::RegisterId::ARM64_D20, AArch64::D20}, 188 {codeview::RegisterId::ARM64_D21, AArch64::D21}, 189 {codeview::RegisterId::ARM64_D22, AArch64::D22}, 190 {codeview::RegisterId::ARM64_D23, AArch64::D23}, 191 {codeview::RegisterId::ARM64_D24, AArch64::D24}, 192 {codeview::RegisterId::ARM64_D25, AArch64::D25}, 193 {codeview::RegisterId::ARM64_D26, AArch64::D26}, 194 {codeview::RegisterId::ARM64_D27, AArch64::D27}, 195 {codeview::RegisterId::ARM64_D28, AArch64::D28}, 196 {codeview::RegisterId::ARM64_D29, AArch64::D29}, 197 {codeview::RegisterId::ARM64_D30, AArch64::D30}, 198 {codeview::RegisterId::ARM64_D31, AArch64::D31}, 199 {codeview::RegisterId::ARM64_Q0, AArch64::Q0}, 200 {codeview::RegisterId::ARM64_Q1, AArch64::Q1}, 201 {codeview::RegisterId::ARM64_Q2, AArch64::Q2}, 202 {codeview::RegisterId::ARM64_Q3, AArch64::Q3}, 203 {codeview::RegisterId::ARM64_Q4, AArch64::Q4}, 204 {codeview::RegisterId::ARM64_Q5, AArch64::Q5}, 205 {codeview::RegisterId::ARM64_Q6, AArch64::Q6}, 206 {codeview::RegisterId::ARM64_Q7, AArch64::Q7}, 207 {codeview::RegisterId::ARM64_Q8, AArch64::Q8}, 208 {codeview::RegisterId::ARM64_Q9, AArch64::Q9}, 209 {codeview::RegisterId::ARM64_Q10, AArch64::Q10}, 210 {codeview::RegisterId::ARM64_Q11, AArch64::Q11}, 211 {codeview::RegisterId::ARM64_Q12, AArch64::Q12}, 212 {codeview::RegisterId::ARM64_Q13, AArch64::Q13}, 213 {codeview::RegisterId::ARM64_Q14, AArch64::Q14}, 214 {codeview::RegisterId::ARM64_Q15, AArch64::Q15}, 215 {codeview::RegisterId::ARM64_Q16, AArch64::Q16}, 216 {codeview::RegisterId::ARM64_Q17, AArch64::Q17}, 217 {codeview::RegisterId::ARM64_Q18, AArch64::Q18}, 218 {codeview::RegisterId::ARM64_Q19, AArch64::Q19}, 219 {codeview::RegisterId::ARM64_Q20, AArch64::Q20}, 220 {codeview::RegisterId::ARM64_Q21, AArch64::Q21}, 221 {codeview::RegisterId::ARM64_Q22, AArch64::Q22}, 222 {codeview::RegisterId::ARM64_Q23, AArch64::Q23}, 223 {codeview::RegisterId::ARM64_Q24, AArch64::Q24}, 224 {codeview::RegisterId::ARM64_Q25, AArch64::Q25}, 225 {codeview::RegisterId::ARM64_Q26, AArch64::Q26}, 226 {codeview::RegisterId::ARM64_Q27, AArch64::Q27}, 227 {codeview::RegisterId::ARM64_Q28, AArch64::Q28}, 228 {codeview::RegisterId::ARM64_Q29, AArch64::Q29}, 229 {codeview::RegisterId::ARM64_Q30, AArch64::Q30}, 230 {codeview::RegisterId::ARM64_Q31, AArch64::Q31}, 231 232 }; 233 for (const auto &I : RegMap) 234 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 235 } 236 237 bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) { 238 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; 239 return llvm::any_of(MI, [&](const MCOperand &Op) { 240 return Op.isReg() && FPR128.contains(Op.getReg()); 241 }); 242 } 243 244 bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) { 245 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; 246 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID]; 247 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID]; 248 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID]; 249 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID]; 250 251 auto IsFPR = [&](const MCOperand &Op) { 252 if (!Op.isReg()) 253 return false; 254 auto Reg = Op.getReg(); 255 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || 256 FPR16.contains(Reg) || FPR8.contains(Reg); 257 }; 258 259 return llvm::any_of(MI, IsFPR); 260 } 261 262 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) { 263 MCRegisterInfo *X = new MCRegisterInfo(); 264 InitAArch64MCRegisterInfo(X, AArch64::LR); 265 AArch64_MC::initLLVMToCVRegMapping(X); 266 return X; 267 } 268 269 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, 270 const Triple &TheTriple, 271 const MCTargetOptions &Options) { 272 MCAsmInfo *MAI; 273 if (TheTriple.isOSBinFormatMachO()) 274 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32); 275 else if (TheTriple.isWindowsMSVCEnvironment()) 276 MAI = new AArch64MCAsmInfoMicrosoftCOFF(); 277 else if (TheTriple.isOSBinFormatCOFF()) 278 MAI = new AArch64MCAsmInfoGNUCOFF(); 279 else { 280 assert(TheTriple.isOSBinFormatELF() && "Invalid target"); 281 MAI = new AArch64MCAsmInfoELF(TheTriple); 282 } 283 284 // Initial state of the frame pointer is SP. 285 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); 286 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); 287 MAI->addInitialFrameState(Inst); 288 289 return MAI; 290 } 291 292 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, 293 unsigned SyntaxVariant, 294 const MCAsmInfo &MAI, 295 const MCInstrInfo &MII, 296 const MCRegisterInfo &MRI) { 297 if (SyntaxVariant == 0) 298 return new AArch64InstPrinter(MAI, MII, MRI); 299 if (SyntaxVariant == 1) 300 return new AArch64AppleInstPrinter(MAI, MII, MRI); 301 302 return nullptr; 303 } 304 305 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 306 std::unique_ptr<MCAsmBackend> &&TAB, 307 std::unique_ptr<MCObjectWriter> &&OW, 308 std::unique_ptr<MCCodeEmitter> &&Emitter, 309 bool RelaxAll) { 310 return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW), 311 std::move(Emitter), RelaxAll); 312 } 313 314 static MCStreamer *createMachOStreamer(MCContext &Ctx, 315 std::unique_ptr<MCAsmBackend> &&TAB, 316 std::unique_ptr<MCObjectWriter> &&OW, 317 std::unique_ptr<MCCodeEmitter> &&Emitter, 318 bool RelaxAll, 319 bool DWARFMustBeAtTheEnd) { 320 return createMachOStreamer(Ctx, std::move(TAB), std::move(OW), 321 std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd, 322 /*LabelSections*/ true); 323 } 324 325 static MCStreamer * 326 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB, 327 std::unique_ptr<MCObjectWriter> &&OW, 328 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll, 329 bool IncrementalLinkerCompatible) { 330 return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW), 331 std::move(Emitter), RelaxAll, 332 IncrementalLinkerCompatible); 333 } 334 335 namespace { 336 337 class AArch64MCInstrAnalysis : public MCInstrAnalysis { 338 public: 339 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 340 341 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 342 uint64_t &Target) const override { 343 // Search for a PC-relative argument. 344 // This will handle instructions like bcc (where the first argument is the 345 // condition code) and cbz (where it is a register). 346 const auto &Desc = Info->get(Inst.getOpcode()); 347 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) { 348 if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) { 349 int64_t Imm = Inst.getOperand(i).getImm() * 4; 350 Target = Addr + Imm; 351 return true; 352 } 353 } 354 return false; 355 } 356 357 std::vector<std::pair<uint64_t, uint64_t>> 358 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 359 uint64_t GotPltSectionVA, 360 const Triple &TargetTriple) const override { 361 // Do a lightweight parsing of PLT entries. 362 std::vector<std::pair<uint64_t, uint64_t>> Result; 363 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End; 364 Byte += 4) { 365 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); 366 uint64_t Off = 0; 367 // Check for optional bti c that prefixes adrp in BTI enabled entries 368 if (Insn == 0xd503245f) { 369 Off = 4; 370 Insn = support::endian::read32le(PltContents.data() + Byte + Off); 371 } 372 // Check for adrp. 373 if ((Insn & 0x9f000000) != 0x90000000) 374 continue; 375 Off += 4; 376 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) + 377 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14); 378 uint32_t Insn2 = 379 support::endian::read32le(PltContents.data() + Byte + Off); 380 // Check for: ldr Xt, [Xn, #pimm]. 381 if (Insn2 >> 22 == 0x3e5) { 382 Imm += ((Insn2 >> 10) & 0xfff) << 3; 383 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 384 Byte += 4; 385 } 386 } 387 return Result; 388 } 389 }; 390 391 } // end anonymous namespace 392 393 static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) { 394 return new AArch64MCInstrAnalysis(Info); 395 } 396 397 // Force static initialization. 398 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC() { 399 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(), 400 &getTheAArch64_32Target(), &getTheARM64Target(), 401 &getTheARM64_32Target()}) { 402 // Register the MC asm info. 403 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); 404 405 // Register the MC instruction info. 406 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); 407 408 // Register the MC register info. 409 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo); 410 411 // Register the MC subtarget info. 412 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo); 413 414 // Register the MC instruction analyzer. 415 TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis); 416 417 // Register the MC Code Emitter 418 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter); 419 420 // Register the obj streamers. 421 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 422 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer); 423 TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer); 424 425 // Register the obj target streamer. 426 TargetRegistry::RegisterObjectTargetStreamer( 427 *T, createAArch64ObjectTargetStreamer); 428 429 // Register the asm streamer. 430 TargetRegistry::RegisterAsmTargetStreamer(*T, 431 createAArch64AsmTargetStreamer); 432 // Register the MCInstPrinter. 433 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter); 434 } 435 436 // Register the asm backend. 437 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(), 438 &getTheARM64Target(), &getTheARM64_32Target()}) 439 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); 440 TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(), 441 createAArch64beAsmBackend); 442 } 443