1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AArch64 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64MCTargetDesc.h"
15 #include "AArch64ELFStreamer.h"
16 #include "AArch64MCAsmInfo.h"
17 #include "AArch64WinCOFFStreamer.h"
18 #include "InstPrinter/AArch64InstPrinter.h"
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28 
29 using namespace llvm;
30 
31 #define GET_INSTRINFO_MC_DESC
32 #include "AArch64GenInstrInfo.inc"
33 
34 #define GET_SUBTARGETINFO_MC_DESC
35 #include "AArch64GenSubtargetInfo.inc"
36 
37 #define GET_REGINFO_MC_DESC
38 #include "AArch64GenRegisterInfo.inc"
39 
40 static MCInstrInfo *createAArch64MCInstrInfo() {
41   MCInstrInfo *X = new MCInstrInfo();
42   InitAArch64MCInstrInfo(X);
43   return X;
44 }
45 
46 static MCSubtargetInfo *
47 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
48   if (CPU.empty())
49     CPU = "generic";
50 
51   return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
52 }
53 
54 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
55   for (unsigned Reg = AArch64::NoRegister + 1;
56        Reg < AArch64::NUM_TARGET_REGS; ++Reg) {
57     unsigned CV = MRI->getEncodingValue(Reg);
58     MRI->mapLLVMRegToCVReg(Reg, CV);
59   }
60 }
61 
62 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
63   MCRegisterInfo *X = new MCRegisterInfo();
64   InitAArch64MCRegisterInfo(X, AArch64::LR);
65   AArch64_MC::initLLVMToCVRegMapping(X);
66   return X;
67 }
68 
69 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
70                                          const Triple &TheTriple) {
71   MCAsmInfo *MAI;
72   if (TheTriple.isOSBinFormatMachO())
73     MAI = new AArch64MCAsmInfoDarwin();
74   else if (TheTriple.isWindowsMSVCEnvironment())
75     MAI = new AArch64MCAsmInfoMicrosoftCOFF();
76   else if (TheTriple.isOSBinFormatCOFF())
77     MAI = new AArch64MCAsmInfoGNUCOFF();
78   else {
79     assert(TheTriple.isOSBinFormatELF() && "Invalid target");
80     MAI = new AArch64MCAsmInfoELF(TheTriple);
81   }
82 
83   // Initial state of the frame pointer is SP.
84   unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
85   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
86   MAI->addInitialFrameState(Inst);
87 
88   return MAI;
89 }
90 
91 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
92                                                  unsigned SyntaxVariant,
93                                                  const MCAsmInfo &MAI,
94                                                  const MCInstrInfo &MII,
95                                                  const MCRegisterInfo &MRI) {
96   if (SyntaxVariant == 0)
97     return new AArch64InstPrinter(MAI, MII, MRI);
98   if (SyntaxVariant == 1)
99     return new AArch64AppleInstPrinter(MAI, MII, MRI);
100 
101   return nullptr;
102 }
103 
104 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
105                                      std::unique_ptr<MCAsmBackend> &&TAB,
106                                      raw_pwrite_stream &OS,
107                                      std::unique_ptr<MCCodeEmitter> &&Emitter,
108                                      bool RelaxAll) {
109   return createAArch64ELFStreamer(Ctx, std::move(TAB), OS, std::move(Emitter),
110                                   RelaxAll);
111 }
112 
113 static MCStreamer *createMachOStreamer(MCContext &Ctx,
114                                        std::unique_ptr<MCAsmBackend> &&TAB,
115                                        raw_pwrite_stream &OS,
116                                        std::unique_ptr<MCCodeEmitter> &&Emitter,
117                                        bool RelaxAll,
118                                        bool DWARFMustBeAtTheEnd) {
119   return createMachOStreamer(Ctx, std::move(TAB), OS, std::move(Emitter),
120                              RelaxAll, DWARFMustBeAtTheEnd,
121                              /*LabelSections*/ true);
122 }
123 
124 static MCStreamer *
125 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
126                       raw_pwrite_stream &OS,
127                       std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
128                       bool IncrementalLinkerCompatible) {
129   return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), OS,
130                                       std::move(Emitter), RelaxAll,
131                                       IncrementalLinkerCompatible);
132 }
133 
134 static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
135   return new MCInstrAnalysis(Info);
136 }
137 
138 // Force static initialization.
139 extern "C" void LLVMInitializeAArch64TargetMC() {
140   for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
141                     &getTheARM64Target()}) {
142     // Register the MC asm info.
143     RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
144 
145     // Register the MC instruction info.
146     TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
147 
148     // Register the MC register info.
149     TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
150 
151     // Register the MC subtarget info.
152     TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
153 
154     // Register the MC instruction analyzer.
155     TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);
156 
157     // Register the MC Code Emitter
158     TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
159 
160     // Register the obj streamers.
161     TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
162     TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
163     TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer);
164 
165     // Register the obj target streamer.
166     TargetRegistry::RegisterObjectTargetStreamer(
167         *T, createAArch64ObjectTargetStreamer);
168 
169     // Register the asm streamer.
170     TargetRegistry::RegisterAsmTargetStreamer(*T,
171                                               createAArch64AsmTargetStreamer);
172     // Register the MCInstPrinter.
173     TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
174   }
175 
176   // Register the asm backend.
177   for (Target *T : {&getTheAArch64leTarget(), &getTheARM64Target()})
178     TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
179   TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
180                                        createAArch64beAsmBackend);
181 }
182