1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AArch64 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64MCTargetDesc.h"
15 #include "AArch64ELFStreamer.h"
16 #include "AArch64MCAsmInfo.h"
17 #include "InstPrinter/AArch64InstPrinter.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
25 
26 using namespace llvm;
27 
28 #define GET_INSTRINFO_MC_DESC
29 #include "AArch64GenInstrInfo.inc"
30 
31 #define GET_SUBTARGETINFO_MC_DESC
32 #include "AArch64GenSubtargetInfo.inc"
33 
34 #define GET_REGINFO_MC_DESC
35 #include "AArch64GenRegisterInfo.inc"
36 
37 static MCInstrInfo *createAArch64MCInstrInfo() {
38   MCInstrInfo *X = new MCInstrInfo();
39   InitAArch64MCInstrInfo(X);
40   return X;
41 }
42 
43 static MCSubtargetInfo *
44 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
45   MCSubtargetInfo *X = new MCSubtargetInfo();
46 
47   if (CPU.empty())
48     CPU = "generic";
49 
50   InitAArch64MCSubtargetInfo(X, TT, CPU, FS);
51   return X;
52 }
53 
54 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
55   MCRegisterInfo *X = new MCRegisterInfo();
56   InitAArch64MCRegisterInfo(X, AArch64::LR);
57   return X;
58 }
59 
60 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
61                                          const Triple &TheTriple) {
62   MCAsmInfo *MAI;
63   if (TheTriple.isOSBinFormatMachO())
64     MAI = new AArch64MCAsmInfoDarwin();
65   else {
66     assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
67     MAI = new AArch64MCAsmInfoELF(TheTriple);
68   }
69 
70   // Initial state of the frame pointer is SP.
71   unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
72   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
73   MAI->addInitialFrameState(Inst);
74 
75   return MAI;
76 }
77 
78 static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT,
79                                                  Reloc::Model RM,
80                                                  CodeModel::Model CM,
81                                                  CodeGenOpt::Level OL) {
82   assert((TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()) &&
83          "Only expect Darwin and ELF targets");
84 
85   if (CM == CodeModel::Default)
86     CM = CodeModel::Small;
87   // The default MCJIT memory managers make no guarantees about where they can
88   // find an executable page; JITed code needs to be able to refer to globals
89   // no matter how far away they are.
90   else if (CM == CodeModel::JITDefault)
91     CM = CodeModel::Large;
92   else if (CM != CodeModel::Small && CM != CodeModel::Large)
93     report_fatal_error(
94         "Only small and large code models are allowed on AArch64");
95 
96   // AArch64 Darwin is always PIC.
97   if (TT.isOSDarwin())
98     RM = Reloc::PIC_;
99   // On ELF platforms the default static relocation model has a smart enough
100   // linker to cope with referencing external symbols defined in a shared
101   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
102   else if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
103     RM = Reloc::Static;
104 
105   MCCodeGenInfo *X = new MCCodeGenInfo();
106   X->initMCCodeGenInfo(RM, CM, OL);
107   return X;
108 }
109 
110 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
111                                                  unsigned SyntaxVariant,
112                                                  const MCAsmInfo &MAI,
113                                                  const MCInstrInfo &MII,
114                                                  const MCRegisterInfo &MRI) {
115   if (SyntaxVariant == 0)
116     return new AArch64InstPrinter(MAI, MII, MRI);
117   if (SyntaxVariant == 1)
118     return new AArch64AppleInstPrinter(MAI, MII, MRI);
119 
120   return nullptr;
121 }
122 
123 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
124                                      MCAsmBackend &TAB, raw_pwrite_stream &OS,
125                                      MCCodeEmitter *Emitter, bool RelaxAll) {
126   return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
127 }
128 
129 static MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
130                                        raw_pwrite_stream &OS,
131                                        MCCodeEmitter *Emitter, bool RelaxAll,
132                                        bool DWARFMustBeAtTheEnd) {
133   return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
134                              DWARFMustBeAtTheEnd,
135                              /*LabelSections*/ true);
136 }
137 
138 // Force static initialization.
139 extern "C" void LLVMInitializeAArch64TargetMC() {
140   for (Target *T :
141        {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) {
142     // Register the MC asm info.
143     RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
144 
145     // Register the MC codegen info.
146     TargetRegistry::RegisterMCCodeGenInfo(*T, createAArch64MCCodeGenInfo);
147 
148     // Register the MC instruction info.
149     TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
150 
151     // Register the MC register info.
152     TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
153 
154     // Register the MC subtarget info.
155     TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
156 
157     // Register the MC Code Emitter
158     TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
159 
160     // Register the obj streamers.
161     TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
162     TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
163 
164     // Register the obj target streamer.
165     TargetRegistry::RegisterObjectTargetStreamer(
166         *T, createAArch64ObjectTargetStreamer);
167 
168     // Register the asm streamer.
169     TargetRegistry::RegisterAsmTargetStreamer(*T,
170                                               createAArch64AsmTargetStreamer);
171     // Register the MCInstPrinter.
172     TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
173   }
174 
175   // Register the asm backend.
176   for (Target *T : {&TheAArch64leTarget, &TheARM64Target})
177     TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
178   TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget,
179                                        createAArch64beAsmBackend);
180 }
181