1 //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file handles ELF-specific object emission, converting LLVM's internal 10 // fixups into the appropriate relocations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/AArch64FixupKinds.h" 15 #include "MCTargetDesc/AArch64MCExpr.h" 16 #include "MCTargetDesc/AArch64MCTargetDesc.h" 17 #include "llvm/BinaryFormat/ELF.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCELFObjectWriter.h" 20 #include "llvm/MC/MCFixup.h" 21 #include "llvm/MC/MCObjectWriter.h" 22 #include "llvm/MC/MCValue.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include <cassert> 25 #include <cstdint> 26 27 using namespace llvm; 28 29 namespace { 30 31 class AArch64ELFObjectWriter : public MCELFObjectTargetWriter { 32 public: 33 AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32); 34 35 ~AArch64ELFObjectWriter() override = default; 36 37 protected: 38 unsigned getRelocType(MCContext &Ctx, const MCValue &Target, 39 const MCFixup &Fixup, bool IsPCRel) const override; 40 bool IsILP32; 41 }; 42 43 } // end anonymous namespace 44 45 AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) 46 : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64, 47 /*HasRelocationAddend*/ true), 48 IsILP32(IsILP32) {} 49 50 #define R_CLS(rtype) \ 51 IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype 52 #define BAD_ILP32_MOV(lp64rtype) \ 53 "ILP32 absolute MOV relocation not " \ 54 "supported (LP64 eqv: " #lp64rtype ")" 55 56 // assumes IsILP32 is true 57 static bool isNonILP32reloc(const MCFixup &Fixup, 58 AArch64MCExpr::VariantKind RefKind, 59 MCContext &Ctx) { 60 if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw) 61 return false; 62 switch (RefKind) { 63 case AArch64MCExpr::VK_ABS_G3: 64 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3)); 65 return true; 66 case AArch64MCExpr::VK_ABS_G2: 67 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2)); 68 return true; 69 case AArch64MCExpr::VK_ABS_G2_S: 70 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2)); 71 return true; 72 case AArch64MCExpr::VK_ABS_G2_NC: 73 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC)); 74 return true; 75 case AArch64MCExpr::VK_ABS_G1_S: 76 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1)); 77 return true; 78 case AArch64MCExpr::VK_ABS_G1_NC: 79 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC)); 80 return true; 81 case AArch64MCExpr::VK_DTPREL_G2: 82 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2)); 83 return true; 84 case AArch64MCExpr::VK_DTPREL_G1_NC: 85 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC)); 86 return true; 87 case AArch64MCExpr::VK_TPREL_G2: 88 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2)); 89 return true; 90 case AArch64MCExpr::VK_TPREL_G1_NC: 91 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC)); 92 return true; 93 case AArch64MCExpr::VK_GOTTPREL_G1: 94 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1)); 95 return true; 96 case AArch64MCExpr::VK_GOTTPREL_G0_NC: 97 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC)); 98 return true; 99 default: 100 return false; 101 } 102 return false; 103 } 104 105 unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, 106 const MCValue &Target, 107 const MCFixup &Fixup, 108 bool IsPCRel) const { 109 unsigned Kind = Fixup.getTargetKind(); 110 if (Kind >= FirstLiteralRelocationKind) 111 return Kind - FirstLiteralRelocationKind; 112 AArch64MCExpr::VariantKind RefKind = 113 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind()); 114 AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind); 115 bool IsNC = AArch64MCExpr::isNotChecked(RefKind); 116 117 assert((!Target.getSymA() || 118 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) && 119 "Should only be expression-level modifiers here"); 120 121 assert((!Target.getSymB() || 122 Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) && 123 "Should only be expression-level modifiers here"); 124 125 if (IsPCRel) { 126 switch (Kind) { 127 case FK_Data_1: 128 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported"); 129 return ELF::R_AARCH64_NONE; 130 case FK_Data_2: 131 return R_CLS(PREL16); 132 case FK_Data_4: 133 return R_CLS(PREL32); 134 case FK_Data_8: 135 if (IsILP32) { 136 Ctx.reportError(Fixup.getLoc(), 137 "ILP32 8 byte PC relative data " 138 "relocation not supported (LP64 eqv: PREL64)"); 139 return ELF::R_AARCH64_NONE; 140 } else 141 return ELF::R_AARCH64_PREL64; 142 case AArch64::fixup_aarch64_pcrel_adr_imm21: 143 if (SymLoc != AArch64MCExpr::VK_ABS) 144 Ctx.reportError(Fixup.getLoc(), 145 "invalid symbol kind for ADR relocation"); 146 return R_CLS(ADR_PREL_LO21); 147 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 148 if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC) 149 return R_CLS(ADR_PREL_PG_HI21); 150 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) { 151 if (IsILP32) { 152 Ctx.reportError(Fixup.getLoc(), 153 "invalid fixup for 32-bit pcrel ADRP instruction " 154 "VK_ABS VK_NC"); 155 return ELF::R_AARCH64_NONE; 156 } else { 157 return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC; 158 } 159 } 160 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) 161 return R_CLS(ADR_GOT_PAGE); 162 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC) 163 return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21); 164 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) 165 return R_CLS(TLSDESC_ADR_PAGE21); 166 Ctx.reportError(Fixup.getLoc(), 167 "invalid symbol kind for ADRP relocation"); 168 return ELF::R_AARCH64_NONE; 169 case AArch64::fixup_aarch64_pcrel_branch26: 170 return R_CLS(JUMP26); 171 case AArch64::fixup_aarch64_pcrel_call26: 172 return R_CLS(CALL26); 173 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 174 if (SymLoc == AArch64MCExpr::VK_GOTTPREL) 175 return R_CLS(TLSIE_LD_GOTTPREL_PREL19); 176 if (SymLoc == AArch64MCExpr::VK_GOT) 177 return R_CLS(GOT_LD_PREL19); 178 return R_CLS(LD_PREL_LO19); 179 case AArch64::fixup_aarch64_pcrel_branch14: 180 return R_CLS(TSTBR14); 181 case AArch64::fixup_aarch64_pcrel_branch19: 182 return R_CLS(CONDBR19); 183 default: 184 Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind"); 185 return ELF::R_AARCH64_NONE; 186 } 187 } else { 188 if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx)) 189 return ELF::R_AARCH64_NONE; 190 switch (Fixup.getTargetKind()) { 191 case FK_Data_1: 192 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported"); 193 return ELF::R_AARCH64_NONE; 194 case FK_Data_2: 195 return R_CLS(ABS16); 196 case FK_Data_4: 197 return R_CLS(ABS32); 198 case FK_Data_8: 199 if (IsILP32) { 200 Ctx.reportError(Fixup.getLoc(), 201 "ILP32 8 byte absolute data " 202 "relocation not supported (LP64 eqv: ABS64)"); 203 return ELF::R_AARCH64_NONE; 204 } else 205 return ELF::R_AARCH64_ABS64; 206 case AArch64::fixup_aarch64_add_imm12: 207 if (RefKind == AArch64MCExpr::VK_DTPREL_HI12) 208 return R_CLS(TLSLD_ADD_DTPREL_HI12); 209 if (RefKind == AArch64MCExpr::VK_TPREL_HI12) 210 return R_CLS(TLSLE_ADD_TPREL_HI12); 211 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC) 212 return R_CLS(TLSLD_ADD_DTPREL_LO12_NC); 213 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12) 214 return R_CLS(TLSLD_ADD_DTPREL_LO12); 215 if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC) 216 return R_CLS(TLSLE_ADD_TPREL_LO12_NC); 217 if (RefKind == AArch64MCExpr::VK_TPREL_LO12) 218 return R_CLS(TLSLE_ADD_TPREL_LO12); 219 if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12) 220 return R_CLS(TLSDESC_ADD_LO12); 221 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 222 return R_CLS(ADD_ABS_LO12_NC); 223 224 Ctx.reportError(Fixup.getLoc(), 225 "invalid fixup for add (uimm12) instruction"); 226 return ELF::R_AARCH64_NONE; 227 case AArch64::fixup_aarch64_ldst_imm12_scale1: 228 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 229 return R_CLS(LDST8_ABS_LO12_NC); 230 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 231 return R_CLS(TLSLD_LDST8_DTPREL_LO12); 232 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 233 return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC); 234 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 235 return R_CLS(TLSLE_LDST8_TPREL_LO12); 236 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 237 return R_CLS(TLSLE_LDST8_TPREL_LO12_NC); 238 239 Ctx.reportError(Fixup.getLoc(), 240 "invalid fixup for 8-bit load/store instruction"); 241 return ELF::R_AARCH64_NONE; 242 case AArch64::fixup_aarch64_ldst_imm12_scale2: 243 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 244 return R_CLS(LDST16_ABS_LO12_NC); 245 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 246 return R_CLS(TLSLD_LDST16_DTPREL_LO12); 247 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 248 return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC); 249 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 250 return R_CLS(TLSLE_LDST16_TPREL_LO12); 251 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 252 return R_CLS(TLSLE_LDST16_TPREL_LO12_NC); 253 254 Ctx.reportError(Fixup.getLoc(), 255 "invalid fixup for 16-bit load/store instruction"); 256 return ELF::R_AARCH64_NONE; 257 case AArch64::fixup_aarch64_ldst_imm12_scale4: 258 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 259 return R_CLS(LDST32_ABS_LO12_NC); 260 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 261 return R_CLS(TLSLD_LDST32_DTPREL_LO12); 262 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 263 return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC); 264 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 265 return R_CLS(TLSLE_LDST32_TPREL_LO12); 266 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 267 return R_CLS(TLSLE_LDST32_TPREL_LO12_NC); 268 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) { 269 if (IsILP32) { 270 return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC; 271 } else { 272 Ctx.reportError(Fixup.getLoc(), 273 "LP64 4 byte unchecked GOT load/store relocation " 274 "not supported (ILP32 eqv: LD32_GOT_LO12_NC"); 275 return ELF::R_AARCH64_NONE; 276 } 277 } 278 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) { 279 if (IsILP32) { 280 Ctx.reportError(Fixup.getLoc(), 281 "ILP32 4 byte checked GOT load/store relocation " 282 "not supported (unchecked eqv: LD32_GOT_LO12_NC)"); 283 } else { 284 Ctx.reportError(Fixup.getLoc(), 285 "LP64 4 byte checked GOT load/store relocation " 286 "not supported (unchecked/ILP32 eqv: " 287 "LD32_GOT_LO12_NC)"); 288 } 289 return ELF::R_AARCH64_NONE; 290 } 291 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) { 292 if (IsILP32) { 293 return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC; 294 } else { 295 Ctx.reportError(Fixup.getLoc(), 296 "LP64 32-bit load/store " 297 "relocation not supported (ILP32 eqv: " 298 "TLSIE_LD32_GOTTPREL_LO12_NC)"); 299 return ELF::R_AARCH64_NONE; 300 } 301 } 302 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) { 303 if (IsILP32) { 304 return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12; 305 } else { 306 Ctx.reportError(Fixup.getLoc(), 307 "LP64 4 byte TLSDESC load/store relocation " 308 "not supported (ILP32 eqv: TLSDESC_LD64_LO12)"); 309 return ELF::R_AARCH64_NONE; 310 } 311 } 312 313 Ctx.reportError(Fixup.getLoc(), 314 "invalid fixup for 32-bit load/store instruction " 315 "fixup_aarch64_ldst_imm12_scale4"); 316 return ELF::R_AARCH64_NONE; 317 case AArch64::fixup_aarch64_ldst_imm12_scale8: 318 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 319 return R_CLS(LDST64_ABS_LO12_NC); 320 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) { 321 if (!IsILP32) { 322 return ELF::R_AARCH64_LD64_GOT_LO12_NC; 323 } else { 324 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " 325 "relocation not supported (LP64 eqv: " 326 "LD64_GOT_LO12_NC)"); 327 return ELF::R_AARCH64_NONE; 328 } 329 } 330 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 331 return R_CLS(TLSLD_LDST64_DTPREL_LO12); 332 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 333 return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC); 334 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 335 return R_CLS(TLSLE_LDST64_TPREL_LO12); 336 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 337 return R_CLS(TLSLE_LDST64_TPREL_LO12_NC); 338 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) { 339 if (!IsILP32) { 340 return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 341 } else { 342 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " 343 "relocation not supported (LP64 eqv: " 344 "TLSIE_LD64_GOTTPREL_LO12_NC)"); 345 return ELF::R_AARCH64_NONE; 346 } 347 } 348 if (SymLoc == AArch64MCExpr::VK_TLSDESC) { 349 if (!IsILP32) { 350 return ELF::R_AARCH64_TLSDESC_LD64_LO12; 351 } else { 352 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " 353 "relocation not supported (LP64 eqv: " 354 "TLSDESC_LD64_LO12)"); 355 return ELF::R_AARCH64_NONE; 356 } 357 } 358 Ctx.reportError(Fixup.getLoc(), 359 "invalid fixup for 64-bit load/store instruction"); 360 return ELF::R_AARCH64_NONE; 361 case AArch64::fixup_aarch64_ldst_imm12_scale16: 362 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 363 return R_CLS(LDST128_ABS_LO12_NC); 364 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 365 return R_CLS(TLSLD_LDST128_DTPREL_LO12); 366 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 367 return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC); 368 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 369 return R_CLS(TLSLE_LDST128_TPREL_LO12); 370 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 371 return R_CLS(TLSLE_LDST128_TPREL_LO12_NC); 372 373 Ctx.reportError(Fixup.getLoc(), 374 "invalid fixup for 128-bit load/store instruction"); 375 return ELF::R_AARCH64_NONE; 376 // ILP32 case not reached here, tested with isNonILP32reloc 377 case AArch64::fixup_aarch64_movw: 378 if (RefKind == AArch64MCExpr::VK_ABS_G3) 379 return ELF::R_AARCH64_MOVW_UABS_G3; 380 if (RefKind == AArch64MCExpr::VK_ABS_G2) 381 return ELF::R_AARCH64_MOVW_UABS_G2; 382 if (RefKind == AArch64MCExpr::VK_ABS_G2_S) 383 return ELF::R_AARCH64_MOVW_SABS_G2; 384 if (RefKind == AArch64MCExpr::VK_ABS_G2_NC) 385 return ELF::R_AARCH64_MOVW_UABS_G2_NC; 386 if (RefKind == AArch64MCExpr::VK_ABS_G1) 387 return R_CLS(MOVW_UABS_G1); 388 if (RefKind == AArch64MCExpr::VK_ABS_G1_S) 389 return ELF::R_AARCH64_MOVW_SABS_G1; 390 if (RefKind == AArch64MCExpr::VK_ABS_G1_NC) 391 return ELF::R_AARCH64_MOVW_UABS_G1_NC; 392 if (RefKind == AArch64MCExpr::VK_ABS_G0) 393 return R_CLS(MOVW_UABS_G0); 394 if (RefKind == AArch64MCExpr::VK_ABS_G0_S) 395 return R_CLS(MOVW_SABS_G0); 396 if (RefKind == AArch64MCExpr::VK_ABS_G0_NC) 397 return R_CLS(MOVW_UABS_G0_NC); 398 if (RefKind == AArch64MCExpr::VK_PREL_G3) 399 return ELF::R_AARCH64_MOVW_PREL_G3; 400 if (RefKind == AArch64MCExpr::VK_PREL_G2) 401 return ELF::R_AARCH64_MOVW_PREL_G2; 402 if (RefKind == AArch64MCExpr::VK_PREL_G2_NC) 403 return ELF::R_AARCH64_MOVW_PREL_G2_NC; 404 if (RefKind == AArch64MCExpr::VK_PREL_G1) 405 return R_CLS(MOVW_PREL_G1); 406 if (RefKind == AArch64MCExpr::VK_PREL_G1_NC) 407 return ELF::R_AARCH64_MOVW_PREL_G1_NC; 408 if (RefKind == AArch64MCExpr::VK_PREL_G0) 409 return R_CLS(MOVW_PREL_G0); 410 if (RefKind == AArch64MCExpr::VK_PREL_G0_NC) 411 return R_CLS(MOVW_PREL_G0_NC); 412 if (RefKind == AArch64MCExpr::VK_DTPREL_G2) 413 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2; 414 if (RefKind == AArch64MCExpr::VK_DTPREL_G1) 415 return R_CLS(TLSLD_MOVW_DTPREL_G1); 416 if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC) 417 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC; 418 if (RefKind == AArch64MCExpr::VK_DTPREL_G0) 419 return R_CLS(TLSLD_MOVW_DTPREL_G0); 420 if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC) 421 return R_CLS(TLSLD_MOVW_DTPREL_G0_NC); 422 if (RefKind == AArch64MCExpr::VK_TPREL_G2) 423 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2; 424 if (RefKind == AArch64MCExpr::VK_TPREL_G1) 425 return R_CLS(TLSLE_MOVW_TPREL_G1); 426 if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC) 427 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC; 428 if (RefKind == AArch64MCExpr::VK_TPREL_G0) 429 return R_CLS(TLSLE_MOVW_TPREL_G0); 430 if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC) 431 return R_CLS(TLSLE_MOVW_TPREL_G0_NC); 432 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1) 433 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1; 434 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC) 435 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC; 436 Ctx.reportError(Fixup.getLoc(), 437 "invalid fixup for movz/movk instruction"); 438 return ELF::R_AARCH64_NONE; 439 case AArch64::fixup_aarch64_tlsdesc_call: 440 return R_CLS(TLSDESC_CALL); 441 default: 442 Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type"); 443 return ELF::R_AARCH64_NONE; 444 } 445 } 446 447 llvm_unreachable("Unimplemented fixup -> relocation"); 448 } 449 450 std::unique_ptr<MCObjectTargetWriter> 451 llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) { 452 return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32); 453 } 454