1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the AArch64 implementation of the MCAsmBackend class, 11 // which is principally concerned with relaxation of the various fixup kinds. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MCTargetDesc/AArch64FixupKinds.h" 16 #include "MCTargetDesc/AArch64MCTargetDesc.h" 17 #include "llvm/MC/MCAsmBackend.h" 18 #include "llvm/MC/MCELFObjectWriter.h" 19 #include "llvm/MC/MCFixupKindInfo.h" 20 #include "llvm/MC/MCObjectWriter.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/ELF.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/raw_ostream.h" 25 using namespace llvm; 26 27 namespace { 28 class AArch64AsmBackend : public MCAsmBackend { 29 const MCSubtargetInfo* STI; 30 public: 31 AArch64AsmBackend(const Target &T, const StringRef TT) 32 : MCAsmBackend(), 33 STI(AArch64_MC::createAArch64MCSubtargetInfo(TT, "", "")) 34 {} 35 36 37 ~AArch64AsmBackend() { 38 delete STI; 39 } 40 41 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; 42 43 virtual void processFixupValue(const MCAssembler &Asm, 44 const MCAsmLayout &Layout, 45 const MCFixup &Fixup, const MCFragment *DF, 46 const MCValue &Target, uint64_t &Value, 47 bool &IsResolved); 48 }; 49 } // end anonymous namespace 50 51 void AArch64AsmBackend::processFixupValue(const MCAssembler &Asm, 52 const MCAsmLayout &Layout, 53 const MCFixup &Fixup, 54 const MCFragment *DF, 55 const MCValue &Target, 56 uint64_t &Value, bool &IsResolved) { 57 // The ADRP instruction adds some multiple of 0x1000 to the current PC & 58 // ~0xfff. This means that the required offset to reach a symbol can vary by 59 // up to one step depending on where the ADRP is in memory. For example: 60 // 61 // ADRP x0, there 62 // there: 63 // 64 // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and 65 // we'll need that as an offset. At any other address "there" will be in the 66 // same page as the ADRP and the instruction should encode 0x0. Assuming the 67 // section isn't 0x1000-aligned, we therefore need to delegate this decision 68 // to the linker -- a relocation! 69 if ((uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_page || 70 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_got_page || 71 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_gottprel_page || 72 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_tlsdesc_adr_page) 73 IsResolved = false; 74 } 75 76 77 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value); 78 79 namespace { 80 81 class ELFAArch64AsmBackend : public AArch64AsmBackend { 82 uint8_t OSABI; 83 bool IsLittle; // Big or little endian 84 public: 85 ELFAArch64AsmBackend(const Target &T, const StringRef TT, 86 uint8_t _OSABI, bool isLittle) 87 : AArch64AsmBackend(T, TT), OSABI(_OSABI), IsLittle(isLittle) { } 88 89 bool fixupNeedsRelaxation(const MCFixup &Fixup, 90 uint64_t Value, 91 const MCRelaxableFragment *DF, 92 const MCAsmLayout &Layout) const; 93 94 unsigned int getNumFixupKinds() const { 95 return AArch64::NumTargetFixupKinds; 96 } 97 98 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 99 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = { 100 // This table *must* be in the order that the fixup_* kinds are defined in 101 // AArch64FixupKinds.h. 102 // 103 // Name Offset (bits) Size (bits) Flags 104 { "fixup_a64_ld_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 105 { "fixup_a64_adr_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 106 { "fixup_a64_adr_prel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 107 { "fixup_a64_add_lo12", 0, 32, 0 }, 108 { "fixup_a64_ldst8_lo12", 0, 32, 0 }, 109 { "fixup_a64_ldst16_lo12", 0, 32, 0 }, 110 { "fixup_a64_ldst32_lo12", 0, 32, 0 }, 111 { "fixup_a64_ldst64_lo12", 0, 32, 0 }, 112 { "fixup_a64_ldst128_lo12", 0, 32, 0 }, 113 { "fixup_a64_tstbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 114 { "fixup_a64_condbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 115 { "fixup_a64_uncondbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 116 { "fixup_a64_call", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 117 { "fixup_a64_movw_uabs_g0", 0, 32, 0 }, 118 { "fixup_a64_movw_uabs_g0_nc", 0, 32, 0 }, 119 { "fixup_a64_movw_uabs_g1", 0, 32, 0 }, 120 { "fixup_a64_movw_uabs_g1_nc", 0, 32, 0 }, 121 { "fixup_a64_movw_uabs_g2", 0, 32, 0 }, 122 { "fixup_a64_movw_uabs_g2_nc", 0, 32, 0 }, 123 { "fixup_a64_movw_uabs_g3", 0, 32, 0 }, 124 { "fixup_a64_movw_sabs_g0", 0, 32, 0 }, 125 { "fixup_a64_movw_sabs_g1", 0, 32, 0 }, 126 { "fixup_a64_movw_sabs_g2", 0, 32, 0 }, 127 { "fixup_a64_adr_prel_got_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 128 { "fixup_a64_ld64_got_lo12_nc", 0, 32, 0 }, 129 { "fixup_a64_movw_dtprel_g2", 0, 32, 0 }, 130 { "fixup_a64_movw_dtprel_g1", 0, 32, 0 }, 131 { "fixup_a64_movw_dtprel_g1_nc", 0, 32, 0 }, 132 { "fixup_a64_movw_dtprel_g0", 0, 32, 0 }, 133 { "fixup_a64_movw_dtprel_g0_nc", 0, 32, 0 }, 134 { "fixup_a64_add_dtprel_hi12", 0, 32, 0 }, 135 { "fixup_a64_add_dtprel_lo12", 0, 32, 0 }, 136 { "fixup_a64_add_dtprel_lo12_nc", 0, 32, 0 }, 137 { "fixup_a64_ldst8_dtprel_lo12", 0, 32, 0 }, 138 { "fixup_a64_ldst8_dtprel_lo12_nc", 0, 32, 0 }, 139 { "fixup_a64_ldst16_dtprel_lo12", 0, 32, 0 }, 140 { "fixup_a64_ldst16_dtprel_lo12_nc", 0, 32, 0 }, 141 { "fixup_a64_ldst32_dtprel_lo12", 0, 32, 0 }, 142 { "fixup_a64_ldst32_dtprel_lo12_nc", 0, 32, 0 }, 143 { "fixup_a64_ldst64_dtprel_lo12", 0, 32, 0 }, 144 { "fixup_a64_ldst64_dtprel_lo12_nc", 0, 32, 0 }, 145 { "fixup_a64_movw_gottprel_g1", 0, 32, 0 }, 146 { "fixup_a64_movw_gottprel_g0_nc", 0, 32, 0 }, 147 { "fixup_a64_adr_gottprel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 148 { "fixup_a64_ld64_gottprel_lo12_nc", 0, 32, 0 }, 149 { "fixup_a64_ld_gottprel_prel19", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 150 { "fixup_a64_movw_tprel_g2", 0, 32, 0 }, 151 { "fixup_a64_movw_tprel_g1", 0, 32, 0 }, 152 { "fixup_a64_movw_tprel_g1_nc", 0, 32, 0 }, 153 { "fixup_a64_movw_tprel_g0", 0, 32, 0 }, 154 { "fixup_a64_movw_tprel_g0_nc", 0, 32, 0 }, 155 { "fixup_a64_add_tprel_hi12", 0, 32, 0 }, 156 { "fixup_a64_add_tprel_lo12", 0, 32, 0 }, 157 { "fixup_a64_add_tprel_lo12_nc", 0, 32, 0 }, 158 { "fixup_a64_ldst8_tprel_lo12", 0, 32, 0 }, 159 { "fixup_a64_ldst8_tprel_lo12_nc", 0, 32, 0 }, 160 { "fixup_a64_ldst16_tprel_lo12", 0, 32, 0 }, 161 { "fixup_a64_ldst16_tprel_lo12_nc", 0, 32, 0 }, 162 { "fixup_a64_ldst32_tprel_lo12", 0, 32, 0 }, 163 { "fixup_a64_ldst32_tprel_lo12_nc", 0, 32, 0 }, 164 { "fixup_a64_ldst64_tprel_lo12", 0, 32, 0 }, 165 { "fixup_a64_ldst64_tprel_lo12_nc", 0, 32, 0 }, 166 { "fixup_a64_tlsdesc_adr_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 167 { "fixup_a64_tlsdesc_ld64_lo12_nc", 0, 32, 0 }, 168 { "fixup_a64_tlsdesc_add_lo12_nc", 0, 32, 0 }, 169 { "fixup_a64_tlsdesc_call", 0, 0, 0 } 170 }; 171 if (Kind < FirstTargetFixupKind) 172 return MCAsmBackend::getFixupKindInfo(Kind); 173 174 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 175 "Invalid kind!"); 176 return Infos[Kind - FirstTargetFixupKind]; 177 } 178 179 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 180 uint64_t Value, bool IsPCRel) const { 181 unsigned NumBytes = getFixupKindInfo(Fixup.getKind()).TargetSize / 8; 182 Value = adjustFixupValue(Fixup.getKind(), Value); 183 if (!Value) return; // Doesn't change encoding. 184 185 unsigned Offset = Fixup.getOffset(); 186 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 187 188 // For each byte of the fragment that the fixup touches, mask in the bits 189 // from the fixup value. 190 for (unsigned i = 0; i != NumBytes; ++i) { 191 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 192 } 193 } 194 195 bool mayNeedRelaxation(const MCInst&) const { 196 return false; 197 } 198 199 void relaxInstruction(const MCInst&, llvm::MCInst&) const { 200 llvm_unreachable("Cannot relax instructions"); 201 } 202 203 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 204 return createAArch64ELFObjectWriter(OS, OSABI, IsLittle); 205 } 206 }; 207 208 } // end anonymous namespace 209 210 bool 211 ELFAArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 212 uint64_t Value, 213 const MCRelaxableFragment *DF, 214 const MCAsmLayout &Layout) const { 215 // Correct for now. With all instructions 32-bit only very low-level 216 // considerations could make you select something which may fail. 217 return false; 218 } 219 220 221 bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 222 // Can't emit NOP with size not multiple of 32-bits 223 if (Count % 4 != 0) 224 return false; 225 226 uint64_t NumNops = Count / 4; 227 for (uint64_t i = 0; i != NumNops; ++i) 228 OW->Write32(0xd503201f); 229 230 return true; 231 } 232 233 static unsigned ADRImmBits(unsigned Value) { 234 unsigned lo2 = Value & 0x3; 235 unsigned hi19 = (Value & 0x1fffff) >> 2; 236 237 return (hi19 << 5) | (lo2 << 29); 238 } 239 240 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { 241 switch (Kind) { 242 default: 243 llvm_unreachable("Unknown fixup kind!"); 244 case FK_Data_2: 245 assert((int64_t)Value >= -32768 && 246 (int64_t)Value <= 65536 && 247 "Out of range ABS16 fixup"); 248 return Value; 249 case FK_Data_4: 250 assert((int64_t)Value >= -(1LL << 31) && 251 (int64_t)Value <= (1LL << 32) - 1 && 252 "Out of range ABS32 fixup"); 253 return Value; 254 case FK_Data_8: 255 return Value; 256 257 case AArch64::fixup_a64_ld_gottprel_prel19: 258 // R_AARCH64_LD_GOTTPREL_PREL19: Set a load-literal immediate to bits 1F 259 // FFFC of G(TPREL(S+A)) - P; check -2^20 <= X < 2^20. 260 case AArch64::fixup_a64_ld_prel: 261 // R_AARCH64_LD_PREL_LO19: Sets a load-literal (immediate) value to bits 262 // 1F FFFC of S+A-P, checking that -2^20 <= S+A-P < 2^20. 263 assert((int64_t)Value >= -(1LL << 20) && 264 (int64_t)Value < (1LL << 20) && "Out of range LDR (lit) fixup"); 265 return (Value & 0x1ffffc) << 3; 266 267 case AArch64::fixup_a64_adr_prel: 268 // R_AARCH64_ADR_PREL_LO21: Sets an ADR immediate value to bits 1F FFFF of 269 // the result of S+A-P, checking that -2^20 <= S+A-P < 2^20. 270 assert((int64_t)Value >= -(1LL << 20) && 271 (int64_t)Value < (1LL << 20) && "Out of range ADR fixup"); 272 return ADRImmBits(Value & 0x1fffff); 273 274 case AArch64::fixup_a64_adr_prel_page: 275 // R_AARCH64_ADR_PREL_PG_HI21: Sets an ADRP immediate value to bits 1 FFFF 276 // F000 of the result of the operation, checking that -2^32 <= result < 277 // 2^32. 278 assert((int64_t)Value >= -(1LL << 32) && 279 (int64_t)Value < (1LL << 32) && "Out of range ADRP fixup"); 280 return ADRImmBits((Value & 0x1fffff000ULL) >> 12); 281 282 case AArch64::fixup_a64_add_dtprel_hi12: 283 // R_AARCH64_TLSLD_ADD_DTPREL_LO12: Set an ADD immediate field to bits 284 // FF F000 of DTPREL(S+A), check 0 <= X < 2^24. 285 case AArch64::fixup_a64_add_tprel_hi12: 286 // R_AARCH64_TLSLD_ADD_TPREL_LO12: Set an ADD immediate field to bits 287 // FF F000 of TPREL(S+A), check 0 <= X < 2^24. 288 assert((int64_t)Value >= 0 && 289 (int64_t)Value < (1LL << 24) && "Out of range ADD fixup"); 290 return (Value & 0xfff000) >> 2; 291 292 case AArch64::fixup_a64_add_dtprel_lo12: 293 // R_AARCH64_TLSLD_ADD_DTPREL_LO12: Set an ADD immediate field to bits 294 // FFF of DTPREL(S+A), check 0 <= X < 2^12. 295 case AArch64::fixup_a64_add_tprel_lo12: 296 // R_AARCH64_TLSLD_ADD_TPREL_LO12: Set an ADD immediate field to bits 297 // FFF of TPREL(S+A), check 0 <= X < 2^12. 298 assert((int64_t)Value >= 0 && 299 (int64_t)Value < (1LL << 12) && "Out of range ADD fixup"); 300 // ... fallthrough to no-checking versions ... 301 case AArch64::fixup_a64_add_dtprel_lo12_nc: 302 // R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: Set an ADD immediate field to bits 303 // FFF of DTPREL(S+A) with no overflow check. 304 case AArch64::fixup_a64_add_tprel_lo12_nc: 305 // R_AARCH64_TLSLD_ADD_TPREL_LO12_NC: Set an ADD immediate field to bits 306 // FFF of TPREL(S+A) with no overflow check. 307 case AArch64::fixup_a64_tlsdesc_add_lo12_nc: 308 // R_AARCH64_TLSDESC_ADD_LO12_NC: Set an ADD immediate field to bits 309 // FFF of G(TLSDESC(S+A)), with no overflow check. 310 case AArch64::fixup_a64_add_lo12: 311 // R_AARCH64_ADD_ABS_LO12_NC: Sets an ADD immediate value to bits FFF of 312 // S+A, with no overflow check. 313 return (Value & 0xfff) << 10; 314 315 case AArch64::fixup_a64_ldst8_dtprel_lo12: 316 // R_AARCH64_TLSLD_LDST8_DTPREL_LO12: Set an LD/ST offset field to bits FFF 317 // of DTPREL(S+A), check 0 <= X < 2^12. 318 case AArch64::fixup_a64_ldst8_tprel_lo12: 319 // R_AARCH64_TLSLE_LDST8_TPREL_LO12: Set an LD/ST offset field to bits FFF 320 // of DTPREL(S+A), check 0 <= X < 2^12. 321 assert((int64_t) Value >= 0 && 322 (int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup"); 323 // ... fallthrough to no-checking versions ... 324 case AArch64::fixup_a64_ldst8_dtprel_lo12_nc: 325 // R_AARCH64_TLSLD_LDST8_DTPREL_LO12: Set an LD/ST offset field to bits FFF 326 // of DTPREL(S+A), with no overflow check. 327 case AArch64::fixup_a64_ldst8_tprel_lo12_nc: 328 // R_AARCH64_TLSLD_LDST8_TPREL_LO12: Set an LD/ST offset field to bits FFF 329 // of TPREL(S+A), with no overflow check. 330 case AArch64::fixup_a64_ldst8_lo12: 331 // R_AARCH64_LDST8_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFF 332 // of S+A, with no overflow check. 333 return (Value & 0xfff) << 10; 334 335 case AArch64::fixup_a64_ldst16_dtprel_lo12: 336 // R_AARCH64_TLSLD_LDST16_DTPREL_LO12: Set an LD/ST offset field to bits FFE 337 // of DTPREL(S+A), check 0 <= X < 2^12. 338 case AArch64::fixup_a64_ldst16_tprel_lo12: 339 // R_AARCH64_TLSLE_LDST16_TPREL_LO12: Set an LD/ST offset field to bits FFE 340 // of DTPREL(S+A), check 0 <= X < 2^12. 341 assert((int64_t) Value >= 0 && 342 (int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup"); 343 // ... fallthrough to no-checking versions ... 344 case AArch64::fixup_a64_ldst16_dtprel_lo12_nc: 345 // R_AARCH64_TLSLD_LDST16_DTPREL_LO12: Set an LD/ST offset field to bits FFE 346 // of DTPREL(S+A), with no overflow check. 347 case AArch64::fixup_a64_ldst16_tprel_lo12_nc: 348 // R_AARCH64_TLSLD_LDST16_TPREL_LO12: Set an LD/ST offset field to bits FFE 349 // of TPREL(S+A), with no overflow check. 350 case AArch64::fixup_a64_ldst16_lo12: 351 // R_AARCH64_LDST16_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFE 352 // of S+A, with no overflow check. 353 return (Value & 0xffe) << 9; 354 355 case AArch64::fixup_a64_ldst32_dtprel_lo12: 356 // R_AARCH64_TLSLD_LDST32_DTPREL_LO12: Set an LD/ST offset field to bits FFC 357 // of DTPREL(S+A), check 0 <= X < 2^12. 358 case AArch64::fixup_a64_ldst32_tprel_lo12: 359 // R_AARCH64_TLSLE_LDST32_TPREL_LO12: Set an LD/ST offset field to bits FFC 360 // of DTPREL(S+A), check 0 <= X < 2^12. 361 assert((int64_t) Value >= 0 && 362 (int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup"); 363 // ... fallthrough to no-checking versions ... 364 case AArch64::fixup_a64_ldst32_dtprel_lo12_nc: 365 // R_AARCH64_TLSLD_LDST32_DTPREL_LO12: Set an LD/ST offset field to bits FFC 366 // of DTPREL(S+A), with no overflow check. 367 case AArch64::fixup_a64_ldst32_tprel_lo12_nc: 368 // R_AARCH64_TLSLD_LDST32_TPREL_LO12: Set an LD/ST offset field to bits FFC 369 // of TPREL(S+A), with no overflow check. 370 case AArch64::fixup_a64_ldst32_lo12: 371 // R_AARCH64_LDST32_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFC 372 // of S+A, with no overflow check. 373 return (Value & 0xffc) << 8; 374 375 case AArch64::fixup_a64_ldst64_dtprel_lo12: 376 // R_AARCH64_TLSLD_LDST64_DTPREL_LO12: Set an LD/ST offset field to bits FF8 377 // of DTPREL(S+A), check 0 <= X < 2^12. 378 case AArch64::fixup_a64_ldst64_tprel_lo12: 379 // R_AARCH64_TLSLE_LDST64_TPREL_LO12: Set an LD/ST offset field to bits FF8 380 // of DTPREL(S+A), check 0 <= X < 2^12. 381 assert((int64_t) Value >= 0 && 382 (int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup"); 383 // ... fallthrough to no-checking versions ... 384 case AArch64::fixup_a64_ldst64_dtprel_lo12_nc: 385 // R_AARCH64_TLSLD_LDST64_DTPREL_LO12: Set an LD/ST offset field to bits FF8 386 // of DTPREL(S+A), with no overflow check. 387 case AArch64::fixup_a64_ldst64_tprel_lo12_nc: 388 // R_AARCH64_TLSLD_LDST64_TPREL_LO12: Set an LD/ST offset field to bits FF8 389 // of TPREL(S+A), with no overflow check. 390 case AArch64::fixup_a64_ldst64_lo12: 391 // R_AARCH64_LDST64_ABS_LO12_NC: Sets an LD/ST immediate value to bits FF8 392 // of S+A, with no overflow check. 393 return (Value & 0xff8) << 7; 394 395 case AArch64::fixup_a64_ldst128_lo12: 396 // R_AARCH64_LDST128_ABS_LO12_NC: Sets an LD/ST immediate value to bits FF0 397 // of S+A, with no overflow check. 398 return (Value & 0xff0) << 6; 399 400 case AArch64::fixup_a64_movw_uabs_g0: 401 // R_AARCH64_MOVW_UABS_G0: Sets a MOVZ immediate field to bits FFFF of S+A 402 // with a check that S+A < 2^16 403 assert(Value <= 0xffff && "Out of range move wide fixup"); 404 return (Value & 0xffff) << 5; 405 406 case AArch64::fixup_a64_movw_dtprel_g0_nc: 407 // R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: Sets a MOVK immediate field to bits 408 // FFFF of DTPREL(S+A) with no overflow check. 409 case AArch64::fixup_a64_movw_gottprel_g0_nc: 410 // R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: Sets a MOVK immediate field to bits 411 // FFFF of G(TPREL(S+A)) - GOT with no overflow check. 412 case AArch64::fixup_a64_movw_tprel_g0_nc: 413 // R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: Sets a MOVK immediate field to bits 414 // FFFF of TPREL(S+A) with no overflow check. 415 case AArch64::fixup_a64_movw_uabs_g0_nc: 416 // R_AARCH64_MOVW_UABS_G0_NC: Sets a MOVK immediate field to bits FFFF of 417 // S+A with no overflow check. 418 return (Value & 0xffff) << 5; 419 420 case AArch64::fixup_a64_movw_uabs_g1: 421 // R_AARCH64_MOVW_UABS_G1: Sets a MOVZ immediate field to bits FFFF0000 of 422 // S+A with a check that S+A < 2^32 423 assert(Value <= 0xffffffffull && "Out of range move wide fixup"); 424 return ((Value >> 16) & 0xffff) << 5; 425 426 case AArch64::fixup_a64_movw_dtprel_g1_nc: 427 // R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: Set a MOVK immediate field 428 // to bits FFFF0000 of DTPREL(S+A), with no overflow check. 429 case AArch64::fixup_a64_movw_tprel_g1_nc: 430 // R_AARCH64_TLSLD_MOVW_TPREL_G1_NC: Set a MOVK immediate field 431 // to bits FFFF0000 of TPREL(S+A), with no overflow check. 432 case AArch64::fixup_a64_movw_uabs_g1_nc: 433 // R_AARCH64_MOVW_UABS_G1_NC: Sets a MOVK immediate field to bits 434 // FFFF0000 of S+A with no overflow check. 435 return ((Value >> 16) & 0xffff) << 5; 436 437 case AArch64::fixup_a64_movw_uabs_g2: 438 // R_AARCH64_MOVW_UABS_G2: Sets a MOVZ immediate field to bits FFFF 0000 439 // 0000 of S+A with a check that S+A < 2^48 440 assert(Value <= 0xffffffffffffull && "Out of range move wide fixup"); 441 return ((Value >> 32) & 0xffff) << 5; 442 443 case AArch64::fixup_a64_movw_uabs_g2_nc: 444 // R_AARCH64_MOVW_UABS_G2: Sets a MOVK immediate field to bits FFFF 0000 445 // 0000 of S+A with no overflow check. 446 return ((Value >> 32) & 0xffff) << 5; 447 448 case AArch64::fixup_a64_movw_uabs_g3: 449 // R_AARCH64_MOVW_UABS_G3: Sets a MOVZ immediate field to bits FFFF 0000 450 // 0000 0000 of S+A (no overflow check needed) 451 return ((Value >> 48) & 0xffff) << 5; 452 453 case AArch64::fixup_a64_movw_dtprel_g0: 454 // R_AARCH64_TLSLD_MOVW_DTPREL_G0: Set a MOV[NZ] immediate field 455 // to bits FFFF of DTPREL(S+A). 456 case AArch64::fixup_a64_movw_tprel_g0: 457 // R_AARCH64_TLSLE_MOVW_TPREL_G0: Set a MOV[NZ] immediate field to 458 // bits FFFF of TPREL(S+A). 459 case AArch64::fixup_a64_movw_sabs_g0: { 460 // R_AARCH64_MOVW_SABS_G0: Sets MOV[NZ] immediate field using bits FFFF of 461 // S+A (see notes below); check -2^16 <= S+A < 2^16. (notes say that we 462 // should convert between MOVN and MOVZ to achieve our goals). 463 int64_t Signed = Value; 464 assert(Signed >= -(1LL << 16) && Signed < (1LL << 16) 465 && "Out of range move wide fixup"); 466 if (Signed >= 0) { 467 Value = (Value & 0xffff) << 5; 468 // Bit 30 converts the MOVN encoding into a MOVZ 469 Value |= 1 << 30; 470 } else { 471 // MCCodeEmitter should have encoded a MOVN, which is fine. 472 Value = (~Value & 0xffff) << 5; 473 } 474 return Value; 475 } 476 477 case AArch64::fixup_a64_movw_dtprel_g1: 478 // R_AARCH64_TLSLD_MOVW_DTPREL_G1: Set a MOV[NZ] immediate field 479 // to bits FFFF0000 of DTPREL(S+A). 480 case AArch64::fixup_a64_movw_gottprel_g1: 481 // R_AARCH64_TLSIE_MOVW_GOTTPREL_G1: Set a MOV[NZ] immediate field 482 // to bits FFFF0000 of G(TPREL(S+A)) - GOT. 483 case AArch64::fixup_a64_movw_tprel_g1: 484 // R_AARCH64_TLSLE_MOVW_TPREL_G1: Set a MOV[NZ] immediate field to 485 // bits FFFF0000 of TPREL(S+A). 486 case AArch64::fixup_a64_movw_sabs_g1: { 487 // R_AARCH64_MOVW_SABS_G1: Sets MOV[NZ] immediate field using bits FFFF 0000 488 // of S+A (see notes below); check -2^32 <= S+A < 2^32. (notes say that we 489 // should convert between MOVN and MOVZ to achieve our goals). 490 int64_t Signed = Value; 491 assert(Signed >= -(1LL << 32) && Signed < (1LL << 32) 492 && "Out of range move wide fixup"); 493 if (Signed >= 0) { 494 Value = ((Value >> 16) & 0xffff) << 5; 495 // Bit 30 converts the MOVN encoding into a MOVZ 496 Value |= 1 << 30; 497 } else { 498 Value = ((~Value >> 16) & 0xffff) << 5; 499 } 500 return Value; 501 } 502 503 case AArch64::fixup_a64_movw_dtprel_g2: 504 // R_AARCH64_TLSLD_MOVW_DTPREL_G2: Set a MOV[NZ] immediate field 505 // to bits FFFF 0000 0000 of DTPREL(S+A). 506 case AArch64::fixup_a64_movw_tprel_g2: 507 // R_AARCH64_TLSLE_MOVW_TPREL_G2: Set a MOV[NZ] immediate field to 508 // bits FFFF 0000 0000 of TPREL(S+A). 509 case AArch64::fixup_a64_movw_sabs_g2: { 510 // R_AARCH64_MOVW_SABS_G2: Sets MOV[NZ] immediate field using bits FFFF 0000 511 // 0000 of S+A (see notes below); check -2^48 <= S+A < 2^48. (notes say that 512 // we should convert between MOVN and MOVZ to achieve our goals). 513 int64_t Signed = Value; 514 assert(Signed >= -(1LL << 48) && Signed < (1LL << 48) 515 && "Out of range move wide fixup"); 516 if (Signed >= 0) { 517 Value = ((Value >> 32) & 0xffff) << 5; 518 // Bit 30 converts the MOVN encoding into a MOVZ 519 Value |= 1 << 30; 520 } else { 521 Value = ((~Value >> 32) & 0xffff) << 5; 522 } 523 return Value; 524 } 525 526 case AArch64::fixup_a64_tstbr: 527 // R_AARCH64_TSTBR14: Sets the immediate field of a TBZ/TBNZ instruction to 528 // bits FFFC of S+A-P, checking -2^15 <= S+A-P < 2^15. 529 assert((int64_t)Value >= -(1LL << 15) && 530 (int64_t)Value < (1LL << 15) && "Out of range TBZ/TBNZ fixup"); 531 return (Value & 0xfffc) << (5 - 2); 532 533 case AArch64::fixup_a64_condbr: 534 // R_AARCH64_CONDBR19: Sets the immediate field of a conditional branch 535 // instruction to bits 1FFFFC of S+A-P, checking -2^20 <= S+A-P < 2^20. 536 assert((int64_t)Value >= -(1LL << 20) && 537 (int64_t)Value < (1LL << 20) && "Out of range B.cond fixup"); 538 return (Value & 0x1ffffc) << (5 - 2); 539 540 case AArch64::fixup_a64_uncondbr: 541 // R_AARCH64_JUMP26 same as below (except to a linker, possibly). 542 case AArch64::fixup_a64_call: 543 // R_AARCH64_CALL26: Sets a CALL immediate field to bits FFFFFFC of S+A-P, 544 // checking that -2^27 <= S+A-P < 2^27. 545 assert((int64_t)Value >= -(1LL << 27) && 546 (int64_t)Value < (1LL << 27) && "Out of range branch fixup"); 547 return (Value & 0xffffffc) >> 2; 548 549 case AArch64::fixup_a64_adr_gottprel_page: 550 // R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: Set an ADRP immediate field to bits 551 // 1FFFFF000 of Page(G(TPREL(S+A))) - Page(P); check -2^32 <= X < 2^32. 552 case AArch64::fixup_a64_tlsdesc_adr_page: 553 // R_AARCH64_TLSDESC_ADR_PAGE: Set an ADRP immediate field to bits 1FFFFF000 554 // of Page(G(TLSDESC(S+A))) - Page(P); check -2^32 <= X < 2^32. 555 case AArch64::fixup_a64_adr_prel_got_page: 556 // R_AARCH64_ADR_GOT_PAGE: Sets the immediate value of an ADRP to bits 557 // 1FFFFF000 of the operation, checking that -2^32 < Page(G(S))-Page(GOT) < 558 // 2^32. 559 assert((int64_t)Value >= -(1LL << 32) && 560 (int64_t)Value < (1LL << 32) && "Out of range ADRP fixup"); 561 return ADRImmBits((Value & 0x1fffff000ULL) >> 12); 562 563 case AArch64::fixup_a64_ld64_gottprel_lo12_nc: 564 // R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: Set an LD offset field to bits FF8 565 // of X, with no overflow check. Check that X & 7 == 0. 566 case AArch64::fixup_a64_tlsdesc_ld64_lo12_nc: 567 // R_AARCH64_TLSDESC_LD64_LO12_NC: Set an LD offset field to bits FF8 of 568 // G(TLSDESC(S+A)), with no overflow check. Check that X & 7 == 0. 569 case AArch64::fixup_a64_ld64_got_lo12_nc: 570 // R_AARCH64_LD64_GOT_LO12_NC: Sets the LD/ST immediate field to bits FF8 of 571 // G(S) with no overflow check. Check X & 7 == 0 572 assert(((int64_t)Value & 7) == 0 && "Misaligned fixup"); 573 return (Value & 0xff8) << 7; 574 575 case AArch64::fixup_a64_tlsdesc_call: 576 // R_AARCH64_TLSDESC_CALL: For relaxation only. 577 return 0; 578 } 579 } 580 581 MCAsmBackend * 582 llvm::createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, 583 StringRef TT, StringRef CPU) { 584 Triple TheTriple(TT); 585 return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS(), /*isLittle*/ true); 586 } 587 588 MCAsmBackend * 589 llvm::createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, 590 StringRef TT, StringRef CPU) { 591 Triple TheTriple(TT); 592 return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS(), /*isLittle*/ false); 593 } 594