1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "AArch64.h" 11 #include "AArch64RegisterInfo.h" 12 #include "MCTargetDesc/AArch64FixupKinds.h" 13 #include "llvm/ADT/Triple.h" 14 #include "llvm/BinaryFormat/MachO.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCAssembler.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDirectives.h" 19 #include "llvm/MC/MCELFObjectWriter.h" 20 #include "llvm/MC/MCFixupKindInfo.h" 21 #include "llvm/MC/MCObjectWriter.h" 22 #include "llvm/MC/MCSectionELF.h" 23 #include "llvm/MC/MCSectionMachO.h" 24 #include "llvm/MC/MCValue.h" 25 #include "llvm/Support/ErrorHandling.h" 26 using namespace llvm; 27 28 namespace { 29 30 class AArch64AsmBackend : public MCAsmBackend { 31 static const unsigned PCRelFlagVal = 32 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel; 33 public: 34 bool IsLittleEndian; 35 36 public: 37 AArch64AsmBackend(const Target &T, bool IsLittleEndian) 38 : MCAsmBackend(), IsLittleEndian(IsLittleEndian) {} 39 40 unsigned getNumFixupKinds() const override { 41 return AArch64::NumTargetFixupKinds; 42 } 43 44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 45 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = { 46 // This table *must* be in the order that the fixup_* kinds are defined 47 // in AArch64FixupKinds.h. 48 // 49 // Name Offset (bits) Size (bits) Flags 50 {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal}, 51 {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal}, 52 {"fixup_aarch64_add_imm12", 10, 12, 0}, 53 {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0}, 54 {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0}, 55 {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0}, 56 {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0}, 57 {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0}, 58 {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal}, 59 {"fixup_aarch64_movw", 5, 16, 0}, 60 {"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal}, 61 {"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal}, 62 {"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal}, 63 {"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal}, 64 {"fixup_aarch64_tlsdesc_call", 0, 0, 0}}; 65 66 if (Kind < FirstTargetFixupKind) 67 return MCAsmBackend::getFixupKindInfo(Kind); 68 69 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 70 "Invalid kind!"); 71 return Infos[Kind - FirstTargetFixupKind]; 72 } 73 74 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 75 const MCValue &Target, MutableArrayRef<char> Data, 76 uint64_t Value, bool IsPCRel) const override; 77 78 bool mayNeedRelaxation(const MCInst &Inst) const override; 79 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 80 const MCRelaxableFragment *DF, 81 const MCAsmLayout &Layout) const override; 82 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 83 MCInst &Res) const override; 84 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; 85 86 void HandleAssemblerFlag(MCAssemblerFlag Flag) {} 87 88 unsigned getPointerSize() const { return 8; } 89 90 unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const; 91 }; 92 93 } // end anonymous namespace 94 95 /// \brief The number of bytes the fixup may change. 96 static unsigned getFixupKindNumBytes(unsigned Kind) { 97 switch (Kind) { 98 default: 99 llvm_unreachable("Unknown fixup kind!"); 100 101 case AArch64::fixup_aarch64_tlsdesc_call: 102 return 0; 103 104 case FK_Data_1: 105 return 1; 106 107 case FK_Data_2: 108 case AArch64::fixup_aarch64_movw: 109 return 2; 110 111 case AArch64::fixup_aarch64_pcrel_branch14: 112 case AArch64::fixup_aarch64_add_imm12: 113 case AArch64::fixup_aarch64_ldst_imm12_scale1: 114 case AArch64::fixup_aarch64_ldst_imm12_scale2: 115 case AArch64::fixup_aarch64_ldst_imm12_scale4: 116 case AArch64::fixup_aarch64_ldst_imm12_scale8: 117 case AArch64::fixup_aarch64_ldst_imm12_scale16: 118 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 119 case AArch64::fixup_aarch64_pcrel_branch19: 120 return 3; 121 122 case AArch64::fixup_aarch64_pcrel_adr_imm21: 123 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 124 case AArch64::fixup_aarch64_pcrel_branch26: 125 case AArch64::fixup_aarch64_pcrel_call26: 126 case FK_Data_4: 127 return 4; 128 129 case FK_Data_8: 130 return 8; 131 } 132 } 133 134 static unsigned AdrImmBits(unsigned Value) { 135 unsigned lo2 = Value & 0x3; 136 unsigned hi19 = (Value & 0x1ffffc) >> 2; 137 return (hi19 << 5) | (lo2 << 29); 138 } 139 140 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 141 MCContext &Ctx) { 142 unsigned Kind = Fixup.getKind(); 143 int64_t SignedValue = static_cast<int64_t>(Value); 144 switch (Kind) { 145 default: 146 llvm_unreachable("Unknown fixup kind!"); 147 case AArch64::fixup_aarch64_pcrel_adr_imm21: 148 if (SignedValue > 2097151 || SignedValue < -2097152) 149 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 150 return AdrImmBits(Value & 0x1fffffULL); 151 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 152 return AdrImmBits((Value & 0x1fffff000ULL) >> 12); 153 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 154 case AArch64::fixup_aarch64_pcrel_branch19: 155 // Signed 21-bit immediate 156 if (SignedValue > 2097151 || SignedValue < -2097152) 157 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 158 if (Value & 0x3) 159 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 160 // Low two bits are not encoded. 161 return (Value >> 2) & 0x7ffff; 162 case AArch64::fixup_aarch64_add_imm12: 163 case AArch64::fixup_aarch64_ldst_imm12_scale1: 164 // Unsigned 12-bit immediate 165 if (Value >= 0x1000) 166 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 167 return Value; 168 case AArch64::fixup_aarch64_ldst_imm12_scale2: 169 // Unsigned 12-bit immediate which gets multiplied by 2 170 if (Value >= 0x2000) 171 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 172 if (Value & 0x1) 173 Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned"); 174 return Value >> 1; 175 case AArch64::fixup_aarch64_ldst_imm12_scale4: 176 // Unsigned 12-bit immediate which gets multiplied by 4 177 if (Value >= 0x4000) 178 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 179 if (Value & 0x3) 180 Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned"); 181 return Value >> 2; 182 case AArch64::fixup_aarch64_ldst_imm12_scale8: 183 // Unsigned 12-bit immediate which gets multiplied by 8 184 if (Value >= 0x8000) 185 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 186 if (Value & 0x7) 187 Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned"); 188 return Value >> 3; 189 case AArch64::fixup_aarch64_ldst_imm12_scale16: 190 // Unsigned 12-bit immediate which gets multiplied by 16 191 if (Value >= 0x10000) 192 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 193 if (Value & 0xf) 194 Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned"); 195 return Value >> 4; 196 case AArch64::fixup_aarch64_movw: 197 Ctx.reportError(Fixup.getLoc(), 198 "no resolvable MOVZ/MOVK fixups supported yet"); 199 return Value; 200 case AArch64::fixup_aarch64_pcrel_branch14: 201 // Signed 16-bit immediate 202 if (SignedValue > 32767 || SignedValue < -32768) 203 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 204 // Low two bits are not encoded (4-byte alignment assumed). 205 if (Value & 0x3) 206 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 207 return (Value >> 2) & 0x3fff; 208 case AArch64::fixup_aarch64_pcrel_branch26: 209 case AArch64::fixup_aarch64_pcrel_call26: 210 // Signed 28-bit immediate 211 if (SignedValue > 134217727 || SignedValue < -134217728) 212 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 213 // Low two bits are not encoded (4-byte alignment assumed). 214 if (Value & 0x3) 215 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 216 return (Value >> 2) & 0x3ffffff; 217 case FK_Data_1: 218 case FK_Data_2: 219 case FK_Data_4: 220 case FK_Data_8: 221 return Value; 222 } 223 } 224 225 /// getFixupKindContainereSizeInBytes - The number of bytes of the 226 /// container involved in big endian or 0 if the item is little endian 227 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const { 228 if (IsLittleEndian) 229 return 0; 230 231 switch (Kind) { 232 default: 233 llvm_unreachable("Unknown fixup kind!"); 234 235 case FK_Data_1: 236 return 1; 237 case FK_Data_2: 238 return 2; 239 case FK_Data_4: 240 return 4; 241 case FK_Data_8: 242 return 8; 243 244 case AArch64::fixup_aarch64_tlsdesc_call: 245 case AArch64::fixup_aarch64_movw: 246 case AArch64::fixup_aarch64_pcrel_branch14: 247 case AArch64::fixup_aarch64_add_imm12: 248 case AArch64::fixup_aarch64_ldst_imm12_scale1: 249 case AArch64::fixup_aarch64_ldst_imm12_scale2: 250 case AArch64::fixup_aarch64_ldst_imm12_scale4: 251 case AArch64::fixup_aarch64_ldst_imm12_scale8: 252 case AArch64::fixup_aarch64_ldst_imm12_scale16: 253 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 254 case AArch64::fixup_aarch64_pcrel_branch19: 255 case AArch64::fixup_aarch64_pcrel_adr_imm21: 256 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 257 case AArch64::fixup_aarch64_pcrel_branch26: 258 case AArch64::fixup_aarch64_pcrel_call26: 259 // Instructions are always little endian 260 return 0; 261 } 262 } 263 264 void AArch64AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 265 const MCValue &Target, 266 MutableArrayRef<char> Data, uint64_t Value, 267 bool IsPCRel) const { 268 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 269 if (!Value) 270 return; // Doesn't change encoding. 271 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); 272 MCContext &Ctx = Asm.getContext(); 273 // Apply any target-specific value adjustments. 274 Value = adjustFixupValue(Fixup, Value, Ctx); 275 276 // Shift the value into position. 277 Value <<= Info.TargetOffset; 278 279 unsigned Offset = Fixup.getOffset(); 280 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); 281 282 // Used to point to big endian bytes. 283 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind()); 284 285 // For each byte of the fragment that the fixup touches, mask in the 286 // bits from the fixup value. 287 if (FulleSizeInBytes == 0) { 288 // Handle as little-endian 289 for (unsigned i = 0; i != NumBytes; ++i) { 290 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 291 } 292 } else { 293 // Handle as big-endian 294 assert((Offset + FulleSizeInBytes) <= Data.size() && "Invalid fixup size!"); 295 assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!"); 296 for (unsigned i = 0; i != NumBytes; ++i) { 297 unsigned Idx = FulleSizeInBytes - 1 - i; 298 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 299 } 300 } 301 } 302 303 bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 304 return false; 305 } 306 307 bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 308 uint64_t Value, 309 const MCRelaxableFragment *DF, 310 const MCAsmLayout &Layout) const { 311 // FIXME: This isn't correct for AArch64. Just moving the "generic" logic 312 // into the targets for now. 313 // 314 // Relax if the value is too big for a (signed) i8. 315 return int64_t(Value) != int64_t(int8_t(Value)); 316 } 317 318 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst, 319 const MCSubtargetInfo &STI, 320 MCInst &Res) const { 321 llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented"); 322 } 323 324 bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 325 // If the count is not 4-byte aligned, we must be writing data into the text 326 // section (otherwise we have unaligned instructions, and thus have far 327 // bigger problems), so just write zeros instead. 328 OW->WriteZeros(Count % 4); 329 330 // We are properly aligned, so write NOPs as requested. 331 Count /= 4; 332 for (uint64_t i = 0; i != Count; ++i) 333 OW->write32(0xd503201f); 334 return true; 335 } 336 337 namespace { 338 339 namespace CU { 340 341 /// \brief Compact unwind encoding values. 342 enum CompactUnwindEncodings { 343 /// \brief A "frameless" leaf function, where no non-volatile registers are 344 /// saved. The return remains in LR throughout the function. 345 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000, 346 347 /// \brief No compact unwind encoding available. Instead the low 23-bits of 348 /// the compact unwind encoding is the offset of the DWARF FDE in the 349 /// __eh_frame section. This mode is never used in object files. It is only 350 /// generated by the linker in final linked images, which have only DWARF info 351 /// for a function. 352 UNWIND_ARM64_MODE_DWARF = 0x03000000, 353 354 /// \brief This is a standard arm64 prologue where FP/LR are immediately 355 /// pushed on the stack, then SP is copied to FP. If there are any 356 /// non-volatile register saved, they are copied into the stack fame in pairs 357 /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the 358 /// five X pairs and four D pairs can be saved, but the memory layout must be 359 /// in register number order. 360 UNWIND_ARM64_MODE_FRAME = 0x04000000, 361 362 /// \brief Frame register pair encodings. 363 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001, 364 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002, 365 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004, 366 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008, 367 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010, 368 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100, 369 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200, 370 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400, 371 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800 372 }; 373 374 } // end CU namespace 375 376 // FIXME: This should be in a separate file. 377 class DarwinAArch64AsmBackend : public AArch64AsmBackend { 378 const MCRegisterInfo &MRI; 379 380 /// \brief Encode compact unwind stack adjustment for frameless functions. 381 /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h. 382 /// The stack size always needs to be 16 byte aligned. 383 uint32_t encodeStackAdjustment(uint32_t StackSize) const { 384 return (StackSize / 16) << 12; 385 } 386 387 public: 388 DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI) 389 : AArch64AsmBackend(T, /*IsLittleEndian*/true), MRI(MRI) {} 390 391 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 392 return createAArch64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64, 393 MachO::CPU_SUBTYPE_ARM64_ALL); 394 } 395 396 /// \brief Generate the compact unwind encoding from the CFI directives. 397 uint32_t generateCompactUnwindEncoding( 398 ArrayRef<MCCFIInstruction> Instrs) const override { 399 if (Instrs.empty()) 400 return CU::UNWIND_ARM64_MODE_FRAMELESS; 401 402 bool HasFP = false; 403 unsigned StackSize = 0; 404 405 uint32_t CompactUnwindEncoding = 0; 406 for (size_t i = 0, e = Instrs.size(); i != e; ++i) { 407 const MCCFIInstruction &Inst = Instrs[i]; 408 409 switch (Inst.getOperation()) { 410 default: 411 // Cannot handle this directive: bail out. 412 return CU::UNWIND_ARM64_MODE_DWARF; 413 case MCCFIInstruction::OpDefCfa: { 414 // Defines a frame pointer. 415 assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) == 416 AArch64::FP && 417 "Invalid frame pointer!"); 418 assert(i + 2 < e && "Insufficient CFI instructions to define a frame!"); 419 420 const MCCFIInstruction &LRPush = Instrs[++i]; 421 assert(LRPush.getOperation() == MCCFIInstruction::OpOffset && 422 "Link register not pushed!"); 423 const MCCFIInstruction &FPPush = Instrs[++i]; 424 assert(FPPush.getOperation() == MCCFIInstruction::OpOffset && 425 "Frame pointer not pushed!"); 426 427 unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true); 428 unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true); 429 430 LRReg = getXRegFromWReg(LRReg); 431 FPReg = getXRegFromWReg(FPReg); 432 433 assert(LRReg == AArch64::LR && FPReg == AArch64::FP && 434 "Pushing invalid registers for frame!"); 435 436 // Indicate that the function has a frame. 437 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME; 438 HasFP = true; 439 break; 440 } 441 case MCCFIInstruction::OpDefCfaOffset: { 442 assert(StackSize == 0 && "We already have the CFA offset!"); 443 StackSize = std::abs(Inst.getOffset()); 444 break; 445 } 446 case MCCFIInstruction::OpOffset: { 447 // Registers are saved in pairs. We expect there to be two consecutive 448 // `.cfi_offset' instructions with the appropriate registers specified. 449 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); 450 if (i + 1 == e) 451 return CU::UNWIND_ARM64_MODE_DWARF; 452 453 const MCCFIInstruction &Inst2 = Instrs[++i]; 454 if (Inst2.getOperation() != MCCFIInstruction::OpOffset) 455 return CU::UNWIND_ARM64_MODE_DWARF; 456 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); 457 458 // N.B. The encodings must be in register number order, and the X 459 // registers before the D registers. 460 461 // X19/X20 pair = 0x00000001, 462 // X21/X22 pair = 0x00000002, 463 // X23/X24 pair = 0x00000004, 464 // X25/X26 pair = 0x00000008, 465 // X27/X28 pair = 0x00000010 466 Reg1 = getXRegFromWReg(Reg1); 467 Reg2 = getXRegFromWReg(Reg2); 468 469 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && 470 (CompactUnwindEncoding & 0xF1E) == 0) 471 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR; 472 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && 473 (CompactUnwindEncoding & 0xF1C) == 0) 474 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR; 475 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && 476 (CompactUnwindEncoding & 0xF18) == 0) 477 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR; 478 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && 479 (CompactUnwindEncoding & 0xF10) == 0) 480 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR; 481 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && 482 (CompactUnwindEncoding & 0xF00) == 0) 483 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR; 484 else { 485 Reg1 = getDRegFromBReg(Reg1); 486 Reg2 = getDRegFromBReg(Reg2); 487 488 // D8/D9 pair = 0x00000100, 489 // D10/D11 pair = 0x00000200, 490 // D12/D13 pair = 0x00000400, 491 // D14/D15 pair = 0x00000800 492 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && 493 (CompactUnwindEncoding & 0xE00) == 0) 494 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR; 495 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && 496 (CompactUnwindEncoding & 0xC00) == 0) 497 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR; 498 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 && 499 (CompactUnwindEncoding & 0x800) == 0) 500 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR; 501 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15) 502 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR; 503 else 504 // A pair was pushed which we cannot handle. 505 return CU::UNWIND_ARM64_MODE_DWARF; 506 } 507 508 break; 509 } 510 } 511 } 512 513 if (!HasFP) { 514 // With compact unwind info we can only represent stack adjustments of up 515 // to 65520 bytes. 516 if (StackSize > 65520) 517 return CU::UNWIND_ARM64_MODE_DWARF; 518 519 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS; 520 CompactUnwindEncoding |= encodeStackAdjustment(StackSize); 521 } 522 523 return CompactUnwindEncoding; 524 } 525 }; 526 527 } // end anonymous namespace 528 529 namespace { 530 531 class ELFAArch64AsmBackend : public AArch64AsmBackend { 532 public: 533 uint8_t OSABI; 534 bool IsILP32; 535 536 ELFAArch64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian, 537 bool IsILP32) 538 : AArch64AsmBackend(T, IsLittleEndian), OSABI(OSABI), IsILP32(IsILP32) {} 539 540 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 541 return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian, IsILP32); 542 } 543 544 void processFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, 545 const MCValue &Target, bool &IsResolved) override; 546 }; 547 548 void ELFAArch64AsmBackend::processFixupValue(const MCAssembler &Asm, 549 const MCFixup &Fixup, 550 const MCValue &Target, 551 bool &IsResolved) { 552 // The ADRP instruction adds some multiple of 0x1000 to the current PC & 553 // ~0xfff. This means that the required offset to reach a symbol can vary by 554 // up to one step depending on where the ADRP is in memory. For example: 555 // 556 // ADRP x0, there 557 // there: 558 // 559 // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and 560 // we'll need that as an offset. At any other address "there" will be in the 561 // same page as the ADRP and the instruction should encode 0x0. Assuming the 562 // section isn't 0x1000-aligned, we therefore need to delegate this decision 563 // to the linker -- a relocation! 564 if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21) 565 IsResolved = false; 566 } 567 568 } 569 570 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, 571 const MCRegisterInfo &MRI, 572 const Triple &TheTriple, 573 StringRef CPU, 574 const MCTargetOptions &Options) { 575 if (TheTriple.isOSBinFormatMachO()) 576 return new DarwinAArch64AsmBackend(T, MRI); 577 578 assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target"); 579 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 580 bool IsILP32 = Options.getABIName() == "ilp32"; 581 return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true, IsILP32); 582 } 583 584 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, 585 const MCRegisterInfo &MRI, 586 const Triple &TheTriple, 587 StringRef CPU, 588 const MCTargetOptions &Options) { 589 assert(TheTriple.isOSBinFormatELF() && 590 "Big endian is only supported for ELF targets!"); 591 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 592 bool IsILP32 = Options.getABIName() == "ilp32"; 593 return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/false, IsILP32); 594 } 595