1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the functions necessary to decode AArch64 instruction 11 // bitpatterns into MCInsts (with the help of TableGenerated information from 12 // the instruction definitions). 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "AArch64.h" 17 #include "AArch64RegisterInfo.h" 18 #include "AArch64Subtarget.h" 19 #include "Utils/AArch64BaseInfo.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/MC/MCExpr.h" 23 #include "llvm/MC/MCFixedLenDisassembler.h" 24 #include "llvm/MC/MCInst.h" 25 #include "llvm/MC/MCInstrDesc.h" 26 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/MemoryObject.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 typedef MCDisassembler::DecodeStatus DecodeStatus; 37 38 namespace { 39 /// AArch64 disassembler for all AArch64 platforms. 40 class AArch64Disassembler : public MCDisassembler { 41 public: 42 /// Initializes the disassembler. 43 /// 44 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 45 : MCDisassembler(STI, Ctx) { 46 } 47 48 ~AArch64Disassembler() {} 49 50 /// See MCDisassembler. 51 DecodeStatus getInstruction(MCInst &instr, 52 uint64_t &size, 53 const MemoryObject ®ion, 54 uint64_t address, 55 raw_ostream &vStream, 56 raw_ostream &cStream) const override; 57 }; 58 59 } 60 61 // Forward-declarations used in the auto-generated files. 62 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 63 uint64_t Address, const void *Decoder); 64 static DecodeStatus 65 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 66 uint64_t Address, const void *Decoder); 67 68 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 uint64_t Address, const void *Decoder); 70 static DecodeStatus 71 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 uint64_t Address, const void *Decoder); 73 74 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 uint64_t Address, const void *Decoder); 76 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 77 uint64_t Address, const void *Decoder); 78 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 79 uint64_t Address, const void *Decoder); 80 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 81 uint64_t Address, const void *Decoder); 82 static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 83 uint64_t Address, const void *Decoder); 84 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 85 unsigned RegNo, uint64_t Address, 86 const void *Decoder); 87 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, 88 unsigned RegNo, uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const void *Decoder); 99 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 103 unsigned RegNo, uint64_t Address, 104 const void *Decoder); 105 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114 115 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 116 unsigned OptionHiS, 117 uint64_t Address, 118 const void *Decoder); 119 120 121 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 122 unsigned Imm6Bits, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 127 unsigned Imm6Bits, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 132 unsigned RmBits, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 139 uint64_t Address, 140 const void *Decoder); 141 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 142 uint64_t Address, 143 const void *Decoder); 144 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 145 uint64_t Address, 146 const void *Decoder); 147 148 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, 151 uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, 154 uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, 157 uint64_t Address, 158 const void *Decoder); 159 160 template<int RegWidth> 161 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 162 unsigned FullImm, 163 uint64_t Address, 164 const void *Decoder); 165 166 template<int RegWidth> 167 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 168 unsigned Bits, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 173 unsigned ShiftAmount, 174 uint64_t Address, 175 const void *Decoder); 176 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 177 static DecodeStatus 178 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 179 uint64_t Address, const void *Decoder); 180 181 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 182 unsigned ShiftAmount, 183 uint64_t Address, 184 const void *Decoder); 185 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 186 uint64_t Address, 187 const void *Decoder); 188 189 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 190 uint64_t Address, 191 const void *Decoder); 192 193 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 194 unsigned Insn, 195 uint64_t Address, 196 const void *Decoder); 197 198 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 199 unsigned Val, 200 uint64_t Address, 201 const void *Decoder); 202 203 template<typename SomeNamedImmMapper> 204 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 205 unsigned Val, 206 uint64_t Address, 207 const void *Decoder); 208 209 static DecodeStatus 210 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper, 211 llvm::MCInst &Inst, unsigned Val, 212 uint64_t Address, const void *Decoder); 213 214 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 215 unsigned Val, 216 uint64_t Address, 217 const void *Decoder); 218 219 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 220 unsigned Val, 221 uint64_t Address, 222 const void *Decoder); 223 224 225 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 226 unsigned Val, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Val, 231 uint64_t Address, 232 const void *Decoder); 233 234 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, 235 uint64_t Address, 236 const void *Decoder); 237 238 static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, 240 const void *Decoder); 241 242 static bool Check(DecodeStatus &Out, DecodeStatus In); 243 244 #include "AArch64GenDisassemblerTables.inc" 245 246 static bool Check(DecodeStatus &Out, DecodeStatus In) { 247 switch (In) { 248 case MCDisassembler::Success: 249 // Out stays the same. 250 return true; 251 case MCDisassembler::SoftFail: 252 Out = In; 253 return true; 254 case MCDisassembler::Fail: 255 Out = In; 256 return false; 257 } 258 llvm_unreachable("Invalid DecodeStatus!"); 259 } 260 261 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 262 const MemoryObject &Region, 263 uint64_t Address, 264 raw_ostream &os, 265 raw_ostream &cs) const { 266 CommentStream = &cs; 267 268 uint8_t bytes[4]; 269 270 // We want to read exactly 4 bytes of data. 271 if (Region.readBytes(Address, 4, bytes) == -1) { 272 Size = 0; 273 return MCDisassembler::Fail; 274 } 275 276 // Encoded as a small-endian 32-bit word in the stream. 277 uint32_t insn = (bytes[3] << 24) | 278 (bytes[2] << 16) | 279 (bytes[1] << 8) | 280 (bytes[0] << 0); 281 282 // Calling the auto-generated decoder function. 283 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, 284 this, STI); 285 if (result != MCDisassembler::Fail) { 286 Size = 4; 287 return result; 288 } 289 290 MI.clear(); 291 Size = 0; 292 return MCDisassembler::Fail; 293 } 294 295 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 296 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D); 297 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 298 return RegInfo->getRegClass(RC).getRegister(RegNo); 299 } 300 301 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 302 uint64_t Address, const void *Decoder) { 303 if (RegNo > 31) 304 return MCDisassembler::Fail; 305 306 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo); 307 Inst.addOperand(MCOperand::CreateReg(Register)); 308 return MCDisassembler::Success; 309 } 310 311 static DecodeStatus 312 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 313 uint64_t Address, const void *Decoder) { 314 if (RegNo > 31) 315 return MCDisassembler::Fail; 316 317 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo); 318 Inst.addOperand(MCOperand::CreateReg(Register)); 319 return MCDisassembler::Success; 320 } 321 322 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 323 uint64_t Address, 324 const void *Decoder) { 325 if (RegNo > 31) 326 return MCDisassembler::Fail; 327 328 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo); 329 Inst.addOperand(MCOperand::CreateReg(Register)); 330 return MCDisassembler::Success; 331 } 332 333 static DecodeStatus 334 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 335 uint64_t Address, const void *Decoder) { 336 if (RegNo > 31) 337 return MCDisassembler::Fail; 338 339 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo); 340 Inst.addOperand(MCOperand::CreateReg(Register)); 341 return MCDisassembler::Success; 342 } 343 344 static DecodeStatus 345 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 346 uint64_t Address, const void *Decoder) { 347 if (RegNo > 31) 348 return MCDisassembler::Fail; 349 350 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo); 351 Inst.addOperand(MCOperand::CreateReg(Register)); 352 return MCDisassembler::Success; 353 } 354 355 static DecodeStatus 356 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 357 uint64_t Address, const void *Decoder) { 358 if (RegNo > 31) 359 return MCDisassembler::Fail; 360 361 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo); 362 Inst.addOperand(MCOperand::CreateReg(Register)); 363 return MCDisassembler::Success; 364 } 365 366 367 static DecodeStatus 368 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 369 uint64_t Address, const void *Decoder) { 370 if (RegNo > 31) 371 return MCDisassembler::Fail; 372 373 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo); 374 Inst.addOperand(MCOperand::CreateReg(Register)); 375 return MCDisassembler::Success; 376 } 377 378 static DecodeStatus 379 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 380 uint64_t Address, const void *Decoder) { 381 if (RegNo > 31) 382 return MCDisassembler::Fail; 383 384 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo); 385 Inst.addOperand(MCOperand::CreateReg(Register)); 386 return MCDisassembler::Success; 387 } 388 389 static DecodeStatus 390 DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 391 uint64_t Address, const void *Decoder) { 392 if (RegNo > 15) 393 return MCDisassembler::Fail; 394 395 return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder); 396 } 397 398 static DecodeStatus 399 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 400 uint64_t Address, const void *Decoder) { 401 if (RegNo > 31) 402 return MCDisassembler::Fail; 403 404 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo); 405 Inst.addOperand(MCOperand::CreateReg(Register)); 406 return MCDisassembler::Success; 407 } 408 409 static DecodeStatus 410 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 411 uint64_t Address, const void *Decoder) { 412 if (RegNo > 15) 413 return MCDisassembler::Fail; 414 415 return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder); 416 } 417 418 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, 419 unsigned RegNo, 420 uint64_t Address, 421 const void *Decoder) { 422 if (RegNo > 30) 423 return MCDisassembler::Fail; 424 425 uint16_t Register = getReg(Decoder, AArch64::GPR64noxzrRegClassID, RegNo); 426 Inst.addOperand(MCOperand::CreateReg(Register)); 427 return MCDisassembler::Success; 428 } 429 430 static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo, 431 unsigned RegID, 432 const void *Decoder) { 433 if (RegNo > 31) 434 return MCDisassembler::Fail; 435 436 uint16_t Register = getReg(Decoder, RegID, RegNo); 437 Inst.addOperand(MCOperand::CreateReg(Register)); 438 return MCDisassembler::Success; 439 } 440 441 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 442 uint64_t Address, 443 const void *Decoder) { 444 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID, 445 Decoder); 446 } 447 448 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 449 uint64_t Address, 450 const void *Decoder) { 451 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID, 452 Decoder); 453 } 454 455 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 456 unsigned RegNo, uint64_t Address, 457 const void *Decoder) { 458 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID, 459 Decoder); 460 } 461 462 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 463 unsigned RegNo, uint64_t Address, 464 const void *Decoder) { 465 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID, 466 Decoder); 467 } 468 469 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 470 uint64_t Address, 471 const void *Decoder) { 472 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID, 473 Decoder); 474 } 475 476 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 477 uint64_t Address, 478 const void *Decoder) { 479 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID, 480 Decoder); 481 } 482 483 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 484 unsigned OptionHiS, 485 uint64_t Address, 486 const void *Decoder) { 487 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1}, 488 // S}. Hence we want to check bit 1. 489 if (!(OptionHiS & 2)) 490 return MCDisassembler::Fail; 491 492 Inst.addOperand(MCOperand::CreateImm(OptionHiS)); 493 return MCDisassembler::Success; 494 } 495 496 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 497 unsigned Imm6Bits, 498 uint64_t Address, 499 const void *Decoder) { 500 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be 501 // between 0 and 31. 502 if (Imm6Bits > 31) 503 return MCDisassembler::Fail; 504 505 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 506 return MCDisassembler::Success; 507 } 508 509 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 510 unsigned Imm6Bits, 511 uint64_t Address, 512 const void *Decoder) { 513 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32. 514 if (Imm6Bits < 32) 515 return MCDisassembler::Fail; 516 517 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 518 return MCDisassembler::Success; 519 } 520 521 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 522 unsigned RmBits, 523 uint64_t Address, 524 const void *Decoder) { 525 // Any bits are valid in the instruction (they're architecturally ignored), 526 // but a code generator should insert 0. 527 Inst.addOperand(MCOperand::CreateImm(0)); 528 return MCDisassembler::Success; 529 } 530 531 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 532 uint64_t Address, 533 const void *Decoder) { 534 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 535 return MCDisassembler::Success; 536 } 537 538 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 539 uint64_t Address, 540 const void *Decoder) { 541 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 542 return MCDisassembler::Success; 543 } 544 545 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 546 uint64_t Address, 547 const void *Decoder) { 548 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 549 return MCDisassembler::Success; 550 } 551 552 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 553 uint64_t Address, 554 const void *Decoder) { 555 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 556 return MCDisassembler::Success; 557 } 558 559 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, 560 uint64_t Address, 561 const void *Decoder) { 562 if (Val > 7) 563 return MCDisassembler::Fail; 564 565 Inst.addOperand(MCOperand::CreateImm(Val)); 566 return MCDisassembler::Success; 567 } 568 569 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, 570 uint64_t Address, 571 const void *Decoder) { 572 if (Val > 15) 573 return MCDisassembler::Fail; 574 575 Inst.addOperand(MCOperand::CreateImm(Val)); 576 return MCDisassembler::Success; 577 } 578 579 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, 580 uint64_t Address, 581 const void *Decoder) { 582 if (Val > 31) 583 return MCDisassembler::Fail; 584 585 Inst.addOperand(MCOperand::CreateImm(Val)); 586 return MCDisassembler::Success; 587 } 588 589 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, 590 uint64_t Address, 591 const void *Decoder) { 592 if (Val > 63) 593 return MCDisassembler::Fail; 594 595 Inst.addOperand(MCOperand::CreateImm(Val)); 596 return MCDisassembler::Success; 597 } 598 599 template<int RegWidth> 600 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 601 unsigned FullImm, 602 uint64_t Address, 603 const void *Decoder) { 604 unsigned Imm16 = FullImm & 0xffff; 605 unsigned Shift = FullImm >> 16; 606 607 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail; 608 609 Inst.addOperand(MCOperand::CreateImm(Imm16)); 610 Inst.addOperand(MCOperand::CreateImm(Shift)); 611 return MCDisassembler::Success; 612 } 613 614 template<int RegWidth> 615 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 616 unsigned Bits, 617 uint64_t Address, 618 const void *Decoder) { 619 uint64_t Imm; 620 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm)) 621 return MCDisassembler::Fail; 622 623 Inst.addOperand(MCOperand::CreateImm(Bits)); 624 return MCDisassembler::Success; 625 } 626 627 628 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 629 unsigned ShiftAmount, 630 uint64_t Address, 631 const void *Decoder) { 632 // Only values 0-4 are valid for this 3-bit field 633 if (ShiftAmount > 4) 634 return MCDisassembler::Fail; 635 636 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 637 return MCDisassembler::Success; 638 } 639 640 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 641 unsigned ShiftAmount, 642 uint64_t Address, 643 const void *Decoder) { 644 // Only values below 32 are valid for a 32-bit register 645 if (ShiftAmount > 31) 646 return MCDisassembler::Fail; 647 648 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 649 return MCDisassembler::Success; 650 } 651 652 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 653 uint64_t Address, 654 const void *Decoder) { 655 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 656 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 657 unsigned ImmS = fieldFromInstruction(Insn, 10, 6); 658 unsigned ImmR = fieldFromInstruction(Insn, 16, 6); 659 unsigned SF = fieldFromInstruction(Insn, 31, 1); 660 661 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise 662 // out assertions that it thinks should never be hit. 663 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; 664 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); 665 666 if (!SF) { 667 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions. 668 if (ImmR > 31 || ImmS > 31) 669 return MCDisassembler::Fail; 670 } 671 672 if (SF) { 673 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 674 // BFM MCInsts use Rd as a source too. 675 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 676 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 677 } else { 678 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 679 // BFM MCInsts use Rd as a source too. 680 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 681 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder); 682 } 683 684 // ASR and LSR have more specific patterns so they won't get here: 685 assert(!(ImmS == 31 && !SF && Opc != BFM) 686 && "shift should have used auto decode"); 687 assert(!(ImmS == 63 && SF && Opc != BFM) 688 && "shift should have used auto decode"); 689 690 // Extension instructions similarly: 691 if (Opc == SBFM && ImmR == 0) { 692 assert((ImmS != 7 && ImmS != 15) && "extension got here"); 693 assert((ImmS != 31 || SF == 0) && "extension got here"); 694 } else if (Opc == UBFM && ImmR == 0) { 695 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here"); 696 } 697 698 if (Opc == UBFM) { 699 // It might be a LSL instruction, which actually takes the shift amount 700 // itself as an MCInst operand. 701 if (SF && (ImmS + 1) % 64 == ImmR) { 702 Inst.setOpcode(AArch64::LSLxxi); 703 Inst.addOperand(MCOperand::CreateImm(63 - ImmS)); 704 return MCDisassembler::Success; 705 } else if (!SF && (ImmS + 1) % 32 == ImmR) { 706 Inst.setOpcode(AArch64::LSLwwi); 707 Inst.addOperand(MCOperand::CreateImm(31 - ImmS)); 708 return MCDisassembler::Success; 709 } 710 } 711 712 // Otherwise it's definitely either an extract or an insert depending on which 713 // of ImmR or ImmS is larger. 714 unsigned ExtractOp, InsertOp; 715 switch (Opc) { 716 default: llvm_unreachable("unexpected instruction trying to decode bitfield"); 717 case SBFM: 718 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii; 719 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii; 720 break; 721 case BFM: 722 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii; 723 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii; 724 break; 725 case UBFM: 726 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii; 727 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii; 728 break; 729 } 730 731 // Otherwise it's a boring insert or extract 732 Inst.addOperand(MCOperand::CreateImm(ImmR)); 733 Inst.addOperand(MCOperand::CreateImm(ImmS)); 734 735 736 if (ImmS < ImmR) 737 Inst.setOpcode(InsertOp); 738 else 739 Inst.setOpcode(ExtractOp); 740 741 return MCDisassembler::Success; 742 } 743 744 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 745 uint64_t Address, 746 const void *Decoder) { 747 // This decoder exists to add the dummy Lane operand to the MCInst, which must 748 // be 1 in assembly but has no other real manifestation. 749 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 750 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 751 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 752 753 if (IsToVec) { 754 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 755 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 756 } else { 757 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 758 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 759 } 760 761 // Add the lane 762 Inst.addOperand(MCOperand::CreateImm(1)); 763 764 return MCDisassembler::Success; 765 } 766 767 768 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 769 unsigned Insn, 770 uint64_t Address, 771 const void *Decoder) { 772 DecodeStatus Result = MCDisassembler::Success; 773 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 774 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 775 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5); 776 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7); 777 unsigned L = fieldFromInstruction(Insn, 22, 1); 778 unsigned V = fieldFromInstruction(Insn, 26, 1); 779 unsigned Opc = fieldFromInstruction(Insn, 30, 2); 780 781 // Not an official name, but it turns out that bit 23 distinguishes indexed 782 // from non-indexed operations. 783 unsigned Indexed = fieldFromInstruction(Insn, 23, 1); 784 785 if (Indexed && L == 0) { 786 // The MCInst for an indexed store has an out operand and 4 ins: 787 // Rn_wb, Rt, Rt2, Rn, Imm 788 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 789 } 790 791 // You shouldn't load to the same register twice in an instruction... 792 if (L && Rt == Rt2) 793 Result = MCDisassembler::SoftFail; 794 795 // ... or do any operation that writes-back to a transfer register. But note 796 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 797 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 798 Result = MCDisassembler::SoftFail; 799 800 // Exactly how we decode the MCInst's registers depends on the Opc and V 801 // fields of the instruction. These also obviously determine the size of the 802 // operation so we can fill in that information while we're at it. 803 if (V) { 804 // The instruction operates on the FP/SIMD registers 805 switch (Opc) { 806 default: return MCDisassembler::Fail; 807 case 0: 808 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 809 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder); 810 break; 811 case 1: 812 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 813 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder); 814 break; 815 case 2: 816 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 817 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder); 818 break; 819 } 820 } else { 821 switch (Opc) { 822 default: return MCDisassembler::Fail; 823 case 0: 824 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 825 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder); 826 break; 827 case 1: 828 assert(L && "unexpected \"store signed\" attempt"); 829 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 830 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 831 break; 832 case 2: 833 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 834 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 835 break; 836 } 837 } 838 839 if (Indexed && L == 1) { 840 // The MCInst for an indexed load has 3 out operands and an 3 ins: 841 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm 842 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 843 } 844 845 846 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 847 Inst.addOperand(MCOperand::CreateImm(SImm7)); 848 849 return Result; 850 } 851 852 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 853 uint32_t Val, 854 uint64_t Address, 855 const void *Decoder) { 856 unsigned Rt = fieldFromInstruction(Val, 0, 5); 857 unsigned Rn = fieldFromInstruction(Val, 5, 5); 858 unsigned Rt2 = fieldFromInstruction(Val, 10, 5); 859 unsigned MemSize = fieldFromInstruction(Val, 30, 2); 860 861 DecodeStatus S = MCDisassembler::Success; 862 if (Rt == Rt2) S = MCDisassembler::SoftFail; 863 864 switch (MemSize) { 865 case 2: 866 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder))) 867 return MCDisassembler::Fail; 868 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder))) 869 return MCDisassembler::Fail; 870 break; 871 case 3: 872 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder))) 873 return MCDisassembler::Fail; 874 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder))) 875 return MCDisassembler::Fail; 876 break; 877 default: 878 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction"); 879 } 880 881 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder))) 882 return MCDisassembler::Fail; 883 884 return S; 885 } 886 887 template<typename SomeNamedImmMapper> 888 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 889 unsigned Val, 890 uint64_t Address, 891 const void *Decoder) { 892 SomeNamedImmMapper Mapper; 893 bool ValidNamed; 894 Mapper.toString(Val, ValidNamed); 895 if (ValidNamed || Mapper.validImm(Val)) { 896 Inst.addOperand(MCOperand::CreateImm(Val)); 897 return MCDisassembler::Success; 898 } 899 900 return MCDisassembler::Fail; 901 } 902 903 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, 904 llvm::MCInst &Inst, 905 unsigned Val, 906 uint64_t Address, 907 const void *Decoder) { 908 bool ValidNamed; 909 Mapper.toString(Val, ValidNamed); 910 911 Inst.addOperand(MCOperand::CreateImm(Val)); 912 913 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail; 914 } 915 916 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 917 unsigned Val, 918 uint64_t Address, 919 const void *Decoder) { 920 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address, 921 Decoder); 922 } 923 924 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 925 unsigned Val, 926 uint64_t Address, 927 const void *Decoder) { 928 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address, 929 Decoder); 930 } 931 932 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 933 unsigned Insn, 934 uint64_t Address, 935 const void *Decoder) { 936 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 937 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 938 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9); 939 940 unsigned Opc = fieldFromInstruction(Insn, 22, 2); 941 unsigned V = fieldFromInstruction(Insn, 26, 1); 942 unsigned Size = fieldFromInstruction(Insn, 30, 2); 943 944 if (Opc == 0 || (V == 1 && Opc == 2)) { 945 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm 946 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 947 } 948 949 if (V == 0 && (Opc == 2 || Size == 3)) { 950 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 951 } else if (V == 0) { 952 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 953 } else if (V == 1 && (Opc & 2)) { 954 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 955 } else { 956 switch (Size) { 957 case 0: 958 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder); 959 break; 960 case 1: 961 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder); 962 break; 963 case 2: 964 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 965 break; 966 case 3: 967 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 968 break; 969 } 970 } 971 972 if (Opc != 0 && (V != 1 || Opc != 2)) { 973 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm 974 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 975 } 976 977 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 978 979 Inst.addOperand(MCOperand::CreateImm(Imm9)); 980 981 // N.b. The official documentation says undpredictable if Rt == Rn, but this 982 // takes place at the architectural rather than encoding level: 983 // 984 // "STR xzr, [sp], #4" is perfectly valid. 985 if (V == 0 && Rt == Rn && Rn != 31) 986 return MCDisassembler::SoftFail; 987 else 988 return MCDisassembler::Success; 989 } 990 991 static MCDisassembler *createAArch64Disassembler(const Target &T, 992 const MCSubtargetInfo &STI, 993 MCContext &Ctx) { 994 return new AArch64Disassembler(STI, Ctx); 995 } 996 997 extern "C" void LLVMInitializeAArch64Disassembler() { 998 TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget, 999 createAArch64Disassembler); 1000 TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget, 1001 createAArch64Disassembler); 1002 } 1003 1004 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 1005 static DecodeStatus 1006 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 1007 uint64_t Address, const void *Decoder) { 1008 bool IsLSL = false; 1009 if (Ext == A64SE::LSL) 1010 IsLSL = true; 1011 else if (Ext != A64SE::MSL) 1012 return MCDisassembler::Fail; 1013 1014 // MSL and LSLH accepts encoded shift amount 0 or 1. 1015 if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1) 1016 return MCDisassembler::Fail; 1017 1018 // LSL accepts encoded shift amount 0, 1, 2 or 3. 1019 if (IsLSL && ShiftAmount > 3) 1020 return MCDisassembler::Fail; 1021 1022 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 1023 return MCDisassembler::Success; 1024 } 1025 1026 // Decode post-index vector load/store instructions. 1027 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1028 // operand is an immediate equal the the length of vector list in bytes, 1029 // or Rm is decoded to a GPR64noxzr register. 1030 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn, 1031 uint64_t Address, 1032 const void *Decoder) { 1033 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 1034 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1035 unsigned Rm = fieldFromInstruction(Insn, 16, 5); 1036 unsigned Opcode = fieldFromInstruction(Insn, 12, 4); 1037 unsigned IsLoad = fieldFromInstruction(Insn, 22, 1); 1038 // 0 for 64bit vector list, 1 for 128bit vector list 1039 unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1); 1040 1041 unsigned NumVecs; 1042 switch (Opcode) { 1043 case 0: // ld4/st4 1044 case 2: // ld1/st1 with 4 vectors 1045 NumVecs = 4; break; 1046 case 4: // ld3/st3 1047 case 6: // ld1/st1 with 3 vectors 1048 NumVecs = 3; break; 1049 case 7: // ld1/st1 with 1 vector 1050 NumVecs = 1; break; 1051 case 8: // ld2/st2 1052 case 10: // ld1/st1 with 2 vectors 1053 NumVecs = 2; break; 1054 default: 1055 llvm_unreachable("Invalid opcode for post-index load/store instructions"); 1056 } 1057 1058 // Decode vector list of 1/2/3/4 vectors for load instructions. 1059 if (IsLoad) { 1060 switch (NumVecs) { 1061 case 1: 1062 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder) 1063 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 1064 break; 1065 case 2: 1066 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder) 1067 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder); 1068 break; 1069 case 3: 1070 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder) 1071 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder); 1072 break; 1073 case 4: 1074 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder) 1075 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder); 1076 break; 1077 } 1078 } 1079 1080 // Decode write back register, which is equal to Rn. 1081 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1082 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1083 1084 if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte 1085 Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8))); 1086 else // Decode Rm 1087 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1088 1089 // Decode vector list of 1/2/3/4 vectors for load instructions. 1090 if (!IsLoad) { 1091 switch (NumVecs) { 1092 case 1: 1093 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder) 1094 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 1095 break; 1096 case 2: 1097 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder) 1098 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder); 1099 break; 1100 case 3: 1101 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder) 1102 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder); 1103 break; 1104 case 4: 1105 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder) 1106 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder); 1107 break; 1108 } 1109 } 1110 1111 return MCDisassembler::Success; 1112 } 1113 1114 // Decode post-index vector load/store lane instructions. 1115 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1116 // operand is an immediate equal the the length of the changed bytes, 1117 // or Rm is decoded to a GPR64noxzr register. 1118 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, 1119 uint64_t Address, 1120 const void *Decoder) { 1121 bool Is64bitVec = false; 1122 bool IsLoadDup = false; 1123 bool IsLoad = false; 1124 // The total number of bytes transferred. 1125 // TransferBytes = NumVecs * OneLaneBytes 1126 unsigned TransferBytes = 0; 1127 unsigned NumVecs = 0; 1128 unsigned Opc = Inst.getOpcode(); 1129 switch (Opc) { 1130 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register: 1131 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register: 1132 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register: 1133 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: { 1134 switch (Opc) { 1135 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register: 1136 TransferBytes = 1; break; 1137 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register: 1138 TransferBytes = 2; break; 1139 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register: 1140 TransferBytes = 4; break; 1141 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: 1142 TransferBytes = 8; break; 1143 } 1144 Is64bitVec = true; 1145 IsLoadDup = true; 1146 NumVecs = 1; 1147 break; 1148 } 1149 1150 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register: 1151 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register: 1152 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register: 1153 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: { 1154 switch (Opc) { 1155 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register: 1156 TransferBytes = 1; break; 1157 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register: 1158 TransferBytes = 2; break; 1159 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register: 1160 TransferBytes = 4; break; 1161 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: 1162 TransferBytes = 8; break; 1163 } 1164 IsLoadDup = true; 1165 NumVecs = 1; 1166 break; 1167 } 1168 1169 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register: 1170 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register: 1171 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register: 1172 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: { 1173 switch (Opc) { 1174 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register: 1175 TransferBytes = 2; break; 1176 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register: 1177 TransferBytes = 4; break; 1178 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register: 1179 TransferBytes = 8; break; 1180 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: 1181 TransferBytes = 16; break; 1182 } 1183 Is64bitVec = true; 1184 IsLoadDup = true; 1185 NumVecs = 2; 1186 break; 1187 } 1188 1189 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register: 1190 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register: 1191 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register: 1192 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: { 1193 switch (Opc) { 1194 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register: 1195 TransferBytes = 2; break; 1196 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register: 1197 TransferBytes = 4; break; 1198 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register: 1199 TransferBytes = 8; break; 1200 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: 1201 TransferBytes = 16; break; 1202 } 1203 IsLoadDup = true; 1204 NumVecs = 2; 1205 break; 1206 } 1207 1208 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register: 1209 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register: 1210 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register: 1211 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: { 1212 switch (Opc) { 1213 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register: 1214 TransferBytes = 3; break; 1215 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register: 1216 TransferBytes = 6; break; 1217 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register: 1218 TransferBytes = 12; break; 1219 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: 1220 TransferBytes = 24; break; 1221 } 1222 Is64bitVec = true; 1223 IsLoadDup = true; 1224 NumVecs = 3; 1225 break; 1226 } 1227 1228 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register: 1229 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_8H_register: 1230 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_4S_register: 1231 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: { 1232 switch (Opc) { 1233 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register: 1234 TransferBytes = 3; break; 1235 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_8H_register: 1236 TransferBytes = 6; break; 1237 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_4S_register: 1238 TransferBytes = 12; break; 1239 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: 1240 TransferBytes = 24; break; 1241 } 1242 IsLoadDup = true; 1243 NumVecs = 3; 1244 break; 1245 } 1246 1247 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register: 1248 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register: 1249 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register: 1250 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: { 1251 switch (Opc) { 1252 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register: 1253 TransferBytes = 4; break; 1254 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register: 1255 TransferBytes = 8; break; 1256 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register: 1257 TransferBytes = 16; break; 1258 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: 1259 TransferBytes = 32; break; 1260 } 1261 Is64bitVec = true; 1262 IsLoadDup = true; 1263 NumVecs = 4; 1264 break; 1265 } 1266 1267 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register: 1268 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_8H_register: 1269 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_4S_register: 1270 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: { 1271 switch (Opc) { 1272 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register: 1273 TransferBytes = 4; break; 1274 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_8H_register: 1275 TransferBytes = 8; break; 1276 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_4S_register: 1277 TransferBytes = 16; break; 1278 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: 1279 TransferBytes = 32; break; 1280 } 1281 IsLoadDup = true; 1282 NumVecs = 4; 1283 break; 1284 } 1285 1286 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register: 1287 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register: 1288 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register: 1289 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: { 1290 switch (Opc) { 1291 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register: 1292 TransferBytes = 1; break; 1293 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register: 1294 TransferBytes = 2; break; 1295 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register: 1296 TransferBytes = 4; break; 1297 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: 1298 TransferBytes = 8; break; 1299 } 1300 IsLoad = true; 1301 NumVecs = 1; 1302 break; 1303 } 1304 1305 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register: 1306 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register: 1307 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register: 1308 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: { 1309 switch (Opc) { 1310 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register: 1311 TransferBytes = 2; break; 1312 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register: 1313 TransferBytes = 4; break; 1314 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register: 1315 TransferBytes = 8; break; 1316 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: 1317 TransferBytes = 16; break; 1318 } 1319 IsLoad = true; 1320 NumVecs = 2; 1321 break; 1322 } 1323 1324 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register: 1325 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register: 1326 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register: 1327 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: { 1328 switch (Opc) { 1329 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register: 1330 TransferBytes = 3; break; 1331 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register: 1332 TransferBytes = 6; break; 1333 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register: 1334 TransferBytes = 12; break; 1335 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: 1336 TransferBytes = 24; break; 1337 } 1338 IsLoad = true; 1339 NumVecs = 3; 1340 break; 1341 } 1342 1343 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: 1344 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: 1345 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: 1346 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: { 1347 switch (Opc) { 1348 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: 1349 TransferBytes = 4; break; 1350 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: 1351 TransferBytes = 8; break; 1352 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: 1353 TransferBytes = 16; break; 1354 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: 1355 TransferBytes = 32; break; 1356 } 1357 IsLoad = true; 1358 NumVecs = 4; 1359 break; 1360 } 1361 1362 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register: 1363 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register: 1364 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register: 1365 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: { 1366 switch (Opc) { 1367 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register: 1368 TransferBytes = 1; break; 1369 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register: 1370 TransferBytes = 2; break; 1371 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register: 1372 TransferBytes = 4; break; 1373 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: 1374 TransferBytes = 8; break; 1375 } 1376 NumVecs = 1; 1377 break; 1378 } 1379 1380 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register: 1381 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register: 1382 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register: 1383 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: { 1384 switch (Opc) { 1385 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register: 1386 TransferBytes = 2; break; 1387 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register: 1388 TransferBytes = 4; break; 1389 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register: 1390 TransferBytes = 8; break; 1391 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: 1392 TransferBytes = 16; break; 1393 } 1394 NumVecs = 2; 1395 break; 1396 } 1397 1398 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register: 1399 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register: 1400 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register: 1401 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: { 1402 switch (Opc) { 1403 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register: 1404 TransferBytes = 3; break; 1405 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register: 1406 TransferBytes = 6; break; 1407 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register: 1408 TransferBytes = 12; break; 1409 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: 1410 TransferBytes = 24; break; 1411 } 1412 NumVecs = 3; 1413 break; 1414 } 1415 1416 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register: 1417 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register: 1418 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register: 1419 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: { 1420 switch (Opc) { 1421 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register: 1422 TransferBytes = 4; break; 1423 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register: 1424 TransferBytes = 8; break; 1425 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register: 1426 TransferBytes = 16; break; 1427 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: 1428 TransferBytes = 32; break; 1429 } 1430 NumVecs = 4; 1431 break; 1432 } 1433 1434 default: 1435 return MCDisassembler::Fail; 1436 } // End of switch (Opc) 1437 1438 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 1439 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1440 unsigned Rm = fieldFromInstruction(Insn, 16, 5); 1441 1442 // Decode post-index of load duplicate lane 1443 if (IsLoadDup) { 1444 switch (NumVecs) { 1445 case 1: 1446 Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder) 1447 : DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1448 break; 1449 case 2: 1450 Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder) 1451 : DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1452 break; 1453 case 3: 1454 Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder) 1455 : DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1456 break; 1457 case 4: 1458 Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder) 1459 : DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1460 } 1461 1462 // Decode write back register, which is equal to Rn. 1463 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1464 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1465 1466 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes 1467 Inst.addOperand(MCOperand::CreateImm(TransferBytes)); 1468 else // Decode Rm 1469 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1470 1471 return MCDisassembler::Success; 1472 } 1473 1474 // Decode post-index of load/store lane 1475 // Loads have a vector list as output. 1476 if (IsLoad) { 1477 switch (NumVecs) { 1478 case 1: 1479 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1480 break; 1481 case 2: 1482 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1483 break; 1484 case 3: 1485 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1486 break; 1487 case 4: 1488 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1489 } 1490 } 1491 1492 // Decode write back register, which is equal to Rn. 1493 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1494 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1495 1496 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes 1497 Inst.addOperand(MCOperand::CreateImm(TransferBytes)); 1498 else // Decode Rm 1499 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1500 1501 // Decode the source vector list. 1502 switch (NumVecs) { 1503 case 1: 1504 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1505 break; 1506 case 2: 1507 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1508 break; 1509 case 3: 1510 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1511 break; 1512 case 4: 1513 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1514 } 1515 1516 // Decode lane 1517 unsigned Q = fieldFromInstruction(Insn, 30, 1); 1518 unsigned S = fieldFromInstruction(Insn, 10, 3); 1519 unsigned lane = 0; 1520 // Calculate the number of lanes by number of vectors and transferred bytes. 1521 // NumLanes = 16 bytes / bytes of each lane 1522 unsigned NumLanes = 16 / (TransferBytes / NumVecs); 1523 switch (NumLanes) { 1524 case 16: // A vector has 16 lanes, each lane is 1 bytes. 1525 lane = (Q << 3) | S; 1526 break; 1527 case 8: 1528 lane = (Q << 2) | (S >> 1); 1529 break; 1530 case 4: 1531 lane = (Q << 1) | (S >> 2); 1532 break; 1533 case 2: 1534 lane = Q; 1535 break; 1536 } 1537 Inst.addOperand(MCOperand::CreateImm(lane)); 1538 1539 return MCDisassembler::Success; 1540 } 1541 1542 static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, 1543 uint64_t Address, 1544 const void *Decoder) { 1545 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 1546 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1547 unsigned size = fieldFromInstruction(Insn, 22, 2); 1548 unsigned Q = fieldFromInstruction(Insn, 30, 1); 1549 1550 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 1551 1552 if(Q) 1553 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 1554 else 1555 DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder); 1556 1557 switch (size) { 1558 case 0: 1559 Inst.addOperand(MCOperand::CreateImm(8)); 1560 break; 1561 case 1: 1562 Inst.addOperand(MCOperand::CreateImm(16)); 1563 break; 1564 case 2: 1565 Inst.addOperand(MCOperand::CreateImm(32)); 1566 break; 1567 default : 1568 return MCDisassembler::Fail; 1569 } 1570 return MCDisassembler::Success; 1571 } 1572 1573