1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "MCTargetDesc/AArch64AddressingModes.h" 16 #include "MCTargetDesc/AArch64MCTargetDesc.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 66 unsigned RegNo, uint64_t Address, 67 const void *Decoder); 68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 72 unsigned RegNo, uint64_t Address, 73 const void *Decoder); 74 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 81 uint64_t Address, 82 const void *Decoder); 83 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 96 uint64_t Address, 97 const void *Decoder); 98 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 99 uint64_t Address, 100 const void *Decoder); 101 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 102 uint64_t Address, 103 const void *Decoder); 104 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 118 uint64_t Address, 119 const void *Decoder); 120 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 121 uint64_t Address, 122 const void *Decoder); 123 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 124 uint64_t Address, const void *Decoder); 125 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 126 uint64_t Address, const void *Decoder); 127 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 132 uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 135 uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 138 uint64_t Address, 139 const void *Decoder); 140 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 141 uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 144 uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 166 uint64_t Address, 167 const void *Decoder); 168 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 169 uint64_t Address, 170 const void *Decoder); 171 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 172 uint64_t Address, const void *Decoder); 173 174 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 175 uint64_t Address, 176 const void *Decoder); 177 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, const void *Decoder); 179 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 180 uint64_t Addr, 181 const void *Decoder); 182 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 183 uint64_t Addr, const void *Decoder); 184 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, 186 const void *Decoder); 187 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 188 uint64_t Addr, const void *Decoder); 189 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 190 uint64_t Addr, 191 const void *Decoder); 192 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 193 uint64_t Addr, const void *Decoder); 194 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 195 uint64_t Addr, const void *Decoder); 196 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, const void *Decoder); 198 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, const void *Decoder); 200 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 201 uint64_t Addr, const void *Decoder); 202 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 203 unsigned RegNo, 204 uint64_t Addr, 205 const void *Decoder); 206 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 207 unsigned RegNo, 208 uint64_t Addr, 209 const void *Decoder); 210 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 211 uint32_t insn, 212 uint64_t Address, 213 const void *Decoder); 214 template<int Bits> 215 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 216 uint64_t Address, const void *Decoder); 217 template <int ElementWidth> 218 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 219 uint64_t Addr, const void *Decoder); 220 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 221 uint64_t Addr, const void *Decoder); 222 223 static bool Check(DecodeStatus &Out, DecodeStatus In) { 224 switch (In) { 225 case MCDisassembler::Success: 226 // Out stays the same. 227 return true; 228 case MCDisassembler::SoftFail: 229 Out = In; 230 return true; 231 case MCDisassembler::Fail: 232 Out = In; 233 return false; 234 } 235 llvm_unreachable("Invalid DecodeStatus!"); 236 } 237 238 #include "AArch64GenDisassemblerTables.inc" 239 #include "AArch64GenInstrInfo.inc" 240 241 #define Success MCDisassembler::Success 242 #define Fail MCDisassembler::Fail 243 #define SoftFail MCDisassembler::SoftFail 244 245 static MCDisassembler *createAArch64Disassembler(const Target &T, 246 const MCSubtargetInfo &STI, 247 MCContext &Ctx) { 248 return new AArch64Disassembler(STI, Ctx); 249 } 250 251 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 252 ArrayRef<uint8_t> Bytes, 253 uint64_t Address, 254 raw_ostream &OS, 255 raw_ostream &CS) const { 256 CommentStream = &CS; 257 258 Size = 0; 259 // We want to read exactly 4 bytes of data. 260 if (Bytes.size() < 4) 261 return Fail; 262 Size = 4; 263 264 // Encoded as a small-endian 32-bit word in the stream. 265 uint32_t Insn = 266 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 267 268 // Calling the auto-generated decoder function. 269 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 270 } 271 272 static MCSymbolizer * 273 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 274 LLVMSymbolLookupCallback SymbolLookUp, 275 void *DisInfo, MCContext *Ctx, 276 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 277 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 278 SymbolLookUp, DisInfo); 279 } 280 281 extern "C" void LLVMInitializeAArch64Disassembler() { 282 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 283 createAArch64Disassembler); 284 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 285 createAArch64Disassembler); 286 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 287 createAArch64ExternalSymbolizer); 288 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 289 createAArch64ExternalSymbolizer); 290 291 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 292 createAArch64Disassembler); 293 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 294 createAArch64ExternalSymbolizer); 295 } 296 297 static const unsigned FPR128DecoderTable[] = { 298 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 299 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 300 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 301 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 302 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 303 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 304 AArch64::Q30, AArch64::Q31 305 }; 306 307 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 308 uint64_t Addr, 309 const void *Decoder) { 310 if (RegNo > 31) 311 return Fail; 312 313 unsigned Register = FPR128DecoderTable[RegNo]; 314 Inst.addOperand(MCOperand::createReg(Register)); 315 return Success; 316 } 317 318 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 319 uint64_t Addr, 320 const void *Decoder) { 321 if (RegNo > 15) 322 return Fail; 323 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 324 } 325 326 static const unsigned FPR64DecoderTable[] = { 327 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 328 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 329 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 330 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 331 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 332 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 333 AArch64::D30, AArch64::D31 334 }; 335 336 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 337 uint64_t Addr, 338 const void *Decoder) { 339 if (RegNo > 31) 340 return Fail; 341 342 unsigned Register = FPR64DecoderTable[RegNo]; 343 Inst.addOperand(MCOperand::createReg(Register)); 344 return Success; 345 } 346 347 static const unsigned FPR32DecoderTable[] = { 348 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 349 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 350 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 351 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 352 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 353 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 354 AArch64::S30, AArch64::S31 355 }; 356 357 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 358 uint64_t Addr, 359 const void *Decoder) { 360 if (RegNo > 31) 361 return Fail; 362 363 unsigned Register = FPR32DecoderTable[RegNo]; 364 Inst.addOperand(MCOperand::createReg(Register)); 365 return Success; 366 } 367 368 static const unsigned FPR16DecoderTable[] = { 369 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 370 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 371 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 372 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 373 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 374 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 375 AArch64::H30, AArch64::H31 376 }; 377 378 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 379 uint64_t Addr, 380 const void *Decoder) { 381 if (RegNo > 31) 382 return Fail; 383 384 unsigned Register = FPR16DecoderTable[RegNo]; 385 Inst.addOperand(MCOperand::createReg(Register)); 386 return Success; 387 } 388 389 static const unsigned FPR8DecoderTable[] = { 390 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 391 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 392 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 393 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 394 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 395 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 396 AArch64::B30, AArch64::B31 397 }; 398 399 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 400 uint64_t Addr, 401 const void *Decoder) { 402 if (RegNo > 31) 403 return Fail; 404 405 unsigned Register = FPR8DecoderTable[RegNo]; 406 Inst.addOperand(MCOperand::createReg(Register)); 407 return Success; 408 } 409 410 static const unsigned GPR64DecoderTable[] = { 411 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 412 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 413 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 414 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 415 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 416 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 417 AArch64::LR, AArch64::XZR 418 }; 419 420 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 421 uint64_t Addr, 422 const void *Decoder) { 423 if (RegNo > 30) 424 return Fail; 425 426 unsigned Register = GPR64DecoderTable[RegNo]; 427 Inst.addOperand(MCOperand::createReg(Register)); 428 return Success; 429 } 430 431 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 432 uint64_t Addr, 433 const void *Decoder) { 434 if (RegNo > 31) 435 return Fail; 436 437 unsigned Register = GPR64DecoderTable[RegNo]; 438 Inst.addOperand(MCOperand::createReg(Register)); 439 return Success; 440 } 441 442 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 443 uint64_t Addr, 444 const void *Decoder) { 445 if (RegNo > 31) 446 return Fail; 447 unsigned Register = GPR64DecoderTable[RegNo]; 448 if (Register == AArch64::XZR) 449 Register = AArch64::SP; 450 Inst.addOperand(MCOperand::createReg(Register)); 451 return Success; 452 } 453 454 static const unsigned GPR32DecoderTable[] = { 455 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 456 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 457 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 458 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 459 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 460 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 461 AArch64::W30, AArch64::WZR 462 }; 463 464 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 465 uint64_t Addr, 466 const void *Decoder) { 467 if (RegNo > 31) 468 return Fail; 469 470 unsigned Register = GPR32DecoderTable[RegNo]; 471 Inst.addOperand(MCOperand::createReg(Register)); 472 return Success; 473 } 474 475 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 476 uint64_t Addr, 477 const void *Decoder) { 478 if (RegNo > 31) 479 return Fail; 480 481 unsigned Register = GPR32DecoderTable[RegNo]; 482 if (Register == AArch64::WZR) 483 Register = AArch64::WSP; 484 Inst.addOperand(MCOperand::createReg(Register)); 485 return Success; 486 } 487 static const unsigned ZPRDecoderTable[] = { 488 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 489 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 490 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 491 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 492 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 493 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 494 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 495 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 496 }; 497 498 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 499 uint64_t Address, 500 const void* Decoder) { 501 if (RegNo > 31) 502 return Fail; 503 504 unsigned Register = ZPRDecoderTable[RegNo]; 505 Inst.addOperand(MCOperand::createReg(Register)); 506 return Success; 507 } 508 509 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 510 uint64_t Address, 511 const void *Decoder) { 512 if (RegNo > 15) 513 return Fail; 514 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 515 } 516 517 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 518 uint64_t Address, 519 const void *Decoder) { 520 if (RegNo > 7) 521 return Fail; 522 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 523 } 524 525 static const unsigned ZZDecoderTable[] = { 526 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 527 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 528 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 529 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 530 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 531 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 532 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 533 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 534 }; 535 536 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 537 uint64_t Address, 538 const void* Decoder) { 539 if (RegNo > 31) 540 return Fail; 541 unsigned Register = ZZDecoderTable[RegNo]; 542 Inst.addOperand(MCOperand::createReg(Register)); 543 return Success; 544 } 545 546 static const unsigned ZZZDecoderTable[] = { 547 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 548 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 549 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 550 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 551 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 552 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 553 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 554 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 555 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 556 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 557 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 558 }; 559 560 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 561 uint64_t Address, 562 const void* Decoder) { 563 if (RegNo > 31) 564 return Fail; 565 unsigned Register = ZZZDecoderTable[RegNo]; 566 Inst.addOperand(MCOperand::createReg(Register)); 567 return Success; 568 } 569 570 static const unsigned ZZZZDecoderTable[] = { 571 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 572 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 573 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 574 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 575 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 576 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 577 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 578 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 579 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 580 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 581 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 582 }; 583 584 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 585 uint64_t Address, 586 const void* Decoder) { 587 if (RegNo > 31) 588 return Fail; 589 unsigned Register = ZZZZDecoderTable[RegNo]; 590 Inst.addOperand(MCOperand::createReg(Register)); 591 return Success; 592 } 593 594 static const unsigned PPRDecoderTable[] = { 595 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 596 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 597 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 598 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 599 }; 600 601 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 602 uint64_t Addr, const void *Decoder) { 603 if (RegNo > 15) 604 return Fail; 605 606 unsigned Register = PPRDecoderTable[RegNo]; 607 Inst.addOperand(MCOperand::createReg(Register)); 608 return Success; 609 } 610 611 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 612 uint64_t Addr, 613 const void* Decoder) { 614 if (RegNo > 7) 615 return Fail; 616 617 // Just reuse the PPR decode table 618 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 619 } 620 621 static const unsigned VectorDecoderTable[] = { 622 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 623 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 624 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 625 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 626 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 627 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 628 AArch64::Q30, AArch64::Q31 629 }; 630 631 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 632 uint64_t Addr, 633 const void *Decoder) { 634 if (RegNo > 31) 635 return Fail; 636 637 unsigned Register = VectorDecoderTable[RegNo]; 638 Inst.addOperand(MCOperand::createReg(Register)); 639 return Success; 640 } 641 642 static const unsigned QQDecoderTable[] = { 643 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 644 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 645 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 646 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 647 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 648 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 649 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 650 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 651 }; 652 653 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 654 uint64_t Addr, const void *Decoder) { 655 if (RegNo > 31) 656 return Fail; 657 unsigned Register = QQDecoderTable[RegNo]; 658 Inst.addOperand(MCOperand::createReg(Register)); 659 return Success; 660 } 661 662 static const unsigned QQQDecoderTable[] = { 663 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 664 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 665 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 666 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 667 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 668 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 669 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 670 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 671 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 672 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 673 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 674 }; 675 676 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 677 uint64_t Addr, const void *Decoder) { 678 if (RegNo > 31) 679 return Fail; 680 unsigned Register = QQQDecoderTable[RegNo]; 681 Inst.addOperand(MCOperand::createReg(Register)); 682 return Success; 683 } 684 685 static const unsigned QQQQDecoderTable[] = { 686 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 687 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 688 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 689 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 690 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 691 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 692 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 693 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 694 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 695 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 696 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 697 }; 698 699 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 700 uint64_t Addr, 701 const void *Decoder) { 702 if (RegNo > 31) 703 return Fail; 704 unsigned Register = QQQQDecoderTable[RegNo]; 705 Inst.addOperand(MCOperand::createReg(Register)); 706 return Success; 707 } 708 709 static const unsigned DDDecoderTable[] = { 710 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 711 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 712 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 713 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 714 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 715 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 716 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 717 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 718 }; 719 720 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 721 uint64_t Addr, const void *Decoder) { 722 if (RegNo > 31) 723 return Fail; 724 unsigned Register = DDDecoderTable[RegNo]; 725 Inst.addOperand(MCOperand::createReg(Register)); 726 return Success; 727 } 728 729 static const unsigned DDDDecoderTable[] = { 730 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 731 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 732 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 733 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 734 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 735 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 736 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 737 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 738 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 739 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 740 AArch64::D30_D31_D0, AArch64::D31_D0_D1 741 }; 742 743 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 744 uint64_t Addr, const void *Decoder) { 745 if (RegNo > 31) 746 return Fail; 747 unsigned Register = DDDDecoderTable[RegNo]; 748 Inst.addOperand(MCOperand::createReg(Register)); 749 return Success; 750 } 751 752 static const unsigned DDDDDecoderTable[] = { 753 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 754 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 755 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 756 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 757 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 758 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 759 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 760 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 761 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 762 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 763 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 764 }; 765 766 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 767 uint64_t Addr, 768 const void *Decoder) { 769 if (RegNo > 31) 770 return Fail; 771 unsigned Register = DDDDDecoderTable[RegNo]; 772 Inst.addOperand(MCOperand::createReg(Register)); 773 return Success; 774 } 775 776 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 777 uint64_t Addr, 778 const void *Decoder) { 779 // scale{5} is asserted as 1 in tblgen. 780 Imm |= 0x20; 781 Inst.addOperand(MCOperand::createImm(64 - Imm)); 782 return Success; 783 } 784 785 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 786 uint64_t Addr, 787 const void *Decoder) { 788 Inst.addOperand(MCOperand::createImm(64 - Imm)); 789 return Success; 790 } 791 792 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 793 uint64_t Addr, const void *Decoder) { 794 int64_t ImmVal = Imm; 795 const AArch64Disassembler *Dis = 796 static_cast<const AArch64Disassembler *>(Decoder); 797 798 // Sign-extend 19-bit immediate. 799 if (ImmVal & (1 << (19 - 1))) 800 ImmVal |= ~((1LL << 19) - 1); 801 802 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 803 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 804 Inst.addOperand(MCOperand::createImm(ImmVal)); 805 return Success; 806 } 807 808 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 809 uint64_t Address, const void *Decoder) { 810 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 811 Inst.addOperand(MCOperand::createImm(Imm & 1)); 812 return Success; 813 } 814 815 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 816 uint64_t Address, 817 const void *Decoder) { 818 Inst.addOperand(MCOperand::createImm(Imm)); 819 820 // Every system register in the encoding space is valid with the syntax 821 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 822 return Success; 823 } 824 825 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 826 uint64_t Address, 827 const void *Decoder) { 828 Inst.addOperand(MCOperand::createImm(Imm)); 829 830 return Success; 831 } 832 833 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 834 uint64_t Address, 835 const void *Decoder) { 836 // This decoder exists to add the dummy Lane operand to the MCInst, which must 837 // be 1 in assembly but has no other real manifestation. 838 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 839 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 840 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 841 842 if (IsToVec) { 843 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 844 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 845 } else { 846 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 847 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 848 } 849 850 // Add the lane 851 Inst.addOperand(MCOperand::createImm(1)); 852 853 return Success; 854 } 855 856 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 857 unsigned Add) { 858 Inst.addOperand(MCOperand::createImm(Add - Imm)); 859 return Success; 860 } 861 862 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 863 unsigned Add) { 864 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 865 return Success; 866 } 867 868 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 869 uint64_t Addr, const void *Decoder) { 870 return DecodeVecShiftRImm(Inst, Imm, 64); 871 } 872 873 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 874 uint64_t Addr, 875 const void *Decoder) { 876 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 877 } 878 879 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 880 uint64_t Addr, const void *Decoder) { 881 return DecodeVecShiftRImm(Inst, Imm, 32); 882 } 883 884 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 885 uint64_t Addr, 886 const void *Decoder) { 887 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 888 } 889 890 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 891 uint64_t Addr, const void *Decoder) { 892 return DecodeVecShiftRImm(Inst, Imm, 16); 893 } 894 895 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 896 uint64_t Addr, 897 const void *Decoder) { 898 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 899 } 900 901 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 902 uint64_t Addr, const void *Decoder) { 903 return DecodeVecShiftRImm(Inst, Imm, 8); 904 } 905 906 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 907 uint64_t Addr, const void *Decoder) { 908 return DecodeVecShiftLImm(Inst, Imm, 64); 909 } 910 911 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 912 uint64_t Addr, const void *Decoder) { 913 return DecodeVecShiftLImm(Inst, Imm, 32); 914 } 915 916 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 917 uint64_t Addr, const void *Decoder) { 918 return DecodeVecShiftLImm(Inst, Imm, 16); 919 } 920 921 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 922 uint64_t Addr, const void *Decoder) { 923 return DecodeVecShiftLImm(Inst, Imm, 8); 924 } 925 926 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 927 uint64_t Addr, 928 const void *Decoder) { 929 unsigned Rd = fieldFromInstruction(insn, 0, 5); 930 unsigned Rn = fieldFromInstruction(insn, 5, 5); 931 unsigned Rm = fieldFromInstruction(insn, 16, 5); 932 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 933 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 934 unsigned shift = (shiftHi << 6) | shiftLo; 935 switch (Inst.getOpcode()) { 936 default: 937 return Fail; 938 case AArch64::ADDWrs: 939 case AArch64::ADDSWrs: 940 case AArch64::SUBWrs: 941 case AArch64::SUBSWrs: 942 // if shift == '11' then ReservedValue() 943 if (shiftHi == 0x3) 944 return Fail; 945 LLVM_FALLTHROUGH; 946 case AArch64::ANDWrs: 947 case AArch64::ANDSWrs: 948 case AArch64::BICWrs: 949 case AArch64::BICSWrs: 950 case AArch64::ORRWrs: 951 case AArch64::ORNWrs: 952 case AArch64::EORWrs: 953 case AArch64::EONWrs: { 954 // if sf == '0' and imm6<5> == '1' then ReservedValue() 955 if (shiftLo >> 5 == 1) 956 return Fail; 957 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 958 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 959 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 960 break; 961 } 962 case AArch64::ADDXrs: 963 case AArch64::ADDSXrs: 964 case AArch64::SUBXrs: 965 case AArch64::SUBSXrs: 966 // if shift == '11' then ReservedValue() 967 if (shiftHi == 0x3) 968 return Fail; 969 LLVM_FALLTHROUGH; 970 case AArch64::ANDXrs: 971 case AArch64::ANDSXrs: 972 case AArch64::BICXrs: 973 case AArch64::BICSXrs: 974 case AArch64::ORRXrs: 975 case AArch64::ORNXrs: 976 case AArch64::EORXrs: 977 case AArch64::EONXrs: 978 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 979 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 980 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 981 break; 982 } 983 984 Inst.addOperand(MCOperand::createImm(shift)); 985 return Success; 986 } 987 988 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 989 uint64_t Addr, 990 const void *Decoder) { 991 unsigned Rd = fieldFromInstruction(insn, 0, 5); 992 unsigned imm = fieldFromInstruction(insn, 5, 16); 993 unsigned shift = fieldFromInstruction(insn, 21, 2); 994 shift <<= 4; 995 switch (Inst.getOpcode()) { 996 default: 997 return Fail; 998 case AArch64::MOVZWi: 999 case AArch64::MOVNWi: 1000 case AArch64::MOVKWi: 1001 if (shift & (1U << 5)) 1002 return Fail; 1003 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1004 break; 1005 case AArch64::MOVZXi: 1006 case AArch64::MOVNXi: 1007 case AArch64::MOVKXi: 1008 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1009 break; 1010 } 1011 1012 if (Inst.getOpcode() == AArch64::MOVKWi || 1013 Inst.getOpcode() == AArch64::MOVKXi) 1014 Inst.addOperand(Inst.getOperand(0)); 1015 1016 Inst.addOperand(MCOperand::createImm(imm)); 1017 Inst.addOperand(MCOperand::createImm(shift)); 1018 return Success; 1019 } 1020 1021 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1022 uint64_t Addr, 1023 const void *Decoder) { 1024 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1025 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1026 unsigned offset = fieldFromInstruction(insn, 10, 12); 1027 const AArch64Disassembler *Dis = 1028 static_cast<const AArch64Disassembler *>(Decoder); 1029 1030 switch (Inst.getOpcode()) { 1031 default: 1032 return Fail; 1033 case AArch64::PRFMui: 1034 // Rt is an immediate in prefetch. 1035 Inst.addOperand(MCOperand::createImm(Rt)); 1036 break; 1037 case AArch64::STRBBui: 1038 case AArch64::LDRBBui: 1039 case AArch64::LDRSBWui: 1040 case AArch64::STRHHui: 1041 case AArch64::LDRHHui: 1042 case AArch64::LDRSHWui: 1043 case AArch64::STRWui: 1044 case AArch64::LDRWui: 1045 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1046 break; 1047 case AArch64::LDRSBXui: 1048 case AArch64::LDRSHXui: 1049 case AArch64::LDRSWui: 1050 case AArch64::STRXui: 1051 case AArch64::LDRXui: 1052 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1053 break; 1054 case AArch64::LDRQui: 1055 case AArch64::STRQui: 1056 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1057 break; 1058 case AArch64::LDRDui: 1059 case AArch64::STRDui: 1060 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1061 break; 1062 case AArch64::LDRSui: 1063 case AArch64::STRSui: 1064 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1065 break; 1066 case AArch64::LDRHui: 1067 case AArch64::STRHui: 1068 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1069 break; 1070 case AArch64::LDRBui: 1071 case AArch64::STRBui: 1072 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1073 break; 1074 } 1075 1076 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1077 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1078 Inst.addOperand(MCOperand::createImm(offset)); 1079 return Success; 1080 } 1081 1082 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1083 uint64_t Addr, 1084 const void *Decoder) { 1085 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1086 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1087 int64_t offset = fieldFromInstruction(insn, 12, 9); 1088 1089 // offset is a 9-bit signed immediate, so sign extend it to 1090 // fill the unsigned. 1091 if (offset & (1 << (9 - 1))) 1092 offset |= ~((1LL << 9) - 1); 1093 1094 // First operand is always the writeback to the address register, if needed. 1095 switch (Inst.getOpcode()) { 1096 default: 1097 break; 1098 case AArch64::LDRSBWpre: 1099 case AArch64::LDRSHWpre: 1100 case AArch64::STRBBpre: 1101 case AArch64::LDRBBpre: 1102 case AArch64::STRHHpre: 1103 case AArch64::LDRHHpre: 1104 case AArch64::STRWpre: 1105 case AArch64::LDRWpre: 1106 case AArch64::LDRSBWpost: 1107 case AArch64::LDRSHWpost: 1108 case AArch64::STRBBpost: 1109 case AArch64::LDRBBpost: 1110 case AArch64::STRHHpost: 1111 case AArch64::LDRHHpost: 1112 case AArch64::STRWpost: 1113 case AArch64::LDRWpost: 1114 case AArch64::LDRSBXpre: 1115 case AArch64::LDRSHXpre: 1116 case AArch64::STRXpre: 1117 case AArch64::LDRSWpre: 1118 case AArch64::LDRXpre: 1119 case AArch64::LDRSBXpost: 1120 case AArch64::LDRSHXpost: 1121 case AArch64::STRXpost: 1122 case AArch64::LDRSWpost: 1123 case AArch64::LDRXpost: 1124 case AArch64::LDRQpre: 1125 case AArch64::STRQpre: 1126 case AArch64::LDRQpost: 1127 case AArch64::STRQpost: 1128 case AArch64::LDRDpre: 1129 case AArch64::STRDpre: 1130 case AArch64::LDRDpost: 1131 case AArch64::STRDpost: 1132 case AArch64::LDRSpre: 1133 case AArch64::STRSpre: 1134 case AArch64::LDRSpost: 1135 case AArch64::STRSpost: 1136 case AArch64::LDRHpre: 1137 case AArch64::STRHpre: 1138 case AArch64::LDRHpost: 1139 case AArch64::STRHpost: 1140 case AArch64::LDRBpre: 1141 case AArch64::STRBpre: 1142 case AArch64::LDRBpost: 1143 case AArch64::STRBpost: 1144 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1145 break; 1146 } 1147 1148 switch (Inst.getOpcode()) { 1149 default: 1150 return Fail; 1151 case AArch64::PRFUMi: 1152 // Rt is an immediate in prefetch. 1153 Inst.addOperand(MCOperand::createImm(Rt)); 1154 break; 1155 case AArch64::STURBBi: 1156 case AArch64::LDURBBi: 1157 case AArch64::LDURSBWi: 1158 case AArch64::STURHHi: 1159 case AArch64::LDURHHi: 1160 case AArch64::LDURSHWi: 1161 case AArch64::STURWi: 1162 case AArch64::LDURWi: 1163 case AArch64::LDTRSBWi: 1164 case AArch64::LDTRSHWi: 1165 case AArch64::STTRWi: 1166 case AArch64::LDTRWi: 1167 case AArch64::STTRHi: 1168 case AArch64::LDTRHi: 1169 case AArch64::LDTRBi: 1170 case AArch64::STTRBi: 1171 case AArch64::LDRSBWpre: 1172 case AArch64::LDRSHWpre: 1173 case AArch64::STRBBpre: 1174 case AArch64::LDRBBpre: 1175 case AArch64::STRHHpre: 1176 case AArch64::LDRHHpre: 1177 case AArch64::STRWpre: 1178 case AArch64::LDRWpre: 1179 case AArch64::LDRSBWpost: 1180 case AArch64::LDRSHWpost: 1181 case AArch64::STRBBpost: 1182 case AArch64::LDRBBpost: 1183 case AArch64::STRHHpost: 1184 case AArch64::LDRHHpost: 1185 case AArch64::STRWpost: 1186 case AArch64::LDRWpost: 1187 case AArch64::STLURBi: 1188 case AArch64::STLURHi: 1189 case AArch64::STLURWi: 1190 case AArch64::LDAPURBi: 1191 case AArch64::LDAPURSBWi: 1192 case AArch64::LDAPURHi: 1193 case AArch64::LDAPURSHWi: 1194 case AArch64::LDAPURi: 1195 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1196 break; 1197 case AArch64::LDURSBXi: 1198 case AArch64::LDURSHXi: 1199 case AArch64::LDURSWi: 1200 case AArch64::STURXi: 1201 case AArch64::LDURXi: 1202 case AArch64::LDTRSBXi: 1203 case AArch64::LDTRSHXi: 1204 case AArch64::LDTRSWi: 1205 case AArch64::STTRXi: 1206 case AArch64::LDTRXi: 1207 case AArch64::LDRSBXpre: 1208 case AArch64::LDRSHXpre: 1209 case AArch64::STRXpre: 1210 case AArch64::LDRSWpre: 1211 case AArch64::LDRXpre: 1212 case AArch64::LDRSBXpost: 1213 case AArch64::LDRSHXpost: 1214 case AArch64::STRXpost: 1215 case AArch64::LDRSWpost: 1216 case AArch64::LDRXpost: 1217 case AArch64::LDAPURSWi: 1218 case AArch64::LDAPURSHXi: 1219 case AArch64::LDAPURSBXi: 1220 case AArch64::STLURXi: 1221 case AArch64::LDAPURXi: 1222 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1223 break; 1224 case AArch64::LDURQi: 1225 case AArch64::STURQi: 1226 case AArch64::LDRQpre: 1227 case AArch64::STRQpre: 1228 case AArch64::LDRQpost: 1229 case AArch64::STRQpost: 1230 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1231 break; 1232 case AArch64::LDURDi: 1233 case AArch64::STURDi: 1234 case AArch64::LDRDpre: 1235 case AArch64::STRDpre: 1236 case AArch64::LDRDpost: 1237 case AArch64::STRDpost: 1238 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1239 break; 1240 case AArch64::LDURSi: 1241 case AArch64::STURSi: 1242 case AArch64::LDRSpre: 1243 case AArch64::STRSpre: 1244 case AArch64::LDRSpost: 1245 case AArch64::STRSpost: 1246 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1247 break; 1248 case AArch64::LDURHi: 1249 case AArch64::STURHi: 1250 case AArch64::LDRHpre: 1251 case AArch64::STRHpre: 1252 case AArch64::LDRHpost: 1253 case AArch64::STRHpost: 1254 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1255 break; 1256 case AArch64::LDURBi: 1257 case AArch64::STURBi: 1258 case AArch64::LDRBpre: 1259 case AArch64::STRBpre: 1260 case AArch64::LDRBpost: 1261 case AArch64::STRBpost: 1262 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1263 break; 1264 } 1265 1266 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1267 Inst.addOperand(MCOperand::createImm(offset)); 1268 1269 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1270 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1271 bool IsFP = fieldFromInstruction(insn, 26, 1); 1272 1273 // Cannot write back to a transfer register (but xzr != sp). 1274 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1275 return SoftFail; 1276 1277 return Success; 1278 } 1279 1280 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1281 uint64_t Addr, 1282 const void *Decoder) { 1283 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1284 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1285 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1286 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1287 1288 unsigned Opcode = Inst.getOpcode(); 1289 switch (Opcode) { 1290 default: 1291 return Fail; 1292 case AArch64::STLXRW: 1293 case AArch64::STLXRB: 1294 case AArch64::STLXRH: 1295 case AArch64::STXRW: 1296 case AArch64::STXRB: 1297 case AArch64::STXRH: 1298 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1299 LLVM_FALLTHROUGH; 1300 case AArch64::LDARW: 1301 case AArch64::LDARB: 1302 case AArch64::LDARH: 1303 case AArch64::LDAXRW: 1304 case AArch64::LDAXRB: 1305 case AArch64::LDAXRH: 1306 case AArch64::LDXRW: 1307 case AArch64::LDXRB: 1308 case AArch64::LDXRH: 1309 case AArch64::STLRW: 1310 case AArch64::STLRB: 1311 case AArch64::STLRH: 1312 case AArch64::STLLRW: 1313 case AArch64::STLLRB: 1314 case AArch64::STLLRH: 1315 case AArch64::LDLARW: 1316 case AArch64::LDLARB: 1317 case AArch64::LDLARH: 1318 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1319 break; 1320 case AArch64::STLXRX: 1321 case AArch64::STXRX: 1322 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1323 LLVM_FALLTHROUGH; 1324 case AArch64::LDARX: 1325 case AArch64::LDAXRX: 1326 case AArch64::LDXRX: 1327 case AArch64::STLRX: 1328 case AArch64::LDLARX: 1329 case AArch64::STLLRX: 1330 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1331 break; 1332 case AArch64::STLXPW: 1333 case AArch64::STXPW: 1334 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1335 LLVM_FALLTHROUGH; 1336 case AArch64::LDAXPW: 1337 case AArch64::LDXPW: 1338 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1339 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1340 break; 1341 case AArch64::STLXPX: 1342 case AArch64::STXPX: 1343 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1344 LLVM_FALLTHROUGH; 1345 case AArch64::LDAXPX: 1346 case AArch64::LDXPX: 1347 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1348 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1349 break; 1350 } 1351 1352 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1353 1354 // You shouldn't load to the same register twice in an instruction... 1355 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1356 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1357 Rt == Rt2) 1358 return SoftFail; 1359 1360 return Success; 1361 } 1362 1363 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1364 uint64_t Addr, 1365 const void *Decoder) { 1366 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1367 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1368 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1369 int64_t offset = fieldFromInstruction(insn, 15, 7); 1370 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1371 1372 // offset is a 7-bit signed immediate, so sign extend it to 1373 // fill the unsigned. 1374 if (offset & (1 << (7 - 1))) 1375 offset |= ~((1LL << 7) - 1); 1376 1377 unsigned Opcode = Inst.getOpcode(); 1378 bool NeedsDisjointWritebackTransfer = false; 1379 1380 // First operand is always writeback of base register. 1381 switch (Opcode) { 1382 default: 1383 break; 1384 case AArch64::LDPXpost: 1385 case AArch64::STPXpost: 1386 case AArch64::LDPSWpost: 1387 case AArch64::LDPXpre: 1388 case AArch64::STPXpre: 1389 case AArch64::LDPSWpre: 1390 case AArch64::LDPWpost: 1391 case AArch64::STPWpost: 1392 case AArch64::LDPWpre: 1393 case AArch64::STPWpre: 1394 case AArch64::LDPQpost: 1395 case AArch64::STPQpost: 1396 case AArch64::LDPQpre: 1397 case AArch64::STPQpre: 1398 case AArch64::LDPDpost: 1399 case AArch64::STPDpost: 1400 case AArch64::LDPDpre: 1401 case AArch64::STPDpre: 1402 case AArch64::LDPSpost: 1403 case AArch64::STPSpost: 1404 case AArch64::LDPSpre: 1405 case AArch64::STPSpre: 1406 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1407 break; 1408 } 1409 1410 switch (Opcode) { 1411 default: 1412 return Fail; 1413 case AArch64::LDPXpost: 1414 case AArch64::STPXpost: 1415 case AArch64::LDPSWpost: 1416 case AArch64::LDPXpre: 1417 case AArch64::STPXpre: 1418 case AArch64::LDPSWpre: 1419 NeedsDisjointWritebackTransfer = true; 1420 LLVM_FALLTHROUGH; 1421 case AArch64::LDNPXi: 1422 case AArch64::STNPXi: 1423 case AArch64::LDPXi: 1424 case AArch64::STPXi: 1425 case AArch64::LDPSWi: 1426 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1427 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1428 break; 1429 case AArch64::LDPWpost: 1430 case AArch64::STPWpost: 1431 case AArch64::LDPWpre: 1432 case AArch64::STPWpre: 1433 NeedsDisjointWritebackTransfer = true; 1434 LLVM_FALLTHROUGH; 1435 case AArch64::LDNPWi: 1436 case AArch64::STNPWi: 1437 case AArch64::LDPWi: 1438 case AArch64::STPWi: 1439 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1440 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1441 break; 1442 case AArch64::LDNPQi: 1443 case AArch64::STNPQi: 1444 case AArch64::LDPQpost: 1445 case AArch64::STPQpost: 1446 case AArch64::LDPQi: 1447 case AArch64::STPQi: 1448 case AArch64::LDPQpre: 1449 case AArch64::STPQpre: 1450 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1451 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1452 break; 1453 case AArch64::LDNPDi: 1454 case AArch64::STNPDi: 1455 case AArch64::LDPDpost: 1456 case AArch64::STPDpost: 1457 case AArch64::LDPDi: 1458 case AArch64::STPDi: 1459 case AArch64::LDPDpre: 1460 case AArch64::STPDpre: 1461 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1462 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1463 break; 1464 case AArch64::LDNPSi: 1465 case AArch64::STNPSi: 1466 case AArch64::LDPSpost: 1467 case AArch64::STPSpost: 1468 case AArch64::LDPSi: 1469 case AArch64::STPSi: 1470 case AArch64::LDPSpre: 1471 case AArch64::STPSpre: 1472 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1473 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1474 break; 1475 } 1476 1477 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1478 Inst.addOperand(MCOperand::createImm(offset)); 1479 1480 // You shouldn't load to the same register twice in an instruction... 1481 if (IsLoad && Rt == Rt2) 1482 return SoftFail; 1483 1484 // ... or do any operation that writes-back to a transfer register. But note 1485 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1486 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1487 return SoftFail; 1488 1489 return Success; 1490 } 1491 1492 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1493 uint64_t Addr, 1494 const void *Decoder) { 1495 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1496 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1497 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1498 unsigned extend = fieldFromInstruction(insn, 10, 6); 1499 1500 unsigned shift = extend & 0x7; 1501 if (shift > 4) 1502 return Fail; 1503 1504 switch (Inst.getOpcode()) { 1505 default: 1506 return Fail; 1507 case AArch64::ADDWrx: 1508 case AArch64::SUBWrx: 1509 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1510 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1511 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1512 break; 1513 case AArch64::ADDSWrx: 1514 case AArch64::SUBSWrx: 1515 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1516 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1517 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1518 break; 1519 case AArch64::ADDXrx: 1520 case AArch64::SUBXrx: 1521 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1522 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1523 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1524 break; 1525 case AArch64::ADDSXrx: 1526 case AArch64::SUBSXrx: 1527 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1528 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1529 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1530 break; 1531 case AArch64::ADDXrx64: 1532 case AArch64::SUBXrx64: 1533 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1534 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1535 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1536 break; 1537 case AArch64::SUBSXrx64: 1538 case AArch64::ADDSXrx64: 1539 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1540 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1541 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1542 break; 1543 } 1544 1545 Inst.addOperand(MCOperand::createImm(extend)); 1546 return Success; 1547 } 1548 1549 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1550 uint64_t Addr, 1551 const void *Decoder) { 1552 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1553 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1554 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1555 unsigned imm; 1556 1557 if (Datasize) { 1558 if (Inst.getOpcode() == AArch64::ANDSXri) 1559 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1560 else 1561 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1562 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1563 imm = fieldFromInstruction(insn, 10, 13); 1564 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1565 return Fail; 1566 } else { 1567 if (Inst.getOpcode() == AArch64::ANDSWri) 1568 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1569 else 1570 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1571 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1572 imm = fieldFromInstruction(insn, 10, 12); 1573 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1574 return Fail; 1575 } 1576 Inst.addOperand(MCOperand::createImm(imm)); 1577 return Success; 1578 } 1579 1580 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1581 uint64_t Addr, 1582 const void *Decoder) { 1583 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1584 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1585 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1586 imm |= fieldFromInstruction(insn, 5, 5); 1587 1588 if (Inst.getOpcode() == AArch64::MOVID) 1589 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1590 else 1591 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1592 1593 Inst.addOperand(MCOperand::createImm(imm)); 1594 1595 switch (Inst.getOpcode()) { 1596 default: 1597 break; 1598 case AArch64::MOVIv4i16: 1599 case AArch64::MOVIv8i16: 1600 case AArch64::MVNIv4i16: 1601 case AArch64::MVNIv8i16: 1602 case AArch64::MOVIv2i32: 1603 case AArch64::MOVIv4i32: 1604 case AArch64::MVNIv2i32: 1605 case AArch64::MVNIv4i32: 1606 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1607 break; 1608 case AArch64::MOVIv2s_msl: 1609 case AArch64::MOVIv4s_msl: 1610 case AArch64::MVNIv2s_msl: 1611 case AArch64::MVNIv4s_msl: 1612 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1613 break; 1614 } 1615 1616 return Success; 1617 } 1618 1619 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1620 uint64_t Addr, 1621 const void *Decoder) { 1622 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1623 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1624 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1625 imm |= fieldFromInstruction(insn, 5, 5); 1626 1627 // Tied operands added twice. 1628 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1629 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1630 1631 Inst.addOperand(MCOperand::createImm(imm)); 1632 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1633 1634 return Success; 1635 } 1636 1637 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1638 uint64_t Addr, const void *Decoder) { 1639 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1640 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1641 imm |= fieldFromInstruction(insn, 29, 2); 1642 const AArch64Disassembler *Dis = 1643 static_cast<const AArch64Disassembler *>(Decoder); 1644 1645 // Sign-extend the 21-bit immediate. 1646 if (imm & (1 << (21 - 1))) 1647 imm |= ~((1LL << 21) - 1); 1648 1649 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1650 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1651 Inst.addOperand(MCOperand::createImm(imm)); 1652 1653 return Success; 1654 } 1655 1656 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1657 uint64_t Addr, const void *Decoder) { 1658 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1659 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1660 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1661 unsigned S = fieldFromInstruction(insn, 29, 1); 1662 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1663 1664 unsigned ShifterVal = (Imm >> 12) & 3; 1665 unsigned ImmVal = Imm & 0xFFF; 1666 const AArch64Disassembler *Dis = 1667 static_cast<const AArch64Disassembler *>(Decoder); 1668 1669 if (ShifterVal != 0 && ShifterVal != 1) 1670 return Fail; 1671 1672 if (Datasize) { 1673 if (Rd == 31 && !S) 1674 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1675 else 1676 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1677 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1678 } else { 1679 if (Rd == 31 && !S) 1680 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1681 else 1682 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1683 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1684 } 1685 1686 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1687 Inst.addOperand(MCOperand::createImm(ImmVal)); 1688 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1689 return Success; 1690 } 1691 1692 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1693 uint64_t Addr, 1694 const void *Decoder) { 1695 int64_t imm = fieldFromInstruction(insn, 0, 26); 1696 const AArch64Disassembler *Dis = 1697 static_cast<const AArch64Disassembler *>(Decoder); 1698 1699 // Sign-extend the 26-bit immediate. 1700 if (imm & (1 << (26 - 1))) 1701 imm |= ~((1LL << 26) - 1); 1702 1703 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1704 Inst.addOperand(MCOperand::createImm(imm)); 1705 1706 return Success; 1707 } 1708 1709 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1710 uint64_t Addr, 1711 const void *Decoder) { 1712 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1713 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1714 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1715 1716 uint64_t pstate_field = (op1 << 3) | op2; 1717 1718 if ((pstate_field == AArch64PState::PAN || 1719 pstate_field == AArch64PState::UAO) && crm > 1) 1720 return Fail; 1721 1722 Inst.addOperand(MCOperand::createImm(pstate_field)); 1723 Inst.addOperand(MCOperand::createImm(crm)); 1724 1725 const AArch64Disassembler *Dis = 1726 static_cast<const AArch64Disassembler *>(Decoder); 1727 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1728 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1729 return Success; 1730 return Fail; 1731 } 1732 1733 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1734 uint64_t Addr, const void *Decoder) { 1735 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1736 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1737 bit |= fieldFromInstruction(insn, 19, 5); 1738 int64_t dst = fieldFromInstruction(insn, 5, 14); 1739 const AArch64Disassembler *Dis = 1740 static_cast<const AArch64Disassembler *>(Decoder); 1741 1742 // Sign-extend 14-bit immediate. 1743 if (dst & (1 << (14 - 1))) 1744 dst |= ~((1LL << 14) - 1); 1745 1746 if (fieldFromInstruction(insn, 31, 1) == 0) 1747 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1748 else 1749 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1750 Inst.addOperand(MCOperand::createImm(bit)); 1751 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1752 Inst.addOperand(MCOperand::createImm(dst)); 1753 1754 return Success; 1755 } 1756 1757 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1758 unsigned RegClassID, 1759 unsigned RegNo, 1760 uint64_t Addr, 1761 const void *Decoder) { 1762 // Register number must be even (see CASP instruction) 1763 if (RegNo & 0x1) 1764 return Fail; 1765 1766 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1767 Inst.addOperand(MCOperand::createReg(Register)); 1768 return Success; 1769 } 1770 1771 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1772 unsigned RegNo, 1773 uint64_t Addr, 1774 const void *Decoder) { 1775 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1776 AArch64::WSeqPairsClassRegClassID, 1777 RegNo, Addr, Decoder); 1778 } 1779 1780 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1781 unsigned RegNo, 1782 uint64_t Addr, 1783 const void *Decoder) { 1784 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1785 AArch64::XSeqPairsClassRegClassID, 1786 RegNo, Addr, Decoder); 1787 } 1788 1789 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1790 uint32_t insn, 1791 uint64_t Addr, 1792 const void *Decoder) { 1793 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1794 unsigned imm = fieldFromInstruction(insn, 5, 13); 1795 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1796 return Fail; 1797 1798 // The same (tied) operand is added twice to the instruction. 1799 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1800 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1801 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1802 Inst.addOperand(MCOperand::createImm(imm)); 1803 return Success; 1804 } 1805 1806 template<int Bits> 1807 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1808 uint64_t Address, const void *Decoder) { 1809 if (Imm & ~((1LL << Bits) - 1)) 1810 return Fail; 1811 1812 // Imm is a signed immediate, so sign extend it. 1813 if (Imm & (1 << (Bits - 1))) 1814 Imm |= ~((1LL << Bits) - 1); 1815 1816 Inst.addOperand(MCOperand::createImm(Imm)); 1817 return Success; 1818 } 1819 1820 // Decode 8-bit signed/unsigned immediate for a given element width. 1821 template <int ElementWidth> 1822 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1823 uint64_t Addr, const void *Decoder) { 1824 unsigned Val = (uint8_t)Imm; 1825 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1826 if (ElementWidth == 8 && Shift) 1827 return Fail; 1828 Inst.addOperand(MCOperand::createImm(Val)); 1829 Inst.addOperand(MCOperand::createImm(Shift)); 1830 return Success; 1831 } 1832 1833 // Decode uimm4 ranged from 1-16. 1834 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1835 uint64_t Addr, const void *Decoder) { 1836 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1837 return Success; 1838 } 1839