1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm-c/Disassembler.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include <algorithm> 28 #include <memory> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "aarch64-disassembler" 33 34 // Pull DecodeStatus and its enum values into the global namespace. 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 // Forward declare these because the autogenerated code will reference them. 38 // Definitions are further down. 39 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 40 unsigned RegNo, uint64_t Address, 41 const void *Decoder); 42 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 43 unsigned RegNo, 44 uint64_t Address, 45 const void *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const void *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const void *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const void *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const void *Decoder); 58 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 59 uint64_t Address, 60 const void *Decoder); 61 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 62 unsigned RegNo, uint64_t Address, 63 const void *Decoder); 64 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 65 uint64_t Address, 66 const void *Decoder); 67 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 68 unsigned RegNo, uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decode); 91 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decode); 94 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decode); 97 98 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 99 uint64_t Address, 100 const void *Decoder); 101 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 102 uint64_t Address, 103 const void *Decoder); 104 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 105 uint64_t Address, const void *Decoder); 106 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 116 uint64_t Address, 117 const void *Decoder); 118 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 134 uint64_t Address, 135 const void *Decoder); 136 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 137 uint64_t Address, 138 const void *Decoder); 139 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 140 uint64_t Address, 141 const void *Decoder); 142 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 153 uint64_t Address, const void *Decoder); 154 155 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 159 uint64_t Addr, const void *Decoder); 160 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 161 uint64_t Addr, 162 const void *Decoder); 163 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 164 uint64_t Addr, const void *Decoder); 165 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 166 uint64_t Addr, 167 const void *Decoder); 168 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 169 uint64_t Addr, const void *Decoder); 170 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, 172 const void *Decoder); 173 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 174 uint64_t Addr, const void *Decoder); 175 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 176 uint64_t Addr, const void *Decoder); 177 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, const void *Decoder); 179 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 180 uint64_t Addr, const void *Decoder); 181 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 182 uint64_t Addr, const void *Decoder); 183 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 184 unsigned RegNo, 185 uint64_t Addr, 186 const void *Decoder); 187 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Addr, 190 const void *Decoder); 191 template<int Bits> 192 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 193 uint64_t Address, const void *Decoder); 194 195 static bool Check(DecodeStatus &Out, DecodeStatus In) { 196 switch (In) { 197 case MCDisassembler::Success: 198 // Out stays the same. 199 return true; 200 case MCDisassembler::SoftFail: 201 Out = In; 202 return true; 203 case MCDisassembler::Fail: 204 Out = In; 205 return false; 206 } 207 llvm_unreachable("Invalid DecodeStatus!"); 208 } 209 210 #include "AArch64GenDisassemblerTables.inc" 211 #include "AArch64GenInstrInfo.inc" 212 213 #define Success MCDisassembler::Success 214 #define Fail MCDisassembler::Fail 215 #define SoftFail MCDisassembler::SoftFail 216 217 static MCDisassembler *createAArch64Disassembler(const Target &T, 218 const MCSubtargetInfo &STI, 219 MCContext &Ctx) { 220 return new AArch64Disassembler(STI, Ctx); 221 } 222 223 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 224 ArrayRef<uint8_t> Bytes, 225 uint64_t Address, 226 raw_ostream &OS, 227 raw_ostream &CS) const { 228 CommentStream = &CS; 229 230 Size = 0; 231 // We want to read exactly 4 bytes of data. 232 if (Bytes.size() < 4) 233 return Fail; 234 Size = 4; 235 236 // Encoded as a small-endian 32-bit word in the stream. 237 uint32_t Insn = 238 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 239 240 // Calling the auto-generated decoder function. 241 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 242 } 243 244 static MCSymbolizer * 245 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 246 LLVMSymbolLookupCallback SymbolLookUp, 247 void *DisInfo, MCContext *Ctx, 248 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 249 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 250 SymbolLookUp, DisInfo); 251 } 252 253 extern "C" void LLVMInitializeAArch64Disassembler() { 254 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 255 createAArch64Disassembler); 256 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 257 createAArch64Disassembler); 258 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 259 createAArch64ExternalSymbolizer); 260 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 261 createAArch64ExternalSymbolizer); 262 263 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 264 createAArch64Disassembler); 265 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 266 createAArch64ExternalSymbolizer); 267 } 268 269 static const unsigned FPR128DecoderTable[] = { 270 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 271 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 272 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 273 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 274 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 275 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 276 AArch64::Q30, AArch64::Q31 277 }; 278 279 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 280 uint64_t Addr, 281 const void *Decoder) { 282 if (RegNo > 31) 283 return Fail; 284 285 unsigned Register = FPR128DecoderTable[RegNo]; 286 Inst.addOperand(MCOperand::createReg(Register)); 287 return Success; 288 } 289 290 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 291 uint64_t Addr, 292 const void *Decoder) { 293 if (RegNo > 15) 294 return Fail; 295 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 296 } 297 298 static const unsigned FPR64DecoderTable[] = { 299 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 300 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 301 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 302 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 303 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 304 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 305 AArch64::D30, AArch64::D31 306 }; 307 308 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 309 uint64_t Addr, 310 const void *Decoder) { 311 if (RegNo > 31) 312 return Fail; 313 314 unsigned Register = FPR64DecoderTable[RegNo]; 315 Inst.addOperand(MCOperand::createReg(Register)); 316 return Success; 317 } 318 319 static const unsigned FPR32DecoderTable[] = { 320 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 321 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 322 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 323 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 324 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 325 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 326 AArch64::S30, AArch64::S31 327 }; 328 329 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 330 uint64_t Addr, 331 const void *Decoder) { 332 if (RegNo > 31) 333 return Fail; 334 335 unsigned Register = FPR32DecoderTable[RegNo]; 336 Inst.addOperand(MCOperand::createReg(Register)); 337 return Success; 338 } 339 340 static const unsigned FPR16DecoderTable[] = { 341 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 342 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 343 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 344 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 345 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 346 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 347 AArch64::H30, AArch64::H31 348 }; 349 350 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 351 uint64_t Addr, 352 const void *Decoder) { 353 if (RegNo > 31) 354 return Fail; 355 356 unsigned Register = FPR16DecoderTable[RegNo]; 357 Inst.addOperand(MCOperand::createReg(Register)); 358 return Success; 359 } 360 361 static const unsigned FPR8DecoderTable[] = { 362 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 363 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 364 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 365 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 366 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 367 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 368 AArch64::B30, AArch64::B31 369 }; 370 371 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 372 uint64_t Addr, 373 const void *Decoder) { 374 if (RegNo > 31) 375 return Fail; 376 377 unsigned Register = FPR8DecoderTable[RegNo]; 378 Inst.addOperand(MCOperand::createReg(Register)); 379 return Success; 380 } 381 382 static const unsigned GPR64DecoderTable[] = { 383 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 384 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 385 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 386 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 387 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 388 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 389 AArch64::LR, AArch64::XZR 390 }; 391 392 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 393 uint64_t Addr, 394 const void *Decoder) { 395 if (RegNo > 31) 396 return Fail; 397 398 unsigned Register = GPR64DecoderTable[RegNo]; 399 Inst.addOperand(MCOperand::createReg(Register)); 400 return Success; 401 } 402 403 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 404 uint64_t Addr, 405 const void *Decoder) { 406 if (RegNo > 31) 407 return Fail; 408 unsigned Register = GPR64DecoderTable[RegNo]; 409 if (Register == AArch64::XZR) 410 Register = AArch64::SP; 411 Inst.addOperand(MCOperand::createReg(Register)); 412 return Success; 413 } 414 415 static const unsigned GPR32DecoderTable[] = { 416 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 417 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 418 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 419 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 420 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 421 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 422 AArch64::W30, AArch64::WZR 423 }; 424 425 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 426 uint64_t Addr, 427 const void *Decoder) { 428 if (RegNo > 31) 429 return Fail; 430 431 unsigned Register = GPR32DecoderTable[RegNo]; 432 Inst.addOperand(MCOperand::createReg(Register)); 433 return Success; 434 } 435 436 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 437 uint64_t Addr, 438 const void *Decoder) { 439 if (RegNo > 31) 440 return Fail; 441 442 unsigned Register = GPR32DecoderTable[RegNo]; 443 if (Register == AArch64::WZR) 444 Register = AArch64::WSP; 445 Inst.addOperand(MCOperand::createReg(Register)); 446 return Success; 447 } 448 static const unsigned ZPRDecoderTable[] = { 449 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 450 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 451 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 452 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 453 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 454 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 455 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 456 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 457 }; 458 459 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 460 uint64_t Address, 461 const void* Decoder) { 462 if (RegNo > 31) 463 return Fail; 464 465 unsigned Register = ZPRDecoderTable[RegNo]; 466 Inst.addOperand(MCOperand::createReg(Register)); 467 return Success; 468 } 469 470 static const unsigned PPRDecoderTable[] = { 471 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 472 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 473 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 474 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 475 }; 476 477 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 478 uint64_t Addr, const void *Decoder) { 479 if (RegNo > 15) 480 return Fail; 481 482 unsigned Register = PPRDecoderTable[RegNo]; 483 Inst.addOperand(MCOperand::createReg(Register)); 484 return Success; 485 } 486 487 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 488 uint64_t Addr, 489 const void* Decoder) { 490 if (RegNo > 7) 491 return Fail; 492 493 // Just reuse the PPR decode table 494 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 495 } 496 497 static const unsigned VectorDecoderTable[] = { 498 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 499 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 500 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 501 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 502 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 503 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 504 AArch64::Q30, AArch64::Q31 505 }; 506 507 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 508 uint64_t Addr, 509 const void *Decoder) { 510 if (RegNo > 31) 511 return Fail; 512 513 unsigned Register = VectorDecoderTable[RegNo]; 514 Inst.addOperand(MCOperand::createReg(Register)); 515 return Success; 516 } 517 518 static const unsigned QQDecoderTable[] = { 519 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 520 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 521 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 522 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 523 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 524 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 525 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 526 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 527 }; 528 529 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 530 uint64_t Addr, const void *Decoder) { 531 if (RegNo > 31) 532 return Fail; 533 unsigned Register = QQDecoderTable[RegNo]; 534 Inst.addOperand(MCOperand::createReg(Register)); 535 return Success; 536 } 537 538 static const unsigned QQQDecoderTable[] = { 539 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 540 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 541 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 542 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 543 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 544 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 545 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 546 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 547 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 548 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 549 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 550 }; 551 552 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 553 uint64_t Addr, const void *Decoder) { 554 if (RegNo > 31) 555 return Fail; 556 unsigned Register = QQQDecoderTable[RegNo]; 557 Inst.addOperand(MCOperand::createReg(Register)); 558 return Success; 559 } 560 561 static const unsigned QQQQDecoderTable[] = { 562 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 563 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 564 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 565 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 566 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 567 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 568 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 569 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 570 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 571 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 572 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 573 }; 574 575 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 576 uint64_t Addr, 577 const void *Decoder) { 578 if (RegNo > 31) 579 return Fail; 580 unsigned Register = QQQQDecoderTable[RegNo]; 581 Inst.addOperand(MCOperand::createReg(Register)); 582 return Success; 583 } 584 585 static const unsigned DDDecoderTable[] = { 586 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 587 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 588 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 589 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 590 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 591 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 592 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 593 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 594 }; 595 596 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 597 uint64_t Addr, const void *Decoder) { 598 if (RegNo > 31) 599 return Fail; 600 unsigned Register = DDDecoderTable[RegNo]; 601 Inst.addOperand(MCOperand::createReg(Register)); 602 return Success; 603 } 604 605 static const unsigned DDDDecoderTable[] = { 606 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 607 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 608 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 609 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 610 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 611 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 612 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 613 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 614 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 615 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 616 AArch64::D30_D31_D0, AArch64::D31_D0_D1 617 }; 618 619 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 620 uint64_t Addr, const void *Decoder) { 621 if (RegNo > 31) 622 return Fail; 623 unsigned Register = DDDDecoderTable[RegNo]; 624 Inst.addOperand(MCOperand::createReg(Register)); 625 return Success; 626 } 627 628 static const unsigned DDDDDecoderTable[] = { 629 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 630 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 631 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 632 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 633 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 634 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 635 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 636 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 637 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 638 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 639 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 640 }; 641 642 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 643 uint64_t Addr, 644 const void *Decoder) { 645 if (RegNo > 31) 646 return Fail; 647 unsigned Register = DDDDDecoderTable[RegNo]; 648 Inst.addOperand(MCOperand::createReg(Register)); 649 return Success; 650 } 651 652 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 653 uint64_t Addr, 654 const void *Decoder) { 655 // scale{5} is asserted as 1 in tblgen. 656 Imm |= 0x20; 657 Inst.addOperand(MCOperand::createImm(64 - Imm)); 658 return Success; 659 } 660 661 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 662 uint64_t Addr, 663 const void *Decoder) { 664 Inst.addOperand(MCOperand::createImm(64 - Imm)); 665 return Success; 666 } 667 668 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 669 uint64_t Addr, const void *Decoder) { 670 int64_t ImmVal = Imm; 671 const AArch64Disassembler *Dis = 672 static_cast<const AArch64Disassembler *>(Decoder); 673 674 // Sign-extend 19-bit immediate. 675 if (ImmVal & (1 << (19 - 1))) 676 ImmVal |= ~((1LL << 19) - 1); 677 678 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 679 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 680 Inst.addOperand(MCOperand::createImm(ImmVal)); 681 return Success; 682 } 683 684 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 685 uint64_t Address, const void *Decoder) { 686 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 687 Inst.addOperand(MCOperand::createImm(Imm & 1)); 688 return Success; 689 } 690 691 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 692 uint64_t Address, 693 const void *Decoder) { 694 Inst.addOperand(MCOperand::createImm(Imm)); 695 696 // Every system register in the encoding space is valid with the syntax 697 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 698 return Success; 699 } 700 701 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 702 uint64_t Address, 703 const void *Decoder) { 704 Inst.addOperand(MCOperand::createImm(Imm)); 705 706 return Success; 707 } 708 709 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 710 uint64_t Address, 711 const void *Decoder) { 712 // This decoder exists to add the dummy Lane operand to the MCInst, which must 713 // be 1 in assembly but has no other real manifestation. 714 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 715 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 716 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 717 718 if (IsToVec) { 719 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 720 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 721 } else { 722 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 723 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 724 } 725 726 // Add the lane 727 Inst.addOperand(MCOperand::createImm(1)); 728 729 return Success; 730 } 731 732 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 733 unsigned Add) { 734 Inst.addOperand(MCOperand::createImm(Add - Imm)); 735 return Success; 736 } 737 738 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 739 unsigned Add) { 740 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 741 return Success; 742 } 743 744 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 745 uint64_t Addr, const void *Decoder) { 746 return DecodeVecShiftRImm(Inst, Imm, 64); 747 } 748 749 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 750 uint64_t Addr, 751 const void *Decoder) { 752 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 753 } 754 755 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 756 uint64_t Addr, const void *Decoder) { 757 return DecodeVecShiftRImm(Inst, Imm, 32); 758 } 759 760 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 761 uint64_t Addr, 762 const void *Decoder) { 763 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 764 } 765 766 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 767 uint64_t Addr, const void *Decoder) { 768 return DecodeVecShiftRImm(Inst, Imm, 16); 769 } 770 771 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 772 uint64_t Addr, 773 const void *Decoder) { 774 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 775 } 776 777 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 778 uint64_t Addr, const void *Decoder) { 779 return DecodeVecShiftRImm(Inst, Imm, 8); 780 } 781 782 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 783 uint64_t Addr, const void *Decoder) { 784 return DecodeVecShiftLImm(Inst, Imm, 64); 785 } 786 787 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 788 uint64_t Addr, const void *Decoder) { 789 return DecodeVecShiftLImm(Inst, Imm, 32); 790 } 791 792 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 793 uint64_t Addr, const void *Decoder) { 794 return DecodeVecShiftLImm(Inst, Imm, 16); 795 } 796 797 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 798 uint64_t Addr, const void *Decoder) { 799 return DecodeVecShiftLImm(Inst, Imm, 8); 800 } 801 802 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 803 uint64_t Addr, 804 const void *Decoder) { 805 unsigned Rd = fieldFromInstruction(insn, 0, 5); 806 unsigned Rn = fieldFromInstruction(insn, 5, 5); 807 unsigned Rm = fieldFromInstruction(insn, 16, 5); 808 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 809 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 810 unsigned shift = (shiftHi << 6) | shiftLo; 811 switch (Inst.getOpcode()) { 812 default: 813 return Fail; 814 case AArch64::ADDWrs: 815 case AArch64::ADDSWrs: 816 case AArch64::SUBWrs: 817 case AArch64::SUBSWrs: 818 // if shift == '11' then ReservedValue() 819 if (shiftHi == 0x3) 820 return Fail; 821 LLVM_FALLTHROUGH; 822 case AArch64::ANDWrs: 823 case AArch64::ANDSWrs: 824 case AArch64::BICWrs: 825 case AArch64::BICSWrs: 826 case AArch64::ORRWrs: 827 case AArch64::ORNWrs: 828 case AArch64::EORWrs: 829 case AArch64::EONWrs: { 830 // if sf == '0' and imm6<5> == '1' then ReservedValue() 831 if (shiftLo >> 5 == 1) 832 return Fail; 833 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 834 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 835 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 836 break; 837 } 838 case AArch64::ADDXrs: 839 case AArch64::ADDSXrs: 840 case AArch64::SUBXrs: 841 case AArch64::SUBSXrs: 842 // if shift == '11' then ReservedValue() 843 if (shiftHi == 0x3) 844 return Fail; 845 LLVM_FALLTHROUGH; 846 case AArch64::ANDXrs: 847 case AArch64::ANDSXrs: 848 case AArch64::BICXrs: 849 case AArch64::BICSXrs: 850 case AArch64::ORRXrs: 851 case AArch64::ORNXrs: 852 case AArch64::EORXrs: 853 case AArch64::EONXrs: 854 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 855 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 856 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 857 break; 858 } 859 860 Inst.addOperand(MCOperand::createImm(shift)); 861 return Success; 862 } 863 864 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 865 uint64_t Addr, 866 const void *Decoder) { 867 unsigned Rd = fieldFromInstruction(insn, 0, 5); 868 unsigned imm = fieldFromInstruction(insn, 5, 16); 869 unsigned shift = fieldFromInstruction(insn, 21, 2); 870 shift <<= 4; 871 switch (Inst.getOpcode()) { 872 default: 873 return Fail; 874 case AArch64::MOVZWi: 875 case AArch64::MOVNWi: 876 case AArch64::MOVKWi: 877 if (shift & (1U << 5)) 878 return Fail; 879 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 880 break; 881 case AArch64::MOVZXi: 882 case AArch64::MOVNXi: 883 case AArch64::MOVKXi: 884 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 885 break; 886 } 887 888 if (Inst.getOpcode() == AArch64::MOVKWi || 889 Inst.getOpcode() == AArch64::MOVKXi) 890 Inst.addOperand(Inst.getOperand(0)); 891 892 Inst.addOperand(MCOperand::createImm(imm)); 893 Inst.addOperand(MCOperand::createImm(shift)); 894 return Success; 895 } 896 897 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 898 uint64_t Addr, 899 const void *Decoder) { 900 unsigned Rt = fieldFromInstruction(insn, 0, 5); 901 unsigned Rn = fieldFromInstruction(insn, 5, 5); 902 unsigned offset = fieldFromInstruction(insn, 10, 12); 903 const AArch64Disassembler *Dis = 904 static_cast<const AArch64Disassembler *>(Decoder); 905 906 switch (Inst.getOpcode()) { 907 default: 908 return Fail; 909 case AArch64::PRFMui: 910 // Rt is an immediate in prefetch. 911 Inst.addOperand(MCOperand::createImm(Rt)); 912 break; 913 case AArch64::STRBBui: 914 case AArch64::LDRBBui: 915 case AArch64::LDRSBWui: 916 case AArch64::STRHHui: 917 case AArch64::LDRHHui: 918 case AArch64::LDRSHWui: 919 case AArch64::STRWui: 920 case AArch64::LDRWui: 921 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 922 break; 923 case AArch64::LDRSBXui: 924 case AArch64::LDRSHXui: 925 case AArch64::LDRSWui: 926 case AArch64::STRXui: 927 case AArch64::LDRXui: 928 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 929 break; 930 case AArch64::LDRQui: 931 case AArch64::STRQui: 932 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 933 break; 934 case AArch64::LDRDui: 935 case AArch64::STRDui: 936 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 937 break; 938 case AArch64::LDRSui: 939 case AArch64::STRSui: 940 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 941 break; 942 case AArch64::LDRHui: 943 case AArch64::STRHui: 944 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 945 break; 946 case AArch64::LDRBui: 947 case AArch64::STRBui: 948 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 949 break; 950 } 951 952 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 953 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 954 Inst.addOperand(MCOperand::createImm(offset)); 955 return Success; 956 } 957 958 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 959 uint64_t Addr, 960 const void *Decoder) { 961 unsigned Rt = fieldFromInstruction(insn, 0, 5); 962 unsigned Rn = fieldFromInstruction(insn, 5, 5); 963 int64_t offset = fieldFromInstruction(insn, 12, 9); 964 965 // offset is a 9-bit signed immediate, so sign extend it to 966 // fill the unsigned. 967 if (offset & (1 << (9 - 1))) 968 offset |= ~((1LL << 9) - 1); 969 970 // First operand is always the writeback to the address register, if needed. 971 switch (Inst.getOpcode()) { 972 default: 973 break; 974 case AArch64::LDRSBWpre: 975 case AArch64::LDRSHWpre: 976 case AArch64::STRBBpre: 977 case AArch64::LDRBBpre: 978 case AArch64::STRHHpre: 979 case AArch64::LDRHHpre: 980 case AArch64::STRWpre: 981 case AArch64::LDRWpre: 982 case AArch64::LDRSBWpost: 983 case AArch64::LDRSHWpost: 984 case AArch64::STRBBpost: 985 case AArch64::LDRBBpost: 986 case AArch64::STRHHpost: 987 case AArch64::LDRHHpost: 988 case AArch64::STRWpost: 989 case AArch64::LDRWpost: 990 case AArch64::LDRSBXpre: 991 case AArch64::LDRSHXpre: 992 case AArch64::STRXpre: 993 case AArch64::LDRSWpre: 994 case AArch64::LDRXpre: 995 case AArch64::LDRSBXpost: 996 case AArch64::LDRSHXpost: 997 case AArch64::STRXpost: 998 case AArch64::LDRSWpost: 999 case AArch64::LDRXpost: 1000 case AArch64::LDRQpre: 1001 case AArch64::STRQpre: 1002 case AArch64::LDRQpost: 1003 case AArch64::STRQpost: 1004 case AArch64::LDRDpre: 1005 case AArch64::STRDpre: 1006 case AArch64::LDRDpost: 1007 case AArch64::STRDpost: 1008 case AArch64::LDRSpre: 1009 case AArch64::STRSpre: 1010 case AArch64::LDRSpost: 1011 case AArch64::STRSpost: 1012 case AArch64::LDRHpre: 1013 case AArch64::STRHpre: 1014 case AArch64::LDRHpost: 1015 case AArch64::STRHpost: 1016 case AArch64::LDRBpre: 1017 case AArch64::STRBpre: 1018 case AArch64::LDRBpost: 1019 case AArch64::STRBpost: 1020 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1021 break; 1022 } 1023 1024 switch (Inst.getOpcode()) { 1025 default: 1026 return Fail; 1027 case AArch64::PRFUMi: 1028 // Rt is an immediate in prefetch. 1029 Inst.addOperand(MCOperand::createImm(Rt)); 1030 break; 1031 case AArch64::STURBBi: 1032 case AArch64::LDURBBi: 1033 case AArch64::LDURSBWi: 1034 case AArch64::STURHHi: 1035 case AArch64::LDURHHi: 1036 case AArch64::LDURSHWi: 1037 case AArch64::STURWi: 1038 case AArch64::LDURWi: 1039 case AArch64::LDTRSBWi: 1040 case AArch64::LDTRSHWi: 1041 case AArch64::STTRWi: 1042 case AArch64::LDTRWi: 1043 case AArch64::STTRHi: 1044 case AArch64::LDTRHi: 1045 case AArch64::LDTRBi: 1046 case AArch64::STTRBi: 1047 case AArch64::LDRSBWpre: 1048 case AArch64::LDRSHWpre: 1049 case AArch64::STRBBpre: 1050 case AArch64::LDRBBpre: 1051 case AArch64::STRHHpre: 1052 case AArch64::LDRHHpre: 1053 case AArch64::STRWpre: 1054 case AArch64::LDRWpre: 1055 case AArch64::LDRSBWpost: 1056 case AArch64::LDRSHWpost: 1057 case AArch64::STRBBpost: 1058 case AArch64::LDRBBpost: 1059 case AArch64::STRHHpost: 1060 case AArch64::LDRHHpost: 1061 case AArch64::STRWpost: 1062 case AArch64::LDRWpost: 1063 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1064 break; 1065 case AArch64::LDURSBXi: 1066 case AArch64::LDURSHXi: 1067 case AArch64::LDURSWi: 1068 case AArch64::STURXi: 1069 case AArch64::LDURXi: 1070 case AArch64::LDTRSBXi: 1071 case AArch64::LDTRSHXi: 1072 case AArch64::LDTRSWi: 1073 case AArch64::STTRXi: 1074 case AArch64::LDTRXi: 1075 case AArch64::LDRSBXpre: 1076 case AArch64::LDRSHXpre: 1077 case AArch64::STRXpre: 1078 case AArch64::LDRSWpre: 1079 case AArch64::LDRXpre: 1080 case AArch64::LDRSBXpost: 1081 case AArch64::LDRSHXpost: 1082 case AArch64::STRXpost: 1083 case AArch64::LDRSWpost: 1084 case AArch64::LDRXpost: 1085 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1086 break; 1087 case AArch64::LDURQi: 1088 case AArch64::STURQi: 1089 case AArch64::LDRQpre: 1090 case AArch64::STRQpre: 1091 case AArch64::LDRQpost: 1092 case AArch64::STRQpost: 1093 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1094 break; 1095 case AArch64::LDURDi: 1096 case AArch64::STURDi: 1097 case AArch64::LDRDpre: 1098 case AArch64::STRDpre: 1099 case AArch64::LDRDpost: 1100 case AArch64::STRDpost: 1101 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1102 break; 1103 case AArch64::LDURSi: 1104 case AArch64::STURSi: 1105 case AArch64::LDRSpre: 1106 case AArch64::STRSpre: 1107 case AArch64::LDRSpost: 1108 case AArch64::STRSpost: 1109 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1110 break; 1111 case AArch64::LDURHi: 1112 case AArch64::STURHi: 1113 case AArch64::LDRHpre: 1114 case AArch64::STRHpre: 1115 case AArch64::LDRHpost: 1116 case AArch64::STRHpost: 1117 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1118 break; 1119 case AArch64::LDURBi: 1120 case AArch64::STURBi: 1121 case AArch64::LDRBpre: 1122 case AArch64::STRBpre: 1123 case AArch64::LDRBpost: 1124 case AArch64::STRBpost: 1125 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1126 break; 1127 } 1128 1129 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1130 Inst.addOperand(MCOperand::createImm(offset)); 1131 1132 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1133 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1134 bool IsFP = fieldFromInstruction(insn, 26, 1); 1135 1136 // Cannot write back to a transfer register (but xzr != sp). 1137 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1138 return SoftFail; 1139 1140 return Success; 1141 } 1142 1143 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1144 uint64_t Addr, 1145 const void *Decoder) { 1146 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1147 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1148 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1149 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1150 1151 unsigned Opcode = Inst.getOpcode(); 1152 switch (Opcode) { 1153 default: 1154 return Fail; 1155 case AArch64::STLXRW: 1156 case AArch64::STLXRB: 1157 case AArch64::STLXRH: 1158 case AArch64::STXRW: 1159 case AArch64::STXRB: 1160 case AArch64::STXRH: 1161 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1162 LLVM_FALLTHROUGH; 1163 case AArch64::LDARW: 1164 case AArch64::LDARB: 1165 case AArch64::LDARH: 1166 case AArch64::LDAXRW: 1167 case AArch64::LDAXRB: 1168 case AArch64::LDAXRH: 1169 case AArch64::LDXRW: 1170 case AArch64::LDXRB: 1171 case AArch64::LDXRH: 1172 case AArch64::STLRW: 1173 case AArch64::STLRB: 1174 case AArch64::STLRH: 1175 case AArch64::STLLRW: 1176 case AArch64::STLLRB: 1177 case AArch64::STLLRH: 1178 case AArch64::LDLARW: 1179 case AArch64::LDLARB: 1180 case AArch64::LDLARH: 1181 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1182 break; 1183 case AArch64::STLXRX: 1184 case AArch64::STXRX: 1185 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1186 LLVM_FALLTHROUGH; 1187 case AArch64::LDARX: 1188 case AArch64::LDAXRX: 1189 case AArch64::LDXRX: 1190 case AArch64::STLRX: 1191 case AArch64::LDLARX: 1192 case AArch64::STLLRX: 1193 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1194 break; 1195 case AArch64::STLXPW: 1196 case AArch64::STXPW: 1197 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1198 LLVM_FALLTHROUGH; 1199 case AArch64::LDAXPW: 1200 case AArch64::LDXPW: 1201 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1202 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1203 break; 1204 case AArch64::STLXPX: 1205 case AArch64::STXPX: 1206 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1207 LLVM_FALLTHROUGH; 1208 case AArch64::LDAXPX: 1209 case AArch64::LDXPX: 1210 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1211 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1212 break; 1213 } 1214 1215 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1216 1217 // You shouldn't load to the same register twice in an instruction... 1218 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1219 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1220 Rt == Rt2) 1221 return SoftFail; 1222 1223 return Success; 1224 } 1225 1226 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1227 uint64_t Addr, 1228 const void *Decoder) { 1229 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1230 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1231 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1232 int64_t offset = fieldFromInstruction(insn, 15, 7); 1233 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1234 1235 // offset is a 7-bit signed immediate, so sign extend it to 1236 // fill the unsigned. 1237 if (offset & (1 << (7 - 1))) 1238 offset |= ~((1LL << 7) - 1); 1239 1240 unsigned Opcode = Inst.getOpcode(); 1241 bool NeedsDisjointWritebackTransfer = false; 1242 1243 // First operand is always writeback of base register. 1244 switch (Opcode) { 1245 default: 1246 break; 1247 case AArch64::LDPXpost: 1248 case AArch64::STPXpost: 1249 case AArch64::LDPSWpost: 1250 case AArch64::LDPXpre: 1251 case AArch64::STPXpre: 1252 case AArch64::LDPSWpre: 1253 case AArch64::LDPWpost: 1254 case AArch64::STPWpost: 1255 case AArch64::LDPWpre: 1256 case AArch64::STPWpre: 1257 case AArch64::LDPQpost: 1258 case AArch64::STPQpost: 1259 case AArch64::LDPQpre: 1260 case AArch64::STPQpre: 1261 case AArch64::LDPDpost: 1262 case AArch64::STPDpost: 1263 case AArch64::LDPDpre: 1264 case AArch64::STPDpre: 1265 case AArch64::LDPSpost: 1266 case AArch64::STPSpost: 1267 case AArch64::LDPSpre: 1268 case AArch64::STPSpre: 1269 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1270 break; 1271 } 1272 1273 switch (Opcode) { 1274 default: 1275 return Fail; 1276 case AArch64::LDPXpost: 1277 case AArch64::STPXpost: 1278 case AArch64::LDPSWpost: 1279 case AArch64::LDPXpre: 1280 case AArch64::STPXpre: 1281 case AArch64::LDPSWpre: 1282 NeedsDisjointWritebackTransfer = true; 1283 LLVM_FALLTHROUGH; 1284 case AArch64::LDNPXi: 1285 case AArch64::STNPXi: 1286 case AArch64::LDPXi: 1287 case AArch64::STPXi: 1288 case AArch64::LDPSWi: 1289 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1290 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1291 break; 1292 case AArch64::LDPWpost: 1293 case AArch64::STPWpost: 1294 case AArch64::LDPWpre: 1295 case AArch64::STPWpre: 1296 NeedsDisjointWritebackTransfer = true; 1297 LLVM_FALLTHROUGH; 1298 case AArch64::LDNPWi: 1299 case AArch64::STNPWi: 1300 case AArch64::LDPWi: 1301 case AArch64::STPWi: 1302 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1303 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1304 break; 1305 case AArch64::LDNPQi: 1306 case AArch64::STNPQi: 1307 case AArch64::LDPQpost: 1308 case AArch64::STPQpost: 1309 case AArch64::LDPQi: 1310 case AArch64::STPQi: 1311 case AArch64::LDPQpre: 1312 case AArch64::STPQpre: 1313 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1314 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1315 break; 1316 case AArch64::LDNPDi: 1317 case AArch64::STNPDi: 1318 case AArch64::LDPDpost: 1319 case AArch64::STPDpost: 1320 case AArch64::LDPDi: 1321 case AArch64::STPDi: 1322 case AArch64::LDPDpre: 1323 case AArch64::STPDpre: 1324 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1325 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1326 break; 1327 case AArch64::LDNPSi: 1328 case AArch64::STNPSi: 1329 case AArch64::LDPSpost: 1330 case AArch64::STPSpost: 1331 case AArch64::LDPSi: 1332 case AArch64::STPSi: 1333 case AArch64::LDPSpre: 1334 case AArch64::STPSpre: 1335 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1336 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1337 break; 1338 } 1339 1340 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1341 Inst.addOperand(MCOperand::createImm(offset)); 1342 1343 // You shouldn't load to the same register twice in an instruction... 1344 if (IsLoad && Rt == Rt2) 1345 return SoftFail; 1346 1347 // ... or do any operation that writes-back to a transfer register. But note 1348 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1349 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1350 return SoftFail; 1351 1352 return Success; 1353 } 1354 1355 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1356 uint64_t Addr, 1357 const void *Decoder) { 1358 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1359 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1360 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1361 unsigned extend = fieldFromInstruction(insn, 10, 6); 1362 1363 unsigned shift = extend & 0x7; 1364 if (shift > 4) 1365 return Fail; 1366 1367 switch (Inst.getOpcode()) { 1368 default: 1369 return Fail; 1370 case AArch64::ADDWrx: 1371 case AArch64::SUBWrx: 1372 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1373 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1374 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1375 break; 1376 case AArch64::ADDSWrx: 1377 case AArch64::SUBSWrx: 1378 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1379 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1380 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1381 break; 1382 case AArch64::ADDXrx: 1383 case AArch64::SUBXrx: 1384 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1385 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1386 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1387 break; 1388 case AArch64::ADDSXrx: 1389 case AArch64::SUBSXrx: 1390 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1391 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1392 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1393 break; 1394 case AArch64::ADDXrx64: 1395 case AArch64::SUBXrx64: 1396 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1397 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1398 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1399 break; 1400 case AArch64::SUBSXrx64: 1401 case AArch64::ADDSXrx64: 1402 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1403 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1404 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1405 break; 1406 } 1407 1408 Inst.addOperand(MCOperand::createImm(extend)); 1409 return Success; 1410 } 1411 1412 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1413 uint64_t Addr, 1414 const void *Decoder) { 1415 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1416 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1417 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1418 unsigned imm; 1419 1420 if (Datasize) { 1421 if (Inst.getOpcode() == AArch64::ANDSXri) 1422 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1423 else 1424 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1425 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1426 imm = fieldFromInstruction(insn, 10, 13); 1427 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1428 return Fail; 1429 } else { 1430 if (Inst.getOpcode() == AArch64::ANDSWri) 1431 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1432 else 1433 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1434 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1435 imm = fieldFromInstruction(insn, 10, 12); 1436 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1437 return Fail; 1438 } 1439 Inst.addOperand(MCOperand::createImm(imm)); 1440 return Success; 1441 } 1442 1443 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1444 uint64_t Addr, 1445 const void *Decoder) { 1446 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1447 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1448 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1449 imm |= fieldFromInstruction(insn, 5, 5); 1450 1451 if (Inst.getOpcode() == AArch64::MOVID) 1452 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1453 else 1454 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1455 1456 Inst.addOperand(MCOperand::createImm(imm)); 1457 1458 switch (Inst.getOpcode()) { 1459 default: 1460 break; 1461 case AArch64::MOVIv4i16: 1462 case AArch64::MOVIv8i16: 1463 case AArch64::MVNIv4i16: 1464 case AArch64::MVNIv8i16: 1465 case AArch64::MOVIv2i32: 1466 case AArch64::MOVIv4i32: 1467 case AArch64::MVNIv2i32: 1468 case AArch64::MVNIv4i32: 1469 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1470 break; 1471 case AArch64::MOVIv2s_msl: 1472 case AArch64::MOVIv4s_msl: 1473 case AArch64::MVNIv2s_msl: 1474 case AArch64::MVNIv4s_msl: 1475 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1476 break; 1477 } 1478 1479 return Success; 1480 } 1481 1482 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1483 uint64_t Addr, 1484 const void *Decoder) { 1485 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1486 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1487 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1488 imm |= fieldFromInstruction(insn, 5, 5); 1489 1490 // Tied operands added twice. 1491 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1492 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1493 1494 Inst.addOperand(MCOperand::createImm(imm)); 1495 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1496 1497 return Success; 1498 } 1499 1500 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1501 uint64_t Addr, const void *Decoder) { 1502 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1503 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1504 imm |= fieldFromInstruction(insn, 29, 2); 1505 const AArch64Disassembler *Dis = 1506 static_cast<const AArch64Disassembler *>(Decoder); 1507 1508 // Sign-extend the 21-bit immediate. 1509 if (imm & (1 << (21 - 1))) 1510 imm |= ~((1LL << 21) - 1); 1511 1512 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1513 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1514 Inst.addOperand(MCOperand::createImm(imm)); 1515 1516 return Success; 1517 } 1518 1519 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1520 uint64_t Addr, const void *Decoder) { 1521 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1522 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1523 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1524 unsigned S = fieldFromInstruction(insn, 29, 1); 1525 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1526 1527 unsigned ShifterVal = (Imm >> 12) & 3; 1528 unsigned ImmVal = Imm & 0xFFF; 1529 const AArch64Disassembler *Dis = 1530 static_cast<const AArch64Disassembler *>(Decoder); 1531 1532 if (ShifterVal != 0 && ShifterVal != 1) 1533 return Fail; 1534 1535 if (Datasize) { 1536 if (Rd == 31 && !S) 1537 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1538 else 1539 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1540 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1541 } else { 1542 if (Rd == 31 && !S) 1543 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1544 else 1545 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1546 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1547 } 1548 1549 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1550 Inst.addOperand(MCOperand::createImm(ImmVal)); 1551 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1552 return Success; 1553 } 1554 1555 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1556 uint64_t Addr, 1557 const void *Decoder) { 1558 int64_t imm = fieldFromInstruction(insn, 0, 26); 1559 const AArch64Disassembler *Dis = 1560 static_cast<const AArch64Disassembler *>(Decoder); 1561 1562 // Sign-extend the 26-bit immediate. 1563 if (imm & (1 << (26 - 1))) 1564 imm |= ~((1LL << 26) - 1); 1565 1566 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1567 Inst.addOperand(MCOperand::createImm(imm)); 1568 1569 return Success; 1570 } 1571 1572 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1573 uint64_t Addr, 1574 const void *Decoder) { 1575 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1576 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1577 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1578 1579 uint64_t pstate_field = (op1 << 3) | op2; 1580 1581 if ((pstate_field == AArch64PState::PAN || 1582 pstate_field == AArch64PState::UAO) && crm > 1) 1583 return Fail; 1584 1585 Inst.addOperand(MCOperand::createImm(pstate_field)); 1586 Inst.addOperand(MCOperand::createImm(crm)); 1587 1588 const AArch64Disassembler *Dis = 1589 static_cast<const AArch64Disassembler *>(Decoder); 1590 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1591 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1592 return Success; 1593 return Fail; 1594 } 1595 1596 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1597 uint64_t Addr, const void *Decoder) { 1598 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1599 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1600 bit |= fieldFromInstruction(insn, 19, 5); 1601 int64_t dst = fieldFromInstruction(insn, 5, 14); 1602 const AArch64Disassembler *Dis = 1603 static_cast<const AArch64Disassembler *>(Decoder); 1604 1605 // Sign-extend 14-bit immediate. 1606 if (dst & (1 << (14 - 1))) 1607 dst |= ~((1LL << 14) - 1); 1608 1609 if (fieldFromInstruction(insn, 31, 1) == 0) 1610 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1611 else 1612 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1613 Inst.addOperand(MCOperand::createImm(bit)); 1614 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1615 Inst.addOperand(MCOperand::createImm(dst)); 1616 1617 return Success; 1618 } 1619 1620 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1621 unsigned RegClassID, 1622 unsigned RegNo, 1623 uint64_t Addr, 1624 const void *Decoder) { 1625 // Register number must be even (see CASP instruction) 1626 if (RegNo & 0x1) 1627 return Fail; 1628 1629 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1630 Inst.addOperand(MCOperand::createReg(Register)); 1631 return Success; 1632 } 1633 1634 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1635 unsigned RegNo, 1636 uint64_t Addr, 1637 const void *Decoder) { 1638 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1639 AArch64::WSeqPairsClassRegClassID, 1640 RegNo, Addr, Decoder); 1641 } 1642 1643 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1644 unsigned RegNo, 1645 uint64_t Addr, 1646 const void *Decoder) { 1647 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1648 AArch64::XSeqPairsClassRegClassID, 1649 RegNo, Addr, Decoder); 1650 } 1651 1652 template<int Bits> 1653 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1654 uint64_t Address, const void *Decoder) { 1655 if (Imm & ~((1LL << Bits) - 1)) 1656 return Fail; 1657 1658 // Imm is a signed immediate, so sign extend it. 1659 if (Imm & (1 << (Bits - 1))) 1660 Imm |= ~((1LL << Bits) - 1); 1661 1662 Inst.addOperand(MCOperand::createImm(Imm)); 1663 return Success; 1664 } 1665 1666