1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/MC/TargetRegistry.h" 25 #include "llvm/Support/Compiler.h" 26 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 41 uint64_t Address, 42 const MCDisassembler *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 44 uint64_t Address, 45 const MCDisassembler *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const MCDisassembler *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const MCDisassembler *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const MCDisassembler *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const MCDisassembler *Decoder); 58 static DecodeStatus 59 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 60 const MCDisassembler *Decoder); 61 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 62 uint64_t Address, 63 const MCDisassembler *Decoder); 64 static DecodeStatus 65 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 66 const MCDisassembler *Decoder); 67 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 68 uint64_t Address, 69 const MCDisassembler *Decoder); 70 static DecodeStatus 71 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, 72 uint64_t Address, 73 const MCDisassembler *Decoder); 74 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 75 uint64_t Address, 76 const MCDisassembler *Decoder); 77 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 78 uint64_t Address, 79 const MCDisassembler *Decoder); 80 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 81 uint64_t Address, 82 const MCDisassembler *Decoder); 83 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 84 uint64_t Address, 85 const MCDisassembler *Decoder); 86 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 87 uint64_t Address, 88 const MCDisassembler *Decoder); 89 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 90 uint64_t Address, 91 const MCDisassembler *Decoder); 92 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 93 uint64_t Address, 94 const MCDisassembler *Decoder); 95 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 96 uint64_t Address, 97 const MCDisassembler *Decoder); 98 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 99 uint64_t Address, 100 const MCDisassembler *Decoder); 101 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 102 uint64_t Address, 103 const MCDisassembler *Decoder); 104 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 105 uint64_t Address, 106 const MCDisassembler *Decoder); 107 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 108 uint64_t Address, 109 const MCDisassembler *Decoder); 110 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, 112 const MCDisassembler *Decoder); 113 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 114 uint64_t Address, 115 const MCDisassembler *Decoder); 116 template <unsigned NumBitsForTile> 117 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 118 uint64_t Address, 119 const MCDisassembler *Decoder); 120 static DecodeStatus 121 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, 122 uint64_t Address, 123 const MCDisassembler *Decoder); 124 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 125 uint64_t Address, 126 const MCDisassembler *Decoder); 127 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const MCDisassembler *Decoder); 130 131 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 132 uint64_t Address, 133 const MCDisassembler *Decoder); 134 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 135 uint64_t Address, 136 const MCDisassembler *Decoder); 137 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 138 uint64_t Address, 139 const MCDisassembler *Decoder); 140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 141 uint64_t Address, 142 const MCDisassembler *Decoder); 143 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 144 uint64_t Address, 145 const MCDisassembler *Decoder); 146 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 147 uint64_t Address, 148 const MCDisassembler *Decoder); 149 static DecodeStatus 150 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 151 const MCDisassembler *Decoder); 152 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const MCDisassembler *Decoder); 155 static DecodeStatus 156 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 157 const MCDisassembler *Decoder); 158 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const MCDisassembler *Decoder); 161 static DecodeStatus 162 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 163 const MCDisassembler *Decoder); 164 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 165 uint64_t Address, 166 const MCDisassembler *Decoder); 167 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 168 uint64_t Address, 169 const MCDisassembler *Decoder); 170 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 171 uint64_t Address, 172 const MCDisassembler *Decoder); 173 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 174 uint64_t Address, 175 const MCDisassembler *Decoder); 176 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 177 uint64_t Address, 178 const MCDisassembler *Decoder); 179 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 180 uint64_t Address, 181 const MCDisassembler *Decoder); 182 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 183 uint64_t Address, 184 const MCDisassembler *Decoder); 185 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 186 uint64_t Address, 187 const MCDisassembler *Decoder); 188 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 189 uint64_t Address, 190 const MCDisassembler *Decoder); 191 static DecodeStatus 192 DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 193 const MCDisassembler *Decoder); 194 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 195 uint64_t Address, 196 const MCDisassembler *Decoder); 197 198 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 199 uint64_t Address, 200 const MCDisassembler *Decoder); 201 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 202 uint64_t Addr, 203 const MCDisassembler *Decoder); 204 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 205 uint64_t Addr, 206 const MCDisassembler *Decoder); 207 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 208 uint64_t Addr, 209 const MCDisassembler *Decoder); 210 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, 212 const MCDisassembler *Decoder); 213 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 214 uint64_t Addr, 215 const MCDisassembler *Decoder); 216 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, 218 const MCDisassembler *Decoder); 219 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, 221 const MCDisassembler *Decoder); 222 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 223 uint64_t Addr, 224 const MCDisassembler *Decoder); 225 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 226 uint64_t Addr, 227 const MCDisassembler *Decoder); 228 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 229 uint64_t Addr, 230 const MCDisassembler *Decoder); 231 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 232 uint64_t Addr, 233 const MCDisassembler *Decoder); 234 static DecodeStatus 235 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 236 const MCDisassembler *Decoder); 237 static DecodeStatus 238 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 239 const MCDisassembler *Decoder); 240 static DecodeStatus 241 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 242 const MCDisassembler *Decoder); 243 template <int Bits> 244 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 245 const MCDisassembler *Decoder); 246 template <int ElementWidth> 247 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, 248 const MCDisassembler *Decoder); 249 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 250 uint64_t Addr, 251 const MCDisassembler *Decoder); 252 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 253 const MCDisassembler *Decoder); 254 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, 255 uint64_t Addr, 256 const MCDisassembler *Decoder); 257 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, 258 uint64_t Addr, 259 const MCDisassembler *Decoder); 260 261 static bool Check(DecodeStatus &Out, DecodeStatus In) { 262 switch (In) { 263 case MCDisassembler::Success: 264 // Out stays the same. 265 return true; 266 case MCDisassembler::SoftFail: 267 Out = In; 268 return true; 269 case MCDisassembler::Fail: 270 Out = In; 271 return false; 272 } 273 llvm_unreachable("Invalid DecodeStatus!"); 274 } 275 276 #include "AArch64GenDisassemblerTables.inc" 277 #include "AArch64GenInstrInfo.inc" 278 279 #define Success MCDisassembler::Success 280 #define Fail MCDisassembler::Fail 281 #define SoftFail MCDisassembler::SoftFail 282 283 static MCDisassembler *createAArch64Disassembler(const Target &T, 284 const MCSubtargetInfo &STI, 285 MCContext &Ctx) { 286 return new AArch64Disassembler(STI, Ctx); 287 } 288 289 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 290 ArrayRef<uint8_t> Bytes, 291 uint64_t Address, 292 raw_ostream &CS) const { 293 CommentStream = &CS; 294 295 Size = 0; 296 // We want to read exactly 4 bytes of data. 297 if (Bytes.size() < 4) 298 return Fail; 299 Size = 4; 300 301 // Encoded as a small-endian 32-bit word in the stream. 302 uint32_t Insn = 303 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 304 305 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 306 307 for (auto Table : Tables) { 308 DecodeStatus Result = 309 decodeInstruction(Table, MI, Insn, Address, this, STI); 310 311 switch (MI.getOpcode()) { 312 default: 313 break; 314 // For Scalable Matrix Extension (SME) instructions that have an implicit 315 // operand for the accumulator (ZA) which isn't encoded, manually insert 316 // operand. 317 case AArch64::LDR_ZA: 318 case AArch64::STR_ZA: { 319 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA)); 320 // Spill and fill instructions have a single immediate used for both the 321 // vector select offset and optional memory offset. Replicate the decoded 322 // immediate. 323 const MCOperand &Imm4Op = MI.getOperand(2); 324 assert(Imm4Op.isImm() && "Unexpected operand type!"); 325 MI.addOperand(Imm4Op); 326 break; 327 } 328 case AArch64::LD1_MXIPXX_H_B: 329 case AArch64::LD1_MXIPXX_V_B: 330 case AArch64::ST1_MXIPXX_H_B: 331 case AArch64::ST1_MXIPXX_V_B: 332 case AArch64::INSERT_MXIPZ_H_B: 333 case AArch64::INSERT_MXIPZ_V_B: 334 // e.g. 335 // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B 336 // ^ insert implicit 8-bit element tile 337 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 338 break; 339 case AArch64::EXTRACT_ZPMXI_H_B: 340 case AArch64::EXTRACT_ZPMXI_V_B: 341 // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>] 342 // ^ insert implicit 8-bit element tile 343 MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0)); 344 break; 345 case AArch64::LD1_MXIPXX_H_Q: 346 case AArch64::LD1_MXIPXX_V_Q: 347 case AArch64::ST1_MXIPXX_H_Q: 348 case AArch64::ST1_MXIPXX_V_Q: 349 // 128-bit load/store have implicit zero vector index. 350 MI.insert(MI.begin()+2, MCOperand::createImm(0)); 351 break; 352 // 128-bit mova have implicit zero vector index. 353 case AArch64::INSERT_MXIPZ_H_Q: 354 case AArch64::INSERT_MXIPZ_V_Q: 355 MI.insert(MI.begin()+2, MCOperand::createImm(0)); 356 break; 357 case AArch64::EXTRACT_ZPMXI_H_Q: 358 case AArch64::EXTRACT_ZPMXI_V_Q: 359 MI.addOperand(MCOperand::createImm(0)); 360 break; 361 case AArch64::SMOVvi8to32_idx0: 362 case AArch64::SMOVvi8to64_idx0: 363 case AArch64::SMOVvi16to32_idx0: 364 case AArch64::SMOVvi16to64_idx0: 365 case AArch64::SMOVvi32to64_idx0: 366 case AArch64::UMOVvi8_idx0: 367 case AArch64::UMOVvi16_idx0: 368 case AArch64::UMOVvi32_idx0: 369 case AArch64::UMOVvi64_idx0: 370 MI.addOperand(MCOperand::createImm(0)); 371 break; 372 } 373 374 if (Result != MCDisassembler::Fail) 375 return Result; 376 } 377 378 return MCDisassembler::Fail; 379 } 380 381 static MCSymbolizer * 382 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 383 LLVMSymbolLookupCallback SymbolLookUp, 384 void *DisInfo, MCContext *Ctx, 385 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 386 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 387 SymbolLookUp, DisInfo); 388 } 389 390 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 391 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 392 createAArch64Disassembler); 393 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 394 createAArch64Disassembler); 395 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 396 createAArch64ExternalSymbolizer); 397 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 398 createAArch64ExternalSymbolizer); 399 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 400 createAArch64Disassembler); 401 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 402 createAArch64ExternalSymbolizer); 403 404 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 405 createAArch64Disassembler); 406 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 407 createAArch64ExternalSymbolizer); 408 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 409 createAArch64Disassembler); 410 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 411 createAArch64ExternalSymbolizer); 412 } 413 414 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 415 uint64_t Addr, 416 const MCDisassembler *Decoder) { 417 if (RegNo > 31) 418 return Fail; 419 420 unsigned Register = 421 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo); 422 Inst.addOperand(MCOperand::createReg(Register)); 423 return Success; 424 } 425 426 static DecodeStatus 427 DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 428 const MCDisassembler *Decoder) { 429 if (RegNo > 15) 430 return Fail; 431 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 432 } 433 434 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 435 uint64_t Addr, 436 const MCDisassembler *Decoder) { 437 if (RegNo > 31) 438 return Fail; 439 440 unsigned Register = 441 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo); 442 Inst.addOperand(MCOperand::createReg(Register)); 443 return Success; 444 } 445 446 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 447 uint64_t Addr, 448 const MCDisassembler *Decoder) { 449 if (RegNo > 31) 450 return Fail; 451 452 unsigned Register = 453 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo); 454 Inst.addOperand(MCOperand::createReg(Register)); 455 return Success; 456 } 457 458 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 459 uint64_t Addr, 460 const MCDisassembler *Decoder) { 461 if (RegNo > 31) 462 return Fail; 463 464 unsigned Register = 465 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo); 466 Inst.addOperand(MCOperand::createReg(Register)); 467 return Success; 468 } 469 470 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 471 uint64_t Addr, 472 const MCDisassembler *Decoder) { 473 if (RegNo > 31) 474 return Fail; 475 476 unsigned Register = 477 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo); 478 Inst.addOperand(MCOperand::createReg(Register)); 479 return Success; 480 } 481 482 static DecodeStatus 483 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 484 const MCDisassembler *Decoder) { 485 if (RegNo > 30) 486 return Fail; 487 488 unsigned Register = 489 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister( 490 RegNo); 491 Inst.addOperand(MCOperand::createReg(Register)); 492 return Success; 493 } 494 495 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 496 uint64_t Addr, 497 const MCDisassembler *Decoder) { 498 if (RegNo > 31) 499 return Fail; 500 501 unsigned Register = 502 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo); 503 Inst.addOperand(MCOperand::createReg(Register)); 504 return Success; 505 } 506 507 static DecodeStatus 508 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 509 const MCDisassembler *Decoder) { 510 if (RegNo > 22) 511 return Fail; 512 if (RegNo & 1) 513 return Fail; 514 515 unsigned Register = 516 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister( 517 RegNo >> 1); 518 Inst.addOperand(MCOperand::createReg(Register)); 519 return Success; 520 } 521 522 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 523 uint64_t Addr, 524 const MCDisassembler *Decoder) { 525 if (RegNo > 31) 526 return Fail; 527 unsigned Register = 528 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo); 529 Inst.addOperand(MCOperand::createReg(Register)); 530 return Success; 531 } 532 533 static DecodeStatus 534 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, 535 uint64_t Addr, 536 const MCDisassembler *Decoder) { 537 if (RegNo > 3) 538 return Fail; 539 540 unsigned Register = 541 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID] 542 .getRegister(RegNo); 543 Inst.addOperand(MCOperand::createReg(Register)); 544 return Success; 545 } 546 547 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 548 uint64_t Addr, 549 const MCDisassembler *Decoder) { 550 if (RegNo > 31) 551 return Fail; 552 553 unsigned Register = 554 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo); 555 Inst.addOperand(MCOperand::createReg(Register)); 556 return Success; 557 } 558 559 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 560 uint64_t Addr, 561 const MCDisassembler *Decoder) { 562 if (RegNo > 31) 563 return Fail; 564 565 unsigned Register = 566 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo); 567 Inst.addOperand(MCOperand::createReg(Register)); 568 return Success; 569 } 570 571 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 572 uint64_t Address, 573 const MCDisassembler *Decoder) { 574 if (RegNo > 31) 575 return Fail; 576 577 unsigned Register = 578 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo); 579 Inst.addOperand(MCOperand::createReg(Register)); 580 return Success; 581 } 582 583 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 584 uint64_t Address, 585 const MCDisassembler *Decoder) { 586 if (RegNo > 15) 587 return Fail; 588 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 589 } 590 591 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 592 uint64_t Address, 593 const MCDisassembler *Decoder) { 594 if (RegNo > 7) 595 return Fail; 596 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 597 } 598 599 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 600 uint64_t Address, 601 const MCDisassembler *Decoder) { 602 if (RegNo > 31) 603 return Fail; 604 unsigned Register = 605 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo); 606 Inst.addOperand(MCOperand::createReg(Register)); 607 return Success; 608 } 609 610 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 611 uint64_t Address, 612 const MCDisassembler *Decoder) { 613 if (RegNo > 31) 614 return Fail; 615 unsigned Register = 616 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo); 617 Inst.addOperand(MCOperand::createReg(Register)); 618 return Success; 619 } 620 621 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 622 uint64_t Address, 623 const MCDisassembler *Decoder) { 624 if (RegNo > 31) 625 return Fail; 626 unsigned Register = 627 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo); 628 Inst.addOperand(MCOperand::createReg(Register)); 629 return Success; 630 } 631 632 static DecodeStatus 633 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, 634 uint64_t Address, 635 const MCDisassembler *Decoder) { 636 if (RegMask > 0xFF) 637 return Fail; 638 Inst.addOperand(MCOperand::createImm(RegMask)); 639 return Success; 640 } 641 642 static const SmallVector<SmallVector<unsigned, 16>, 5> 643 MatrixZATileDecoderTable = { 644 {AArch64::ZAB0}, 645 {AArch64::ZAH0, AArch64::ZAH1}, 646 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 647 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 648 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 649 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 650 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 651 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 652 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 653 654 template <unsigned NumBitsForTile> 655 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 656 uint64_t Address, 657 const MCDisassembler *Decoder) { 658 unsigned LastReg = (1 << NumBitsForTile) - 1; 659 if (RegNo > LastReg) 660 return Fail; 661 Inst.addOperand( 662 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 663 return Success; 664 } 665 666 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 667 uint64_t Addr, 668 const MCDisassembler *Decoder) { 669 if (RegNo > 15) 670 return Fail; 671 672 unsigned Register = 673 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo); 674 Inst.addOperand(MCOperand::createReg(Register)); 675 return Success; 676 } 677 678 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 679 uint64_t Addr, 680 const MCDisassembler *Decoder) { 681 if (RegNo > 7) 682 return Fail; 683 684 // Just reuse the PPR decode table 685 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 686 } 687 688 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 689 uint64_t Addr, 690 const MCDisassembler *Decoder) { 691 if (RegNo > 31) 692 return Fail; 693 unsigned Register = 694 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo); 695 Inst.addOperand(MCOperand::createReg(Register)); 696 return Success; 697 } 698 699 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 700 uint64_t Addr, 701 const MCDisassembler *Decoder) { 702 if (RegNo > 31) 703 return Fail; 704 unsigned Register = 705 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo); 706 Inst.addOperand(MCOperand::createReg(Register)); 707 return Success; 708 } 709 710 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 711 uint64_t Addr, 712 const MCDisassembler *Decoder) { 713 if (RegNo > 31) 714 return Fail; 715 unsigned Register = 716 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo); 717 Inst.addOperand(MCOperand::createReg(Register)); 718 return Success; 719 } 720 721 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 722 uint64_t Addr, 723 const MCDisassembler *Decoder) { 724 if (RegNo > 31) 725 return Fail; 726 unsigned Register = 727 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo); 728 Inst.addOperand(MCOperand::createReg(Register)); 729 return Success; 730 } 731 732 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 733 uint64_t Addr, 734 const MCDisassembler *Decoder) { 735 if (RegNo > 31) 736 return Fail; 737 unsigned Register = 738 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo); 739 Inst.addOperand(MCOperand::createReg(Register)); 740 return Success; 741 } 742 743 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 744 uint64_t Addr, 745 const MCDisassembler *Decoder) { 746 if (RegNo > 31) 747 return Fail; 748 unsigned Register = 749 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo); 750 Inst.addOperand(MCOperand::createReg(Register)); 751 return Success; 752 } 753 754 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 755 uint64_t Addr, 756 const MCDisassembler *Decoder) { 757 // scale{5} is asserted as 1 in tblgen. 758 Imm |= 0x20; 759 Inst.addOperand(MCOperand::createImm(64 - Imm)); 760 return Success; 761 } 762 763 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 764 uint64_t Addr, 765 const MCDisassembler *Decoder) { 766 Inst.addOperand(MCOperand::createImm(64 - Imm)); 767 return Success; 768 } 769 770 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 771 uint64_t Addr, 772 const MCDisassembler *Decoder) { 773 int64_t ImmVal = Imm; 774 775 // Sign-extend 19-bit immediate. 776 if (ImmVal & (1 << (19 - 1))) 777 ImmVal |= ~((1LL << 19) - 1); 778 779 if (!Decoder->tryAddingSymbolicOperand( 780 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 781 Inst.addOperand(MCOperand::createImm(ImmVal)); 782 return Success; 783 } 784 785 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 786 uint64_t Address, 787 const MCDisassembler *Decoder) { 788 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 789 Inst.addOperand(MCOperand::createImm(Imm & 1)); 790 return Success; 791 } 792 793 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 794 uint64_t Address, 795 const MCDisassembler *Decoder) { 796 Inst.addOperand(MCOperand::createImm(Imm)); 797 798 // Every system register in the encoding space is valid with the syntax 799 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 800 return Success; 801 } 802 803 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 804 uint64_t Address, 805 const MCDisassembler *Decoder) { 806 Inst.addOperand(MCOperand::createImm(Imm)); 807 808 return Success; 809 } 810 811 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 812 uint64_t Address, 813 const MCDisassembler *Decoder) { 814 // This decoder exists to add the dummy Lane operand to the MCInst, which must 815 // be 1 in assembly but has no other real manifestation. 816 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 817 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 818 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 819 820 if (IsToVec) { 821 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 822 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 823 } else { 824 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 825 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 826 } 827 828 // Add the lane 829 Inst.addOperand(MCOperand::createImm(1)); 830 831 return Success; 832 } 833 834 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 835 unsigned Add) { 836 Inst.addOperand(MCOperand::createImm(Add - Imm)); 837 return Success; 838 } 839 840 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 841 unsigned Add) { 842 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 843 return Success; 844 } 845 846 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 847 uint64_t Addr, 848 const MCDisassembler *Decoder) { 849 return DecodeVecShiftRImm(Inst, Imm, 64); 850 } 851 852 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 853 uint64_t Addr, 854 const MCDisassembler *Decoder) { 855 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 856 } 857 858 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 859 uint64_t Addr, 860 const MCDisassembler *Decoder) { 861 return DecodeVecShiftRImm(Inst, Imm, 32); 862 } 863 864 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 865 uint64_t Addr, 866 const MCDisassembler *Decoder) { 867 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 868 } 869 870 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 871 uint64_t Addr, 872 const MCDisassembler *Decoder) { 873 return DecodeVecShiftRImm(Inst, Imm, 16); 874 } 875 876 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 877 uint64_t Addr, 878 const MCDisassembler *Decoder) { 879 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 880 } 881 882 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 883 uint64_t Addr, 884 const MCDisassembler *Decoder) { 885 return DecodeVecShiftRImm(Inst, Imm, 8); 886 } 887 888 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 889 uint64_t Addr, 890 const MCDisassembler *Decoder) { 891 return DecodeVecShiftLImm(Inst, Imm, 64); 892 } 893 894 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 895 uint64_t Addr, 896 const MCDisassembler *Decoder) { 897 return DecodeVecShiftLImm(Inst, Imm, 32); 898 } 899 900 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 901 uint64_t Addr, 902 const MCDisassembler *Decoder) { 903 return DecodeVecShiftLImm(Inst, Imm, 16); 904 } 905 906 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 907 uint64_t Addr, 908 const MCDisassembler *Decoder) { 909 return DecodeVecShiftLImm(Inst, Imm, 8); 910 } 911 912 static DecodeStatus 913 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 914 const MCDisassembler *Decoder) { 915 unsigned Rd = fieldFromInstruction(insn, 0, 5); 916 unsigned Rn = fieldFromInstruction(insn, 5, 5); 917 unsigned Rm = fieldFromInstruction(insn, 16, 5); 918 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 919 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 920 unsigned shift = (shiftHi << 6) | shiftLo; 921 switch (Inst.getOpcode()) { 922 default: 923 return Fail; 924 case AArch64::ADDWrs: 925 case AArch64::ADDSWrs: 926 case AArch64::SUBWrs: 927 case AArch64::SUBSWrs: 928 // if shift == '11' then ReservedValue() 929 if (shiftHi == 0x3) 930 return Fail; 931 LLVM_FALLTHROUGH; 932 case AArch64::ANDWrs: 933 case AArch64::ANDSWrs: 934 case AArch64::BICWrs: 935 case AArch64::BICSWrs: 936 case AArch64::ORRWrs: 937 case AArch64::ORNWrs: 938 case AArch64::EORWrs: 939 case AArch64::EONWrs: { 940 // if sf == '0' and imm6<5> == '1' then ReservedValue() 941 if (shiftLo >> 5 == 1) 942 return Fail; 943 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 944 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 945 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 946 break; 947 } 948 case AArch64::ADDXrs: 949 case AArch64::ADDSXrs: 950 case AArch64::SUBXrs: 951 case AArch64::SUBSXrs: 952 // if shift == '11' then ReservedValue() 953 if (shiftHi == 0x3) 954 return Fail; 955 LLVM_FALLTHROUGH; 956 case AArch64::ANDXrs: 957 case AArch64::ANDSXrs: 958 case AArch64::BICXrs: 959 case AArch64::BICSXrs: 960 case AArch64::ORRXrs: 961 case AArch64::ORNXrs: 962 case AArch64::EORXrs: 963 case AArch64::EONXrs: 964 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 965 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 966 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 967 break; 968 } 969 970 Inst.addOperand(MCOperand::createImm(shift)); 971 return Success; 972 } 973 974 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 975 uint64_t Addr, 976 const MCDisassembler *Decoder) { 977 unsigned Rd = fieldFromInstruction(insn, 0, 5); 978 unsigned imm = fieldFromInstruction(insn, 5, 16); 979 unsigned shift = fieldFromInstruction(insn, 21, 2); 980 shift <<= 4; 981 switch (Inst.getOpcode()) { 982 default: 983 return Fail; 984 case AArch64::MOVZWi: 985 case AArch64::MOVNWi: 986 case AArch64::MOVKWi: 987 if (shift & (1U << 5)) 988 return Fail; 989 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 990 break; 991 case AArch64::MOVZXi: 992 case AArch64::MOVNXi: 993 case AArch64::MOVKXi: 994 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 995 break; 996 } 997 998 if (Inst.getOpcode() == AArch64::MOVKWi || 999 Inst.getOpcode() == AArch64::MOVKXi) 1000 Inst.addOperand(Inst.getOperand(0)); 1001 1002 Inst.addOperand(MCOperand::createImm(imm)); 1003 Inst.addOperand(MCOperand::createImm(shift)); 1004 return Success; 1005 } 1006 1007 static DecodeStatus 1008 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1009 const MCDisassembler *Decoder) { 1010 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1011 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1012 unsigned offset = fieldFromInstruction(insn, 10, 12); 1013 1014 switch (Inst.getOpcode()) { 1015 default: 1016 return Fail; 1017 case AArch64::PRFMui: 1018 // Rt is an immediate in prefetch. 1019 Inst.addOperand(MCOperand::createImm(Rt)); 1020 break; 1021 case AArch64::STRBBui: 1022 case AArch64::LDRBBui: 1023 case AArch64::LDRSBWui: 1024 case AArch64::STRHHui: 1025 case AArch64::LDRHHui: 1026 case AArch64::LDRSHWui: 1027 case AArch64::STRWui: 1028 case AArch64::LDRWui: 1029 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1030 break; 1031 case AArch64::LDRSBXui: 1032 case AArch64::LDRSHXui: 1033 case AArch64::LDRSWui: 1034 case AArch64::STRXui: 1035 case AArch64::LDRXui: 1036 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1037 break; 1038 case AArch64::LDRQui: 1039 case AArch64::STRQui: 1040 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1041 break; 1042 case AArch64::LDRDui: 1043 case AArch64::STRDui: 1044 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1045 break; 1046 case AArch64::LDRSui: 1047 case AArch64::STRSui: 1048 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1049 break; 1050 case AArch64::LDRHui: 1051 case AArch64::STRHui: 1052 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1053 break; 1054 case AArch64::LDRBui: 1055 case AArch64::STRBui: 1056 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1057 break; 1058 } 1059 1060 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1061 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1062 Inst.addOperand(MCOperand::createImm(offset)); 1063 return Success; 1064 } 1065 1066 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1067 uint64_t Addr, 1068 const MCDisassembler *Decoder) { 1069 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1070 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1071 int64_t offset = fieldFromInstruction(insn, 12, 9); 1072 1073 // offset is a 9-bit signed immediate, so sign extend it to 1074 // fill the unsigned. 1075 if (offset & (1 << (9 - 1))) 1076 offset |= ~((1LL << 9) - 1); 1077 1078 // First operand is always the writeback to the address register, if needed. 1079 switch (Inst.getOpcode()) { 1080 default: 1081 break; 1082 case AArch64::LDRSBWpre: 1083 case AArch64::LDRSHWpre: 1084 case AArch64::STRBBpre: 1085 case AArch64::LDRBBpre: 1086 case AArch64::STRHHpre: 1087 case AArch64::LDRHHpre: 1088 case AArch64::STRWpre: 1089 case AArch64::LDRWpre: 1090 case AArch64::LDRSBWpost: 1091 case AArch64::LDRSHWpost: 1092 case AArch64::STRBBpost: 1093 case AArch64::LDRBBpost: 1094 case AArch64::STRHHpost: 1095 case AArch64::LDRHHpost: 1096 case AArch64::STRWpost: 1097 case AArch64::LDRWpost: 1098 case AArch64::LDRSBXpre: 1099 case AArch64::LDRSHXpre: 1100 case AArch64::STRXpre: 1101 case AArch64::LDRSWpre: 1102 case AArch64::LDRXpre: 1103 case AArch64::LDRSBXpost: 1104 case AArch64::LDRSHXpost: 1105 case AArch64::STRXpost: 1106 case AArch64::LDRSWpost: 1107 case AArch64::LDRXpost: 1108 case AArch64::LDRQpre: 1109 case AArch64::STRQpre: 1110 case AArch64::LDRQpost: 1111 case AArch64::STRQpost: 1112 case AArch64::LDRDpre: 1113 case AArch64::STRDpre: 1114 case AArch64::LDRDpost: 1115 case AArch64::STRDpost: 1116 case AArch64::LDRSpre: 1117 case AArch64::STRSpre: 1118 case AArch64::LDRSpost: 1119 case AArch64::STRSpost: 1120 case AArch64::LDRHpre: 1121 case AArch64::STRHpre: 1122 case AArch64::LDRHpost: 1123 case AArch64::STRHpost: 1124 case AArch64::LDRBpre: 1125 case AArch64::STRBpre: 1126 case AArch64::LDRBpost: 1127 case AArch64::STRBpost: 1128 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1129 break; 1130 } 1131 1132 switch (Inst.getOpcode()) { 1133 default: 1134 return Fail; 1135 case AArch64::PRFUMi: 1136 // Rt is an immediate in prefetch. 1137 Inst.addOperand(MCOperand::createImm(Rt)); 1138 break; 1139 case AArch64::STURBBi: 1140 case AArch64::LDURBBi: 1141 case AArch64::LDURSBWi: 1142 case AArch64::STURHHi: 1143 case AArch64::LDURHHi: 1144 case AArch64::LDURSHWi: 1145 case AArch64::STURWi: 1146 case AArch64::LDURWi: 1147 case AArch64::LDTRSBWi: 1148 case AArch64::LDTRSHWi: 1149 case AArch64::STTRWi: 1150 case AArch64::LDTRWi: 1151 case AArch64::STTRHi: 1152 case AArch64::LDTRHi: 1153 case AArch64::LDTRBi: 1154 case AArch64::STTRBi: 1155 case AArch64::LDRSBWpre: 1156 case AArch64::LDRSHWpre: 1157 case AArch64::STRBBpre: 1158 case AArch64::LDRBBpre: 1159 case AArch64::STRHHpre: 1160 case AArch64::LDRHHpre: 1161 case AArch64::STRWpre: 1162 case AArch64::LDRWpre: 1163 case AArch64::LDRSBWpost: 1164 case AArch64::LDRSHWpost: 1165 case AArch64::STRBBpost: 1166 case AArch64::LDRBBpost: 1167 case AArch64::STRHHpost: 1168 case AArch64::LDRHHpost: 1169 case AArch64::STRWpost: 1170 case AArch64::LDRWpost: 1171 case AArch64::STLURBi: 1172 case AArch64::STLURHi: 1173 case AArch64::STLURWi: 1174 case AArch64::LDAPURBi: 1175 case AArch64::LDAPURSBWi: 1176 case AArch64::LDAPURHi: 1177 case AArch64::LDAPURSHWi: 1178 case AArch64::LDAPURi: 1179 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1180 break; 1181 case AArch64::LDURSBXi: 1182 case AArch64::LDURSHXi: 1183 case AArch64::LDURSWi: 1184 case AArch64::STURXi: 1185 case AArch64::LDURXi: 1186 case AArch64::LDTRSBXi: 1187 case AArch64::LDTRSHXi: 1188 case AArch64::LDTRSWi: 1189 case AArch64::STTRXi: 1190 case AArch64::LDTRXi: 1191 case AArch64::LDRSBXpre: 1192 case AArch64::LDRSHXpre: 1193 case AArch64::STRXpre: 1194 case AArch64::LDRSWpre: 1195 case AArch64::LDRXpre: 1196 case AArch64::LDRSBXpost: 1197 case AArch64::LDRSHXpost: 1198 case AArch64::STRXpost: 1199 case AArch64::LDRSWpost: 1200 case AArch64::LDRXpost: 1201 case AArch64::LDAPURSWi: 1202 case AArch64::LDAPURSHXi: 1203 case AArch64::LDAPURSBXi: 1204 case AArch64::STLURXi: 1205 case AArch64::LDAPURXi: 1206 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1207 break; 1208 case AArch64::LDURQi: 1209 case AArch64::STURQi: 1210 case AArch64::LDRQpre: 1211 case AArch64::STRQpre: 1212 case AArch64::LDRQpost: 1213 case AArch64::STRQpost: 1214 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1215 break; 1216 case AArch64::LDURDi: 1217 case AArch64::STURDi: 1218 case AArch64::LDRDpre: 1219 case AArch64::STRDpre: 1220 case AArch64::LDRDpost: 1221 case AArch64::STRDpost: 1222 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1223 break; 1224 case AArch64::LDURSi: 1225 case AArch64::STURSi: 1226 case AArch64::LDRSpre: 1227 case AArch64::STRSpre: 1228 case AArch64::LDRSpost: 1229 case AArch64::STRSpost: 1230 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1231 break; 1232 case AArch64::LDURHi: 1233 case AArch64::STURHi: 1234 case AArch64::LDRHpre: 1235 case AArch64::STRHpre: 1236 case AArch64::LDRHpost: 1237 case AArch64::STRHpost: 1238 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1239 break; 1240 case AArch64::LDURBi: 1241 case AArch64::STURBi: 1242 case AArch64::LDRBpre: 1243 case AArch64::STRBpre: 1244 case AArch64::LDRBpost: 1245 case AArch64::STRBpost: 1246 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1247 break; 1248 } 1249 1250 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1251 Inst.addOperand(MCOperand::createImm(offset)); 1252 1253 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1254 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1255 bool IsFP = fieldFromInstruction(insn, 26, 1); 1256 1257 // Cannot write back to a transfer register (but xzr != sp). 1258 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1259 return SoftFail; 1260 1261 return Success; 1262 } 1263 1264 static DecodeStatus 1265 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1266 const MCDisassembler *Decoder) { 1267 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1268 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1269 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1270 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1271 1272 unsigned Opcode = Inst.getOpcode(); 1273 switch (Opcode) { 1274 default: 1275 return Fail; 1276 case AArch64::STLXRW: 1277 case AArch64::STLXRB: 1278 case AArch64::STLXRH: 1279 case AArch64::STXRW: 1280 case AArch64::STXRB: 1281 case AArch64::STXRH: 1282 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1283 LLVM_FALLTHROUGH; 1284 case AArch64::LDARW: 1285 case AArch64::LDARB: 1286 case AArch64::LDARH: 1287 case AArch64::LDAXRW: 1288 case AArch64::LDAXRB: 1289 case AArch64::LDAXRH: 1290 case AArch64::LDXRW: 1291 case AArch64::LDXRB: 1292 case AArch64::LDXRH: 1293 case AArch64::STLRW: 1294 case AArch64::STLRB: 1295 case AArch64::STLRH: 1296 case AArch64::STLLRW: 1297 case AArch64::STLLRB: 1298 case AArch64::STLLRH: 1299 case AArch64::LDLARW: 1300 case AArch64::LDLARB: 1301 case AArch64::LDLARH: 1302 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1303 break; 1304 case AArch64::STLXRX: 1305 case AArch64::STXRX: 1306 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1307 LLVM_FALLTHROUGH; 1308 case AArch64::LDARX: 1309 case AArch64::LDAXRX: 1310 case AArch64::LDXRX: 1311 case AArch64::STLRX: 1312 case AArch64::LDLARX: 1313 case AArch64::STLLRX: 1314 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1315 break; 1316 case AArch64::STLXPW: 1317 case AArch64::STXPW: 1318 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1319 LLVM_FALLTHROUGH; 1320 case AArch64::LDAXPW: 1321 case AArch64::LDXPW: 1322 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1323 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1324 break; 1325 case AArch64::STLXPX: 1326 case AArch64::STXPX: 1327 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1328 LLVM_FALLTHROUGH; 1329 case AArch64::LDAXPX: 1330 case AArch64::LDXPX: 1331 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1332 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1333 break; 1334 } 1335 1336 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1337 1338 // You shouldn't load to the same register twice in an instruction... 1339 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1340 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1341 Rt == Rt2) 1342 return SoftFail; 1343 1344 return Success; 1345 } 1346 1347 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1348 uint64_t Addr, 1349 const MCDisassembler *Decoder) { 1350 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1351 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1352 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1353 int64_t offset = fieldFromInstruction(insn, 15, 7); 1354 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1355 1356 // offset is a 7-bit signed immediate, so sign extend it to 1357 // fill the unsigned. 1358 if (offset & (1 << (7 - 1))) 1359 offset |= ~((1LL << 7) - 1); 1360 1361 unsigned Opcode = Inst.getOpcode(); 1362 bool NeedsDisjointWritebackTransfer = false; 1363 1364 // First operand is always writeback of base register. 1365 switch (Opcode) { 1366 default: 1367 break; 1368 case AArch64::LDPXpost: 1369 case AArch64::STPXpost: 1370 case AArch64::LDPSWpost: 1371 case AArch64::LDPXpre: 1372 case AArch64::STPXpre: 1373 case AArch64::LDPSWpre: 1374 case AArch64::LDPWpost: 1375 case AArch64::STPWpost: 1376 case AArch64::LDPWpre: 1377 case AArch64::STPWpre: 1378 case AArch64::LDPQpost: 1379 case AArch64::STPQpost: 1380 case AArch64::LDPQpre: 1381 case AArch64::STPQpre: 1382 case AArch64::LDPDpost: 1383 case AArch64::STPDpost: 1384 case AArch64::LDPDpre: 1385 case AArch64::STPDpre: 1386 case AArch64::LDPSpost: 1387 case AArch64::STPSpost: 1388 case AArch64::LDPSpre: 1389 case AArch64::STPSpre: 1390 case AArch64::STGPpre: 1391 case AArch64::STGPpost: 1392 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1393 break; 1394 } 1395 1396 switch (Opcode) { 1397 default: 1398 return Fail; 1399 case AArch64::LDPXpost: 1400 case AArch64::STPXpost: 1401 case AArch64::LDPSWpost: 1402 case AArch64::LDPXpre: 1403 case AArch64::STPXpre: 1404 case AArch64::LDPSWpre: 1405 case AArch64::STGPpre: 1406 case AArch64::STGPpost: 1407 NeedsDisjointWritebackTransfer = true; 1408 LLVM_FALLTHROUGH; 1409 case AArch64::LDNPXi: 1410 case AArch64::STNPXi: 1411 case AArch64::LDPXi: 1412 case AArch64::STPXi: 1413 case AArch64::LDPSWi: 1414 case AArch64::STGPi: 1415 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1416 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1417 break; 1418 case AArch64::LDPWpost: 1419 case AArch64::STPWpost: 1420 case AArch64::LDPWpre: 1421 case AArch64::STPWpre: 1422 NeedsDisjointWritebackTransfer = true; 1423 LLVM_FALLTHROUGH; 1424 case AArch64::LDNPWi: 1425 case AArch64::STNPWi: 1426 case AArch64::LDPWi: 1427 case AArch64::STPWi: 1428 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1429 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1430 break; 1431 case AArch64::LDNPQi: 1432 case AArch64::STNPQi: 1433 case AArch64::LDPQpost: 1434 case AArch64::STPQpost: 1435 case AArch64::LDPQi: 1436 case AArch64::STPQi: 1437 case AArch64::LDPQpre: 1438 case AArch64::STPQpre: 1439 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1440 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1441 break; 1442 case AArch64::LDNPDi: 1443 case AArch64::STNPDi: 1444 case AArch64::LDPDpost: 1445 case AArch64::STPDpost: 1446 case AArch64::LDPDi: 1447 case AArch64::STPDi: 1448 case AArch64::LDPDpre: 1449 case AArch64::STPDpre: 1450 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1451 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1452 break; 1453 case AArch64::LDNPSi: 1454 case AArch64::STNPSi: 1455 case AArch64::LDPSpost: 1456 case AArch64::STPSpost: 1457 case AArch64::LDPSi: 1458 case AArch64::STPSi: 1459 case AArch64::LDPSpre: 1460 case AArch64::STPSpre: 1461 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1462 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1463 break; 1464 } 1465 1466 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1467 Inst.addOperand(MCOperand::createImm(offset)); 1468 1469 // You shouldn't load to the same register twice in an instruction... 1470 if (IsLoad && Rt == Rt2) 1471 return SoftFail; 1472 1473 // ... or do any operation that writes-back to a transfer register. But note 1474 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1475 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1476 return SoftFail; 1477 1478 return Success; 1479 } 1480 1481 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1482 uint64_t Addr, 1483 const MCDisassembler *Decoder) { 1484 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1485 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1486 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1487 fieldFromInstruction(insn, 12, 9); 1488 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1489 1490 switch (Inst.getOpcode()) { 1491 default: 1492 return Fail; 1493 case AArch64::LDRAAwriteback: 1494 case AArch64::LDRABwriteback: 1495 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1496 Decoder); 1497 break; 1498 case AArch64::LDRAAindexed: 1499 case AArch64::LDRABindexed: 1500 break; 1501 } 1502 1503 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1504 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1505 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1506 1507 if (writeback && Rt == Rn && Rn != 31) { 1508 return SoftFail; 1509 } 1510 1511 return Success; 1512 } 1513 1514 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1515 uint64_t Addr, 1516 const MCDisassembler *Decoder) { 1517 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1518 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1519 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1520 unsigned extend = fieldFromInstruction(insn, 10, 6); 1521 1522 unsigned shift = extend & 0x7; 1523 if (shift > 4) 1524 return Fail; 1525 1526 switch (Inst.getOpcode()) { 1527 default: 1528 return Fail; 1529 case AArch64::ADDWrx: 1530 case AArch64::SUBWrx: 1531 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1532 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1533 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1534 break; 1535 case AArch64::ADDSWrx: 1536 case AArch64::SUBSWrx: 1537 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1538 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1539 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1540 break; 1541 case AArch64::ADDXrx: 1542 case AArch64::SUBXrx: 1543 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1544 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1545 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1546 break; 1547 case AArch64::ADDSXrx: 1548 case AArch64::SUBSXrx: 1549 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1550 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1551 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1552 break; 1553 case AArch64::ADDXrx64: 1554 case AArch64::SUBXrx64: 1555 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1556 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1557 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1558 break; 1559 case AArch64::SUBSXrx64: 1560 case AArch64::ADDSXrx64: 1561 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1562 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1563 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1564 break; 1565 } 1566 1567 Inst.addOperand(MCOperand::createImm(extend)); 1568 return Success; 1569 } 1570 1571 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1572 uint64_t Addr, 1573 const MCDisassembler *Decoder) { 1574 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1575 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1576 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1577 unsigned imm; 1578 1579 if (Datasize) { 1580 if (Inst.getOpcode() == AArch64::ANDSXri) 1581 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1582 else 1583 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1584 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1585 imm = fieldFromInstruction(insn, 10, 13); 1586 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1587 return Fail; 1588 } else { 1589 if (Inst.getOpcode() == AArch64::ANDSWri) 1590 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1591 else 1592 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1593 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1594 imm = fieldFromInstruction(insn, 10, 12); 1595 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1596 return Fail; 1597 } 1598 Inst.addOperand(MCOperand::createImm(imm)); 1599 return Success; 1600 } 1601 1602 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1603 uint64_t Addr, 1604 const MCDisassembler *Decoder) { 1605 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1606 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1607 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1608 imm |= fieldFromInstruction(insn, 5, 5); 1609 1610 if (Inst.getOpcode() == AArch64::MOVID) 1611 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1612 else 1613 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1614 1615 Inst.addOperand(MCOperand::createImm(imm)); 1616 1617 switch (Inst.getOpcode()) { 1618 default: 1619 break; 1620 case AArch64::MOVIv4i16: 1621 case AArch64::MOVIv8i16: 1622 case AArch64::MVNIv4i16: 1623 case AArch64::MVNIv8i16: 1624 case AArch64::MOVIv2i32: 1625 case AArch64::MOVIv4i32: 1626 case AArch64::MVNIv2i32: 1627 case AArch64::MVNIv4i32: 1628 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1629 break; 1630 case AArch64::MOVIv2s_msl: 1631 case AArch64::MOVIv4s_msl: 1632 case AArch64::MVNIv2s_msl: 1633 case AArch64::MVNIv4s_msl: 1634 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1635 break; 1636 } 1637 1638 return Success; 1639 } 1640 1641 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1642 uint64_t Addr, 1643 const MCDisassembler *Decoder) { 1644 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1645 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1646 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1647 imm |= fieldFromInstruction(insn, 5, 5); 1648 1649 // Tied operands added twice. 1650 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1651 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1652 1653 Inst.addOperand(MCOperand::createImm(imm)); 1654 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1655 1656 return Success; 1657 } 1658 1659 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1660 uint64_t Addr, 1661 const MCDisassembler *Decoder) { 1662 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1663 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1664 imm |= fieldFromInstruction(insn, 29, 2); 1665 1666 // Sign-extend the 21-bit immediate. 1667 if (imm & (1 << (21 - 1))) 1668 imm |= ~((1LL << 21) - 1); 1669 1670 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1671 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1672 Inst.addOperand(MCOperand::createImm(imm)); 1673 1674 return Success; 1675 } 1676 1677 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1678 uint64_t Addr, 1679 const MCDisassembler *Decoder) { 1680 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1681 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1682 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1683 unsigned S = fieldFromInstruction(insn, 29, 1); 1684 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1685 1686 unsigned ShifterVal = (Imm >> 12) & 3; 1687 unsigned ImmVal = Imm & 0xFFF; 1688 1689 if (ShifterVal != 0 && ShifterVal != 1) 1690 return Fail; 1691 1692 if (Datasize) { 1693 if (Rd == 31 && !S) 1694 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1695 else 1696 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1697 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1698 } else { 1699 if (Rd == 31 && !S) 1700 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1701 else 1702 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1703 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1704 } 1705 1706 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1707 Inst.addOperand(MCOperand::createImm(ImmVal)); 1708 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1709 return Success; 1710 } 1711 1712 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1713 uint64_t Addr, 1714 const MCDisassembler *Decoder) { 1715 int64_t imm = fieldFromInstruction(insn, 0, 26); 1716 1717 // Sign-extend the 26-bit immediate. 1718 if (imm & (1 << (26 - 1))) 1719 imm |= ~((1LL << 26) - 1); 1720 1721 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1722 Inst.addOperand(MCOperand::createImm(imm)); 1723 1724 return Success; 1725 } 1726 1727 static DecodeStatus 1728 DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1729 const MCDisassembler *Decoder) { 1730 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1731 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1732 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1733 uint64_t pstate_field = (op1 << 3) | op2; 1734 1735 switch (pstate_field) { 1736 case 0x01: // XAFlag 1737 case 0x02: // AXFlag 1738 return Fail; 1739 } 1740 1741 if ((pstate_field == AArch64PState::PAN || 1742 pstate_field == AArch64PState::UAO || 1743 pstate_field == AArch64PState::SSBS) && crm > 1) 1744 return Fail; 1745 1746 Inst.addOperand(MCOperand::createImm(pstate_field)); 1747 Inst.addOperand(MCOperand::createImm(crm)); 1748 1749 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1750 if (PState && 1751 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits())) 1752 return Success; 1753 return Fail; 1754 } 1755 1756 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1757 uint64_t Addr, 1758 const MCDisassembler *Decoder) { 1759 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1760 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1761 bit |= fieldFromInstruction(insn, 19, 5); 1762 int64_t dst = fieldFromInstruction(insn, 5, 14); 1763 1764 // Sign-extend 14-bit immediate. 1765 if (dst & (1 << (14 - 1))) 1766 dst |= ~((1LL << 14) - 1); 1767 1768 if (fieldFromInstruction(insn, 31, 1) == 0) 1769 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1770 else 1771 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1772 Inst.addOperand(MCOperand::createImm(bit)); 1773 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1774 Inst.addOperand(MCOperand::createImm(dst)); 1775 1776 return Success; 1777 } 1778 1779 static DecodeStatus 1780 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, 1781 unsigned RegNo, uint64_t Addr, 1782 const MCDisassembler *Decoder) { 1783 // Register number must be even (see CASP instruction) 1784 if (RegNo & 0x1) 1785 return Fail; 1786 1787 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1788 Inst.addOperand(MCOperand::createReg(Reg)); 1789 return Success; 1790 } 1791 1792 static DecodeStatus 1793 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 1794 const MCDisassembler *Decoder) { 1795 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1796 AArch64::WSeqPairsClassRegClassID, 1797 RegNo, Addr, Decoder); 1798 } 1799 1800 static DecodeStatus 1801 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 1802 const MCDisassembler *Decoder) { 1803 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1804 AArch64::XSeqPairsClassRegClassID, 1805 RegNo, Addr, Decoder); 1806 } 1807 1808 static DecodeStatus 1809 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1810 const MCDisassembler *Decoder) { 1811 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1812 unsigned imm = fieldFromInstruction(insn, 5, 13); 1813 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1814 return Fail; 1815 1816 // The same (tied) operand is added twice to the instruction. 1817 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1818 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1819 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1820 Inst.addOperand(MCOperand::createImm(imm)); 1821 return Success; 1822 } 1823 1824 template <int Bits> 1825 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 1826 const MCDisassembler *Decoder) { 1827 if (Imm & ~((1LL << Bits) - 1)) 1828 return Fail; 1829 1830 // Imm is a signed immediate, so sign extend it. 1831 if (Imm & (1 << (Bits - 1))) 1832 Imm |= ~((1LL << Bits) - 1); 1833 1834 Inst.addOperand(MCOperand::createImm(Imm)); 1835 return Success; 1836 } 1837 1838 // Decode 8-bit signed/unsigned immediate for a given element width. 1839 template <int ElementWidth> 1840 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, 1841 const MCDisassembler *Decoder) { 1842 unsigned Val = (uint8_t)Imm; 1843 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1844 if (ElementWidth == 8 && Shift) 1845 return Fail; 1846 Inst.addOperand(MCOperand::createImm(Val)); 1847 Inst.addOperand(MCOperand::createImm(Shift)); 1848 return Success; 1849 } 1850 1851 // Decode uimm4 ranged from 1-16. 1852 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1853 uint64_t Addr, 1854 const MCDisassembler *Decoder) { 1855 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1856 return Success; 1857 } 1858 1859 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 1860 const MCDisassembler *Decoder) { 1861 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 1862 Inst.addOperand(MCOperand::createImm(Imm)); 1863 return Success; 1864 } 1865 return Fail; 1866 } 1867 1868 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, 1869 uint64_t Addr, 1870 const MCDisassembler *Decoder) { 1871 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1872 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1873 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1874 1875 // None of the registers may alias: if they do, then the instruction is not 1876 // merely unpredictable but actually entirely unallocated. 1877 if (Rd == Rs || Rs == Rn || Rd == Rn) 1878 return MCDisassembler::Fail; 1879 1880 // All three register operands are written back, so they all appear 1881 // twice in the operand list, once as outputs and once as inputs. 1882 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1883 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) || 1884 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1885 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1886 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) || 1887 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder)) 1888 return MCDisassembler::Fail; 1889 1890 return MCDisassembler::Success; 1891 } 1892 1893 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, 1894 uint64_t Addr, 1895 const MCDisassembler *Decoder) { 1896 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1897 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1898 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1899 1900 // None of the registers may alias: if they do, then the instruction is not 1901 // merely unpredictable but actually entirely unallocated. 1902 if (Rd == Rm || Rm == Rn || Rd == Rn) 1903 return MCDisassembler::Fail; 1904 1905 // Rd and Rn (not Rm) register operands are written back, so they appear 1906 // twice in the operand list, once as outputs and once as inputs. 1907 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1908 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1909 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1910 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1911 !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder)) 1912 return MCDisassembler::Fail; 1913 1914 return MCDisassembler::Success; 1915 } 1916