1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 73 uint64_t Address, 74 const void *Decoder); 75 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 76 unsigned RegNo, uint64_t Address, 77 const void *Decoder); 78 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 82 uint64_t Address, 83 const void *Decoder); 84 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 91 uint64_t Address, 92 const void *Decoder); 93 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const void *Decoder); 99 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114 template <unsigned NumBitsForTile> 115 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 121 uint64_t Address, 122 const void *Decoder); 123 124 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 139 uint64_t Address, 140 const void *Decoder); 141 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 142 uint64_t Address, 143 const void *Decoder); 144 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 145 uint64_t Address, 146 const void *Decoder); 147 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 148 uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 151 uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 154 uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 157 uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 160 uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 163 uint64_t Address, 164 const void *Decoder); 165 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 166 uint64_t Address, 167 const void *Decoder); 168 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 169 uint64_t Address, 170 const void *Decoder); 171 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 176 uint64_t Address, 177 const void *Decoder); 178 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 179 uint64_t Address, 180 const void *Decoder); 181 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 182 uint64_t Address, const void *Decoder); 183 184 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 185 uint64_t Address, 186 const void *Decoder); 187 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 188 uint64_t Addr, const void *Decoder); 189 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 190 uint64_t Addr, 191 const void *Decoder); 192 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 193 uint64_t Addr, const void *Decoder); 194 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 195 uint64_t Addr, 196 const void *Decoder); 197 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 198 uint64_t Addr, const void *Decoder); 199 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, 201 const void *Decoder); 202 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, const void *Decoder); 204 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 205 uint64_t Addr, const void *Decoder); 206 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 207 uint64_t Addr, const void *Decoder); 208 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 209 uint64_t Addr, const void *Decoder); 210 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 213 unsigned RegNo, 214 uint64_t Addr, 215 const void *Decoder); 216 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 217 unsigned RegNo, 218 uint64_t Addr, 219 const void *Decoder); 220 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 221 uint32_t insn, 222 uint64_t Address, 223 const void *Decoder); 224 template<int Bits> 225 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 226 uint64_t Address, const void *Decoder); 227 template <int ElementWidth> 228 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 229 uint64_t Addr, const void *Decoder); 230 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 231 uint64_t Addr, const void *Decoder); 232 233 static bool Check(DecodeStatus &Out, DecodeStatus In) { 234 switch (In) { 235 case MCDisassembler::Success: 236 // Out stays the same. 237 return true; 238 case MCDisassembler::SoftFail: 239 Out = In; 240 return true; 241 case MCDisassembler::Fail: 242 Out = In; 243 return false; 244 } 245 llvm_unreachable("Invalid DecodeStatus!"); 246 } 247 248 #include "AArch64GenDisassemblerTables.inc" 249 #include "AArch64GenInstrInfo.inc" 250 251 #define Success MCDisassembler::Success 252 #define Fail MCDisassembler::Fail 253 #define SoftFail MCDisassembler::SoftFail 254 255 static MCDisassembler *createAArch64Disassembler(const Target &T, 256 const MCSubtargetInfo &STI, 257 MCContext &Ctx) { 258 return new AArch64Disassembler(STI, Ctx); 259 } 260 261 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 262 ArrayRef<uint8_t> Bytes, 263 uint64_t Address, 264 raw_ostream &CS) const { 265 CommentStream = &CS; 266 267 Size = 0; 268 // We want to read exactly 4 bytes of data. 269 if (Bytes.size() < 4) 270 return Fail; 271 Size = 4; 272 273 // Encoded as a small-endian 32-bit word in the stream. 274 uint32_t Insn = 275 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 276 277 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 278 279 for (auto Table : Tables) { 280 DecodeStatus Result = 281 decodeInstruction(Table, MI, Insn, Address, this, STI); 282 if (Result != MCDisassembler::Fail) 283 return Result; 284 } 285 286 return MCDisassembler::Fail; 287 } 288 289 static MCSymbolizer * 290 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 291 LLVMSymbolLookupCallback SymbolLookUp, 292 void *DisInfo, MCContext *Ctx, 293 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 294 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 295 SymbolLookUp, DisInfo); 296 } 297 298 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 299 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 300 createAArch64Disassembler); 301 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 302 createAArch64Disassembler); 303 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 304 createAArch64ExternalSymbolizer); 305 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 306 createAArch64ExternalSymbolizer); 307 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 308 createAArch64Disassembler); 309 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 310 createAArch64ExternalSymbolizer); 311 312 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 313 createAArch64Disassembler); 314 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 315 createAArch64ExternalSymbolizer); 316 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 317 createAArch64Disassembler); 318 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 319 createAArch64ExternalSymbolizer); 320 } 321 322 static const unsigned FPR128DecoderTable[] = { 323 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 324 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 325 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 326 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 327 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 328 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 329 AArch64::Q30, AArch64::Q31 330 }; 331 332 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 333 uint64_t Addr, 334 const void *Decoder) { 335 if (RegNo > 31) 336 return Fail; 337 338 unsigned Register = FPR128DecoderTable[RegNo]; 339 Inst.addOperand(MCOperand::createReg(Register)); 340 return Success; 341 } 342 343 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 344 uint64_t Addr, 345 const void *Decoder) { 346 if (RegNo > 15) 347 return Fail; 348 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 349 } 350 351 static const unsigned FPR64DecoderTable[] = { 352 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 353 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 354 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 355 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 356 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 357 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 358 AArch64::D30, AArch64::D31 359 }; 360 361 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 362 uint64_t Addr, 363 const void *Decoder) { 364 if (RegNo > 31) 365 return Fail; 366 367 unsigned Register = FPR64DecoderTable[RegNo]; 368 Inst.addOperand(MCOperand::createReg(Register)); 369 return Success; 370 } 371 372 static const unsigned FPR32DecoderTable[] = { 373 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 374 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 375 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 376 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 377 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 378 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 379 AArch64::S30, AArch64::S31 380 }; 381 382 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 383 uint64_t Addr, 384 const void *Decoder) { 385 if (RegNo > 31) 386 return Fail; 387 388 unsigned Register = FPR32DecoderTable[RegNo]; 389 Inst.addOperand(MCOperand::createReg(Register)); 390 return Success; 391 } 392 393 static const unsigned FPR16DecoderTable[] = { 394 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 395 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 396 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 397 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 398 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 399 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 400 AArch64::H30, AArch64::H31 401 }; 402 403 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 404 uint64_t Addr, 405 const void *Decoder) { 406 if (RegNo > 31) 407 return Fail; 408 409 unsigned Register = FPR16DecoderTable[RegNo]; 410 Inst.addOperand(MCOperand::createReg(Register)); 411 return Success; 412 } 413 414 static const unsigned FPR8DecoderTable[] = { 415 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 416 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 417 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 418 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 419 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 420 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 421 AArch64::B30, AArch64::B31 422 }; 423 424 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 425 uint64_t Addr, 426 const void *Decoder) { 427 if (RegNo > 31) 428 return Fail; 429 430 unsigned Register = FPR8DecoderTable[RegNo]; 431 Inst.addOperand(MCOperand::createReg(Register)); 432 return Success; 433 } 434 435 static const unsigned GPR64DecoderTable[] = { 436 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 437 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 438 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 439 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 440 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 441 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 442 AArch64::LR, AArch64::XZR 443 }; 444 445 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 446 uint64_t Addr, 447 const void *Decoder) { 448 if (RegNo > 30) 449 return Fail; 450 451 unsigned Register = GPR64DecoderTable[RegNo]; 452 Inst.addOperand(MCOperand::createReg(Register)); 453 return Success; 454 } 455 456 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 457 uint64_t Addr, 458 const void *Decoder) { 459 if (RegNo > 31) 460 return Fail; 461 462 unsigned Register = GPR64DecoderTable[RegNo]; 463 Inst.addOperand(MCOperand::createReg(Register)); 464 return Success; 465 } 466 467 static const unsigned GPR64x8DecoderTable[] = { 468 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 469 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 470 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 471 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 472 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 473 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 474 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 475 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 476 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 477 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 478 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 479 AArch64::X22_X23_X24_X25_X26_X27_X28_FP, 480 }; 481 482 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 483 unsigned RegNo, 484 uint64_t Address, 485 const void *Decoder) { 486 if (RegNo > 22) 487 return Fail; 488 if (RegNo & 1) 489 return Fail; 490 491 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 492 Inst.addOperand(MCOperand::createReg(Register)); 493 return Success; 494 } 495 496 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 497 uint64_t Addr, 498 const void *Decoder) { 499 if (RegNo > 31) 500 return Fail; 501 unsigned Register = GPR64DecoderTable[RegNo]; 502 if (Register == AArch64::XZR) 503 Register = AArch64::SP; 504 Inst.addOperand(MCOperand::createReg(Register)); 505 return Success; 506 } 507 508 static const unsigned GPR32DecoderTable[] = { 509 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 510 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 511 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 512 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 513 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 514 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 515 AArch64::W30, AArch64::WZR 516 }; 517 518 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 519 uint64_t Addr, 520 const void *Decoder) { 521 if (RegNo > 31) 522 return Fail; 523 524 unsigned Register = GPR32DecoderTable[RegNo]; 525 Inst.addOperand(MCOperand::createReg(Register)); 526 return Success; 527 } 528 529 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 530 uint64_t Addr, 531 const void *Decoder) { 532 if (RegNo > 31) 533 return Fail; 534 535 unsigned Register = GPR32DecoderTable[RegNo]; 536 if (Register == AArch64::WZR) 537 Register = AArch64::WSP; 538 Inst.addOperand(MCOperand::createReg(Register)); 539 return Success; 540 } 541 static const unsigned ZPRDecoderTable[] = { 542 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 543 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 544 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 545 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 546 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 547 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 548 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 549 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 550 }; 551 552 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 553 uint64_t Address, 554 const void* Decoder) { 555 if (RegNo > 31) 556 return Fail; 557 558 unsigned Register = ZPRDecoderTable[RegNo]; 559 Inst.addOperand(MCOperand::createReg(Register)); 560 return Success; 561 } 562 563 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 564 uint64_t Address, 565 const void *Decoder) { 566 if (RegNo > 15) 567 return Fail; 568 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 569 } 570 571 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 572 uint64_t Address, 573 const void *Decoder) { 574 if (RegNo > 7) 575 return Fail; 576 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 577 } 578 579 static const unsigned ZZDecoderTable[] = { 580 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 581 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 582 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 583 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 584 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 585 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 586 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 587 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 588 }; 589 590 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 591 uint64_t Address, 592 const void* Decoder) { 593 if (RegNo > 31) 594 return Fail; 595 unsigned Register = ZZDecoderTable[RegNo]; 596 Inst.addOperand(MCOperand::createReg(Register)); 597 return Success; 598 } 599 600 static const unsigned ZZZDecoderTable[] = { 601 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 602 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 603 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 604 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 605 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 606 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 607 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 608 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 609 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 610 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 611 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 612 }; 613 614 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 615 uint64_t Address, 616 const void* Decoder) { 617 if (RegNo > 31) 618 return Fail; 619 unsigned Register = ZZZDecoderTable[RegNo]; 620 Inst.addOperand(MCOperand::createReg(Register)); 621 return Success; 622 } 623 624 static const unsigned ZZZZDecoderTable[] = { 625 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 626 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 627 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 628 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 629 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 630 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 631 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 632 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 633 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 634 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 635 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 636 }; 637 638 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 639 uint64_t Address, 640 const void* Decoder) { 641 if (RegNo > 31) 642 return Fail; 643 unsigned Register = ZZZZDecoderTable[RegNo]; 644 Inst.addOperand(MCOperand::createReg(Register)); 645 return Success; 646 } 647 648 static const SmallVector<SmallVector<unsigned, 16>, 5> 649 MatrixZATileDecoderTable = { 650 {AArch64::ZAB0}, 651 {AArch64::ZAH0, AArch64::ZAH1}, 652 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 653 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 654 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 655 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 656 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 657 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 658 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 659 660 template <unsigned NumBitsForTile> 661 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 662 uint64_t Address, const void *Decoder) { 663 unsigned LastReg = (1 << NumBitsForTile) - 1; 664 if (RegNo > LastReg) 665 return Fail; 666 Inst.addOperand( 667 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 668 return Success; 669 } 670 671 static const unsigned PPRDecoderTable[] = { 672 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 673 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 674 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 675 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 676 }; 677 678 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 679 uint64_t Addr, const void *Decoder) { 680 if (RegNo > 15) 681 return Fail; 682 683 unsigned Register = PPRDecoderTable[RegNo]; 684 Inst.addOperand(MCOperand::createReg(Register)); 685 return Success; 686 } 687 688 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 689 uint64_t Addr, 690 const void* Decoder) { 691 if (RegNo > 7) 692 return Fail; 693 694 // Just reuse the PPR decode table 695 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 696 } 697 698 static const unsigned VectorDecoderTable[] = { 699 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 700 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 701 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 702 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 703 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 704 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 705 AArch64::Q30, AArch64::Q31 706 }; 707 708 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 709 uint64_t Addr, 710 const void *Decoder) { 711 if (RegNo > 31) 712 return Fail; 713 714 unsigned Register = VectorDecoderTable[RegNo]; 715 Inst.addOperand(MCOperand::createReg(Register)); 716 return Success; 717 } 718 719 static const unsigned QQDecoderTable[] = { 720 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 721 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 722 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 723 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 724 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 725 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 726 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 727 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 728 }; 729 730 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 731 uint64_t Addr, const void *Decoder) { 732 if (RegNo > 31) 733 return Fail; 734 unsigned Register = QQDecoderTable[RegNo]; 735 Inst.addOperand(MCOperand::createReg(Register)); 736 return Success; 737 } 738 739 static const unsigned QQQDecoderTable[] = { 740 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 741 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 742 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 743 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 744 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 745 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 746 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 747 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 748 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 749 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 750 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 751 }; 752 753 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 754 uint64_t Addr, const void *Decoder) { 755 if (RegNo > 31) 756 return Fail; 757 unsigned Register = QQQDecoderTable[RegNo]; 758 Inst.addOperand(MCOperand::createReg(Register)); 759 return Success; 760 } 761 762 static const unsigned QQQQDecoderTable[] = { 763 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 764 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 765 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 766 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 767 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 768 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 769 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 770 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 771 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 772 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 773 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 774 }; 775 776 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 777 uint64_t Addr, 778 const void *Decoder) { 779 if (RegNo > 31) 780 return Fail; 781 unsigned Register = QQQQDecoderTable[RegNo]; 782 Inst.addOperand(MCOperand::createReg(Register)); 783 return Success; 784 } 785 786 static const unsigned DDDecoderTable[] = { 787 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 788 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 789 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 790 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 791 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 792 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 793 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 794 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 795 }; 796 797 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 798 uint64_t Addr, const void *Decoder) { 799 if (RegNo > 31) 800 return Fail; 801 unsigned Register = DDDecoderTable[RegNo]; 802 Inst.addOperand(MCOperand::createReg(Register)); 803 return Success; 804 } 805 806 static const unsigned DDDDecoderTable[] = { 807 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 808 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 809 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 810 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 811 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 812 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 813 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 814 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 815 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 816 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 817 AArch64::D30_D31_D0, AArch64::D31_D0_D1 818 }; 819 820 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 821 uint64_t Addr, const void *Decoder) { 822 if (RegNo > 31) 823 return Fail; 824 unsigned Register = DDDDecoderTable[RegNo]; 825 Inst.addOperand(MCOperand::createReg(Register)); 826 return Success; 827 } 828 829 static const unsigned DDDDDecoderTable[] = { 830 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 831 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 832 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 833 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 834 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 835 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 836 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 837 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 838 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 839 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 840 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 841 }; 842 843 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 844 uint64_t Addr, 845 const void *Decoder) { 846 if (RegNo > 31) 847 return Fail; 848 unsigned Register = DDDDDecoderTable[RegNo]; 849 Inst.addOperand(MCOperand::createReg(Register)); 850 return Success; 851 } 852 853 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 854 uint64_t Addr, 855 const void *Decoder) { 856 // scale{5} is asserted as 1 in tblgen. 857 Imm |= 0x20; 858 Inst.addOperand(MCOperand::createImm(64 - Imm)); 859 return Success; 860 } 861 862 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 863 uint64_t Addr, 864 const void *Decoder) { 865 Inst.addOperand(MCOperand::createImm(64 - Imm)); 866 return Success; 867 } 868 869 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 870 uint64_t Addr, const void *Decoder) { 871 int64_t ImmVal = Imm; 872 const AArch64Disassembler *Dis = 873 static_cast<const AArch64Disassembler *>(Decoder); 874 875 // Sign-extend 19-bit immediate. 876 if (ImmVal & (1 << (19 - 1))) 877 ImmVal |= ~((1LL << 19) - 1); 878 879 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 880 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 881 Inst.addOperand(MCOperand::createImm(ImmVal)); 882 return Success; 883 } 884 885 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 886 uint64_t Address, const void *Decoder) { 887 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 888 Inst.addOperand(MCOperand::createImm(Imm & 1)); 889 return Success; 890 } 891 892 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 893 uint64_t Address, 894 const void *Decoder) { 895 Inst.addOperand(MCOperand::createImm(Imm)); 896 897 // Every system register in the encoding space is valid with the syntax 898 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 899 return Success; 900 } 901 902 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 903 uint64_t Address, 904 const void *Decoder) { 905 Inst.addOperand(MCOperand::createImm(Imm)); 906 907 return Success; 908 } 909 910 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 911 uint64_t Address, 912 const void *Decoder) { 913 // This decoder exists to add the dummy Lane operand to the MCInst, which must 914 // be 1 in assembly but has no other real manifestation. 915 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 916 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 917 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 918 919 if (IsToVec) { 920 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 921 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 922 } else { 923 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 924 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 925 } 926 927 // Add the lane 928 Inst.addOperand(MCOperand::createImm(1)); 929 930 return Success; 931 } 932 933 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 934 unsigned Add) { 935 Inst.addOperand(MCOperand::createImm(Add - Imm)); 936 return Success; 937 } 938 939 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 940 unsigned Add) { 941 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 942 return Success; 943 } 944 945 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 946 uint64_t Addr, const void *Decoder) { 947 return DecodeVecShiftRImm(Inst, Imm, 64); 948 } 949 950 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 951 uint64_t Addr, 952 const void *Decoder) { 953 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 954 } 955 956 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 957 uint64_t Addr, const void *Decoder) { 958 return DecodeVecShiftRImm(Inst, Imm, 32); 959 } 960 961 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 962 uint64_t Addr, 963 const void *Decoder) { 964 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 965 } 966 967 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 968 uint64_t Addr, const void *Decoder) { 969 return DecodeVecShiftRImm(Inst, Imm, 16); 970 } 971 972 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 973 uint64_t Addr, 974 const void *Decoder) { 975 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 976 } 977 978 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 979 uint64_t Addr, const void *Decoder) { 980 return DecodeVecShiftRImm(Inst, Imm, 8); 981 } 982 983 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 984 uint64_t Addr, const void *Decoder) { 985 return DecodeVecShiftLImm(Inst, Imm, 64); 986 } 987 988 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 989 uint64_t Addr, const void *Decoder) { 990 return DecodeVecShiftLImm(Inst, Imm, 32); 991 } 992 993 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 994 uint64_t Addr, const void *Decoder) { 995 return DecodeVecShiftLImm(Inst, Imm, 16); 996 } 997 998 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 999 uint64_t Addr, const void *Decoder) { 1000 return DecodeVecShiftLImm(Inst, Imm, 8); 1001 } 1002 1003 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 1004 uint64_t Addr, 1005 const void *Decoder) { 1006 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1007 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1008 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1009 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 1010 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 1011 unsigned shift = (shiftHi << 6) | shiftLo; 1012 switch (Inst.getOpcode()) { 1013 default: 1014 return Fail; 1015 case AArch64::ADDWrs: 1016 case AArch64::ADDSWrs: 1017 case AArch64::SUBWrs: 1018 case AArch64::SUBSWrs: 1019 // if shift == '11' then ReservedValue() 1020 if (shiftHi == 0x3) 1021 return Fail; 1022 LLVM_FALLTHROUGH; 1023 case AArch64::ANDWrs: 1024 case AArch64::ANDSWrs: 1025 case AArch64::BICWrs: 1026 case AArch64::BICSWrs: 1027 case AArch64::ORRWrs: 1028 case AArch64::ORNWrs: 1029 case AArch64::EORWrs: 1030 case AArch64::EONWrs: { 1031 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1032 if (shiftLo >> 5 == 1) 1033 return Fail; 1034 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1035 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1036 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1037 break; 1038 } 1039 case AArch64::ADDXrs: 1040 case AArch64::ADDSXrs: 1041 case AArch64::SUBXrs: 1042 case AArch64::SUBSXrs: 1043 // if shift == '11' then ReservedValue() 1044 if (shiftHi == 0x3) 1045 return Fail; 1046 LLVM_FALLTHROUGH; 1047 case AArch64::ANDXrs: 1048 case AArch64::ANDSXrs: 1049 case AArch64::BICXrs: 1050 case AArch64::BICSXrs: 1051 case AArch64::ORRXrs: 1052 case AArch64::ORNXrs: 1053 case AArch64::EORXrs: 1054 case AArch64::EONXrs: 1055 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1056 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1057 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1058 break; 1059 } 1060 1061 Inst.addOperand(MCOperand::createImm(shift)); 1062 return Success; 1063 } 1064 1065 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1066 uint64_t Addr, 1067 const void *Decoder) { 1068 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1069 unsigned imm = fieldFromInstruction(insn, 5, 16); 1070 unsigned shift = fieldFromInstruction(insn, 21, 2); 1071 shift <<= 4; 1072 switch (Inst.getOpcode()) { 1073 default: 1074 return Fail; 1075 case AArch64::MOVZWi: 1076 case AArch64::MOVNWi: 1077 case AArch64::MOVKWi: 1078 if (shift & (1U << 5)) 1079 return Fail; 1080 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1081 break; 1082 case AArch64::MOVZXi: 1083 case AArch64::MOVNXi: 1084 case AArch64::MOVKXi: 1085 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1086 break; 1087 } 1088 1089 if (Inst.getOpcode() == AArch64::MOVKWi || 1090 Inst.getOpcode() == AArch64::MOVKXi) 1091 Inst.addOperand(Inst.getOperand(0)); 1092 1093 Inst.addOperand(MCOperand::createImm(imm)); 1094 Inst.addOperand(MCOperand::createImm(shift)); 1095 return Success; 1096 } 1097 1098 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1099 uint64_t Addr, 1100 const void *Decoder) { 1101 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1102 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1103 unsigned offset = fieldFromInstruction(insn, 10, 12); 1104 const AArch64Disassembler *Dis = 1105 static_cast<const AArch64Disassembler *>(Decoder); 1106 1107 switch (Inst.getOpcode()) { 1108 default: 1109 return Fail; 1110 case AArch64::PRFMui: 1111 // Rt is an immediate in prefetch. 1112 Inst.addOperand(MCOperand::createImm(Rt)); 1113 break; 1114 case AArch64::STRBBui: 1115 case AArch64::LDRBBui: 1116 case AArch64::LDRSBWui: 1117 case AArch64::STRHHui: 1118 case AArch64::LDRHHui: 1119 case AArch64::LDRSHWui: 1120 case AArch64::STRWui: 1121 case AArch64::LDRWui: 1122 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1123 break; 1124 case AArch64::LDRSBXui: 1125 case AArch64::LDRSHXui: 1126 case AArch64::LDRSWui: 1127 case AArch64::STRXui: 1128 case AArch64::LDRXui: 1129 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1130 break; 1131 case AArch64::LDRQui: 1132 case AArch64::STRQui: 1133 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1134 break; 1135 case AArch64::LDRDui: 1136 case AArch64::STRDui: 1137 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1138 break; 1139 case AArch64::LDRSui: 1140 case AArch64::STRSui: 1141 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1142 break; 1143 case AArch64::LDRHui: 1144 case AArch64::STRHui: 1145 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1146 break; 1147 case AArch64::LDRBui: 1148 case AArch64::STRBui: 1149 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1150 break; 1151 } 1152 1153 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1154 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1155 Inst.addOperand(MCOperand::createImm(offset)); 1156 return Success; 1157 } 1158 1159 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1160 uint64_t Addr, 1161 const void *Decoder) { 1162 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1163 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1164 int64_t offset = fieldFromInstruction(insn, 12, 9); 1165 1166 // offset is a 9-bit signed immediate, so sign extend it to 1167 // fill the unsigned. 1168 if (offset & (1 << (9 - 1))) 1169 offset |= ~((1LL << 9) - 1); 1170 1171 // First operand is always the writeback to the address register, if needed. 1172 switch (Inst.getOpcode()) { 1173 default: 1174 break; 1175 case AArch64::LDRSBWpre: 1176 case AArch64::LDRSHWpre: 1177 case AArch64::STRBBpre: 1178 case AArch64::LDRBBpre: 1179 case AArch64::STRHHpre: 1180 case AArch64::LDRHHpre: 1181 case AArch64::STRWpre: 1182 case AArch64::LDRWpre: 1183 case AArch64::LDRSBWpost: 1184 case AArch64::LDRSHWpost: 1185 case AArch64::STRBBpost: 1186 case AArch64::LDRBBpost: 1187 case AArch64::STRHHpost: 1188 case AArch64::LDRHHpost: 1189 case AArch64::STRWpost: 1190 case AArch64::LDRWpost: 1191 case AArch64::LDRSBXpre: 1192 case AArch64::LDRSHXpre: 1193 case AArch64::STRXpre: 1194 case AArch64::LDRSWpre: 1195 case AArch64::LDRXpre: 1196 case AArch64::LDRSBXpost: 1197 case AArch64::LDRSHXpost: 1198 case AArch64::STRXpost: 1199 case AArch64::LDRSWpost: 1200 case AArch64::LDRXpost: 1201 case AArch64::LDRQpre: 1202 case AArch64::STRQpre: 1203 case AArch64::LDRQpost: 1204 case AArch64::STRQpost: 1205 case AArch64::LDRDpre: 1206 case AArch64::STRDpre: 1207 case AArch64::LDRDpost: 1208 case AArch64::STRDpost: 1209 case AArch64::LDRSpre: 1210 case AArch64::STRSpre: 1211 case AArch64::LDRSpost: 1212 case AArch64::STRSpost: 1213 case AArch64::LDRHpre: 1214 case AArch64::STRHpre: 1215 case AArch64::LDRHpost: 1216 case AArch64::STRHpost: 1217 case AArch64::LDRBpre: 1218 case AArch64::STRBpre: 1219 case AArch64::LDRBpost: 1220 case AArch64::STRBpost: 1221 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1222 break; 1223 } 1224 1225 switch (Inst.getOpcode()) { 1226 default: 1227 return Fail; 1228 case AArch64::PRFUMi: 1229 // Rt is an immediate in prefetch. 1230 Inst.addOperand(MCOperand::createImm(Rt)); 1231 break; 1232 case AArch64::STURBBi: 1233 case AArch64::LDURBBi: 1234 case AArch64::LDURSBWi: 1235 case AArch64::STURHHi: 1236 case AArch64::LDURHHi: 1237 case AArch64::LDURSHWi: 1238 case AArch64::STURWi: 1239 case AArch64::LDURWi: 1240 case AArch64::LDTRSBWi: 1241 case AArch64::LDTRSHWi: 1242 case AArch64::STTRWi: 1243 case AArch64::LDTRWi: 1244 case AArch64::STTRHi: 1245 case AArch64::LDTRHi: 1246 case AArch64::LDTRBi: 1247 case AArch64::STTRBi: 1248 case AArch64::LDRSBWpre: 1249 case AArch64::LDRSHWpre: 1250 case AArch64::STRBBpre: 1251 case AArch64::LDRBBpre: 1252 case AArch64::STRHHpre: 1253 case AArch64::LDRHHpre: 1254 case AArch64::STRWpre: 1255 case AArch64::LDRWpre: 1256 case AArch64::LDRSBWpost: 1257 case AArch64::LDRSHWpost: 1258 case AArch64::STRBBpost: 1259 case AArch64::LDRBBpost: 1260 case AArch64::STRHHpost: 1261 case AArch64::LDRHHpost: 1262 case AArch64::STRWpost: 1263 case AArch64::LDRWpost: 1264 case AArch64::STLURBi: 1265 case AArch64::STLURHi: 1266 case AArch64::STLURWi: 1267 case AArch64::LDAPURBi: 1268 case AArch64::LDAPURSBWi: 1269 case AArch64::LDAPURHi: 1270 case AArch64::LDAPURSHWi: 1271 case AArch64::LDAPURi: 1272 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1273 break; 1274 case AArch64::LDURSBXi: 1275 case AArch64::LDURSHXi: 1276 case AArch64::LDURSWi: 1277 case AArch64::STURXi: 1278 case AArch64::LDURXi: 1279 case AArch64::LDTRSBXi: 1280 case AArch64::LDTRSHXi: 1281 case AArch64::LDTRSWi: 1282 case AArch64::STTRXi: 1283 case AArch64::LDTRXi: 1284 case AArch64::LDRSBXpre: 1285 case AArch64::LDRSHXpre: 1286 case AArch64::STRXpre: 1287 case AArch64::LDRSWpre: 1288 case AArch64::LDRXpre: 1289 case AArch64::LDRSBXpost: 1290 case AArch64::LDRSHXpost: 1291 case AArch64::STRXpost: 1292 case AArch64::LDRSWpost: 1293 case AArch64::LDRXpost: 1294 case AArch64::LDAPURSWi: 1295 case AArch64::LDAPURSHXi: 1296 case AArch64::LDAPURSBXi: 1297 case AArch64::STLURXi: 1298 case AArch64::LDAPURXi: 1299 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1300 break; 1301 case AArch64::LDURQi: 1302 case AArch64::STURQi: 1303 case AArch64::LDRQpre: 1304 case AArch64::STRQpre: 1305 case AArch64::LDRQpost: 1306 case AArch64::STRQpost: 1307 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1308 break; 1309 case AArch64::LDURDi: 1310 case AArch64::STURDi: 1311 case AArch64::LDRDpre: 1312 case AArch64::STRDpre: 1313 case AArch64::LDRDpost: 1314 case AArch64::STRDpost: 1315 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1316 break; 1317 case AArch64::LDURSi: 1318 case AArch64::STURSi: 1319 case AArch64::LDRSpre: 1320 case AArch64::STRSpre: 1321 case AArch64::LDRSpost: 1322 case AArch64::STRSpost: 1323 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1324 break; 1325 case AArch64::LDURHi: 1326 case AArch64::STURHi: 1327 case AArch64::LDRHpre: 1328 case AArch64::STRHpre: 1329 case AArch64::LDRHpost: 1330 case AArch64::STRHpost: 1331 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1332 break; 1333 case AArch64::LDURBi: 1334 case AArch64::STURBi: 1335 case AArch64::LDRBpre: 1336 case AArch64::STRBpre: 1337 case AArch64::LDRBpost: 1338 case AArch64::STRBpost: 1339 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1340 break; 1341 } 1342 1343 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1344 Inst.addOperand(MCOperand::createImm(offset)); 1345 1346 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1347 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1348 bool IsFP = fieldFromInstruction(insn, 26, 1); 1349 1350 // Cannot write back to a transfer register (but xzr != sp). 1351 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1352 return SoftFail; 1353 1354 return Success; 1355 } 1356 1357 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1358 uint64_t Addr, 1359 const void *Decoder) { 1360 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1361 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1362 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1363 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1364 1365 unsigned Opcode = Inst.getOpcode(); 1366 switch (Opcode) { 1367 default: 1368 return Fail; 1369 case AArch64::STLXRW: 1370 case AArch64::STLXRB: 1371 case AArch64::STLXRH: 1372 case AArch64::STXRW: 1373 case AArch64::STXRB: 1374 case AArch64::STXRH: 1375 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1376 LLVM_FALLTHROUGH; 1377 case AArch64::LDARW: 1378 case AArch64::LDARB: 1379 case AArch64::LDARH: 1380 case AArch64::LDAXRW: 1381 case AArch64::LDAXRB: 1382 case AArch64::LDAXRH: 1383 case AArch64::LDXRW: 1384 case AArch64::LDXRB: 1385 case AArch64::LDXRH: 1386 case AArch64::STLRW: 1387 case AArch64::STLRB: 1388 case AArch64::STLRH: 1389 case AArch64::STLLRW: 1390 case AArch64::STLLRB: 1391 case AArch64::STLLRH: 1392 case AArch64::LDLARW: 1393 case AArch64::LDLARB: 1394 case AArch64::LDLARH: 1395 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1396 break; 1397 case AArch64::STLXRX: 1398 case AArch64::STXRX: 1399 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1400 LLVM_FALLTHROUGH; 1401 case AArch64::LDARX: 1402 case AArch64::LDAXRX: 1403 case AArch64::LDXRX: 1404 case AArch64::STLRX: 1405 case AArch64::LDLARX: 1406 case AArch64::STLLRX: 1407 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1408 break; 1409 case AArch64::STLXPW: 1410 case AArch64::STXPW: 1411 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1412 LLVM_FALLTHROUGH; 1413 case AArch64::LDAXPW: 1414 case AArch64::LDXPW: 1415 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1416 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1417 break; 1418 case AArch64::STLXPX: 1419 case AArch64::STXPX: 1420 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1421 LLVM_FALLTHROUGH; 1422 case AArch64::LDAXPX: 1423 case AArch64::LDXPX: 1424 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1425 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1426 break; 1427 } 1428 1429 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1430 1431 // You shouldn't load to the same register twice in an instruction... 1432 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1433 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1434 Rt == Rt2) 1435 return SoftFail; 1436 1437 return Success; 1438 } 1439 1440 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1441 uint64_t Addr, 1442 const void *Decoder) { 1443 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1444 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1445 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1446 int64_t offset = fieldFromInstruction(insn, 15, 7); 1447 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1448 1449 // offset is a 7-bit signed immediate, so sign extend it to 1450 // fill the unsigned. 1451 if (offset & (1 << (7 - 1))) 1452 offset |= ~((1LL << 7) - 1); 1453 1454 unsigned Opcode = Inst.getOpcode(); 1455 bool NeedsDisjointWritebackTransfer = false; 1456 1457 // First operand is always writeback of base register. 1458 switch (Opcode) { 1459 default: 1460 break; 1461 case AArch64::LDPXpost: 1462 case AArch64::STPXpost: 1463 case AArch64::LDPSWpost: 1464 case AArch64::LDPXpre: 1465 case AArch64::STPXpre: 1466 case AArch64::LDPSWpre: 1467 case AArch64::LDPWpost: 1468 case AArch64::STPWpost: 1469 case AArch64::LDPWpre: 1470 case AArch64::STPWpre: 1471 case AArch64::LDPQpost: 1472 case AArch64::STPQpost: 1473 case AArch64::LDPQpre: 1474 case AArch64::STPQpre: 1475 case AArch64::LDPDpost: 1476 case AArch64::STPDpost: 1477 case AArch64::LDPDpre: 1478 case AArch64::STPDpre: 1479 case AArch64::LDPSpost: 1480 case AArch64::STPSpost: 1481 case AArch64::LDPSpre: 1482 case AArch64::STPSpre: 1483 case AArch64::STGPpre: 1484 case AArch64::STGPpost: 1485 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1486 break; 1487 } 1488 1489 switch (Opcode) { 1490 default: 1491 return Fail; 1492 case AArch64::LDPXpost: 1493 case AArch64::STPXpost: 1494 case AArch64::LDPSWpost: 1495 case AArch64::LDPXpre: 1496 case AArch64::STPXpre: 1497 case AArch64::LDPSWpre: 1498 case AArch64::STGPpre: 1499 case AArch64::STGPpost: 1500 NeedsDisjointWritebackTransfer = true; 1501 LLVM_FALLTHROUGH; 1502 case AArch64::LDNPXi: 1503 case AArch64::STNPXi: 1504 case AArch64::LDPXi: 1505 case AArch64::STPXi: 1506 case AArch64::LDPSWi: 1507 case AArch64::STGPi: 1508 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1509 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1510 break; 1511 case AArch64::LDPWpost: 1512 case AArch64::STPWpost: 1513 case AArch64::LDPWpre: 1514 case AArch64::STPWpre: 1515 NeedsDisjointWritebackTransfer = true; 1516 LLVM_FALLTHROUGH; 1517 case AArch64::LDNPWi: 1518 case AArch64::STNPWi: 1519 case AArch64::LDPWi: 1520 case AArch64::STPWi: 1521 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1522 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1523 break; 1524 case AArch64::LDNPQi: 1525 case AArch64::STNPQi: 1526 case AArch64::LDPQpost: 1527 case AArch64::STPQpost: 1528 case AArch64::LDPQi: 1529 case AArch64::STPQi: 1530 case AArch64::LDPQpre: 1531 case AArch64::STPQpre: 1532 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1533 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1534 break; 1535 case AArch64::LDNPDi: 1536 case AArch64::STNPDi: 1537 case AArch64::LDPDpost: 1538 case AArch64::STPDpost: 1539 case AArch64::LDPDi: 1540 case AArch64::STPDi: 1541 case AArch64::LDPDpre: 1542 case AArch64::STPDpre: 1543 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1544 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1545 break; 1546 case AArch64::LDNPSi: 1547 case AArch64::STNPSi: 1548 case AArch64::LDPSpost: 1549 case AArch64::STPSpost: 1550 case AArch64::LDPSi: 1551 case AArch64::STPSi: 1552 case AArch64::LDPSpre: 1553 case AArch64::STPSpre: 1554 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1555 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1556 break; 1557 } 1558 1559 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1560 Inst.addOperand(MCOperand::createImm(offset)); 1561 1562 // You shouldn't load to the same register twice in an instruction... 1563 if (IsLoad && Rt == Rt2) 1564 return SoftFail; 1565 1566 // ... or do any operation that writes-back to a transfer register. But note 1567 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1568 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1569 return SoftFail; 1570 1571 return Success; 1572 } 1573 1574 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1575 uint64_t Addr, 1576 const void *Decoder) { 1577 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1578 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1579 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1580 fieldFromInstruction(insn, 12, 9); 1581 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1582 1583 switch (Inst.getOpcode()) { 1584 default: 1585 return Fail; 1586 case AArch64::LDRAAwriteback: 1587 case AArch64::LDRABwriteback: 1588 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1589 Decoder); 1590 break; 1591 case AArch64::LDRAAindexed: 1592 case AArch64::LDRABindexed: 1593 break; 1594 } 1595 1596 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1597 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1598 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1599 1600 if (writeback && Rt == Rn && Rn != 31) { 1601 return SoftFail; 1602 } 1603 1604 return Success; 1605 } 1606 1607 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1608 uint64_t Addr, 1609 const void *Decoder) { 1610 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1611 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1612 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1613 unsigned extend = fieldFromInstruction(insn, 10, 6); 1614 1615 unsigned shift = extend & 0x7; 1616 if (shift > 4) 1617 return Fail; 1618 1619 switch (Inst.getOpcode()) { 1620 default: 1621 return Fail; 1622 case AArch64::ADDWrx: 1623 case AArch64::SUBWrx: 1624 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1625 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1626 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1627 break; 1628 case AArch64::ADDSWrx: 1629 case AArch64::SUBSWrx: 1630 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1631 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1632 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1633 break; 1634 case AArch64::ADDXrx: 1635 case AArch64::SUBXrx: 1636 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1637 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1638 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1639 break; 1640 case AArch64::ADDSXrx: 1641 case AArch64::SUBSXrx: 1642 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1643 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1644 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1645 break; 1646 case AArch64::ADDXrx64: 1647 case AArch64::SUBXrx64: 1648 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1649 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1650 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1651 break; 1652 case AArch64::SUBSXrx64: 1653 case AArch64::ADDSXrx64: 1654 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1655 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1656 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1657 break; 1658 } 1659 1660 Inst.addOperand(MCOperand::createImm(extend)); 1661 return Success; 1662 } 1663 1664 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1665 uint64_t Addr, 1666 const void *Decoder) { 1667 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1668 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1669 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1670 unsigned imm; 1671 1672 if (Datasize) { 1673 if (Inst.getOpcode() == AArch64::ANDSXri) 1674 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1675 else 1676 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1677 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1678 imm = fieldFromInstruction(insn, 10, 13); 1679 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1680 return Fail; 1681 } else { 1682 if (Inst.getOpcode() == AArch64::ANDSWri) 1683 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1684 else 1685 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1686 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1687 imm = fieldFromInstruction(insn, 10, 12); 1688 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1689 return Fail; 1690 } 1691 Inst.addOperand(MCOperand::createImm(imm)); 1692 return Success; 1693 } 1694 1695 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1696 uint64_t Addr, 1697 const void *Decoder) { 1698 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1699 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1700 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1701 imm |= fieldFromInstruction(insn, 5, 5); 1702 1703 if (Inst.getOpcode() == AArch64::MOVID) 1704 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1705 else 1706 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1707 1708 Inst.addOperand(MCOperand::createImm(imm)); 1709 1710 switch (Inst.getOpcode()) { 1711 default: 1712 break; 1713 case AArch64::MOVIv4i16: 1714 case AArch64::MOVIv8i16: 1715 case AArch64::MVNIv4i16: 1716 case AArch64::MVNIv8i16: 1717 case AArch64::MOVIv2i32: 1718 case AArch64::MOVIv4i32: 1719 case AArch64::MVNIv2i32: 1720 case AArch64::MVNIv4i32: 1721 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1722 break; 1723 case AArch64::MOVIv2s_msl: 1724 case AArch64::MOVIv4s_msl: 1725 case AArch64::MVNIv2s_msl: 1726 case AArch64::MVNIv4s_msl: 1727 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1728 break; 1729 } 1730 1731 return Success; 1732 } 1733 1734 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1735 uint64_t Addr, 1736 const void *Decoder) { 1737 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1738 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1739 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1740 imm |= fieldFromInstruction(insn, 5, 5); 1741 1742 // Tied operands added twice. 1743 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1744 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1745 1746 Inst.addOperand(MCOperand::createImm(imm)); 1747 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1748 1749 return Success; 1750 } 1751 1752 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1753 uint64_t Addr, const void *Decoder) { 1754 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1755 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1756 imm |= fieldFromInstruction(insn, 29, 2); 1757 const AArch64Disassembler *Dis = 1758 static_cast<const AArch64Disassembler *>(Decoder); 1759 1760 // Sign-extend the 21-bit immediate. 1761 if (imm & (1 << (21 - 1))) 1762 imm |= ~((1LL << 21) - 1); 1763 1764 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1765 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1766 Inst.addOperand(MCOperand::createImm(imm)); 1767 1768 return Success; 1769 } 1770 1771 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1772 uint64_t Addr, const void *Decoder) { 1773 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1774 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1775 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1776 unsigned S = fieldFromInstruction(insn, 29, 1); 1777 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1778 1779 unsigned ShifterVal = (Imm >> 12) & 3; 1780 unsigned ImmVal = Imm & 0xFFF; 1781 const AArch64Disassembler *Dis = 1782 static_cast<const AArch64Disassembler *>(Decoder); 1783 1784 if (ShifterVal != 0 && ShifterVal != 1) 1785 return Fail; 1786 1787 if (Datasize) { 1788 if (Rd == 31 && !S) 1789 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1790 else 1791 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1792 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1793 } else { 1794 if (Rd == 31 && !S) 1795 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1796 else 1797 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1798 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1799 } 1800 1801 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1802 Inst.addOperand(MCOperand::createImm(ImmVal)); 1803 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1804 return Success; 1805 } 1806 1807 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1808 uint64_t Addr, 1809 const void *Decoder) { 1810 int64_t imm = fieldFromInstruction(insn, 0, 26); 1811 const AArch64Disassembler *Dis = 1812 static_cast<const AArch64Disassembler *>(Decoder); 1813 1814 // Sign-extend the 26-bit immediate. 1815 if (imm & (1 << (26 - 1))) 1816 imm |= ~((1LL << 26) - 1); 1817 1818 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1819 Inst.addOperand(MCOperand::createImm(imm)); 1820 1821 return Success; 1822 } 1823 1824 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1825 uint64_t Addr, 1826 const void *Decoder) { 1827 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1828 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1829 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1830 uint64_t pstate_field = (op1 << 3) | op2; 1831 1832 switch (pstate_field) { 1833 case 0x01: // XAFlag 1834 case 0x02: // AXFlag 1835 return Fail; 1836 } 1837 1838 if ((pstate_field == AArch64PState::PAN || 1839 pstate_field == AArch64PState::UAO || 1840 pstate_field == AArch64PState::SSBS) && crm > 1) 1841 return Fail; 1842 1843 Inst.addOperand(MCOperand::createImm(pstate_field)); 1844 Inst.addOperand(MCOperand::createImm(crm)); 1845 1846 const AArch64Disassembler *Dis = 1847 static_cast<const AArch64Disassembler *>(Decoder); 1848 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1849 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1850 return Success; 1851 return Fail; 1852 } 1853 1854 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1855 uint64_t Addr, const void *Decoder) { 1856 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1857 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1858 bit |= fieldFromInstruction(insn, 19, 5); 1859 int64_t dst = fieldFromInstruction(insn, 5, 14); 1860 const AArch64Disassembler *Dis = 1861 static_cast<const AArch64Disassembler *>(Decoder); 1862 1863 // Sign-extend 14-bit immediate. 1864 if (dst & (1 << (14 - 1))) 1865 dst |= ~((1LL << 14) - 1); 1866 1867 if (fieldFromInstruction(insn, 31, 1) == 0) 1868 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1869 else 1870 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1871 Inst.addOperand(MCOperand::createImm(bit)); 1872 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1873 Inst.addOperand(MCOperand::createImm(dst)); 1874 1875 return Success; 1876 } 1877 1878 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1879 unsigned RegClassID, 1880 unsigned RegNo, 1881 uint64_t Addr, 1882 const void *Decoder) { 1883 // Register number must be even (see CASP instruction) 1884 if (RegNo & 0x1) 1885 return Fail; 1886 1887 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1888 Inst.addOperand(MCOperand::createReg(Reg)); 1889 return Success; 1890 } 1891 1892 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1893 unsigned RegNo, 1894 uint64_t Addr, 1895 const void *Decoder) { 1896 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1897 AArch64::WSeqPairsClassRegClassID, 1898 RegNo, Addr, Decoder); 1899 } 1900 1901 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1902 unsigned RegNo, 1903 uint64_t Addr, 1904 const void *Decoder) { 1905 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1906 AArch64::XSeqPairsClassRegClassID, 1907 RegNo, Addr, Decoder); 1908 } 1909 1910 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1911 uint32_t insn, 1912 uint64_t Addr, 1913 const void *Decoder) { 1914 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1915 unsigned imm = fieldFromInstruction(insn, 5, 13); 1916 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1917 return Fail; 1918 1919 // The same (tied) operand is added twice to the instruction. 1920 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1921 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1922 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1923 Inst.addOperand(MCOperand::createImm(imm)); 1924 return Success; 1925 } 1926 1927 template<int Bits> 1928 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1929 uint64_t Address, const void *Decoder) { 1930 if (Imm & ~((1LL << Bits) - 1)) 1931 return Fail; 1932 1933 // Imm is a signed immediate, so sign extend it. 1934 if (Imm & (1 << (Bits - 1))) 1935 Imm |= ~((1LL << Bits) - 1); 1936 1937 Inst.addOperand(MCOperand::createImm(Imm)); 1938 return Success; 1939 } 1940 1941 // Decode 8-bit signed/unsigned immediate for a given element width. 1942 template <int ElementWidth> 1943 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1944 uint64_t Addr, const void *Decoder) { 1945 unsigned Val = (uint8_t)Imm; 1946 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1947 if (ElementWidth == 8 && Shift) 1948 return Fail; 1949 Inst.addOperand(MCOperand::createImm(Val)); 1950 Inst.addOperand(MCOperand::createImm(Shift)); 1951 return Success; 1952 } 1953 1954 // Decode uimm4 ranged from 1-16. 1955 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1956 uint64_t Addr, const void *Decoder) { 1957 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1958 return Success; 1959 } 1960