1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the functions necessary to decode AArch64 instruction 11 // bitpatterns into MCInsts (with the help of TableGenerated information from 12 // the instruction definitions). 13 // 14 //===----------------------------------------------------------------------===// 15 16 #define DEBUG_TYPE "arm-disassembler" 17 18 #include "AArch64.h" 19 #include "AArch64RegisterInfo.h" 20 #include "AArch64Subtarget.h" 21 #include "Utils/AArch64BaseInfo.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCDisassembler.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCFixedLenDisassembler.h" 26 #include "llvm/MC/MCInst.h" 27 #include "llvm/MC/MCInstrDesc.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/MemoryObject.h" 31 #include "llvm/Support/TargetRegistry.h" 32 #include "llvm/Support/raw_ostream.h" 33 34 using namespace llvm; 35 36 typedef MCDisassembler::DecodeStatus DecodeStatus; 37 38 namespace { 39 /// AArch64 disassembler for all AArch64 platforms. 40 class AArch64Disassembler : public MCDisassembler { 41 OwningPtr<const MCRegisterInfo> RegInfo; 42 public: 43 /// Initializes the disassembler. 44 /// 45 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) 46 : MCDisassembler(STI), RegInfo(Info) { 47 } 48 49 ~AArch64Disassembler() {} 50 51 /// See MCDisassembler. 52 DecodeStatus getInstruction(MCInst &instr, 53 uint64_t &size, 54 const MemoryObject ®ion, 55 uint64_t address, 56 raw_ostream &vStream, 57 raw_ostream &cStream) const; 58 59 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } 60 }; 61 62 } 63 64 // Forward-declarations used in the auto-generated files. 65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 66 uint64_t Address, const void *Decoder); 67 static DecodeStatus 68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 uint64_t Address, const void *Decoder); 70 71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 uint64_t Address, const void *Decoder); 73 static DecodeStatus 74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 uint64_t Address, const void *Decoder); 76 77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 78 uint64_t Address, const void *Decoder); 79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 80 uint64_t Address, const void *Decoder); 81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 82 uint64_t Address, const void *Decoder); 83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 84 uint64_t Address, const void *Decoder); 85 static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 86 uint64_t Address, const void *Decoder); 87 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 88 unsigned RegNo, uint64_t Address, 89 const void *Decoder); 90 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, 91 unsigned RegNo, uint64_t Address, 92 const void *Decoder); 93 94 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, 95 unsigned RegNo, 96 uint64_t Address, 97 const void *Decoder); 98 99 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 119 unsigned OptionHiS, 120 uint64_t Address, 121 const void *Decoder); 122 123 124 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 125 unsigned Imm6Bits, 126 uint64_t Address, 127 const void *Decoder); 128 129 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 130 unsigned Imm6Bits, 131 uint64_t Address, 132 const void *Decoder); 133 134 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 135 unsigned RmBits, 136 uint64_t Address, 137 const void *Decoder); 138 139 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 142 uint64_t Address, 143 const void *Decoder); 144 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 145 uint64_t Address, 146 const void *Decoder); 147 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, 154 uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, 157 uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, 160 uint64_t Address, 161 const void *Decoder); 162 163 template<int RegWidth> 164 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 165 unsigned FullImm, 166 uint64_t Address, 167 const void *Decoder); 168 169 template<int RegWidth> 170 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 171 unsigned Bits, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 176 unsigned ShiftAmount, 177 uint64_t Address, 178 const void *Decoder); 179 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 180 static DecodeStatus 181 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 182 uint64_t Address, const void *Decoder); 183 184 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 185 unsigned ShiftAmount, 186 uint64_t Address, 187 const void *Decoder); 188 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 202 unsigned Val, 203 uint64_t Address, 204 const void *Decoder); 205 206 template<typename SomeNamedImmMapper> 207 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 208 unsigned Val, 209 uint64_t Address, 210 const void *Decoder); 211 212 static DecodeStatus 213 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper, 214 llvm::MCInst &Inst, unsigned Val, 215 uint64_t Address, const void *Decoder); 216 217 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 218 unsigned Val, 219 uint64_t Address, 220 const void *Decoder); 221 222 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 223 unsigned Val, 224 uint64_t Address, 225 const void *Decoder); 226 227 228 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 229 unsigned Val, 230 uint64_t Address, 231 const void *Decoder); 232 233 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Val, 234 uint64_t Address, 235 const void *Decoder); 236 237 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, 238 uint64_t Address, 239 const void *Decoder); 240 241 static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, 242 uint64_t Address, 243 const void *Decoder); 244 245 static bool Check(DecodeStatus &Out, DecodeStatus In); 246 247 #include "AArch64GenDisassemblerTables.inc" 248 249 static bool Check(DecodeStatus &Out, DecodeStatus In) { 250 switch (In) { 251 case MCDisassembler::Success: 252 // Out stays the same. 253 return true; 254 case MCDisassembler::SoftFail: 255 Out = In; 256 return true; 257 case MCDisassembler::Fail: 258 Out = In; 259 return false; 260 } 261 llvm_unreachable("Invalid DecodeStatus!"); 262 } 263 264 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 265 const MemoryObject &Region, 266 uint64_t Address, 267 raw_ostream &os, 268 raw_ostream &cs) const { 269 CommentStream = &cs; 270 271 uint8_t bytes[4]; 272 273 // We want to read exactly 4 bytes of data. 274 if (Region.readBytes(Address, 4, bytes) == -1) { 275 Size = 0; 276 return MCDisassembler::Fail; 277 } 278 279 // Encoded as a small-endian 32-bit word in the stream. 280 uint32_t insn = (bytes[3] << 24) | 281 (bytes[2] << 16) | 282 (bytes[1] << 8) | 283 (bytes[0] << 0); 284 285 // Calling the auto-generated decoder function. 286 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, 287 this, STI); 288 if (result != MCDisassembler::Fail) { 289 Size = 4; 290 return result; 291 } 292 293 MI.clear(); 294 Size = 0; 295 return MCDisassembler::Fail; 296 } 297 298 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 299 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D); 300 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo); 301 } 302 303 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 304 uint64_t Address, const void *Decoder) { 305 if (RegNo > 31) 306 return MCDisassembler::Fail; 307 308 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo); 309 Inst.addOperand(MCOperand::CreateReg(Register)); 310 return MCDisassembler::Success; 311 } 312 313 static DecodeStatus 314 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 315 uint64_t Address, const void *Decoder) { 316 if (RegNo > 31) 317 return MCDisassembler::Fail; 318 319 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo); 320 Inst.addOperand(MCOperand::CreateReg(Register)); 321 return MCDisassembler::Success; 322 } 323 324 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 325 uint64_t Address, 326 const void *Decoder) { 327 if (RegNo > 31) 328 return MCDisassembler::Fail; 329 330 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo); 331 Inst.addOperand(MCOperand::CreateReg(Register)); 332 return MCDisassembler::Success; 333 } 334 335 static DecodeStatus 336 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 337 uint64_t Address, const void *Decoder) { 338 if (RegNo > 31) 339 return MCDisassembler::Fail; 340 341 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo); 342 Inst.addOperand(MCOperand::CreateReg(Register)); 343 return MCDisassembler::Success; 344 } 345 346 static DecodeStatus 347 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 348 uint64_t Address, const void *Decoder) { 349 if (RegNo > 31) 350 return MCDisassembler::Fail; 351 352 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo); 353 Inst.addOperand(MCOperand::CreateReg(Register)); 354 return MCDisassembler::Success; 355 } 356 357 static DecodeStatus 358 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 359 uint64_t Address, const void *Decoder) { 360 if (RegNo > 31) 361 return MCDisassembler::Fail; 362 363 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo); 364 Inst.addOperand(MCOperand::CreateReg(Register)); 365 return MCDisassembler::Success; 366 } 367 368 369 static DecodeStatus 370 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 371 uint64_t Address, const void *Decoder) { 372 if (RegNo > 31) 373 return MCDisassembler::Fail; 374 375 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo); 376 Inst.addOperand(MCOperand::CreateReg(Register)); 377 return MCDisassembler::Success; 378 } 379 380 static DecodeStatus 381 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 382 uint64_t Address, const void *Decoder) { 383 if (RegNo > 31) 384 return MCDisassembler::Fail; 385 386 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo); 387 Inst.addOperand(MCOperand::CreateReg(Register)); 388 return MCDisassembler::Success; 389 } 390 391 static DecodeStatus 392 DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 393 uint64_t Address, const void *Decoder) { 394 if (RegNo > 15) 395 return MCDisassembler::Fail; 396 397 return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder); 398 } 399 400 static DecodeStatus 401 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 402 uint64_t Address, const void *Decoder) { 403 if (RegNo > 31) 404 return MCDisassembler::Fail; 405 406 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo); 407 Inst.addOperand(MCOperand::CreateReg(Register)); 408 return MCDisassembler::Success; 409 } 410 411 static DecodeStatus 412 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 413 uint64_t Address, const void *Decoder) { 414 if (RegNo > 15) 415 return MCDisassembler::Fail; 416 417 return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder); 418 } 419 420 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, 421 unsigned RegNo, 422 uint64_t Address, 423 const void *Decoder) { 424 if (RegNo > 30) 425 return MCDisassembler::Fail; 426 427 uint16_t Register = getReg(Decoder, AArch64::GPR64noxzrRegClassID, RegNo); 428 Inst.addOperand(MCOperand::CreateReg(Register)); 429 return MCDisassembler::Success; 430 } 431 432 static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo, 433 unsigned RegID, 434 const void *Decoder) { 435 if (RegNo > 31) 436 return MCDisassembler::Fail; 437 438 uint16_t Register = getReg(Decoder, RegID, RegNo); 439 Inst.addOperand(MCOperand::CreateReg(Register)); 440 return MCDisassembler::Success; 441 } 442 443 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 444 uint64_t Address, 445 const void *Decoder) { 446 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID, 447 Decoder); 448 } 449 450 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 451 uint64_t Address, 452 const void *Decoder) { 453 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID, 454 Decoder); 455 } 456 457 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 458 unsigned RegNo, uint64_t Address, 459 const void *Decoder) { 460 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID, 461 Decoder); 462 } 463 464 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 465 unsigned RegNo, uint64_t Address, 466 const void *Decoder) { 467 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID, 468 Decoder); 469 } 470 471 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 472 uint64_t Address, 473 const void *Decoder) { 474 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID, 475 Decoder); 476 } 477 478 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 479 uint64_t Address, 480 const void *Decoder) { 481 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID, 482 Decoder); 483 } 484 485 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 486 unsigned OptionHiS, 487 uint64_t Address, 488 const void *Decoder) { 489 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1}, 490 // S}. Hence we want to check bit 1. 491 if (!(OptionHiS & 2)) 492 return MCDisassembler::Fail; 493 494 Inst.addOperand(MCOperand::CreateImm(OptionHiS)); 495 return MCDisassembler::Success; 496 } 497 498 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 499 unsigned Imm6Bits, 500 uint64_t Address, 501 const void *Decoder) { 502 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be 503 // between 0 and 31. 504 if (Imm6Bits > 31) 505 return MCDisassembler::Fail; 506 507 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 508 return MCDisassembler::Success; 509 } 510 511 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 512 unsigned Imm6Bits, 513 uint64_t Address, 514 const void *Decoder) { 515 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32. 516 if (Imm6Bits < 32) 517 return MCDisassembler::Fail; 518 519 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 520 return MCDisassembler::Success; 521 } 522 523 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 524 unsigned RmBits, 525 uint64_t Address, 526 const void *Decoder) { 527 // Any bits are valid in the instruction (they're architecturally ignored), 528 // but a code generator should insert 0. 529 Inst.addOperand(MCOperand::CreateImm(0)); 530 return MCDisassembler::Success; 531 } 532 533 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 534 uint64_t Address, 535 const void *Decoder) { 536 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 537 return MCDisassembler::Success; 538 } 539 540 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 541 uint64_t Address, 542 const void *Decoder) { 543 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 544 return MCDisassembler::Success; 545 } 546 547 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 548 uint64_t Address, 549 const void *Decoder) { 550 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 551 return MCDisassembler::Success; 552 } 553 554 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 555 uint64_t Address, 556 const void *Decoder) { 557 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 558 return MCDisassembler::Success; 559 } 560 561 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, 562 uint64_t Address, 563 const void *Decoder) { 564 if (Val > 7) 565 return MCDisassembler::Fail; 566 567 Inst.addOperand(MCOperand::CreateImm(Val)); 568 return MCDisassembler::Success; 569 } 570 571 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, 572 uint64_t Address, 573 const void *Decoder) { 574 if (Val > 15) 575 return MCDisassembler::Fail; 576 577 Inst.addOperand(MCOperand::CreateImm(Val)); 578 return MCDisassembler::Success; 579 } 580 581 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, 582 uint64_t Address, 583 const void *Decoder) { 584 if (Val > 31) 585 return MCDisassembler::Fail; 586 587 Inst.addOperand(MCOperand::CreateImm(Val)); 588 return MCDisassembler::Success; 589 } 590 591 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, 592 uint64_t Address, 593 const void *Decoder) { 594 if (Val > 63) 595 return MCDisassembler::Fail; 596 597 Inst.addOperand(MCOperand::CreateImm(Val)); 598 return MCDisassembler::Success; 599 } 600 601 template<int RegWidth> 602 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 603 unsigned FullImm, 604 uint64_t Address, 605 const void *Decoder) { 606 unsigned Imm16 = FullImm & 0xffff; 607 unsigned Shift = FullImm >> 16; 608 609 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail; 610 611 Inst.addOperand(MCOperand::CreateImm(Imm16)); 612 Inst.addOperand(MCOperand::CreateImm(Shift)); 613 return MCDisassembler::Success; 614 } 615 616 template<int RegWidth> 617 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 618 unsigned Bits, 619 uint64_t Address, 620 const void *Decoder) { 621 uint64_t Imm; 622 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm)) 623 return MCDisassembler::Fail; 624 625 Inst.addOperand(MCOperand::CreateImm(Bits)); 626 return MCDisassembler::Success; 627 } 628 629 630 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 631 unsigned ShiftAmount, 632 uint64_t Address, 633 const void *Decoder) { 634 // Only values 0-4 are valid for this 3-bit field 635 if (ShiftAmount > 4) 636 return MCDisassembler::Fail; 637 638 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 639 return MCDisassembler::Success; 640 } 641 642 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 643 unsigned ShiftAmount, 644 uint64_t Address, 645 const void *Decoder) { 646 // Only values below 32 are valid for a 32-bit register 647 if (ShiftAmount > 31) 648 return MCDisassembler::Fail; 649 650 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 651 return MCDisassembler::Success; 652 } 653 654 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 655 uint64_t Address, 656 const void *Decoder) { 657 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 658 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 659 unsigned ImmS = fieldFromInstruction(Insn, 10, 6); 660 unsigned ImmR = fieldFromInstruction(Insn, 16, 6); 661 unsigned SF = fieldFromInstruction(Insn, 31, 1); 662 663 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise 664 // out assertions that it thinks should never be hit. 665 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; 666 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); 667 668 if (!SF) { 669 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions. 670 if (ImmR > 31 || ImmS > 31) 671 return MCDisassembler::Fail; 672 } 673 674 if (SF) { 675 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 676 // BFM MCInsts use Rd as a source too. 677 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 678 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 679 } else { 680 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 681 // BFM MCInsts use Rd as a source too. 682 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 683 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder); 684 } 685 686 // ASR and LSR have more specific patterns so they won't get here: 687 assert(!(ImmS == 31 && !SF && Opc != BFM) 688 && "shift should have used auto decode"); 689 assert(!(ImmS == 63 && SF && Opc != BFM) 690 && "shift should have used auto decode"); 691 692 // Extension instructions similarly: 693 if (Opc == SBFM && ImmR == 0) { 694 assert((ImmS != 7 && ImmS != 15) && "extension got here"); 695 assert((ImmS != 31 || SF == 0) && "extension got here"); 696 } else if (Opc == UBFM && ImmR == 0) { 697 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here"); 698 } 699 700 if (Opc == UBFM) { 701 // It might be a LSL instruction, which actually takes the shift amount 702 // itself as an MCInst operand. 703 if (SF && (ImmS + 1) % 64 == ImmR) { 704 Inst.setOpcode(AArch64::LSLxxi); 705 Inst.addOperand(MCOperand::CreateImm(63 - ImmS)); 706 return MCDisassembler::Success; 707 } else if (!SF && (ImmS + 1) % 32 == ImmR) { 708 Inst.setOpcode(AArch64::LSLwwi); 709 Inst.addOperand(MCOperand::CreateImm(31 - ImmS)); 710 return MCDisassembler::Success; 711 } 712 } 713 714 // Otherwise it's definitely either an extract or an insert depending on which 715 // of ImmR or ImmS is larger. 716 unsigned ExtractOp, InsertOp; 717 switch (Opc) { 718 default: llvm_unreachable("unexpected instruction trying to decode bitfield"); 719 case SBFM: 720 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii; 721 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii; 722 break; 723 case BFM: 724 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii; 725 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii; 726 break; 727 case UBFM: 728 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii; 729 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii; 730 break; 731 } 732 733 // Otherwise it's a boring insert or extract 734 Inst.addOperand(MCOperand::CreateImm(ImmR)); 735 Inst.addOperand(MCOperand::CreateImm(ImmS)); 736 737 738 if (ImmS < ImmR) 739 Inst.setOpcode(InsertOp); 740 else 741 Inst.setOpcode(ExtractOp); 742 743 return MCDisassembler::Success; 744 } 745 746 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 747 uint64_t Address, 748 const void *Decoder) { 749 // This decoder exists to add the dummy Lane operand to the MCInst, which must 750 // be 1 in assembly but has no other real manifestation. 751 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 752 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 753 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 754 755 if (IsToVec) { 756 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 757 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 758 } else { 759 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 760 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 761 } 762 763 // Add the lane 764 Inst.addOperand(MCOperand::CreateImm(1)); 765 766 return MCDisassembler::Success; 767 } 768 769 770 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 771 unsigned Insn, 772 uint64_t Address, 773 const void *Decoder) { 774 DecodeStatus Result = MCDisassembler::Success; 775 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 776 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 777 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5); 778 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7); 779 unsigned L = fieldFromInstruction(Insn, 22, 1); 780 unsigned V = fieldFromInstruction(Insn, 26, 1); 781 unsigned Opc = fieldFromInstruction(Insn, 30, 2); 782 783 // Not an official name, but it turns out that bit 23 distinguishes indexed 784 // from non-indexed operations. 785 unsigned Indexed = fieldFromInstruction(Insn, 23, 1); 786 787 if (Indexed && L == 0) { 788 // The MCInst for an indexed store has an out operand and 4 ins: 789 // Rn_wb, Rt, Rt2, Rn, Imm 790 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 791 } 792 793 // You shouldn't load to the same register twice in an instruction... 794 if (L && Rt == Rt2) 795 Result = MCDisassembler::SoftFail; 796 797 // ... or do any operation that writes-back to a transfer register. But note 798 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 799 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 800 Result = MCDisassembler::SoftFail; 801 802 // Exactly how we decode the MCInst's registers depends on the Opc and V 803 // fields of the instruction. These also obviously determine the size of the 804 // operation so we can fill in that information while we're at it. 805 if (V) { 806 // The instruction operates on the FP/SIMD registers 807 switch (Opc) { 808 default: return MCDisassembler::Fail; 809 case 0: 810 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 811 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder); 812 break; 813 case 1: 814 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 815 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder); 816 break; 817 case 2: 818 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 819 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder); 820 break; 821 } 822 } else { 823 switch (Opc) { 824 default: return MCDisassembler::Fail; 825 case 0: 826 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 827 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder); 828 break; 829 case 1: 830 assert(L && "unexpected \"store signed\" attempt"); 831 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 832 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 833 break; 834 case 2: 835 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 836 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 837 break; 838 } 839 } 840 841 if (Indexed && L == 1) { 842 // The MCInst for an indexed load has 3 out operands and an 3 ins: 843 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm 844 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 845 } 846 847 848 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 849 Inst.addOperand(MCOperand::CreateImm(SImm7)); 850 851 return Result; 852 } 853 854 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 855 uint32_t Val, 856 uint64_t Address, 857 const void *Decoder) { 858 unsigned Rt = fieldFromInstruction(Val, 0, 5); 859 unsigned Rn = fieldFromInstruction(Val, 5, 5); 860 unsigned Rt2 = fieldFromInstruction(Val, 10, 5); 861 unsigned MemSize = fieldFromInstruction(Val, 30, 2); 862 863 DecodeStatus S = MCDisassembler::Success; 864 if (Rt == Rt2) S = MCDisassembler::SoftFail; 865 866 switch (MemSize) { 867 case 2: 868 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder))) 869 return MCDisassembler::Fail; 870 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder))) 871 return MCDisassembler::Fail; 872 break; 873 case 3: 874 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder))) 875 return MCDisassembler::Fail; 876 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder))) 877 return MCDisassembler::Fail; 878 break; 879 default: 880 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction"); 881 } 882 883 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder))) 884 return MCDisassembler::Fail; 885 886 return S; 887 } 888 889 template<typename SomeNamedImmMapper> 890 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 891 unsigned Val, 892 uint64_t Address, 893 const void *Decoder) { 894 SomeNamedImmMapper Mapper; 895 bool ValidNamed; 896 Mapper.toString(Val, ValidNamed); 897 if (ValidNamed || Mapper.validImm(Val)) { 898 Inst.addOperand(MCOperand::CreateImm(Val)); 899 return MCDisassembler::Success; 900 } 901 902 return MCDisassembler::Fail; 903 } 904 905 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, 906 llvm::MCInst &Inst, 907 unsigned Val, 908 uint64_t Address, 909 const void *Decoder) { 910 bool ValidNamed; 911 Mapper.toString(Val, ValidNamed); 912 913 Inst.addOperand(MCOperand::CreateImm(Val)); 914 915 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail; 916 } 917 918 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 919 unsigned Val, 920 uint64_t Address, 921 const void *Decoder) { 922 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address, 923 Decoder); 924 } 925 926 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 927 unsigned Val, 928 uint64_t Address, 929 const void *Decoder) { 930 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address, 931 Decoder); 932 } 933 934 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 935 unsigned Insn, 936 uint64_t Address, 937 const void *Decoder) { 938 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 939 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 940 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9); 941 942 unsigned Opc = fieldFromInstruction(Insn, 22, 2); 943 unsigned V = fieldFromInstruction(Insn, 26, 1); 944 unsigned Size = fieldFromInstruction(Insn, 30, 2); 945 946 if (Opc == 0 || (V == 1 && Opc == 2)) { 947 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm 948 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 949 } 950 951 if (V == 0 && (Opc == 2 || Size == 3)) { 952 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 953 } else if (V == 0) { 954 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 955 } else if (V == 1 && (Opc & 2)) { 956 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 957 } else { 958 switch (Size) { 959 case 0: 960 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder); 961 break; 962 case 1: 963 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder); 964 break; 965 case 2: 966 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 967 break; 968 case 3: 969 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 970 break; 971 } 972 } 973 974 if (Opc != 0 && (V != 1 || Opc != 2)) { 975 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm 976 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 977 } 978 979 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 980 981 Inst.addOperand(MCOperand::CreateImm(Imm9)); 982 983 // N.b. The official documentation says undpredictable if Rt == Rn, but this 984 // takes place at the architectural rather than encoding level: 985 // 986 // "STR xzr, [sp], #4" is perfectly valid. 987 if (V == 0 && Rt == Rn && Rn != 31) 988 return MCDisassembler::SoftFail; 989 else 990 return MCDisassembler::Success; 991 } 992 993 static MCDisassembler *createAArch64Disassembler(const Target &T, 994 const MCSubtargetInfo &STI) { 995 return new AArch64Disassembler(STI, T.createMCRegInfo("")); 996 } 997 998 extern "C" void LLVMInitializeAArch64Disassembler() { 999 TargetRegistry::RegisterMCDisassembler(TheAArch64Target, 1000 createAArch64Disassembler); 1001 } 1002 1003 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 1004 static DecodeStatus 1005 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 1006 uint64_t Address, const void *Decoder) { 1007 bool IsLSL = false; 1008 if (Ext == A64SE::LSL) 1009 IsLSL = true; 1010 else if (Ext != A64SE::MSL) 1011 return MCDisassembler::Fail; 1012 1013 // MSL and LSLH accepts encoded shift amount 0 or 1. 1014 if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1) 1015 return MCDisassembler::Fail; 1016 1017 // LSL accepts encoded shift amount 0, 1, 2 or 3. 1018 if (IsLSL && ShiftAmount > 3) 1019 return MCDisassembler::Fail; 1020 1021 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 1022 return MCDisassembler::Success; 1023 } 1024 1025 // Decode post-index vector load/store instructions. 1026 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1027 // operand is an immediate equal the the length of vector list in bytes, 1028 // or Rm is decoded to a GPR64noxzr register. 1029 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn, 1030 uint64_t Address, 1031 const void *Decoder) { 1032 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 1033 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1034 unsigned Rm = fieldFromInstruction(Insn, 16, 5); 1035 unsigned Opcode = fieldFromInstruction(Insn, 12, 4); 1036 unsigned IsLoad = fieldFromInstruction(Insn, 22, 1); 1037 // 0 for 64bit vector list, 1 for 128bit vector list 1038 unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1); 1039 1040 unsigned NumVecs; 1041 switch (Opcode) { 1042 case 0: // ld4/st4 1043 case 2: // ld1/st1 with 4 vectors 1044 NumVecs = 4; break; 1045 case 4: // ld3/st3 1046 case 6: // ld1/st1 with 3 vectors 1047 NumVecs = 3; break; 1048 case 7: // ld1/st1 with 1 vector 1049 NumVecs = 1; break; 1050 case 8: // ld2/st2 1051 case 10: // ld1/st1 with 2 vectors 1052 NumVecs = 2; break; 1053 default: 1054 llvm_unreachable("Invalid opcode for post-index load/store instructions"); 1055 } 1056 1057 // Decode vector list of 1/2/3/4 vectors for load instructions. 1058 if (IsLoad) { 1059 switch (NumVecs) { 1060 case 1: 1061 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder) 1062 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 1063 break; 1064 case 2: 1065 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder) 1066 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder); 1067 break; 1068 case 3: 1069 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder) 1070 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder); 1071 break; 1072 case 4: 1073 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder) 1074 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder); 1075 break; 1076 } 1077 } 1078 1079 // Decode write back register, which is equal to Rn. 1080 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1081 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1082 1083 if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte 1084 Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8))); 1085 else // Decode Rm 1086 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1087 1088 // Decode vector list of 1/2/3/4 vectors for load instructions. 1089 if (!IsLoad) { 1090 switch (NumVecs) { 1091 case 1: 1092 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder) 1093 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 1094 break; 1095 case 2: 1096 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder) 1097 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder); 1098 break; 1099 case 3: 1100 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder) 1101 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder); 1102 break; 1103 case 4: 1104 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder) 1105 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder); 1106 break; 1107 } 1108 } 1109 1110 return MCDisassembler::Success; 1111 } 1112 1113 // Decode post-index vector load/store lane instructions. 1114 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1115 // operand is an immediate equal the the length of the changed bytes, 1116 // or Rm is decoded to a GPR64noxzr register. 1117 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, 1118 uint64_t Address, 1119 const void *Decoder) { 1120 bool Is64bitVec = false; 1121 bool IsLoadDup = false; 1122 bool IsLoad = false; 1123 // The total number of bytes transferred. 1124 // TransferBytes = NumVecs * OneLaneBytes 1125 unsigned TransferBytes = 0; 1126 unsigned NumVecs = 0; 1127 unsigned Opc = Inst.getOpcode(); 1128 switch (Opc) { 1129 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register: 1130 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register: 1131 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register: 1132 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: { 1133 switch (Opc) { 1134 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register: 1135 TransferBytes = 1; break; 1136 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register: 1137 TransferBytes = 2; break; 1138 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register: 1139 TransferBytes = 4; break; 1140 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: 1141 TransferBytes = 8; break; 1142 } 1143 Is64bitVec = true; 1144 IsLoadDup = true; 1145 NumVecs = 1; 1146 break; 1147 } 1148 1149 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register: 1150 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register: 1151 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register: 1152 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: { 1153 switch (Opc) { 1154 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register: 1155 TransferBytes = 1; break; 1156 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register: 1157 TransferBytes = 2; break; 1158 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register: 1159 TransferBytes = 4; break; 1160 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: 1161 TransferBytes = 8; break; 1162 } 1163 IsLoadDup = true; 1164 NumVecs = 1; 1165 break; 1166 } 1167 1168 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register: 1169 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register: 1170 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register: 1171 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: { 1172 switch (Opc) { 1173 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register: 1174 TransferBytes = 2; break; 1175 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register: 1176 TransferBytes = 4; break; 1177 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register: 1178 TransferBytes = 8; break; 1179 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: 1180 TransferBytes = 16; break; 1181 } 1182 Is64bitVec = true; 1183 IsLoadDup = true; 1184 NumVecs = 2; 1185 break; 1186 } 1187 1188 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register: 1189 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register: 1190 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register: 1191 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: { 1192 switch (Opc) { 1193 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register: 1194 TransferBytes = 2; break; 1195 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register: 1196 TransferBytes = 4; break; 1197 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register: 1198 TransferBytes = 8; break; 1199 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: 1200 TransferBytes = 16; break; 1201 } 1202 IsLoadDup = true; 1203 NumVecs = 2; 1204 break; 1205 } 1206 1207 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register: 1208 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register: 1209 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register: 1210 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: { 1211 switch (Opc) { 1212 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register: 1213 TransferBytes = 3; break; 1214 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register: 1215 TransferBytes = 6; break; 1216 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register: 1217 TransferBytes = 12; break; 1218 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: 1219 TransferBytes = 24; break; 1220 } 1221 Is64bitVec = true; 1222 IsLoadDup = true; 1223 NumVecs = 3; 1224 break; 1225 } 1226 1227 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register: 1228 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_8H_register: 1229 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_4S_register: 1230 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: { 1231 switch (Opc) { 1232 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register: 1233 TransferBytes = 3; break; 1234 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_8H_register: 1235 TransferBytes = 6; break; 1236 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_4S_register: 1237 TransferBytes = 12; break; 1238 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: 1239 TransferBytes = 24; break; 1240 } 1241 IsLoadDup = true; 1242 NumVecs = 3; 1243 break; 1244 } 1245 1246 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register: 1247 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register: 1248 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register: 1249 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: { 1250 switch (Opc) { 1251 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register: 1252 TransferBytes = 4; break; 1253 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register: 1254 TransferBytes = 8; break; 1255 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register: 1256 TransferBytes = 16; break; 1257 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: 1258 TransferBytes = 32; break; 1259 } 1260 Is64bitVec = true; 1261 IsLoadDup = true; 1262 NumVecs = 4; 1263 break; 1264 } 1265 1266 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register: 1267 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_8H_register: 1268 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_4S_register: 1269 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: { 1270 switch (Opc) { 1271 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register: 1272 TransferBytes = 4; break; 1273 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_8H_register: 1274 TransferBytes = 8; break; 1275 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_4S_register: 1276 TransferBytes = 16; break; 1277 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: 1278 TransferBytes = 32; break; 1279 } 1280 IsLoadDup = true; 1281 NumVecs = 4; 1282 break; 1283 } 1284 1285 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register: 1286 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register: 1287 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register: 1288 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: { 1289 switch (Opc) { 1290 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register: 1291 TransferBytes = 1; break; 1292 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register: 1293 TransferBytes = 2; break; 1294 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register: 1295 TransferBytes = 4; break; 1296 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: 1297 TransferBytes = 8; break; 1298 } 1299 IsLoad = true; 1300 NumVecs = 1; 1301 break; 1302 } 1303 1304 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register: 1305 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register: 1306 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register: 1307 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: { 1308 switch (Opc) { 1309 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register: 1310 TransferBytes = 2; break; 1311 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register: 1312 TransferBytes = 4; break; 1313 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register: 1314 TransferBytes = 8; break; 1315 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: 1316 TransferBytes = 16; break; 1317 } 1318 IsLoad = true; 1319 NumVecs = 2; 1320 break; 1321 } 1322 1323 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register: 1324 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register: 1325 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register: 1326 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: { 1327 switch (Opc) { 1328 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register: 1329 TransferBytes = 3; break; 1330 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register: 1331 TransferBytes = 6; break; 1332 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register: 1333 TransferBytes = 12; break; 1334 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: 1335 TransferBytes = 24; break; 1336 } 1337 IsLoad = true; 1338 NumVecs = 3; 1339 break; 1340 } 1341 1342 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: 1343 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: 1344 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: 1345 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: { 1346 switch (Opc) { 1347 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: 1348 TransferBytes = 4; break; 1349 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: 1350 TransferBytes = 8; break; 1351 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: 1352 TransferBytes = 16; break; 1353 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: 1354 TransferBytes = 32; break; 1355 } 1356 IsLoad = true; 1357 NumVecs = 4; 1358 break; 1359 } 1360 1361 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register: 1362 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register: 1363 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register: 1364 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: { 1365 switch (Opc) { 1366 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register: 1367 TransferBytes = 1; break; 1368 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register: 1369 TransferBytes = 2; break; 1370 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register: 1371 TransferBytes = 4; break; 1372 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: 1373 TransferBytes = 8; break; 1374 } 1375 NumVecs = 1; 1376 break; 1377 } 1378 1379 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register: 1380 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register: 1381 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register: 1382 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: { 1383 switch (Opc) { 1384 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register: 1385 TransferBytes = 2; break; 1386 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register: 1387 TransferBytes = 4; break; 1388 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register: 1389 TransferBytes = 8; break; 1390 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: 1391 TransferBytes = 16; break; 1392 } 1393 NumVecs = 2; 1394 break; 1395 } 1396 1397 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register: 1398 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register: 1399 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register: 1400 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: { 1401 switch (Opc) { 1402 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register: 1403 TransferBytes = 3; break; 1404 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register: 1405 TransferBytes = 6; break; 1406 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register: 1407 TransferBytes = 12; break; 1408 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: 1409 TransferBytes = 24; break; 1410 } 1411 NumVecs = 3; 1412 break; 1413 } 1414 1415 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register: 1416 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register: 1417 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register: 1418 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: { 1419 switch (Opc) { 1420 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register: 1421 TransferBytes = 4; break; 1422 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register: 1423 TransferBytes = 8; break; 1424 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register: 1425 TransferBytes = 16; break; 1426 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: 1427 TransferBytes = 32; break; 1428 } 1429 NumVecs = 4; 1430 break; 1431 } 1432 1433 default: 1434 return MCDisassembler::Fail; 1435 } // End of switch (Opc) 1436 1437 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 1438 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1439 unsigned Rm = fieldFromInstruction(Insn, 16, 5); 1440 1441 // Decode post-index of load duplicate lane 1442 if (IsLoadDup) { 1443 switch (NumVecs) { 1444 case 1: 1445 Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder) 1446 : DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1447 break; 1448 case 2: 1449 Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder) 1450 : DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1451 break; 1452 case 3: 1453 Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder) 1454 : DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1455 break; 1456 case 4: 1457 Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder) 1458 : DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1459 } 1460 1461 // Decode write back register, which is equal to Rn. 1462 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1463 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1464 1465 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes 1466 Inst.addOperand(MCOperand::CreateImm(TransferBytes)); 1467 else // Decode Rm 1468 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1469 1470 return MCDisassembler::Success; 1471 } 1472 1473 // Decode post-index of load/store lane 1474 // Loads have a vector list as output. 1475 if (IsLoad) { 1476 switch (NumVecs) { 1477 case 1: 1478 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1479 break; 1480 case 2: 1481 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1482 break; 1483 case 3: 1484 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1485 break; 1486 case 4: 1487 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1488 } 1489 } 1490 1491 // Decode write back register, which is equal to Rn. 1492 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1493 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1494 1495 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes 1496 Inst.addOperand(MCOperand::CreateImm(TransferBytes)); 1497 else // Decode Rm 1498 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1499 1500 // Decode the source vector list. 1501 switch (NumVecs) { 1502 case 1: 1503 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1504 break; 1505 case 2: 1506 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1507 break; 1508 case 3: 1509 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1510 break; 1511 case 4: 1512 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1513 } 1514 1515 // Decode lane 1516 unsigned Q = fieldFromInstruction(Insn, 30, 1); 1517 unsigned S = fieldFromInstruction(Insn, 10, 3); 1518 unsigned lane = 0; 1519 // Calculate the number of lanes by number of vectors and transferred bytes. 1520 // NumLanes = 16 bytes / bytes of each lane 1521 unsigned NumLanes = 16 / (TransferBytes / NumVecs); 1522 switch (NumLanes) { 1523 case 16: // A vector has 16 lanes, each lane is 1 bytes. 1524 lane = (Q << 3) | S; 1525 break; 1526 case 8: 1527 lane = (Q << 2) | (S >> 1); 1528 break; 1529 case 4: 1530 lane = (Q << 1) | (S >> 2); 1531 break; 1532 case 2: 1533 lane = Q; 1534 break; 1535 } 1536 Inst.addOperand(MCOperand::CreateImm(lane)); 1537 1538 return MCDisassembler::Success; 1539 } 1540 1541 static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, 1542 uint64_t Address, 1543 const void *Decoder) { 1544 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 1545 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1546 unsigned size = fieldFromInstruction(Insn, 22, 2); 1547 unsigned Q = fieldFromInstruction(Insn, 30, 1); 1548 1549 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 1550 1551 if(Q) 1552 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 1553 else 1554 DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder); 1555 1556 switch (size) { 1557 case 0: 1558 Inst.addOperand(MCOperand::CreateImm(8)); 1559 break; 1560 case 1: 1561 Inst.addOperand(MCOperand::CreateImm(16)); 1562 break; 1563 case 2: 1564 Inst.addOperand(MCOperand::CreateImm(32)); 1565 break; 1566 default : 1567 return MCDisassembler::Fail; 1568 } 1569 return MCDisassembler::Success; 1570 } 1571 1572