1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 66 unsigned RegNo, uint64_t Address, 67 const void *Decoder); 68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 72 unsigned RegNo, uint64_t Address, 73 const void *Decoder); 74 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 81 uint64_t Address, 82 const void *Decoder); 83 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 96 uint64_t Address, 97 const void *Decoder); 98 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 99 uint64_t Address, 100 const void *Decoder); 101 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 102 uint64_t Address, 103 const void *Decoder); 104 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 118 uint64_t Address, 119 const void *Decoder); 120 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 121 uint64_t Address, 122 const void *Decoder); 123 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 124 uint64_t Address, const void *Decoder); 125 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 126 uint64_t Address, const void *Decoder); 127 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 132 uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 135 uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 138 uint64_t Address, 139 const void *Decoder); 140 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 141 uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 144 uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 162 uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 169 uint64_t Address, 170 const void *Decoder); 171 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 172 uint64_t Address, 173 const void *Decoder); 174 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 175 uint64_t Address, const void *Decoder); 176 177 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 181 uint64_t Addr, const void *Decoder); 182 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 183 uint64_t Addr, 184 const void *Decoder); 185 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 186 uint64_t Addr, const void *Decoder); 187 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 188 uint64_t Addr, 189 const void *Decoder); 190 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 191 uint64_t Addr, const void *Decoder); 192 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 193 uint64_t Addr, 194 const void *Decoder); 195 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, const void *Decoder); 197 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 198 uint64_t Addr, const void *Decoder); 199 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, const void *Decoder); 201 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 202 uint64_t Addr, const void *Decoder); 203 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, const void *Decoder); 205 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 206 unsigned RegNo, 207 uint64_t Addr, 208 const void *Decoder); 209 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 210 unsigned RegNo, 211 uint64_t Addr, 212 const void *Decoder); 213 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 214 uint32_t insn, 215 uint64_t Address, 216 const void *Decoder); 217 template<int Bits> 218 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 219 uint64_t Address, const void *Decoder); 220 template <int ElementWidth> 221 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 222 uint64_t Addr, const void *Decoder); 223 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 224 uint64_t Addr, const void *Decoder); 225 226 static bool Check(DecodeStatus &Out, DecodeStatus In) { 227 switch (In) { 228 case MCDisassembler::Success: 229 // Out stays the same. 230 return true; 231 case MCDisassembler::SoftFail: 232 Out = In; 233 return true; 234 case MCDisassembler::Fail: 235 Out = In; 236 return false; 237 } 238 llvm_unreachable("Invalid DecodeStatus!"); 239 } 240 241 #include "AArch64GenDisassemblerTables.inc" 242 #include "AArch64GenInstrInfo.inc" 243 244 #define Success MCDisassembler::Success 245 #define Fail MCDisassembler::Fail 246 #define SoftFail MCDisassembler::SoftFail 247 248 static MCDisassembler *createAArch64Disassembler(const Target &T, 249 const MCSubtargetInfo &STI, 250 MCContext &Ctx) { 251 return new AArch64Disassembler(STI, Ctx); 252 } 253 254 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 255 ArrayRef<uint8_t> Bytes, 256 uint64_t Address, 257 raw_ostream &CS) const { 258 CommentStream = &CS; 259 260 Size = 0; 261 // We want to read exactly 4 bytes of data. 262 if (Bytes.size() < 4) 263 return Fail; 264 Size = 4; 265 266 // Encoded as a small-endian 32-bit word in the stream. 267 uint32_t Insn = 268 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 269 270 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 271 272 for (auto Table : Tables) { 273 DecodeStatus Result = 274 decodeInstruction(Table, MI, Insn, Address, this, STI); 275 if (Result != MCDisassembler::Fail) 276 return Result; 277 } 278 279 return MCDisassembler::Fail; 280 } 281 282 static MCSymbolizer * 283 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 284 LLVMSymbolLookupCallback SymbolLookUp, 285 void *DisInfo, MCContext *Ctx, 286 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 287 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 288 SymbolLookUp, DisInfo); 289 } 290 291 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 292 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 293 createAArch64Disassembler); 294 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 295 createAArch64Disassembler); 296 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 297 createAArch64ExternalSymbolizer); 298 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 299 createAArch64ExternalSymbolizer); 300 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 301 createAArch64Disassembler); 302 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 303 createAArch64ExternalSymbolizer); 304 305 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 306 createAArch64Disassembler); 307 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 308 createAArch64ExternalSymbolizer); 309 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 310 createAArch64Disassembler); 311 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 312 createAArch64ExternalSymbolizer); 313 } 314 315 static const unsigned FPR128DecoderTable[] = { 316 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 317 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 318 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 319 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 320 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 321 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 322 AArch64::Q30, AArch64::Q31 323 }; 324 325 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 326 uint64_t Addr, 327 const void *Decoder) { 328 if (RegNo > 31) 329 return Fail; 330 331 unsigned Register = FPR128DecoderTable[RegNo]; 332 Inst.addOperand(MCOperand::createReg(Register)); 333 return Success; 334 } 335 336 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 337 uint64_t Addr, 338 const void *Decoder) { 339 if (RegNo > 15) 340 return Fail; 341 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 342 } 343 344 static const unsigned FPR64DecoderTable[] = { 345 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 346 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 347 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 348 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 349 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 350 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 351 AArch64::D30, AArch64::D31 352 }; 353 354 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 355 uint64_t Addr, 356 const void *Decoder) { 357 if (RegNo > 31) 358 return Fail; 359 360 unsigned Register = FPR64DecoderTable[RegNo]; 361 Inst.addOperand(MCOperand::createReg(Register)); 362 return Success; 363 } 364 365 static const unsigned FPR32DecoderTable[] = { 366 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 367 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 368 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 369 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 370 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 371 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 372 AArch64::S30, AArch64::S31 373 }; 374 375 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 376 uint64_t Addr, 377 const void *Decoder) { 378 if (RegNo > 31) 379 return Fail; 380 381 unsigned Register = FPR32DecoderTable[RegNo]; 382 Inst.addOperand(MCOperand::createReg(Register)); 383 return Success; 384 } 385 386 static const unsigned FPR16DecoderTable[] = { 387 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 388 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 389 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 390 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 391 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 392 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 393 AArch64::H30, AArch64::H31 394 }; 395 396 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 397 uint64_t Addr, 398 const void *Decoder) { 399 if (RegNo > 31) 400 return Fail; 401 402 unsigned Register = FPR16DecoderTable[RegNo]; 403 Inst.addOperand(MCOperand::createReg(Register)); 404 return Success; 405 } 406 407 static const unsigned FPR8DecoderTable[] = { 408 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 409 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 410 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 411 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 412 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 413 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 414 AArch64::B30, AArch64::B31 415 }; 416 417 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 418 uint64_t Addr, 419 const void *Decoder) { 420 if (RegNo > 31) 421 return Fail; 422 423 unsigned Register = FPR8DecoderTable[RegNo]; 424 Inst.addOperand(MCOperand::createReg(Register)); 425 return Success; 426 } 427 428 static const unsigned GPR64DecoderTable[] = { 429 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 430 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 431 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 432 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 433 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 434 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 435 AArch64::LR, AArch64::XZR 436 }; 437 438 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 439 uint64_t Addr, 440 const void *Decoder) { 441 if (RegNo > 30) 442 return Fail; 443 444 unsigned Register = GPR64DecoderTable[RegNo]; 445 Inst.addOperand(MCOperand::createReg(Register)); 446 return Success; 447 } 448 449 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 450 uint64_t Addr, 451 const void *Decoder) { 452 if (RegNo > 31) 453 return Fail; 454 455 unsigned Register = GPR64DecoderTable[RegNo]; 456 Inst.addOperand(MCOperand::createReg(Register)); 457 return Success; 458 } 459 460 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 461 uint64_t Addr, 462 const void *Decoder) { 463 if (RegNo > 31) 464 return Fail; 465 unsigned Register = GPR64DecoderTable[RegNo]; 466 if (Register == AArch64::XZR) 467 Register = AArch64::SP; 468 Inst.addOperand(MCOperand::createReg(Register)); 469 return Success; 470 } 471 472 static const unsigned GPR32DecoderTable[] = { 473 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 474 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 475 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 476 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 477 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 478 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 479 AArch64::W30, AArch64::WZR 480 }; 481 482 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 483 uint64_t Addr, 484 const void *Decoder) { 485 if (RegNo > 31) 486 return Fail; 487 488 unsigned Register = GPR32DecoderTable[RegNo]; 489 Inst.addOperand(MCOperand::createReg(Register)); 490 return Success; 491 } 492 493 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 494 uint64_t Addr, 495 const void *Decoder) { 496 if (RegNo > 31) 497 return Fail; 498 499 unsigned Register = GPR32DecoderTable[RegNo]; 500 if (Register == AArch64::WZR) 501 Register = AArch64::WSP; 502 Inst.addOperand(MCOperand::createReg(Register)); 503 return Success; 504 } 505 static const unsigned ZPRDecoderTable[] = { 506 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 507 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 508 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 509 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 510 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 511 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 512 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 513 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 514 }; 515 516 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 517 uint64_t Address, 518 const void* Decoder) { 519 if (RegNo > 31) 520 return Fail; 521 522 unsigned Register = ZPRDecoderTable[RegNo]; 523 Inst.addOperand(MCOperand::createReg(Register)); 524 return Success; 525 } 526 527 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 528 uint64_t Address, 529 const void *Decoder) { 530 if (RegNo > 15) 531 return Fail; 532 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 533 } 534 535 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 536 uint64_t Address, 537 const void *Decoder) { 538 if (RegNo > 7) 539 return Fail; 540 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 541 } 542 543 static const unsigned ZZDecoderTable[] = { 544 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 545 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 546 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 547 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 548 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 549 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 550 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 551 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 552 }; 553 554 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 555 uint64_t Address, 556 const void* Decoder) { 557 if (RegNo > 31) 558 return Fail; 559 unsigned Register = ZZDecoderTable[RegNo]; 560 Inst.addOperand(MCOperand::createReg(Register)); 561 return Success; 562 } 563 564 static const unsigned ZZZDecoderTable[] = { 565 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 566 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 567 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 568 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 569 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 570 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 571 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 572 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 573 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 574 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 575 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 576 }; 577 578 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 579 uint64_t Address, 580 const void* Decoder) { 581 if (RegNo > 31) 582 return Fail; 583 unsigned Register = ZZZDecoderTable[RegNo]; 584 Inst.addOperand(MCOperand::createReg(Register)); 585 return Success; 586 } 587 588 static const unsigned ZZZZDecoderTable[] = { 589 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 590 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 591 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 592 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 593 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 594 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 595 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 596 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 597 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 598 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 599 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 600 }; 601 602 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 603 uint64_t Address, 604 const void* Decoder) { 605 if (RegNo > 31) 606 return Fail; 607 unsigned Register = ZZZZDecoderTable[RegNo]; 608 Inst.addOperand(MCOperand::createReg(Register)); 609 return Success; 610 } 611 612 static const unsigned PPRDecoderTable[] = { 613 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 614 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 615 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 616 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 617 }; 618 619 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 620 uint64_t Addr, const void *Decoder) { 621 if (RegNo > 15) 622 return Fail; 623 624 unsigned Register = PPRDecoderTable[RegNo]; 625 Inst.addOperand(MCOperand::createReg(Register)); 626 return Success; 627 } 628 629 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 630 uint64_t Addr, 631 const void* Decoder) { 632 if (RegNo > 7) 633 return Fail; 634 635 // Just reuse the PPR decode table 636 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 637 } 638 639 static const unsigned VectorDecoderTable[] = { 640 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 641 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 642 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 643 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 644 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 645 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 646 AArch64::Q30, AArch64::Q31 647 }; 648 649 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 650 uint64_t Addr, 651 const void *Decoder) { 652 if (RegNo > 31) 653 return Fail; 654 655 unsigned Register = VectorDecoderTable[RegNo]; 656 Inst.addOperand(MCOperand::createReg(Register)); 657 return Success; 658 } 659 660 static const unsigned QQDecoderTable[] = { 661 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 662 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 663 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 664 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 665 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 666 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 667 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 668 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 669 }; 670 671 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 672 uint64_t Addr, const void *Decoder) { 673 if (RegNo > 31) 674 return Fail; 675 unsigned Register = QQDecoderTable[RegNo]; 676 Inst.addOperand(MCOperand::createReg(Register)); 677 return Success; 678 } 679 680 static const unsigned QQQDecoderTable[] = { 681 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 682 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 683 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 684 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 685 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 686 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 687 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 688 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 689 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 690 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 691 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 692 }; 693 694 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 695 uint64_t Addr, const void *Decoder) { 696 if (RegNo > 31) 697 return Fail; 698 unsigned Register = QQQDecoderTable[RegNo]; 699 Inst.addOperand(MCOperand::createReg(Register)); 700 return Success; 701 } 702 703 static const unsigned QQQQDecoderTable[] = { 704 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 705 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 706 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 707 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 708 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 709 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 710 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 711 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 712 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 713 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 714 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 715 }; 716 717 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 718 uint64_t Addr, 719 const void *Decoder) { 720 if (RegNo > 31) 721 return Fail; 722 unsigned Register = QQQQDecoderTable[RegNo]; 723 Inst.addOperand(MCOperand::createReg(Register)); 724 return Success; 725 } 726 727 static const unsigned DDDecoderTable[] = { 728 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 729 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 730 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 731 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 732 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 733 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 734 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 735 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 736 }; 737 738 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 739 uint64_t Addr, const void *Decoder) { 740 if (RegNo > 31) 741 return Fail; 742 unsigned Register = DDDecoderTable[RegNo]; 743 Inst.addOperand(MCOperand::createReg(Register)); 744 return Success; 745 } 746 747 static const unsigned DDDDecoderTable[] = { 748 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 749 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 750 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 751 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 752 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 753 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 754 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 755 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 756 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 757 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 758 AArch64::D30_D31_D0, AArch64::D31_D0_D1 759 }; 760 761 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 762 uint64_t Addr, const void *Decoder) { 763 if (RegNo > 31) 764 return Fail; 765 unsigned Register = DDDDecoderTable[RegNo]; 766 Inst.addOperand(MCOperand::createReg(Register)); 767 return Success; 768 } 769 770 static const unsigned DDDDDecoderTable[] = { 771 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 772 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 773 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 774 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 775 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 776 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 777 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 778 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 779 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 780 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 781 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 782 }; 783 784 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 785 uint64_t Addr, 786 const void *Decoder) { 787 if (RegNo > 31) 788 return Fail; 789 unsigned Register = DDDDDecoderTable[RegNo]; 790 Inst.addOperand(MCOperand::createReg(Register)); 791 return Success; 792 } 793 794 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 795 uint64_t Addr, 796 const void *Decoder) { 797 // scale{5} is asserted as 1 in tblgen. 798 Imm |= 0x20; 799 Inst.addOperand(MCOperand::createImm(64 - Imm)); 800 return Success; 801 } 802 803 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 804 uint64_t Addr, 805 const void *Decoder) { 806 Inst.addOperand(MCOperand::createImm(64 - Imm)); 807 return Success; 808 } 809 810 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 811 uint64_t Addr, const void *Decoder) { 812 int64_t ImmVal = Imm; 813 const AArch64Disassembler *Dis = 814 static_cast<const AArch64Disassembler *>(Decoder); 815 816 // Sign-extend 19-bit immediate. 817 if (ImmVal & (1 << (19 - 1))) 818 ImmVal |= ~((1LL << 19) - 1); 819 820 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 821 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 822 Inst.addOperand(MCOperand::createImm(ImmVal)); 823 return Success; 824 } 825 826 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 827 uint64_t Address, const void *Decoder) { 828 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 829 Inst.addOperand(MCOperand::createImm(Imm & 1)); 830 return Success; 831 } 832 833 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 834 uint64_t Address, 835 const void *Decoder) { 836 Inst.addOperand(MCOperand::createImm(Imm)); 837 838 // Every system register in the encoding space is valid with the syntax 839 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 840 return Success; 841 } 842 843 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 844 uint64_t Address, 845 const void *Decoder) { 846 Inst.addOperand(MCOperand::createImm(Imm)); 847 848 return Success; 849 } 850 851 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 852 uint64_t Address, 853 const void *Decoder) { 854 // This decoder exists to add the dummy Lane operand to the MCInst, which must 855 // be 1 in assembly but has no other real manifestation. 856 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 857 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 858 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 859 860 if (IsToVec) { 861 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 862 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 863 } else { 864 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 865 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 866 } 867 868 // Add the lane 869 Inst.addOperand(MCOperand::createImm(1)); 870 871 return Success; 872 } 873 874 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 875 unsigned Add) { 876 Inst.addOperand(MCOperand::createImm(Add - Imm)); 877 return Success; 878 } 879 880 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 881 unsigned Add) { 882 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 883 return Success; 884 } 885 886 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 887 uint64_t Addr, const void *Decoder) { 888 return DecodeVecShiftRImm(Inst, Imm, 64); 889 } 890 891 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 892 uint64_t Addr, 893 const void *Decoder) { 894 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 895 } 896 897 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 898 uint64_t Addr, const void *Decoder) { 899 return DecodeVecShiftRImm(Inst, Imm, 32); 900 } 901 902 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 903 uint64_t Addr, 904 const void *Decoder) { 905 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 906 } 907 908 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 909 uint64_t Addr, const void *Decoder) { 910 return DecodeVecShiftRImm(Inst, Imm, 16); 911 } 912 913 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 914 uint64_t Addr, 915 const void *Decoder) { 916 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 917 } 918 919 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 920 uint64_t Addr, const void *Decoder) { 921 return DecodeVecShiftRImm(Inst, Imm, 8); 922 } 923 924 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 925 uint64_t Addr, const void *Decoder) { 926 return DecodeVecShiftLImm(Inst, Imm, 64); 927 } 928 929 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 930 uint64_t Addr, const void *Decoder) { 931 return DecodeVecShiftLImm(Inst, Imm, 32); 932 } 933 934 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 935 uint64_t Addr, const void *Decoder) { 936 return DecodeVecShiftLImm(Inst, Imm, 16); 937 } 938 939 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 940 uint64_t Addr, const void *Decoder) { 941 return DecodeVecShiftLImm(Inst, Imm, 8); 942 } 943 944 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 945 uint64_t Addr, 946 const void *Decoder) { 947 unsigned Rd = fieldFromInstruction(insn, 0, 5); 948 unsigned Rn = fieldFromInstruction(insn, 5, 5); 949 unsigned Rm = fieldFromInstruction(insn, 16, 5); 950 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 951 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 952 unsigned shift = (shiftHi << 6) | shiftLo; 953 switch (Inst.getOpcode()) { 954 default: 955 return Fail; 956 case AArch64::ADDWrs: 957 case AArch64::ADDSWrs: 958 case AArch64::SUBWrs: 959 case AArch64::SUBSWrs: 960 // if shift == '11' then ReservedValue() 961 if (shiftHi == 0x3) 962 return Fail; 963 LLVM_FALLTHROUGH; 964 case AArch64::ANDWrs: 965 case AArch64::ANDSWrs: 966 case AArch64::BICWrs: 967 case AArch64::BICSWrs: 968 case AArch64::ORRWrs: 969 case AArch64::ORNWrs: 970 case AArch64::EORWrs: 971 case AArch64::EONWrs: { 972 // if sf == '0' and imm6<5> == '1' then ReservedValue() 973 if (shiftLo >> 5 == 1) 974 return Fail; 975 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 976 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 977 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 978 break; 979 } 980 case AArch64::ADDXrs: 981 case AArch64::ADDSXrs: 982 case AArch64::SUBXrs: 983 case AArch64::SUBSXrs: 984 // if shift == '11' then ReservedValue() 985 if (shiftHi == 0x3) 986 return Fail; 987 LLVM_FALLTHROUGH; 988 case AArch64::ANDXrs: 989 case AArch64::ANDSXrs: 990 case AArch64::BICXrs: 991 case AArch64::BICSXrs: 992 case AArch64::ORRXrs: 993 case AArch64::ORNXrs: 994 case AArch64::EORXrs: 995 case AArch64::EONXrs: 996 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 997 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 998 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 999 break; 1000 } 1001 1002 Inst.addOperand(MCOperand::createImm(shift)); 1003 return Success; 1004 } 1005 1006 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1007 uint64_t Addr, 1008 const void *Decoder) { 1009 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1010 unsigned imm = fieldFromInstruction(insn, 5, 16); 1011 unsigned shift = fieldFromInstruction(insn, 21, 2); 1012 shift <<= 4; 1013 switch (Inst.getOpcode()) { 1014 default: 1015 return Fail; 1016 case AArch64::MOVZWi: 1017 case AArch64::MOVNWi: 1018 case AArch64::MOVKWi: 1019 if (shift & (1U << 5)) 1020 return Fail; 1021 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1022 break; 1023 case AArch64::MOVZXi: 1024 case AArch64::MOVNXi: 1025 case AArch64::MOVKXi: 1026 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1027 break; 1028 } 1029 1030 if (Inst.getOpcode() == AArch64::MOVKWi || 1031 Inst.getOpcode() == AArch64::MOVKXi) 1032 Inst.addOperand(Inst.getOperand(0)); 1033 1034 Inst.addOperand(MCOperand::createImm(imm)); 1035 Inst.addOperand(MCOperand::createImm(shift)); 1036 return Success; 1037 } 1038 1039 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1040 uint64_t Addr, 1041 const void *Decoder) { 1042 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1043 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1044 unsigned offset = fieldFromInstruction(insn, 10, 12); 1045 const AArch64Disassembler *Dis = 1046 static_cast<const AArch64Disassembler *>(Decoder); 1047 1048 switch (Inst.getOpcode()) { 1049 default: 1050 return Fail; 1051 case AArch64::PRFMui: 1052 // Rt is an immediate in prefetch. 1053 Inst.addOperand(MCOperand::createImm(Rt)); 1054 break; 1055 case AArch64::STRBBui: 1056 case AArch64::LDRBBui: 1057 case AArch64::LDRSBWui: 1058 case AArch64::STRHHui: 1059 case AArch64::LDRHHui: 1060 case AArch64::LDRSHWui: 1061 case AArch64::STRWui: 1062 case AArch64::LDRWui: 1063 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1064 break; 1065 case AArch64::LDRSBXui: 1066 case AArch64::LDRSHXui: 1067 case AArch64::LDRSWui: 1068 case AArch64::STRXui: 1069 case AArch64::LDRXui: 1070 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1071 break; 1072 case AArch64::LDRQui: 1073 case AArch64::STRQui: 1074 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1075 break; 1076 case AArch64::LDRDui: 1077 case AArch64::STRDui: 1078 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1079 break; 1080 case AArch64::LDRSui: 1081 case AArch64::STRSui: 1082 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1083 break; 1084 case AArch64::LDRHui: 1085 case AArch64::STRHui: 1086 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1087 break; 1088 case AArch64::LDRBui: 1089 case AArch64::STRBui: 1090 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1091 break; 1092 } 1093 1094 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1095 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1096 Inst.addOperand(MCOperand::createImm(offset)); 1097 return Success; 1098 } 1099 1100 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1101 uint64_t Addr, 1102 const void *Decoder) { 1103 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1104 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1105 int64_t offset = fieldFromInstruction(insn, 12, 9); 1106 1107 // offset is a 9-bit signed immediate, so sign extend it to 1108 // fill the unsigned. 1109 if (offset & (1 << (9 - 1))) 1110 offset |= ~((1LL << 9) - 1); 1111 1112 // First operand is always the writeback to the address register, if needed. 1113 switch (Inst.getOpcode()) { 1114 default: 1115 break; 1116 case AArch64::LDRSBWpre: 1117 case AArch64::LDRSHWpre: 1118 case AArch64::STRBBpre: 1119 case AArch64::LDRBBpre: 1120 case AArch64::STRHHpre: 1121 case AArch64::LDRHHpre: 1122 case AArch64::STRWpre: 1123 case AArch64::LDRWpre: 1124 case AArch64::LDRSBWpost: 1125 case AArch64::LDRSHWpost: 1126 case AArch64::STRBBpost: 1127 case AArch64::LDRBBpost: 1128 case AArch64::STRHHpost: 1129 case AArch64::LDRHHpost: 1130 case AArch64::STRWpost: 1131 case AArch64::LDRWpost: 1132 case AArch64::LDRSBXpre: 1133 case AArch64::LDRSHXpre: 1134 case AArch64::STRXpre: 1135 case AArch64::LDRSWpre: 1136 case AArch64::LDRXpre: 1137 case AArch64::LDRSBXpost: 1138 case AArch64::LDRSHXpost: 1139 case AArch64::STRXpost: 1140 case AArch64::LDRSWpost: 1141 case AArch64::LDRXpost: 1142 case AArch64::LDRQpre: 1143 case AArch64::STRQpre: 1144 case AArch64::LDRQpost: 1145 case AArch64::STRQpost: 1146 case AArch64::LDRDpre: 1147 case AArch64::STRDpre: 1148 case AArch64::LDRDpost: 1149 case AArch64::STRDpost: 1150 case AArch64::LDRSpre: 1151 case AArch64::STRSpre: 1152 case AArch64::LDRSpost: 1153 case AArch64::STRSpost: 1154 case AArch64::LDRHpre: 1155 case AArch64::STRHpre: 1156 case AArch64::LDRHpost: 1157 case AArch64::STRHpost: 1158 case AArch64::LDRBpre: 1159 case AArch64::STRBpre: 1160 case AArch64::LDRBpost: 1161 case AArch64::STRBpost: 1162 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1163 break; 1164 } 1165 1166 switch (Inst.getOpcode()) { 1167 default: 1168 return Fail; 1169 case AArch64::PRFUMi: 1170 // Rt is an immediate in prefetch. 1171 Inst.addOperand(MCOperand::createImm(Rt)); 1172 break; 1173 case AArch64::STURBBi: 1174 case AArch64::LDURBBi: 1175 case AArch64::LDURSBWi: 1176 case AArch64::STURHHi: 1177 case AArch64::LDURHHi: 1178 case AArch64::LDURSHWi: 1179 case AArch64::STURWi: 1180 case AArch64::LDURWi: 1181 case AArch64::LDTRSBWi: 1182 case AArch64::LDTRSHWi: 1183 case AArch64::STTRWi: 1184 case AArch64::LDTRWi: 1185 case AArch64::STTRHi: 1186 case AArch64::LDTRHi: 1187 case AArch64::LDTRBi: 1188 case AArch64::STTRBi: 1189 case AArch64::LDRSBWpre: 1190 case AArch64::LDRSHWpre: 1191 case AArch64::STRBBpre: 1192 case AArch64::LDRBBpre: 1193 case AArch64::STRHHpre: 1194 case AArch64::LDRHHpre: 1195 case AArch64::STRWpre: 1196 case AArch64::LDRWpre: 1197 case AArch64::LDRSBWpost: 1198 case AArch64::LDRSHWpost: 1199 case AArch64::STRBBpost: 1200 case AArch64::LDRBBpost: 1201 case AArch64::STRHHpost: 1202 case AArch64::LDRHHpost: 1203 case AArch64::STRWpost: 1204 case AArch64::LDRWpost: 1205 case AArch64::STLURBi: 1206 case AArch64::STLURHi: 1207 case AArch64::STLURWi: 1208 case AArch64::LDAPURBi: 1209 case AArch64::LDAPURSBWi: 1210 case AArch64::LDAPURHi: 1211 case AArch64::LDAPURSHWi: 1212 case AArch64::LDAPURi: 1213 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1214 break; 1215 case AArch64::LDURSBXi: 1216 case AArch64::LDURSHXi: 1217 case AArch64::LDURSWi: 1218 case AArch64::STURXi: 1219 case AArch64::LDURXi: 1220 case AArch64::LDTRSBXi: 1221 case AArch64::LDTRSHXi: 1222 case AArch64::LDTRSWi: 1223 case AArch64::STTRXi: 1224 case AArch64::LDTRXi: 1225 case AArch64::LDRSBXpre: 1226 case AArch64::LDRSHXpre: 1227 case AArch64::STRXpre: 1228 case AArch64::LDRSWpre: 1229 case AArch64::LDRXpre: 1230 case AArch64::LDRSBXpost: 1231 case AArch64::LDRSHXpost: 1232 case AArch64::STRXpost: 1233 case AArch64::LDRSWpost: 1234 case AArch64::LDRXpost: 1235 case AArch64::LDAPURSWi: 1236 case AArch64::LDAPURSHXi: 1237 case AArch64::LDAPURSBXi: 1238 case AArch64::STLURXi: 1239 case AArch64::LDAPURXi: 1240 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1241 break; 1242 case AArch64::LDURQi: 1243 case AArch64::STURQi: 1244 case AArch64::LDRQpre: 1245 case AArch64::STRQpre: 1246 case AArch64::LDRQpost: 1247 case AArch64::STRQpost: 1248 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1249 break; 1250 case AArch64::LDURDi: 1251 case AArch64::STURDi: 1252 case AArch64::LDRDpre: 1253 case AArch64::STRDpre: 1254 case AArch64::LDRDpost: 1255 case AArch64::STRDpost: 1256 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1257 break; 1258 case AArch64::LDURSi: 1259 case AArch64::STURSi: 1260 case AArch64::LDRSpre: 1261 case AArch64::STRSpre: 1262 case AArch64::LDRSpost: 1263 case AArch64::STRSpost: 1264 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1265 break; 1266 case AArch64::LDURHi: 1267 case AArch64::STURHi: 1268 case AArch64::LDRHpre: 1269 case AArch64::STRHpre: 1270 case AArch64::LDRHpost: 1271 case AArch64::STRHpost: 1272 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1273 break; 1274 case AArch64::LDURBi: 1275 case AArch64::STURBi: 1276 case AArch64::LDRBpre: 1277 case AArch64::STRBpre: 1278 case AArch64::LDRBpost: 1279 case AArch64::STRBpost: 1280 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1281 break; 1282 } 1283 1284 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1285 Inst.addOperand(MCOperand::createImm(offset)); 1286 1287 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1288 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1289 bool IsFP = fieldFromInstruction(insn, 26, 1); 1290 1291 // Cannot write back to a transfer register (but xzr != sp). 1292 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1293 return SoftFail; 1294 1295 return Success; 1296 } 1297 1298 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1299 uint64_t Addr, 1300 const void *Decoder) { 1301 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1302 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1303 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1304 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1305 1306 unsigned Opcode = Inst.getOpcode(); 1307 switch (Opcode) { 1308 default: 1309 return Fail; 1310 case AArch64::STLXRW: 1311 case AArch64::STLXRB: 1312 case AArch64::STLXRH: 1313 case AArch64::STXRW: 1314 case AArch64::STXRB: 1315 case AArch64::STXRH: 1316 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1317 LLVM_FALLTHROUGH; 1318 case AArch64::LDARW: 1319 case AArch64::LDARB: 1320 case AArch64::LDARH: 1321 case AArch64::LDAXRW: 1322 case AArch64::LDAXRB: 1323 case AArch64::LDAXRH: 1324 case AArch64::LDXRW: 1325 case AArch64::LDXRB: 1326 case AArch64::LDXRH: 1327 case AArch64::STLRW: 1328 case AArch64::STLRB: 1329 case AArch64::STLRH: 1330 case AArch64::STLLRW: 1331 case AArch64::STLLRB: 1332 case AArch64::STLLRH: 1333 case AArch64::LDLARW: 1334 case AArch64::LDLARB: 1335 case AArch64::LDLARH: 1336 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1337 break; 1338 case AArch64::STLXRX: 1339 case AArch64::STXRX: 1340 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1341 LLVM_FALLTHROUGH; 1342 case AArch64::LDARX: 1343 case AArch64::LDAXRX: 1344 case AArch64::LDXRX: 1345 case AArch64::STLRX: 1346 case AArch64::LDLARX: 1347 case AArch64::STLLRX: 1348 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1349 break; 1350 case AArch64::STLXPW: 1351 case AArch64::STXPW: 1352 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1353 LLVM_FALLTHROUGH; 1354 case AArch64::LDAXPW: 1355 case AArch64::LDXPW: 1356 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1357 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1358 break; 1359 case AArch64::STLXPX: 1360 case AArch64::STXPX: 1361 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1362 LLVM_FALLTHROUGH; 1363 case AArch64::LDAXPX: 1364 case AArch64::LDXPX: 1365 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1366 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1367 break; 1368 } 1369 1370 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1371 1372 // You shouldn't load to the same register twice in an instruction... 1373 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1374 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1375 Rt == Rt2) 1376 return SoftFail; 1377 1378 return Success; 1379 } 1380 1381 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1382 uint64_t Addr, 1383 const void *Decoder) { 1384 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1385 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1386 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1387 int64_t offset = fieldFromInstruction(insn, 15, 7); 1388 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1389 1390 // offset is a 7-bit signed immediate, so sign extend it to 1391 // fill the unsigned. 1392 if (offset & (1 << (7 - 1))) 1393 offset |= ~((1LL << 7) - 1); 1394 1395 unsigned Opcode = Inst.getOpcode(); 1396 bool NeedsDisjointWritebackTransfer = false; 1397 1398 // First operand is always writeback of base register. 1399 switch (Opcode) { 1400 default: 1401 break; 1402 case AArch64::LDPXpost: 1403 case AArch64::STPXpost: 1404 case AArch64::LDPSWpost: 1405 case AArch64::LDPXpre: 1406 case AArch64::STPXpre: 1407 case AArch64::LDPSWpre: 1408 case AArch64::LDPWpost: 1409 case AArch64::STPWpost: 1410 case AArch64::LDPWpre: 1411 case AArch64::STPWpre: 1412 case AArch64::LDPQpost: 1413 case AArch64::STPQpost: 1414 case AArch64::LDPQpre: 1415 case AArch64::STPQpre: 1416 case AArch64::LDPDpost: 1417 case AArch64::STPDpost: 1418 case AArch64::LDPDpre: 1419 case AArch64::STPDpre: 1420 case AArch64::LDPSpost: 1421 case AArch64::STPSpost: 1422 case AArch64::LDPSpre: 1423 case AArch64::STPSpre: 1424 case AArch64::STGPpre: 1425 case AArch64::STGPpost: 1426 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1427 break; 1428 } 1429 1430 switch (Opcode) { 1431 default: 1432 return Fail; 1433 case AArch64::LDPXpost: 1434 case AArch64::STPXpost: 1435 case AArch64::LDPSWpost: 1436 case AArch64::LDPXpre: 1437 case AArch64::STPXpre: 1438 case AArch64::LDPSWpre: 1439 case AArch64::STGPpre: 1440 case AArch64::STGPpost: 1441 NeedsDisjointWritebackTransfer = true; 1442 LLVM_FALLTHROUGH; 1443 case AArch64::LDNPXi: 1444 case AArch64::STNPXi: 1445 case AArch64::LDPXi: 1446 case AArch64::STPXi: 1447 case AArch64::LDPSWi: 1448 case AArch64::STGPi: 1449 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1450 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1451 break; 1452 case AArch64::LDPWpost: 1453 case AArch64::STPWpost: 1454 case AArch64::LDPWpre: 1455 case AArch64::STPWpre: 1456 NeedsDisjointWritebackTransfer = true; 1457 LLVM_FALLTHROUGH; 1458 case AArch64::LDNPWi: 1459 case AArch64::STNPWi: 1460 case AArch64::LDPWi: 1461 case AArch64::STPWi: 1462 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1463 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1464 break; 1465 case AArch64::LDNPQi: 1466 case AArch64::STNPQi: 1467 case AArch64::LDPQpost: 1468 case AArch64::STPQpost: 1469 case AArch64::LDPQi: 1470 case AArch64::STPQi: 1471 case AArch64::LDPQpre: 1472 case AArch64::STPQpre: 1473 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1474 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1475 break; 1476 case AArch64::LDNPDi: 1477 case AArch64::STNPDi: 1478 case AArch64::LDPDpost: 1479 case AArch64::STPDpost: 1480 case AArch64::LDPDi: 1481 case AArch64::STPDi: 1482 case AArch64::LDPDpre: 1483 case AArch64::STPDpre: 1484 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1485 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1486 break; 1487 case AArch64::LDNPSi: 1488 case AArch64::STNPSi: 1489 case AArch64::LDPSpost: 1490 case AArch64::STPSpost: 1491 case AArch64::LDPSi: 1492 case AArch64::STPSi: 1493 case AArch64::LDPSpre: 1494 case AArch64::STPSpre: 1495 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1496 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1497 break; 1498 } 1499 1500 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1501 Inst.addOperand(MCOperand::createImm(offset)); 1502 1503 // You shouldn't load to the same register twice in an instruction... 1504 if (IsLoad && Rt == Rt2) 1505 return SoftFail; 1506 1507 // ... or do any operation that writes-back to a transfer register. But note 1508 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1509 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1510 return SoftFail; 1511 1512 return Success; 1513 } 1514 1515 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1516 uint64_t Addr, 1517 const void *Decoder) { 1518 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1519 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1520 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1521 fieldFromInstruction(insn, 12, 9); 1522 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1523 1524 switch (Inst.getOpcode()) { 1525 default: 1526 return Fail; 1527 case AArch64::LDRAAwriteback: 1528 case AArch64::LDRABwriteback: 1529 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1530 Decoder); 1531 break; 1532 case AArch64::LDRAAindexed: 1533 case AArch64::LDRABindexed: 1534 break; 1535 } 1536 1537 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1538 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1539 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1540 1541 if (writeback && Rt == Rn && Rn != 31) { 1542 return SoftFail; 1543 } 1544 1545 return Success; 1546 } 1547 1548 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1549 uint64_t Addr, 1550 const void *Decoder) { 1551 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1552 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1553 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1554 unsigned extend = fieldFromInstruction(insn, 10, 6); 1555 1556 unsigned shift = extend & 0x7; 1557 if (shift > 4) 1558 return Fail; 1559 1560 switch (Inst.getOpcode()) { 1561 default: 1562 return Fail; 1563 case AArch64::ADDWrx: 1564 case AArch64::SUBWrx: 1565 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1566 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1567 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1568 break; 1569 case AArch64::ADDSWrx: 1570 case AArch64::SUBSWrx: 1571 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1572 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1573 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1574 break; 1575 case AArch64::ADDXrx: 1576 case AArch64::SUBXrx: 1577 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1578 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1579 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1580 break; 1581 case AArch64::ADDSXrx: 1582 case AArch64::SUBSXrx: 1583 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1584 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1585 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1586 break; 1587 case AArch64::ADDXrx64: 1588 case AArch64::SUBXrx64: 1589 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1590 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1591 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1592 break; 1593 case AArch64::SUBSXrx64: 1594 case AArch64::ADDSXrx64: 1595 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1596 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1597 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1598 break; 1599 } 1600 1601 Inst.addOperand(MCOperand::createImm(extend)); 1602 return Success; 1603 } 1604 1605 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1606 uint64_t Addr, 1607 const void *Decoder) { 1608 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1609 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1610 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1611 unsigned imm; 1612 1613 if (Datasize) { 1614 if (Inst.getOpcode() == AArch64::ANDSXri) 1615 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1616 else 1617 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1618 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1619 imm = fieldFromInstruction(insn, 10, 13); 1620 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1621 return Fail; 1622 } else { 1623 if (Inst.getOpcode() == AArch64::ANDSWri) 1624 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1625 else 1626 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1627 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1628 imm = fieldFromInstruction(insn, 10, 12); 1629 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1630 return Fail; 1631 } 1632 Inst.addOperand(MCOperand::createImm(imm)); 1633 return Success; 1634 } 1635 1636 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1637 uint64_t Addr, 1638 const void *Decoder) { 1639 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1640 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1641 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1642 imm |= fieldFromInstruction(insn, 5, 5); 1643 1644 if (Inst.getOpcode() == AArch64::MOVID) 1645 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1646 else 1647 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1648 1649 Inst.addOperand(MCOperand::createImm(imm)); 1650 1651 switch (Inst.getOpcode()) { 1652 default: 1653 break; 1654 case AArch64::MOVIv4i16: 1655 case AArch64::MOVIv8i16: 1656 case AArch64::MVNIv4i16: 1657 case AArch64::MVNIv8i16: 1658 case AArch64::MOVIv2i32: 1659 case AArch64::MOVIv4i32: 1660 case AArch64::MVNIv2i32: 1661 case AArch64::MVNIv4i32: 1662 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1663 break; 1664 case AArch64::MOVIv2s_msl: 1665 case AArch64::MOVIv4s_msl: 1666 case AArch64::MVNIv2s_msl: 1667 case AArch64::MVNIv4s_msl: 1668 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1669 break; 1670 } 1671 1672 return Success; 1673 } 1674 1675 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1676 uint64_t Addr, 1677 const void *Decoder) { 1678 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1679 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1680 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1681 imm |= fieldFromInstruction(insn, 5, 5); 1682 1683 // Tied operands added twice. 1684 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1685 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1686 1687 Inst.addOperand(MCOperand::createImm(imm)); 1688 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1689 1690 return Success; 1691 } 1692 1693 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1694 uint64_t Addr, const void *Decoder) { 1695 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1696 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1697 imm |= fieldFromInstruction(insn, 29, 2); 1698 const AArch64Disassembler *Dis = 1699 static_cast<const AArch64Disassembler *>(Decoder); 1700 1701 // Sign-extend the 21-bit immediate. 1702 if (imm & (1 << (21 - 1))) 1703 imm |= ~((1LL << 21) - 1); 1704 1705 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1706 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1707 Inst.addOperand(MCOperand::createImm(imm)); 1708 1709 return Success; 1710 } 1711 1712 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1713 uint64_t Addr, const void *Decoder) { 1714 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1715 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1716 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1717 unsigned S = fieldFromInstruction(insn, 29, 1); 1718 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1719 1720 unsigned ShifterVal = (Imm >> 12) & 3; 1721 unsigned ImmVal = Imm & 0xFFF; 1722 const AArch64Disassembler *Dis = 1723 static_cast<const AArch64Disassembler *>(Decoder); 1724 1725 if (ShifterVal != 0 && ShifterVal != 1) 1726 return Fail; 1727 1728 if (Datasize) { 1729 if (Rd == 31 && !S) 1730 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1731 else 1732 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1733 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1734 } else { 1735 if (Rd == 31 && !S) 1736 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1737 else 1738 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1739 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1740 } 1741 1742 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1743 Inst.addOperand(MCOperand::createImm(ImmVal)); 1744 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1745 return Success; 1746 } 1747 1748 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1749 uint64_t Addr, 1750 const void *Decoder) { 1751 int64_t imm = fieldFromInstruction(insn, 0, 26); 1752 const AArch64Disassembler *Dis = 1753 static_cast<const AArch64Disassembler *>(Decoder); 1754 1755 // Sign-extend the 26-bit immediate. 1756 if (imm & (1 << (26 - 1))) 1757 imm |= ~((1LL << 26) - 1); 1758 1759 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1760 Inst.addOperand(MCOperand::createImm(imm)); 1761 1762 return Success; 1763 } 1764 1765 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1766 uint64_t Addr, 1767 const void *Decoder) { 1768 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1769 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1770 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1771 uint64_t pstate_field = (op1 << 3) | op2; 1772 1773 switch (pstate_field) { 1774 case 0x01: // XAFlag 1775 case 0x02: // AXFlag 1776 return Fail; 1777 } 1778 1779 if ((pstate_field == AArch64PState::PAN || 1780 pstate_field == AArch64PState::UAO || 1781 pstate_field == AArch64PState::SSBS) && crm > 1) 1782 return Fail; 1783 1784 Inst.addOperand(MCOperand::createImm(pstate_field)); 1785 Inst.addOperand(MCOperand::createImm(crm)); 1786 1787 const AArch64Disassembler *Dis = 1788 static_cast<const AArch64Disassembler *>(Decoder); 1789 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1790 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1791 return Success; 1792 return Fail; 1793 } 1794 1795 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1796 uint64_t Addr, const void *Decoder) { 1797 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1798 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1799 bit |= fieldFromInstruction(insn, 19, 5); 1800 int64_t dst = fieldFromInstruction(insn, 5, 14); 1801 const AArch64Disassembler *Dis = 1802 static_cast<const AArch64Disassembler *>(Decoder); 1803 1804 // Sign-extend 14-bit immediate. 1805 if (dst & (1 << (14 - 1))) 1806 dst |= ~((1LL << 14) - 1); 1807 1808 if (fieldFromInstruction(insn, 31, 1) == 0) 1809 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1810 else 1811 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1812 Inst.addOperand(MCOperand::createImm(bit)); 1813 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1814 Inst.addOperand(MCOperand::createImm(dst)); 1815 1816 return Success; 1817 } 1818 1819 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1820 unsigned RegClassID, 1821 unsigned RegNo, 1822 uint64_t Addr, 1823 const void *Decoder) { 1824 // Register number must be even (see CASP instruction) 1825 if (RegNo & 0x1) 1826 return Fail; 1827 1828 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1829 Inst.addOperand(MCOperand::createReg(Reg)); 1830 return Success; 1831 } 1832 1833 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1834 unsigned RegNo, 1835 uint64_t Addr, 1836 const void *Decoder) { 1837 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1838 AArch64::WSeqPairsClassRegClassID, 1839 RegNo, Addr, Decoder); 1840 } 1841 1842 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1843 unsigned RegNo, 1844 uint64_t Addr, 1845 const void *Decoder) { 1846 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1847 AArch64::XSeqPairsClassRegClassID, 1848 RegNo, Addr, Decoder); 1849 } 1850 1851 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1852 uint32_t insn, 1853 uint64_t Addr, 1854 const void *Decoder) { 1855 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1856 unsigned imm = fieldFromInstruction(insn, 5, 13); 1857 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1858 return Fail; 1859 1860 // The same (tied) operand is added twice to the instruction. 1861 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1862 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1863 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1864 Inst.addOperand(MCOperand::createImm(imm)); 1865 return Success; 1866 } 1867 1868 template<int Bits> 1869 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1870 uint64_t Address, const void *Decoder) { 1871 if (Imm & ~((1LL << Bits) - 1)) 1872 return Fail; 1873 1874 // Imm is a signed immediate, so sign extend it. 1875 if (Imm & (1 << (Bits - 1))) 1876 Imm |= ~((1LL << Bits) - 1); 1877 1878 Inst.addOperand(MCOperand::createImm(Imm)); 1879 return Success; 1880 } 1881 1882 // Decode 8-bit signed/unsigned immediate for a given element width. 1883 template <int ElementWidth> 1884 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1885 uint64_t Addr, const void *Decoder) { 1886 unsigned Val = (uint8_t)Imm; 1887 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1888 if (ElementWidth == 8 && Shift) 1889 return Fail; 1890 Inst.addOperand(MCOperand::createImm(Val)); 1891 Inst.addOperand(MCOperand::createImm(Shift)); 1892 return Success; 1893 } 1894 1895 // Decode uimm4 ranged from 1-16. 1896 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1897 uint64_t Addr, const void *Decoder) { 1898 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1899 return Success; 1900 } 1901