1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm-c/Disassembler.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include <algorithm> 28 #include <memory> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "aarch64-disassembler" 33 34 // Pull DecodeStatus and its enum values into the global namespace. 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 // Forward declare these because the autogenerated code will reference them. 38 // Definitions are further down. 39 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 40 unsigned RegNo, uint64_t Address, 41 const void *Decoder); 42 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 43 unsigned RegNo, 44 uint64_t Address, 45 const void *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const void *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const void *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const void *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const void *Decoder); 58 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 59 uint64_t Address, 60 const void *Decoder); 61 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 62 uint64_t Address, 63 const void *Decoder); 64 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 65 unsigned RegNo, uint64_t Address, 66 const void *Decoder); 67 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 68 uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 71 unsigned RegNo, uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decode); 94 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decode); 97 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decode); 100 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decode); 103 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decode); 106 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decode); 109 110 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 111 uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 114 uint64_t Address, 115 const void *Decoder); 116 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 123 uint64_t Address, const void *Decoder); 124 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 134 uint64_t Address, 135 const void *Decoder); 136 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 137 uint64_t Address, 138 const void *Decoder); 139 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 140 uint64_t Address, 141 const void *Decoder); 142 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 143 uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 152 uint64_t Address, 153 const void *Decoder); 154 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 162 uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 165 uint64_t Address, const void *Decoder); 166 167 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 168 uint64_t Address, 169 const void *Decoder); 170 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, const void *Decoder); 172 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 173 uint64_t Addr, 174 const void *Decoder); 175 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 176 uint64_t Addr, const void *Decoder); 177 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, 179 const void *Decoder); 180 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 181 uint64_t Addr, const void *Decoder); 182 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 183 uint64_t Addr, 184 const void *Decoder); 185 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 186 uint64_t Addr, const void *Decoder); 187 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 188 uint64_t Addr, const void *Decoder); 189 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 190 uint64_t Addr, const void *Decoder); 191 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, const void *Decoder); 193 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 194 uint64_t Addr, const void *Decoder); 195 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Addr, 198 const void *Decoder); 199 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 200 unsigned RegNo, 201 uint64_t Addr, 202 const void *Decoder); 203 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 204 uint32_t insn, 205 uint64_t Address, 206 const void *Decoder); 207 template<int Bits> 208 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 209 uint64_t Address, const void *Decoder); 210 template <int ElementWidth> 211 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 212 uint64_t Addr, const void *Decoder); 213 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 214 uint64_t Addr, const void *Decoder); 215 216 static bool Check(DecodeStatus &Out, DecodeStatus In) { 217 switch (In) { 218 case MCDisassembler::Success: 219 // Out stays the same. 220 return true; 221 case MCDisassembler::SoftFail: 222 Out = In; 223 return true; 224 case MCDisassembler::Fail: 225 Out = In; 226 return false; 227 } 228 llvm_unreachable("Invalid DecodeStatus!"); 229 } 230 231 #include "AArch64GenDisassemblerTables.inc" 232 #include "AArch64GenInstrInfo.inc" 233 234 #define Success MCDisassembler::Success 235 #define Fail MCDisassembler::Fail 236 #define SoftFail MCDisassembler::SoftFail 237 238 static MCDisassembler *createAArch64Disassembler(const Target &T, 239 const MCSubtargetInfo &STI, 240 MCContext &Ctx) { 241 return new AArch64Disassembler(STI, Ctx); 242 } 243 244 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 245 ArrayRef<uint8_t> Bytes, 246 uint64_t Address, 247 raw_ostream &OS, 248 raw_ostream &CS) const { 249 CommentStream = &CS; 250 251 Size = 0; 252 // We want to read exactly 4 bytes of data. 253 if (Bytes.size() < 4) 254 return Fail; 255 Size = 4; 256 257 // Encoded as a small-endian 32-bit word in the stream. 258 uint32_t Insn = 259 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 260 261 // Calling the auto-generated decoder function. 262 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 263 } 264 265 static MCSymbolizer * 266 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 267 LLVMSymbolLookupCallback SymbolLookUp, 268 void *DisInfo, MCContext *Ctx, 269 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 270 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 271 SymbolLookUp, DisInfo); 272 } 273 274 extern "C" void LLVMInitializeAArch64Disassembler() { 275 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 276 createAArch64Disassembler); 277 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 278 createAArch64Disassembler); 279 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 280 createAArch64ExternalSymbolizer); 281 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 282 createAArch64ExternalSymbolizer); 283 284 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 285 createAArch64Disassembler); 286 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 287 createAArch64ExternalSymbolizer); 288 } 289 290 static const unsigned FPR128DecoderTable[] = { 291 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 292 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 293 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 294 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 295 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 296 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 297 AArch64::Q30, AArch64::Q31 298 }; 299 300 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 301 uint64_t Addr, 302 const void *Decoder) { 303 if (RegNo > 31) 304 return Fail; 305 306 unsigned Register = FPR128DecoderTable[RegNo]; 307 Inst.addOperand(MCOperand::createReg(Register)); 308 return Success; 309 } 310 311 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 312 uint64_t Addr, 313 const void *Decoder) { 314 if (RegNo > 15) 315 return Fail; 316 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 317 } 318 319 static const unsigned FPR64DecoderTable[] = { 320 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 321 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 322 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 323 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 324 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 325 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 326 AArch64::D30, AArch64::D31 327 }; 328 329 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 330 uint64_t Addr, 331 const void *Decoder) { 332 if (RegNo > 31) 333 return Fail; 334 335 unsigned Register = FPR64DecoderTable[RegNo]; 336 Inst.addOperand(MCOperand::createReg(Register)); 337 return Success; 338 } 339 340 static const unsigned FPR32DecoderTable[] = { 341 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 342 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 343 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 344 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 345 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 346 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 347 AArch64::S30, AArch64::S31 348 }; 349 350 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 351 uint64_t Addr, 352 const void *Decoder) { 353 if (RegNo > 31) 354 return Fail; 355 356 unsigned Register = FPR32DecoderTable[RegNo]; 357 Inst.addOperand(MCOperand::createReg(Register)); 358 return Success; 359 } 360 361 static const unsigned FPR16DecoderTable[] = { 362 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 363 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 364 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 365 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 366 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 367 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 368 AArch64::H30, AArch64::H31 369 }; 370 371 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 372 uint64_t Addr, 373 const void *Decoder) { 374 if (RegNo > 31) 375 return Fail; 376 377 unsigned Register = FPR16DecoderTable[RegNo]; 378 Inst.addOperand(MCOperand::createReg(Register)); 379 return Success; 380 } 381 382 static const unsigned FPR8DecoderTable[] = { 383 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 384 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 385 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 386 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 387 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 388 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 389 AArch64::B30, AArch64::B31 390 }; 391 392 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 393 uint64_t Addr, 394 const void *Decoder) { 395 if (RegNo > 31) 396 return Fail; 397 398 unsigned Register = FPR8DecoderTable[RegNo]; 399 Inst.addOperand(MCOperand::createReg(Register)); 400 return Success; 401 } 402 403 static const unsigned GPR64DecoderTable[] = { 404 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 405 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 406 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 407 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 408 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 409 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 410 AArch64::LR, AArch64::XZR 411 }; 412 413 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 414 uint64_t Addr, 415 const void *Decoder) { 416 if (RegNo > 30) 417 return Fail; 418 419 unsigned Register = GPR64DecoderTable[RegNo]; 420 Inst.addOperand(MCOperand::createReg(Register)); 421 return Success; 422 } 423 424 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 425 uint64_t Addr, 426 const void *Decoder) { 427 if (RegNo > 31) 428 return Fail; 429 430 unsigned Register = GPR64DecoderTable[RegNo]; 431 Inst.addOperand(MCOperand::createReg(Register)); 432 return Success; 433 } 434 435 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 436 uint64_t Addr, 437 const void *Decoder) { 438 if (RegNo > 31) 439 return Fail; 440 unsigned Register = GPR64DecoderTable[RegNo]; 441 if (Register == AArch64::XZR) 442 Register = AArch64::SP; 443 Inst.addOperand(MCOperand::createReg(Register)); 444 return Success; 445 } 446 447 static const unsigned GPR32DecoderTable[] = { 448 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 449 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 450 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 451 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 452 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 453 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 454 AArch64::W30, AArch64::WZR 455 }; 456 457 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 458 uint64_t Addr, 459 const void *Decoder) { 460 if (RegNo > 31) 461 return Fail; 462 463 unsigned Register = GPR32DecoderTable[RegNo]; 464 Inst.addOperand(MCOperand::createReg(Register)); 465 return Success; 466 } 467 468 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 469 uint64_t Addr, 470 const void *Decoder) { 471 if (RegNo > 31) 472 return Fail; 473 474 unsigned Register = GPR32DecoderTable[RegNo]; 475 if (Register == AArch64::WZR) 476 Register = AArch64::WSP; 477 Inst.addOperand(MCOperand::createReg(Register)); 478 return Success; 479 } 480 static const unsigned ZPRDecoderTable[] = { 481 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 482 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 483 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 484 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 485 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 486 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 487 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 488 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 489 }; 490 491 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 492 uint64_t Address, 493 const void* Decoder) { 494 if (RegNo > 31) 495 return Fail; 496 497 unsigned Register = ZPRDecoderTable[RegNo]; 498 Inst.addOperand(MCOperand::createReg(Register)); 499 return Success; 500 } 501 502 static const unsigned ZZDecoderTable[] = { 503 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 504 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 505 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 506 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 507 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 508 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 509 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 510 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 511 }; 512 513 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 514 uint64_t Address, 515 const void* Decoder) { 516 if (RegNo > 31) 517 return Fail; 518 unsigned Register = ZZDecoderTable[RegNo]; 519 Inst.addOperand(MCOperand::createReg(Register)); 520 return Success; 521 } 522 523 static const unsigned ZZZDecoderTable[] = { 524 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 525 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 526 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 527 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 528 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 529 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 530 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 531 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 532 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 533 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 534 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 535 }; 536 537 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 538 uint64_t Address, 539 const void* Decoder) { 540 if (RegNo > 31) 541 return Fail; 542 unsigned Register = ZZZDecoderTable[RegNo]; 543 Inst.addOperand(MCOperand::createReg(Register)); 544 return Success; 545 } 546 547 static const unsigned ZZZZDecoderTable[] = { 548 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 549 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 550 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 551 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 552 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 553 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 554 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 555 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 556 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 557 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 558 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 559 }; 560 561 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 562 uint64_t Address, 563 const void* Decoder) { 564 if (RegNo > 31) 565 return Fail; 566 unsigned Register = ZZZZDecoderTable[RegNo]; 567 Inst.addOperand(MCOperand::createReg(Register)); 568 return Success; 569 } 570 571 static const unsigned PPRDecoderTable[] = { 572 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 573 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 574 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 575 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 576 }; 577 578 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 579 uint64_t Addr, const void *Decoder) { 580 if (RegNo > 15) 581 return Fail; 582 583 unsigned Register = PPRDecoderTable[RegNo]; 584 Inst.addOperand(MCOperand::createReg(Register)); 585 return Success; 586 } 587 588 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 589 uint64_t Addr, 590 const void* Decoder) { 591 if (RegNo > 7) 592 return Fail; 593 594 // Just reuse the PPR decode table 595 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 596 } 597 598 static const unsigned VectorDecoderTable[] = { 599 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 600 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 601 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 602 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 603 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 604 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 605 AArch64::Q30, AArch64::Q31 606 }; 607 608 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 609 uint64_t Addr, 610 const void *Decoder) { 611 if (RegNo > 31) 612 return Fail; 613 614 unsigned Register = VectorDecoderTable[RegNo]; 615 Inst.addOperand(MCOperand::createReg(Register)); 616 return Success; 617 } 618 619 static const unsigned QQDecoderTable[] = { 620 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 621 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 622 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 623 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 624 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 625 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 626 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 627 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 628 }; 629 630 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 631 uint64_t Addr, const void *Decoder) { 632 if (RegNo > 31) 633 return Fail; 634 unsigned Register = QQDecoderTable[RegNo]; 635 Inst.addOperand(MCOperand::createReg(Register)); 636 return Success; 637 } 638 639 static const unsigned QQQDecoderTable[] = { 640 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 641 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 642 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 643 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 644 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 645 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 646 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 647 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 648 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 649 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 650 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 651 }; 652 653 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 654 uint64_t Addr, const void *Decoder) { 655 if (RegNo > 31) 656 return Fail; 657 unsigned Register = QQQDecoderTable[RegNo]; 658 Inst.addOperand(MCOperand::createReg(Register)); 659 return Success; 660 } 661 662 static const unsigned QQQQDecoderTable[] = { 663 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 664 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 665 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 666 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 667 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 668 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 669 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 670 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 671 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 672 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 673 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 674 }; 675 676 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 677 uint64_t Addr, 678 const void *Decoder) { 679 if (RegNo > 31) 680 return Fail; 681 unsigned Register = QQQQDecoderTable[RegNo]; 682 Inst.addOperand(MCOperand::createReg(Register)); 683 return Success; 684 } 685 686 static const unsigned DDDecoderTable[] = { 687 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 688 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 689 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 690 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 691 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 692 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 693 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 694 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 695 }; 696 697 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 698 uint64_t Addr, const void *Decoder) { 699 if (RegNo > 31) 700 return Fail; 701 unsigned Register = DDDecoderTable[RegNo]; 702 Inst.addOperand(MCOperand::createReg(Register)); 703 return Success; 704 } 705 706 static const unsigned DDDDecoderTable[] = { 707 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 708 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 709 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 710 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 711 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 712 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 713 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 714 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 715 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 716 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 717 AArch64::D30_D31_D0, AArch64::D31_D0_D1 718 }; 719 720 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 721 uint64_t Addr, const void *Decoder) { 722 if (RegNo > 31) 723 return Fail; 724 unsigned Register = DDDDecoderTable[RegNo]; 725 Inst.addOperand(MCOperand::createReg(Register)); 726 return Success; 727 } 728 729 static const unsigned DDDDDecoderTable[] = { 730 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 731 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 732 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 733 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 734 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 735 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 736 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 737 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 738 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 739 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 740 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 741 }; 742 743 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 744 uint64_t Addr, 745 const void *Decoder) { 746 if (RegNo > 31) 747 return Fail; 748 unsigned Register = DDDDDecoderTable[RegNo]; 749 Inst.addOperand(MCOperand::createReg(Register)); 750 return Success; 751 } 752 753 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 754 uint64_t Addr, 755 const void *Decoder) { 756 // scale{5} is asserted as 1 in tblgen. 757 Imm |= 0x20; 758 Inst.addOperand(MCOperand::createImm(64 - Imm)); 759 return Success; 760 } 761 762 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 763 uint64_t Addr, 764 const void *Decoder) { 765 Inst.addOperand(MCOperand::createImm(64 - Imm)); 766 return Success; 767 } 768 769 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 770 uint64_t Addr, const void *Decoder) { 771 int64_t ImmVal = Imm; 772 const AArch64Disassembler *Dis = 773 static_cast<const AArch64Disassembler *>(Decoder); 774 775 // Sign-extend 19-bit immediate. 776 if (ImmVal & (1 << (19 - 1))) 777 ImmVal |= ~((1LL << 19) - 1); 778 779 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 780 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 781 Inst.addOperand(MCOperand::createImm(ImmVal)); 782 return Success; 783 } 784 785 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 786 uint64_t Address, const void *Decoder) { 787 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 788 Inst.addOperand(MCOperand::createImm(Imm & 1)); 789 return Success; 790 } 791 792 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 793 uint64_t Address, 794 const void *Decoder) { 795 Inst.addOperand(MCOperand::createImm(Imm)); 796 797 // Every system register in the encoding space is valid with the syntax 798 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 799 return Success; 800 } 801 802 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 803 uint64_t Address, 804 const void *Decoder) { 805 Inst.addOperand(MCOperand::createImm(Imm)); 806 807 return Success; 808 } 809 810 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 811 uint64_t Address, 812 const void *Decoder) { 813 // This decoder exists to add the dummy Lane operand to the MCInst, which must 814 // be 1 in assembly but has no other real manifestation. 815 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 816 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 817 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 818 819 if (IsToVec) { 820 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 821 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 822 } else { 823 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 824 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 825 } 826 827 // Add the lane 828 Inst.addOperand(MCOperand::createImm(1)); 829 830 return Success; 831 } 832 833 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 834 unsigned Add) { 835 Inst.addOperand(MCOperand::createImm(Add - Imm)); 836 return Success; 837 } 838 839 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 840 unsigned Add) { 841 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 842 return Success; 843 } 844 845 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 846 uint64_t Addr, const void *Decoder) { 847 return DecodeVecShiftRImm(Inst, Imm, 64); 848 } 849 850 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 851 uint64_t Addr, 852 const void *Decoder) { 853 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 854 } 855 856 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 857 uint64_t Addr, const void *Decoder) { 858 return DecodeVecShiftRImm(Inst, Imm, 32); 859 } 860 861 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 862 uint64_t Addr, 863 const void *Decoder) { 864 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 865 } 866 867 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 868 uint64_t Addr, const void *Decoder) { 869 return DecodeVecShiftRImm(Inst, Imm, 16); 870 } 871 872 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 873 uint64_t Addr, 874 const void *Decoder) { 875 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 876 } 877 878 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 879 uint64_t Addr, const void *Decoder) { 880 return DecodeVecShiftRImm(Inst, Imm, 8); 881 } 882 883 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 884 uint64_t Addr, const void *Decoder) { 885 return DecodeVecShiftLImm(Inst, Imm, 64); 886 } 887 888 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 889 uint64_t Addr, const void *Decoder) { 890 return DecodeVecShiftLImm(Inst, Imm, 32); 891 } 892 893 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 894 uint64_t Addr, const void *Decoder) { 895 return DecodeVecShiftLImm(Inst, Imm, 16); 896 } 897 898 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 899 uint64_t Addr, const void *Decoder) { 900 return DecodeVecShiftLImm(Inst, Imm, 8); 901 } 902 903 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 904 uint64_t Addr, 905 const void *Decoder) { 906 unsigned Rd = fieldFromInstruction(insn, 0, 5); 907 unsigned Rn = fieldFromInstruction(insn, 5, 5); 908 unsigned Rm = fieldFromInstruction(insn, 16, 5); 909 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 910 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 911 unsigned shift = (shiftHi << 6) | shiftLo; 912 switch (Inst.getOpcode()) { 913 default: 914 return Fail; 915 case AArch64::ADDWrs: 916 case AArch64::ADDSWrs: 917 case AArch64::SUBWrs: 918 case AArch64::SUBSWrs: 919 // if shift == '11' then ReservedValue() 920 if (shiftHi == 0x3) 921 return Fail; 922 LLVM_FALLTHROUGH; 923 case AArch64::ANDWrs: 924 case AArch64::ANDSWrs: 925 case AArch64::BICWrs: 926 case AArch64::BICSWrs: 927 case AArch64::ORRWrs: 928 case AArch64::ORNWrs: 929 case AArch64::EORWrs: 930 case AArch64::EONWrs: { 931 // if sf == '0' and imm6<5> == '1' then ReservedValue() 932 if (shiftLo >> 5 == 1) 933 return Fail; 934 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 935 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 936 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 937 break; 938 } 939 case AArch64::ADDXrs: 940 case AArch64::ADDSXrs: 941 case AArch64::SUBXrs: 942 case AArch64::SUBSXrs: 943 // if shift == '11' then ReservedValue() 944 if (shiftHi == 0x3) 945 return Fail; 946 LLVM_FALLTHROUGH; 947 case AArch64::ANDXrs: 948 case AArch64::ANDSXrs: 949 case AArch64::BICXrs: 950 case AArch64::BICSXrs: 951 case AArch64::ORRXrs: 952 case AArch64::ORNXrs: 953 case AArch64::EORXrs: 954 case AArch64::EONXrs: 955 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 956 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 957 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 958 break; 959 } 960 961 Inst.addOperand(MCOperand::createImm(shift)); 962 return Success; 963 } 964 965 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 966 uint64_t Addr, 967 const void *Decoder) { 968 unsigned Rd = fieldFromInstruction(insn, 0, 5); 969 unsigned imm = fieldFromInstruction(insn, 5, 16); 970 unsigned shift = fieldFromInstruction(insn, 21, 2); 971 shift <<= 4; 972 switch (Inst.getOpcode()) { 973 default: 974 return Fail; 975 case AArch64::MOVZWi: 976 case AArch64::MOVNWi: 977 case AArch64::MOVKWi: 978 if (shift & (1U << 5)) 979 return Fail; 980 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 981 break; 982 case AArch64::MOVZXi: 983 case AArch64::MOVNXi: 984 case AArch64::MOVKXi: 985 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 986 break; 987 } 988 989 if (Inst.getOpcode() == AArch64::MOVKWi || 990 Inst.getOpcode() == AArch64::MOVKXi) 991 Inst.addOperand(Inst.getOperand(0)); 992 993 Inst.addOperand(MCOperand::createImm(imm)); 994 Inst.addOperand(MCOperand::createImm(shift)); 995 return Success; 996 } 997 998 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 999 uint64_t Addr, 1000 const void *Decoder) { 1001 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1002 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1003 unsigned offset = fieldFromInstruction(insn, 10, 12); 1004 const AArch64Disassembler *Dis = 1005 static_cast<const AArch64Disassembler *>(Decoder); 1006 1007 switch (Inst.getOpcode()) { 1008 default: 1009 return Fail; 1010 case AArch64::PRFMui: 1011 // Rt is an immediate in prefetch. 1012 Inst.addOperand(MCOperand::createImm(Rt)); 1013 break; 1014 case AArch64::STRBBui: 1015 case AArch64::LDRBBui: 1016 case AArch64::LDRSBWui: 1017 case AArch64::STRHHui: 1018 case AArch64::LDRHHui: 1019 case AArch64::LDRSHWui: 1020 case AArch64::STRWui: 1021 case AArch64::LDRWui: 1022 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1023 break; 1024 case AArch64::LDRSBXui: 1025 case AArch64::LDRSHXui: 1026 case AArch64::LDRSWui: 1027 case AArch64::STRXui: 1028 case AArch64::LDRXui: 1029 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1030 break; 1031 case AArch64::LDRQui: 1032 case AArch64::STRQui: 1033 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1034 break; 1035 case AArch64::LDRDui: 1036 case AArch64::STRDui: 1037 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1038 break; 1039 case AArch64::LDRSui: 1040 case AArch64::STRSui: 1041 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1042 break; 1043 case AArch64::LDRHui: 1044 case AArch64::STRHui: 1045 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1046 break; 1047 case AArch64::LDRBui: 1048 case AArch64::STRBui: 1049 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1050 break; 1051 } 1052 1053 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1054 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1055 Inst.addOperand(MCOperand::createImm(offset)); 1056 return Success; 1057 } 1058 1059 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1060 uint64_t Addr, 1061 const void *Decoder) { 1062 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1063 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1064 int64_t offset = fieldFromInstruction(insn, 12, 9); 1065 1066 // offset is a 9-bit signed immediate, so sign extend it to 1067 // fill the unsigned. 1068 if (offset & (1 << (9 - 1))) 1069 offset |= ~((1LL << 9) - 1); 1070 1071 // First operand is always the writeback to the address register, if needed. 1072 switch (Inst.getOpcode()) { 1073 default: 1074 break; 1075 case AArch64::LDRSBWpre: 1076 case AArch64::LDRSHWpre: 1077 case AArch64::STRBBpre: 1078 case AArch64::LDRBBpre: 1079 case AArch64::STRHHpre: 1080 case AArch64::LDRHHpre: 1081 case AArch64::STRWpre: 1082 case AArch64::LDRWpre: 1083 case AArch64::LDRSBWpost: 1084 case AArch64::LDRSHWpost: 1085 case AArch64::STRBBpost: 1086 case AArch64::LDRBBpost: 1087 case AArch64::STRHHpost: 1088 case AArch64::LDRHHpost: 1089 case AArch64::STRWpost: 1090 case AArch64::LDRWpost: 1091 case AArch64::LDRSBXpre: 1092 case AArch64::LDRSHXpre: 1093 case AArch64::STRXpre: 1094 case AArch64::LDRSWpre: 1095 case AArch64::LDRXpre: 1096 case AArch64::LDRSBXpost: 1097 case AArch64::LDRSHXpost: 1098 case AArch64::STRXpost: 1099 case AArch64::LDRSWpost: 1100 case AArch64::LDRXpost: 1101 case AArch64::LDRQpre: 1102 case AArch64::STRQpre: 1103 case AArch64::LDRQpost: 1104 case AArch64::STRQpost: 1105 case AArch64::LDRDpre: 1106 case AArch64::STRDpre: 1107 case AArch64::LDRDpost: 1108 case AArch64::STRDpost: 1109 case AArch64::LDRSpre: 1110 case AArch64::STRSpre: 1111 case AArch64::LDRSpost: 1112 case AArch64::STRSpost: 1113 case AArch64::LDRHpre: 1114 case AArch64::STRHpre: 1115 case AArch64::LDRHpost: 1116 case AArch64::STRHpost: 1117 case AArch64::LDRBpre: 1118 case AArch64::STRBpre: 1119 case AArch64::LDRBpost: 1120 case AArch64::STRBpost: 1121 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1122 break; 1123 } 1124 1125 switch (Inst.getOpcode()) { 1126 default: 1127 return Fail; 1128 case AArch64::PRFUMi: 1129 // Rt is an immediate in prefetch. 1130 Inst.addOperand(MCOperand::createImm(Rt)); 1131 break; 1132 case AArch64::STURBBi: 1133 case AArch64::LDURBBi: 1134 case AArch64::LDURSBWi: 1135 case AArch64::STURHHi: 1136 case AArch64::LDURHHi: 1137 case AArch64::LDURSHWi: 1138 case AArch64::STURWi: 1139 case AArch64::LDURWi: 1140 case AArch64::LDTRSBWi: 1141 case AArch64::LDTRSHWi: 1142 case AArch64::STTRWi: 1143 case AArch64::LDTRWi: 1144 case AArch64::STTRHi: 1145 case AArch64::LDTRHi: 1146 case AArch64::LDTRBi: 1147 case AArch64::STTRBi: 1148 case AArch64::LDRSBWpre: 1149 case AArch64::LDRSHWpre: 1150 case AArch64::STRBBpre: 1151 case AArch64::LDRBBpre: 1152 case AArch64::STRHHpre: 1153 case AArch64::LDRHHpre: 1154 case AArch64::STRWpre: 1155 case AArch64::LDRWpre: 1156 case AArch64::LDRSBWpost: 1157 case AArch64::LDRSHWpost: 1158 case AArch64::STRBBpost: 1159 case AArch64::LDRBBpost: 1160 case AArch64::STRHHpost: 1161 case AArch64::LDRHHpost: 1162 case AArch64::STRWpost: 1163 case AArch64::LDRWpost: 1164 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1165 break; 1166 case AArch64::LDURSBXi: 1167 case AArch64::LDURSHXi: 1168 case AArch64::LDURSWi: 1169 case AArch64::STURXi: 1170 case AArch64::LDURXi: 1171 case AArch64::LDTRSBXi: 1172 case AArch64::LDTRSHXi: 1173 case AArch64::LDTRSWi: 1174 case AArch64::STTRXi: 1175 case AArch64::LDTRXi: 1176 case AArch64::LDRSBXpre: 1177 case AArch64::LDRSHXpre: 1178 case AArch64::STRXpre: 1179 case AArch64::LDRSWpre: 1180 case AArch64::LDRXpre: 1181 case AArch64::LDRSBXpost: 1182 case AArch64::LDRSHXpost: 1183 case AArch64::STRXpost: 1184 case AArch64::LDRSWpost: 1185 case AArch64::LDRXpost: 1186 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1187 break; 1188 case AArch64::LDURQi: 1189 case AArch64::STURQi: 1190 case AArch64::LDRQpre: 1191 case AArch64::STRQpre: 1192 case AArch64::LDRQpost: 1193 case AArch64::STRQpost: 1194 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1195 break; 1196 case AArch64::LDURDi: 1197 case AArch64::STURDi: 1198 case AArch64::LDRDpre: 1199 case AArch64::STRDpre: 1200 case AArch64::LDRDpost: 1201 case AArch64::STRDpost: 1202 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1203 break; 1204 case AArch64::LDURSi: 1205 case AArch64::STURSi: 1206 case AArch64::LDRSpre: 1207 case AArch64::STRSpre: 1208 case AArch64::LDRSpost: 1209 case AArch64::STRSpost: 1210 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1211 break; 1212 case AArch64::LDURHi: 1213 case AArch64::STURHi: 1214 case AArch64::LDRHpre: 1215 case AArch64::STRHpre: 1216 case AArch64::LDRHpost: 1217 case AArch64::STRHpost: 1218 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1219 break; 1220 case AArch64::LDURBi: 1221 case AArch64::STURBi: 1222 case AArch64::LDRBpre: 1223 case AArch64::STRBpre: 1224 case AArch64::LDRBpost: 1225 case AArch64::STRBpost: 1226 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1227 break; 1228 } 1229 1230 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1231 Inst.addOperand(MCOperand::createImm(offset)); 1232 1233 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1234 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1235 bool IsFP = fieldFromInstruction(insn, 26, 1); 1236 1237 // Cannot write back to a transfer register (but xzr != sp). 1238 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1239 return SoftFail; 1240 1241 return Success; 1242 } 1243 1244 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1245 uint64_t Addr, 1246 const void *Decoder) { 1247 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1248 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1249 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1250 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1251 1252 unsigned Opcode = Inst.getOpcode(); 1253 switch (Opcode) { 1254 default: 1255 return Fail; 1256 case AArch64::STLXRW: 1257 case AArch64::STLXRB: 1258 case AArch64::STLXRH: 1259 case AArch64::STXRW: 1260 case AArch64::STXRB: 1261 case AArch64::STXRH: 1262 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1263 LLVM_FALLTHROUGH; 1264 case AArch64::LDARW: 1265 case AArch64::LDARB: 1266 case AArch64::LDARH: 1267 case AArch64::LDAXRW: 1268 case AArch64::LDAXRB: 1269 case AArch64::LDAXRH: 1270 case AArch64::LDXRW: 1271 case AArch64::LDXRB: 1272 case AArch64::LDXRH: 1273 case AArch64::STLRW: 1274 case AArch64::STLRB: 1275 case AArch64::STLRH: 1276 case AArch64::STLLRW: 1277 case AArch64::STLLRB: 1278 case AArch64::STLLRH: 1279 case AArch64::LDLARW: 1280 case AArch64::LDLARB: 1281 case AArch64::LDLARH: 1282 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1283 break; 1284 case AArch64::STLXRX: 1285 case AArch64::STXRX: 1286 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1287 LLVM_FALLTHROUGH; 1288 case AArch64::LDARX: 1289 case AArch64::LDAXRX: 1290 case AArch64::LDXRX: 1291 case AArch64::STLRX: 1292 case AArch64::LDLARX: 1293 case AArch64::STLLRX: 1294 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1295 break; 1296 case AArch64::STLXPW: 1297 case AArch64::STXPW: 1298 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1299 LLVM_FALLTHROUGH; 1300 case AArch64::LDAXPW: 1301 case AArch64::LDXPW: 1302 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1303 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1304 break; 1305 case AArch64::STLXPX: 1306 case AArch64::STXPX: 1307 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1308 LLVM_FALLTHROUGH; 1309 case AArch64::LDAXPX: 1310 case AArch64::LDXPX: 1311 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1312 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1313 break; 1314 } 1315 1316 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1317 1318 // You shouldn't load to the same register twice in an instruction... 1319 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1320 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1321 Rt == Rt2) 1322 return SoftFail; 1323 1324 return Success; 1325 } 1326 1327 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1328 uint64_t Addr, 1329 const void *Decoder) { 1330 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1331 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1332 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1333 int64_t offset = fieldFromInstruction(insn, 15, 7); 1334 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1335 1336 // offset is a 7-bit signed immediate, so sign extend it to 1337 // fill the unsigned. 1338 if (offset & (1 << (7 - 1))) 1339 offset |= ~((1LL << 7) - 1); 1340 1341 unsigned Opcode = Inst.getOpcode(); 1342 bool NeedsDisjointWritebackTransfer = false; 1343 1344 // First operand is always writeback of base register. 1345 switch (Opcode) { 1346 default: 1347 break; 1348 case AArch64::LDPXpost: 1349 case AArch64::STPXpost: 1350 case AArch64::LDPSWpost: 1351 case AArch64::LDPXpre: 1352 case AArch64::STPXpre: 1353 case AArch64::LDPSWpre: 1354 case AArch64::LDPWpost: 1355 case AArch64::STPWpost: 1356 case AArch64::LDPWpre: 1357 case AArch64::STPWpre: 1358 case AArch64::LDPQpost: 1359 case AArch64::STPQpost: 1360 case AArch64::LDPQpre: 1361 case AArch64::STPQpre: 1362 case AArch64::LDPDpost: 1363 case AArch64::STPDpost: 1364 case AArch64::LDPDpre: 1365 case AArch64::STPDpre: 1366 case AArch64::LDPSpost: 1367 case AArch64::STPSpost: 1368 case AArch64::LDPSpre: 1369 case AArch64::STPSpre: 1370 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1371 break; 1372 } 1373 1374 switch (Opcode) { 1375 default: 1376 return Fail; 1377 case AArch64::LDPXpost: 1378 case AArch64::STPXpost: 1379 case AArch64::LDPSWpost: 1380 case AArch64::LDPXpre: 1381 case AArch64::STPXpre: 1382 case AArch64::LDPSWpre: 1383 NeedsDisjointWritebackTransfer = true; 1384 LLVM_FALLTHROUGH; 1385 case AArch64::LDNPXi: 1386 case AArch64::STNPXi: 1387 case AArch64::LDPXi: 1388 case AArch64::STPXi: 1389 case AArch64::LDPSWi: 1390 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1391 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1392 break; 1393 case AArch64::LDPWpost: 1394 case AArch64::STPWpost: 1395 case AArch64::LDPWpre: 1396 case AArch64::STPWpre: 1397 NeedsDisjointWritebackTransfer = true; 1398 LLVM_FALLTHROUGH; 1399 case AArch64::LDNPWi: 1400 case AArch64::STNPWi: 1401 case AArch64::LDPWi: 1402 case AArch64::STPWi: 1403 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1404 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1405 break; 1406 case AArch64::LDNPQi: 1407 case AArch64::STNPQi: 1408 case AArch64::LDPQpost: 1409 case AArch64::STPQpost: 1410 case AArch64::LDPQi: 1411 case AArch64::STPQi: 1412 case AArch64::LDPQpre: 1413 case AArch64::STPQpre: 1414 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1415 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1416 break; 1417 case AArch64::LDNPDi: 1418 case AArch64::STNPDi: 1419 case AArch64::LDPDpost: 1420 case AArch64::STPDpost: 1421 case AArch64::LDPDi: 1422 case AArch64::STPDi: 1423 case AArch64::LDPDpre: 1424 case AArch64::STPDpre: 1425 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1426 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1427 break; 1428 case AArch64::LDNPSi: 1429 case AArch64::STNPSi: 1430 case AArch64::LDPSpost: 1431 case AArch64::STPSpost: 1432 case AArch64::LDPSi: 1433 case AArch64::STPSi: 1434 case AArch64::LDPSpre: 1435 case AArch64::STPSpre: 1436 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1437 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1438 break; 1439 } 1440 1441 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1442 Inst.addOperand(MCOperand::createImm(offset)); 1443 1444 // You shouldn't load to the same register twice in an instruction... 1445 if (IsLoad && Rt == Rt2) 1446 return SoftFail; 1447 1448 // ... or do any operation that writes-back to a transfer register. But note 1449 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1450 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1451 return SoftFail; 1452 1453 return Success; 1454 } 1455 1456 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1457 uint64_t Addr, 1458 const void *Decoder) { 1459 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1460 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1461 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1462 unsigned extend = fieldFromInstruction(insn, 10, 6); 1463 1464 unsigned shift = extend & 0x7; 1465 if (shift > 4) 1466 return Fail; 1467 1468 switch (Inst.getOpcode()) { 1469 default: 1470 return Fail; 1471 case AArch64::ADDWrx: 1472 case AArch64::SUBWrx: 1473 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1474 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1475 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1476 break; 1477 case AArch64::ADDSWrx: 1478 case AArch64::SUBSWrx: 1479 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1480 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1481 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1482 break; 1483 case AArch64::ADDXrx: 1484 case AArch64::SUBXrx: 1485 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1486 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1487 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1488 break; 1489 case AArch64::ADDSXrx: 1490 case AArch64::SUBSXrx: 1491 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1492 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1493 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1494 break; 1495 case AArch64::ADDXrx64: 1496 case AArch64::SUBXrx64: 1497 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1498 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1499 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1500 break; 1501 case AArch64::SUBSXrx64: 1502 case AArch64::ADDSXrx64: 1503 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1504 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1505 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1506 break; 1507 } 1508 1509 Inst.addOperand(MCOperand::createImm(extend)); 1510 return Success; 1511 } 1512 1513 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1514 uint64_t Addr, 1515 const void *Decoder) { 1516 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1517 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1518 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1519 unsigned imm; 1520 1521 if (Datasize) { 1522 if (Inst.getOpcode() == AArch64::ANDSXri) 1523 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1524 else 1525 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1526 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1527 imm = fieldFromInstruction(insn, 10, 13); 1528 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1529 return Fail; 1530 } else { 1531 if (Inst.getOpcode() == AArch64::ANDSWri) 1532 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1533 else 1534 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1535 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1536 imm = fieldFromInstruction(insn, 10, 12); 1537 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1538 return Fail; 1539 } 1540 Inst.addOperand(MCOperand::createImm(imm)); 1541 return Success; 1542 } 1543 1544 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1545 uint64_t Addr, 1546 const void *Decoder) { 1547 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1548 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1549 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1550 imm |= fieldFromInstruction(insn, 5, 5); 1551 1552 if (Inst.getOpcode() == AArch64::MOVID) 1553 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1554 else 1555 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1556 1557 Inst.addOperand(MCOperand::createImm(imm)); 1558 1559 switch (Inst.getOpcode()) { 1560 default: 1561 break; 1562 case AArch64::MOVIv4i16: 1563 case AArch64::MOVIv8i16: 1564 case AArch64::MVNIv4i16: 1565 case AArch64::MVNIv8i16: 1566 case AArch64::MOVIv2i32: 1567 case AArch64::MOVIv4i32: 1568 case AArch64::MVNIv2i32: 1569 case AArch64::MVNIv4i32: 1570 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1571 break; 1572 case AArch64::MOVIv2s_msl: 1573 case AArch64::MOVIv4s_msl: 1574 case AArch64::MVNIv2s_msl: 1575 case AArch64::MVNIv4s_msl: 1576 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1577 break; 1578 } 1579 1580 return Success; 1581 } 1582 1583 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1584 uint64_t Addr, 1585 const void *Decoder) { 1586 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1587 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1588 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1589 imm |= fieldFromInstruction(insn, 5, 5); 1590 1591 // Tied operands added twice. 1592 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1593 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1594 1595 Inst.addOperand(MCOperand::createImm(imm)); 1596 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1597 1598 return Success; 1599 } 1600 1601 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1602 uint64_t Addr, const void *Decoder) { 1603 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1604 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1605 imm |= fieldFromInstruction(insn, 29, 2); 1606 const AArch64Disassembler *Dis = 1607 static_cast<const AArch64Disassembler *>(Decoder); 1608 1609 // Sign-extend the 21-bit immediate. 1610 if (imm & (1 << (21 - 1))) 1611 imm |= ~((1LL << 21) - 1); 1612 1613 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1614 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1615 Inst.addOperand(MCOperand::createImm(imm)); 1616 1617 return Success; 1618 } 1619 1620 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1621 uint64_t Addr, const void *Decoder) { 1622 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1623 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1624 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1625 unsigned S = fieldFromInstruction(insn, 29, 1); 1626 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1627 1628 unsigned ShifterVal = (Imm >> 12) & 3; 1629 unsigned ImmVal = Imm & 0xFFF; 1630 const AArch64Disassembler *Dis = 1631 static_cast<const AArch64Disassembler *>(Decoder); 1632 1633 if (ShifterVal != 0 && ShifterVal != 1) 1634 return Fail; 1635 1636 if (Datasize) { 1637 if (Rd == 31 && !S) 1638 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1639 else 1640 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1641 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1642 } else { 1643 if (Rd == 31 && !S) 1644 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1645 else 1646 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1647 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1648 } 1649 1650 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1651 Inst.addOperand(MCOperand::createImm(ImmVal)); 1652 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1653 return Success; 1654 } 1655 1656 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1657 uint64_t Addr, 1658 const void *Decoder) { 1659 int64_t imm = fieldFromInstruction(insn, 0, 26); 1660 const AArch64Disassembler *Dis = 1661 static_cast<const AArch64Disassembler *>(Decoder); 1662 1663 // Sign-extend the 26-bit immediate. 1664 if (imm & (1 << (26 - 1))) 1665 imm |= ~((1LL << 26) - 1); 1666 1667 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1668 Inst.addOperand(MCOperand::createImm(imm)); 1669 1670 return Success; 1671 } 1672 1673 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1674 uint64_t Addr, 1675 const void *Decoder) { 1676 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1677 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1678 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1679 1680 uint64_t pstate_field = (op1 << 3) | op2; 1681 1682 if ((pstate_field == AArch64PState::PAN || 1683 pstate_field == AArch64PState::UAO) && crm > 1) 1684 return Fail; 1685 1686 Inst.addOperand(MCOperand::createImm(pstate_field)); 1687 Inst.addOperand(MCOperand::createImm(crm)); 1688 1689 const AArch64Disassembler *Dis = 1690 static_cast<const AArch64Disassembler *>(Decoder); 1691 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1692 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1693 return Success; 1694 return Fail; 1695 } 1696 1697 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1698 uint64_t Addr, const void *Decoder) { 1699 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1700 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1701 bit |= fieldFromInstruction(insn, 19, 5); 1702 int64_t dst = fieldFromInstruction(insn, 5, 14); 1703 const AArch64Disassembler *Dis = 1704 static_cast<const AArch64Disassembler *>(Decoder); 1705 1706 // Sign-extend 14-bit immediate. 1707 if (dst & (1 << (14 - 1))) 1708 dst |= ~((1LL << 14) - 1); 1709 1710 if (fieldFromInstruction(insn, 31, 1) == 0) 1711 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1712 else 1713 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1714 Inst.addOperand(MCOperand::createImm(bit)); 1715 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1716 Inst.addOperand(MCOperand::createImm(dst)); 1717 1718 return Success; 1719 } 1720 1721 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1722 unsigned RegClassID, 1723 unsigned RegNo, 1724 uint64_t Addr, 1725 const void *Decoder) { 1726 // Register number must be even (see CASP instruction) 1727 if (RegNo & 0x1) 1728 return Fail; 1729 1730 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1731 Inst.addOperand(MCOperand::createReg(Register)); 1732 return Success; 1733 } 1734 1735 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1736 unsigned RegNo, 1737 uint64_t Addr, 1738 const void *Decoder) { 1739 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1740 AArch64::WSeqPairsClassRegClassID, 1741 RegNo, Addr, Decoder); 1742 } 1743 1744 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1745 unsigned RegNo, 1746 uint64_t Addr, 1747 const void *Decoder) { 1748 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1749 AArch64::XSeqPairsClassRegClassID, 1750 RegNo, Addr, Decoder); 1751 } 1752 1753 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1754 uint32_t insn, 1755 uint64_t Addr, 1756 const void *Decoder) { 1757 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1758 unsigned imm = fieldFromInstruction(insn, 5, 13); 1759 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1760 return Fail; 1761 1762 // The same (tied) operand is added twice to the instruction. 1763 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1764 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1765 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1766 Inst.addOperand(MCOperand::createImm(imm)); 1767 return Success; 1768 } 1769 1770 template<int Bits> 1771 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1772 uint64_t Address, const void *Decoder) { 1773 if (Imm & ~((1LL << Bits) - 1)) 1774 return Fail; 1775 1776 // Imm is a signed immediate, so sign extend it. 1777 if (Imm & (1 << (Bits - 1))) 1778 Imm |= ~((1LL << Bits) - 1); 1779 1780 Inst.addOperand(MCOperand::createImm(Imm)); 1781 return Success; 1782 } 1783 1784 // Decode 8-bit signed/unsigned immediate for a given element width. 1785 template <int ElementWidth> 1786 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1787 uint64_t Addr, const void *Decoder) { 1788 unsigned Val = (uint8_t)Imm; 1789 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1790 if (ElementWidth == 8 && Shift) 1791 return Fail; 1792 Inst.addOperand(MCOperand::createImm(Val)); 1793 Inst.addOperand(MCOperand::createImm(Shift)); 1794 return Success; 1795 } 1796 1797 // Decode uimm4 ranged from 1-16. 1798 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1799 uint64_t Addr, const void *Decoder) { 1800 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1801 return Success; 1802 } 1803