1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 80 unsigned RegNo, uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 template <unsigned NumBitsForTile> 119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 129 uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 132 uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 143 uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 152 uint64_t Address, 153 const void *Decoder); 154 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 155 uint64_t Address, 156 const void *Decoder); 157 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 158 uint64_t Address, 159 const void *Decoder); 160 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 161 uint64_t Address, 162 const void *Decoder); 163 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 164 uint64_t Address, 165 const void *Decoder); 166 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 167 uint64_t Address, 168 const void *Decoder); 169 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 170 uint64_t Address, 171 const void *Decoder); 172 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 173 uint64_t Address, 174 const void *Decoder); 175 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 180 uint64_t Address, 181 const void *Decoder); 182 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 183 uint64_t Address, 184 const void *Decoder); 185 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 186 uint64_t Address, const void *Decoder); 187 188 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 189 uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, const void *Decoder); 193 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 194 uint64_t Addr, 195 const void *Decoder); 196 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, const void *Decoder); 198 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const void *Decoder); 201 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 202 uint64_t Addr, const void *Decoder); 203 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, 205 const void *Decoder); 206 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 207 uint64_t Addr, const void *Decoder); 208 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 209 uint64_t Addr, const void *Decoder); 210 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, const void *Decoder); 214 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, const void *Decoder); 216 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 217 unsigned RegNo, 218 uint64_t Addr, 219 const void *Decoder); 220 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Addr, 223 const void *Decoder); 224 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 225 uint32_t insn, 226 uint64_t Address, 227 const void *Decoder); 228 template<int Bits> 229 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 230 uint64_t Address, const void *Decoder); 231 template <int ElementWidth> 232 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 233 uint64_t Addr, const void *Decoder); 234 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 235 uint64_t Addr, const void *Decoder); 236 237 static bool Check(DecodeStatus &Out, DecodeStatus In) { 238 switch (In) { 239 case MCDisassembler::Success: 240 // Out stays the same. 241 return true; 242 case MCDisassembler::SoftFail: 243 Out = In; 244 return true; 245 case MCDisassembler::Fail: 246 Out = In; 247 return false; 248 } 249 llvm_unreachable("Invalid DecodeStatus!"); 250 } 251 252 #include "AArch64GenDisassemblerTables.inc" 253 #include "AArch64GenInstrInfo.inc" 254 255 #define Success MCDisassembler::Success 256 #define Fail MCDisassembler::Fail 257 #define SoftFail MCDisassembler::SoftFail 258 259 static MCDisassembler *createAArch64Disassembler(const Target &T, 260 const MCSubtargetInfo &STI, 261 MCContext &Ctx) { 262 return new AArch64Disassembler(STI, Ctx); 263 } 264 265 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 266 ArrayRef<uint8_t> Bytes, 267 uint64_t Address, 268 raw_ostream &CS) const { 269 CommentStream = &CS; 270 271 Size = 0; 272 // We want to read exactly 4 bytes of data. 273 if (Bytes.size() < 4) 274 return Fail; 275 Size = 4; 276 277 // Encoded as a small-endian 32-bit word in the stream. 278 uint32_t Insn = 279 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 280 281 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 282 283 for (auto Table : Tables) { 284 DecodeStatus Result = 285 decodeInstruction(Table, MI, Insn, Address, this, STI); 286 287 switch (MI.getOpcode()) { 288 default: 289 break; 290 // For Scalable Matrix Extension (SME) instructions that have an implicit 291 // operand for the accumulator (ZA) which isn't encoded, manually insert 292 // operand. 293 case AArch64::LD1_MXIPXX_H_B: 294 case AArch64::LD1_MXIPXX_V_B: 295 case AArch64::ST1_MXIPXX_H_B: 296 case AArch64::ST1_MXIPXX_V_B: 297 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 298 break; 299 } 300 301 if (Result != MCDisassembler::Fail) 302 return Result; 303 } 304 305 return MCDisassembler::Fail; 306 } 307 308 static MCSymbolizer * 309 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 310 LLVMSymbolLookupCallback SymbolLookUp, 311 void *DisInfo, MCContext *Ctx, 312 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 313 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 314 SymbolLookUp, DisInfo); 315 } 316 317 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 318 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 319 createAArch64Disassembler); 320 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 321 createAArch64Disassembler); 322 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 323 createAArch64ExternalSymbolizer); 324 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 325 createAArch64ExternalSymbolizer); 326 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 327 createAArch64Disassembler); 328 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 329 createAArch64ExternalSymbolizer); 330 331 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 332 createAArch64Disassembler); 333 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 334 createAArch64ExternalSymbolizer); 335 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 336 createAArch64Disassembler); 337 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 338 createAArch64ExternalSymbolizer); 339 } 340 341 static const unsigned FPR128DecoderTable[] = { 342 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 343 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 344 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 345 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 346 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 347 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 348 AArch64::Q30, AArch64::Q31 349 }; 350 351 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 352 uint64_t Addr, 353 const void *Decoder) { 354 if (RegNo > 31) 355 return Fail; 356 357 unsigned Register = FPR128DecoderTable[RegNo]; 358 Inst.addOperand(MCOperand::createReg(Register)); 359 return Success; 360 } 361 362 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 363 uint64_t Addr, 364 const void *Decoder) { 365 if (RegNo > 15) 366 return Fail; 367 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 368 } 369 370 static const unsigned FPR64DecoderTable[] = { 371 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 372 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 373 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 374 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 375 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 376 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 377 AArch64::D30, AArch64::D31 378 }; 379 380 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 381 uint64_t Addr, 382 const void *Decoder) { 383 if (RegNo > 31) 384 return Fail; 385 386 unsigned Register = FPR64DecoderTable[RegNo]; 387 Inst.addOperand(MCOperand::createReg(Register)); 388 return Success; 389 } 390 391 static const unsigned FPR32DecoderTable[] = { 392 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 393 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 394 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 395 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 396 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 397 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 398 AArch64::S30, AArch64::S31 399 }; 400 401 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 402 uint64_t Addr, 403 const void *Decoder) { 404 if (RegNo > 31) 405 return Fail; 406 407 unsigned Register = FPR32DecoderTable[RegNo]; 408 Inst.addOperand(MCOperand::createReg(Register)); 409 return Success; 410 } 411 412 static const unsigned FPR16DecoderTable[] = { 413 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 414 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 415 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 416 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 417 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 418 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 419 AArch64::H30, AArch64::H31 420 }; 421 422 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 423 uint64_t Addr, 424 const void *Decoder) { 425 if (RegNo > 31) 426 return Fail; 427 428 unsigned Register = FPR16DecoderTable[RegNo]; 429 Inst.addOperand(MCOperand::createReg(Register)); 430 return Success; 431 } 432 433 static const unsigned FPR8DecoderTable[] = { 434 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 435 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 436 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 437 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 438 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 439 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 440 AArch64::B30, AArch64::B31 441 }; 442 443 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 444 uint64_t Addr, 445 const void *Decoder) { 446 if (RegNo > 31) 447 return Fail; 448 449 unsigned Register = FPR8DecoderTable[RegNo]; 450 Inst.addOperand(MCOperand::createReg(Register)); 451 return Success; 452 } 453 454 static const unsigned GPR64DecoderTable[] = { 455 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 456 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 457 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 458 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 459 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 460 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 461 AArch64::LR, AArch64::XZR 462 }; 463 464 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 465 uint64_t Addr, 466 const void *Decoder) { 467 if (RegNo > 30) 468 return Fail; 469 470 unsigned Register = GPR64DecoderTable[RegNo]; 471 Inst.addOperand(MCOperand::createReg(Register)); 472 return Success; 473 } 474 475 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 476 uint64_t Addr, 477 const void *Decoder) { 478 if (RegNo > 31) 479 return Fail; 480 481 unsigned Register = GPR64DecoderTable[RegNo]; 482 Inst.addOperand(MCOperand::createReg(Register)); 483 return Success; 484 } 485 486 static const unsigned GPR64x8DecoderTable[] = { 487 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 488 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 489 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 490 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 491 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 492 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 493 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 494 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 495 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 496 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 497 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 498 AArch64::X22_X23_X24_X25_X26_X27_X28_FP, 499 }; 500 501 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 502 unsigned RegNo, 503 uint64_t Address, 504 const void *Decoder) { 505 if (RegNo > 22) 506 return Fail; 507 if (RegNo & 1) 508 return Fail; 509 510 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 511 Inst.addOperand(MCOperand::createReg(Register)); 512 return Success; 513 } 514 515 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 516 uint64_t Addr, 517 const void *Decoder) { 518 if (RegNo > 31) 519 return Fail; 520 unsigned Register = GPR64DecoderTable[RegNo]; 521 if (Register == AArch64::XZR) 522 Register = AArch64::SP; 523 Inst.addOperand(MCOperand::createReg(Register)); 524 return Success; 525 } 526 527 static const unsigned MatrixIndexGPR32_12_15DecoderTable[] = { 528 AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15 529 }; 530 531 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 532 unsigned RegNo, 533 uint64_t Addr, 534 const void *Decoder) { 535 if (RegNo > 3) 536 return Fail; 537 538 unsigned Register = MatrixIndexGPR32_12_15DecoderTable[RegNo]; 539 Inst.addOperand(MCOperand::createReg(Register)); 540 return Success; 541 } 542 543 static const unsigned GPR32DecoderTable[] = { 544 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 545 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 546 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 547 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 548 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 549 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 550 AArch64::W30, AArch64::WZR 551 }; 552 553 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 554 uint64_t Addr, 555 const void *Decoder) { 556 if (RegNo > 31) 557 return Fail; 558 559 unsigned Register = GPR32DecoderTable[RegNo]; 560 Inst.addOperand(MCOperand::createReg(Register)); 561 return Success; 562 } 563 564 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 565 uint64_t Addr, 566 const void *Decoder) { 567 if (RegNo > 31) 568 return Fail; 569 570 unsigned Register = GPR32DecoderTable[RegNo]; 571 if (Register == AArch64::WZR) 572 Register = AArch64::WSP; 573 Inst.addOperand(MCOperand::createReg(Register)); 574 return Success; 575 } 576 static const unsigned ZPRDecoderTable[] = { 577 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 578 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 579 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 580 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 581 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 582 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 583 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 584 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 585 }; 586 587 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 588 uint64_t Address, 589 const void* Decoder) { 590 if (RegNo > 31) 591 return Fail; 592 593 unsigned Register = ZPRDecoderTable[RegNo]; 594 Inst.addOperand(MCOperand::createReg(Register)); 595 return Success; 596 } 597 598 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 599 uint64_t Address, 600 const void *Decoder) { 601 if (RegNo > 15) 602 return Fail; 603 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 604 } 605 606 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 607 uint64_t Address, 608 const void *Decoder) { 609 if (RegNo > 7) 610 return Fail; 611 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 612 } 613 614 static const unsigned ZZDecoderTable[] = { 615 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 616 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 617 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 618 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 619 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 620 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 621 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 622 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 623 }; 624 625 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 626 uint64_t Address, 627 const void* Decoder) { 628 if (RegNo > 31) 629 return Fail; 630 unsigned Register = ZZDecoderTable[RegNo]; 631 Inst.addOperand(MCOperand::createReg(Register)); 632 return Success; 633 } 634 635 static const unsigned ZZZDecoderTable[] = { 636 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 637 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 638 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 639 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 640 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 641 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 642 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 643 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 644 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 645 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 646 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 647 }; 648 649 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 650 uint64_t Address, 651 const void* Decoder) { 652 if (RegNo > 31) 653 return Fail; 654 unsigned Register = ZZZDecoderTable[RegNo]; 655 Inst.addOperand(MCOperand::createReg(Register)); 656 return Success; 657 } 658 659 static const unsigned ZZZZDecoderTable[] = { 660 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 661 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 662 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 663 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 664 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 665 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 666 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 667 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 668 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 669 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 670 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 671 }; 672 673 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 674 uint64_t Address, 675 const void* Decoder) { 676 if (RegNo > 31) 677 return Fail; 678 unsigned Register = ZZZZDecoderTable[RegNo]; 679 Inst.addOperand(MCOperand::createReg(Register)); 680 return Success; 681 } 682 683 static const SmallVector<SmallVector<unsigned, 16>, 5> 684 MatrixZATileDecoderTable = { 685 {AArch64::ZAB0}, 686 {AArch64::ZAH0, AArch64::ZAH1}, 687 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 688 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 689 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 690 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 691 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 692 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 693 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 694 695 template <unsigned NumBitsForTile> 696 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 697 uint64_t Address, const void *Decoder) { 698 unsigned LastReg = (1 << NumBitsForTile) - 1; 699 if (RegNo > LastReg) 700 return Fail; 701 Inst.addOperand( 702 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 703 return Success; 704 } 705 706 static const unsigned PPRDecoderTable[] = { 707 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 708 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 709 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 710 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 711 }; 712 713 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 714 uint64_t Addr, const void *Decoder) { 715 if (RegNo > 15) 716 return Fail; 717 718 unsigned Register = PPRDecoderTable[RegNo]; 719 Inst.addOperand(MCOperand::createReg(Register)); 720 return Success; 721 } 722 723 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 724 uint64_t Addr, 725 const void* Decoder) { 726 if (RegNo > 7) 727 return Fail; 728 729 // Just reuse the PPR decode table 730 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 731 } 732 733 static const unsigned VectorDecoderTable[] = { 734 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 735 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 736 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 737 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 738 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 739 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 740 AArch64::Q30, AArch64::Q31 741 }; 742 743 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 744 uint64_t Addr, 745 const void *Decoder) { 746 if (RegNo > 31) 747 return Fail; 748 749 unsigned Register = VectorDecoderTable[RegNo]; 750 Inst.addOperand(MCOperand::createReg(Register)); 751 return Success; 752 } 753 754 static const unsigned QQDecoderTable[] = { 755 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 756 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 757 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 758 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 759 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 760 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 761 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 762 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 763 }; 764 765 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 766 uint64_t Addr, const void *Decoder) { 767 if (RegNo > 31) 768 return Fail; 769 unsigned Register = QQDecoderTable[RegNo]; 770 Inst.addOperand(MCOperand::createReg(Register)); 771 return Success; 772 } 773 774 static const unsigned QQQDecoderTable[] = { 775 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 776 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 777 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 778 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 779 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 780 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 781 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 782 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 783 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 784 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 785 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 786 }; 787 788 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 789 uint64_t Addr, const void *Decoder) { 790 if (RegNo > 31) 791 return Fail; 792 unsigned Register = QQQDecoderTable[RegNo]; 793 Inst.addOperand(MCOperand::createReg(Register)); 794 return Success; 795 } 796 797 static const unsigned QQQQDecoderTable[] = { 798 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 799 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 800 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 801 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 802 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 803 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 804 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 805 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 806 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 807 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 808 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 809 }; 810 811 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 812 uint64_t Addr, 813 const void *Decoder) { 814 if (RegNo > 31) 815 return Fail; 816 unsigned Register = QQQQDecoderTable[RegNo]; 817 Inst.addOperand(MCOperand::createReg(Register)); 818 return Success; 819 } 820 821 static const unsigned DDDecoderTable[] = { 822 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 823 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 824 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 825 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 826 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 827 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 828 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 829 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 830 }; 831 832 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 833 uint64_t Addr, const void *Decoder) { 834 if (RegNo > 31) 835 return Fail; 836 unsigned Register = DDDecoderTable[RegNo]; 837 Inst.addOperand(MCOperand::createReg(Register)); 838 return Success; 839 } 840 841 static const unsigned DDDDecoderTable[] = { 842 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 843 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 844 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 845 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 846 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 847 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 848 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 849 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 850 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 851 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 852 AArch64::D30_D31_D0, AArch64::D31_D0_D1 853 }; 854 855 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 856 uint64_t Addr, const void *Decoder) { 857 if (RegNo > 31) 858 return Fail; 859 unsigned Register = DDDDecoderTable[RegNo]; 860 Inst.addOperand(MCOperand::createReg(Register)); 861 return Success; 862 } 863 864 static const unsigned DDDDDecoderTable[] = { 865 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 866 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 867 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 868 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 869 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 870 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 871 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 872 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 873 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 874 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 875 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 876 }; 877 878 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 879 uint64_t Addr, 880 const void *Decoder) { 881 if (RegNo > 31) 882 return Fail; 883 unsigned Register = DDDDDecoderTable[RegNo]; 884 Inst.addOperand(MCOperand::createReg(Register)); 885 return Success; 886 } 887 888 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 889 uint64_t Addr, 890 const void *Decoder) { 891 // scale{5} is asserted as 1 in tblgen. 892 Imm |= 0x20; 893 Inst.addOperand(MCOperand::createImm(64 - Imm)); 894 return Success; 895 } 896 897 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 898 uint64_t Addr, 899 const void *Decoder) { 900 Inst.addOperand(MCOperand::createImm(64 - Imm)); 901 return Success; 902 } 903 904 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 905 uint64_t Addr, const void *Decoder) { 906 int64_t ImmVal = Imm; 907 const AArch64Disassembler *Dis = 908 static_cast<const AArch64Disassembler *>(Decoder); 909 910 // Sign-extend 19-bit immediate. 911 if (ImmVal & (1 << (19 - 1))) 912 ImmVal |= ~((1LL << 19) - 1); 913 914 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 915 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 916 Inst.addOperand(MCOperand::createImm(ImmVal)); 917 return Success; 918 } 919 920 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 921 uint64_t Address, const void *Decoder) { 922 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 923 Inst.addOperand(MCOperand::createImm(Imm & 1)); 924 return Success; 925 } 926 927 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 928 uint64_t Address, 929 const void *Decoder) { 930 Inst.addOperand(MCOperand::createImm(Imm)); 931 932 // Every system register in the encoding space is valid with the syntax 933 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 934 return Success; 935 } 936 937 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 938 uint64_t Address, 939 const void *Decoder) { 940 Inst.addOperand(MCOperand::createImm(Imm)); 941 942 return Success; 943 } 944 945 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 946 uint64_t Address, 947 const void *Decoder) { 948 // This decoder exists to add the dummy Lane operand to the MCInst, which must 949 // be 1 in assembly but has no other real manifestation. 950 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 951 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 952 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 953 954 if (IsToVec) { 955 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 956 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 957 } else { 958 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 959 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 960 } 961 962 // Add the lane 963 Inst.addOperand(MCOperand::createImm(1)); 964 965 return Success; 966 } 967 968 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 969 unsigned Add) { 970 Inst.addOperand(MCOperand::createImm(Add - Imm)); 971 return Success; 972 } 973 974 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 975 unsigned Add) { 976 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 977 return Success; 978 } 979 980 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 981 uint64_t Addr, const void *Decoder) { 982 return DecodeVecShiftRImm(Inst, Imm, 64); 983 } 984 985 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 986 uint64_t Addr, 987 const void *Decoder) { 988 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 989 } 990 991 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 992 uint64_t Addr, const void *Decoder) { 993 return DecodeVecShiftRImm(Inst, Imm, 32); 994 } 995 996 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 997 uint64_t Addr, 998 const void *Decoder) { 999 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 1000 } 1001 1002 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 1003 uint64_t Addr, const void *Decoder) { 1004 return DecodeVecShiftRImm(Inst, Imm, 16); 1005 } 1006 1007 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 1008 uint64_t Addr, 1009 const void *Decoder) { 1010 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 1011 } 1012 1013 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 1014 uint64_t Addr, const void *Decoder) { 1015 return DecodeVecShiftRImm(Inst, Imm, 8); 1016 } 1017 1018 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 1019 uint64_t Addr, const void *Decoder) { 1020 return DecodeVecShiftLImm(Inst, Imm, 64); 1021 } 1022 1023 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 1024 uint64_t Addr, const void *Decoder) { 1025 return DecodeVecShiftLImm(Inst, Imm, 32); 1026 } 1027 1028 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 1029 uint64_t Addr, const void *Decoder) { 1030 return DecodeVecShiftLImm(Inst, Imm, 16); 1031 } 1032 1033 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 1034 uint64_t Addr, const void *Decoder) { 1035 return DecodeVecShiftLImm(Inst, Imm, 8); 1036 } 1037 1038 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 1039 uint64_t Addr, 1040 const void *Decoder) { 1041 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1042 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1043 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1044 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 1045 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 1046 unsigned shift = (shiftHi << 6) | shiftLo; 1047 switch (Inst.getOpcode()) { 1048 default: 1049 return Fail; 1050 case AArch64::ADDWrs: 1051 case AArch64::ADDSWrs: 1052 case AArch64::SUBWrs: 1053 case AArch64::SUBSWrs: 1054 // if shift == '11' then ReservedValue() 1055 if (shiftHi == 0x3) 1056 return Fail; 1057 LLVM_FALLTHROUGH; 1058 case AArch64::ANDWrs: 1059 case AArch64::ANDSWrs: 1060 case AArch64::BICWrs: 1061 case AArch64::BICSWrs: 1062 case AArch64::ORRWrs: 1063 case AArch64::ORNWrs: 1064 case AArch64::EORWrs: 1065 case AArch64::EONWrs: { 1066 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1067 if (shiftLo >> 5 == 1) 1068 return Fail; 1069 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1070 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1071 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1072 break; 1073 } 1074 case AArch64::ADDXrs: 1075 case AArch64::ADDSXrs: 1076 case AArch64::SUBXrs: 1077 case AArch64::SUBSXrs: 1078 // if shift == '11' then ReservedValue() 1079 if (shiftHi == 0x3) 1080 return Fail; 1081 LLVM_FALLTHROUGH; 1082 case AArch64::ANDXrs: 1083 case AArch64::ANDSXrs: 1084 case AArch64::BICXrs: 1085 case AArch64::BICSXrs: 1086 case AArch64::ORRXrs: 1087 case AArch64::ORNXrs: 1088 case AArch64::EORXrs: 1089 case AArch64::EONXrs: 1090 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1091 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1092 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1093 break; 1094 } 1095 1096 Inst.addOperand(MCOperand::createImm(shift)); 1097 return Success; 1098 } 1099 1100 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1101 uint64_t Addr, 1102 const void *Decoder) { 1103 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1104 unsigned imm = fieldFromInstruction(insn, 5, 16); 1105 unsigned shift = fieldFromInstruction(insn, 21, 2); 1106 shift <<= 4; 1107 switch (Inst.getOpcode()) { 1108 default: 1109 return Fail; 1110 case AArch64::MOVZWi: 1111 case AArch64::MOVNWi: 1112 case AArch64::MOVKWi: 1113 if (shift & (1U << 5)) 1114 return Fail; 1115 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1116 break; 1117 case AArch64::MOVZXi: 1118 case AArch64::MOVNXi: 1119 case AArch64::MOVKXi: 1120 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1121 break; 1122 } 1123 1124 if (Inst.getOpcode() == AArch64::MOVKWi || 1125 Inst.getOpcode() == AArch64::MOVKXi) 1126 Inst.addOperand(Inst.getOperand(0)); 1127 1128 Inst.addOperand(MCOperand::createImm(imm)); 1129 Inst.addOperand(MCOperand::createImm(shift)); 1130 return Success; 1131 } 1132 1133 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1134 uint64_t Addr, 1135 const void *Decoder) { 1136 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1137 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1138 unsigned offset = fieldFromInstruction(insn, 10, 12); 1139 const AArch64Disassembler *Dis = 1140 static_cast<const AArch64Disassembler *>(Decoder); 1141 1142 switch (Inst.getOpcode()) { 1143 default: 1144 return Fail; 1145 case AArch64::PRFMui: 1146 // Rt is an immediate in prefetch. 1147 Inst.addOperand(MCOperand::createImm(Rt)); 1148 break; 1149 case AArch64::STRBBui: 1150 case AArch64::LDRBBui: 1151 case AArch64::LDRSBWui: 1152 case AArch64::STRHHui: 1153 case AArch64::LDRHHui: 1154 case AArch64::LDRSHWui: 1155 case AArch64::STRWui: 1156 case AArch64::LDRWui: 1157 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1158 break; 1159 case AArch64::LDRSBXui: 1160 case AArch64::LDRSHXui: 1161 case AArch64::LDRSWui: 1162 case AArch64::STRXui: 1163 case AArch64::LDRXui: 1164 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1165 break; 1166 case AArch64::LDRQui: 1167 case AArch64::STRQui: 1168 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1169 break; 1170 case AArch64::LDRDui: 1171 case AArch64::STRDui: 1172 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1173 break; 1174 case AArch64::LDRSui: 1175 case AArch64::STRSui: 1176 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1177 break; 1178 case AArch64::LDRHui: 1179 case AArch64::STRHui: 1180 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1181 break; 1182 case AArch64::LDRBui: 1183 case AArch64::STRBui: 1184 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1185 break; 1186 } 1187 1188 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1189 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1190 Inst.addOperand(MCOperand::createImm(offset)); 1191 return Success; 1192 } 1193 1194 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1195 uint64_t Addr, 1196 const void *Decoder) { 1197 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1198 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1199 int64_t offset = fieldFromInstruction(insn, 12, 9); 1200 1201 // offset is a 9-bit signed immediate, so sign extend it to 1202 // fill the unsigned. 1203 if (offset & (1 << (9 - 1))) 1204 offset |= ~((1LL << 9) - 1); 1205 1206 // First operand is always the writeback to the address register, if needed. 1207 switch (Inst.getOpcode()) { 1208 default: 1209 break; 1210 case AArch64::LDRSBWpre: 1211 case AArch64::LDRSHWpre: 1212 case AArch64::STRBBpre: 1213 case AArch64::LDRBBpre: 1214 case AArch64::STRHHpre: 1215 case AArch64::LDRHHpre: 1216 case AArch64::STRWpre: 1217 case AArch64::LDRWpre: 1218 case AArch64::LDRSBWpost: 1219 case AArch64::LDRSHWpost: 1220 case AArch64::STRBBpost: 1221 case AArch64::LDRBBpost: 1222 case AArch64::STRHHpost: 1223 case AArch64::LDRHHpost: 1224 case AArch64::STRWpost: 1225 case AArch64::LDRWpost: 1226 case AArch64::LDRSBXpre: 1227 case AArch64::LDRSHXpre: 1228 case AArch64::STRXpre: 1229 case AArch64::LDRSWpre: 1230 case AArch64::LDRXpre: 1231 case AArch64::LDRSBXpost: 1232 case AArch64::LDRSHXpost: 1233 case AArch64::STRXpost: 1234 case AArch64::LDRSWpost: 1235 case AArch64::LDRXpost: 1236 case AArch64::LDRQpre: 1237 case AArch64::STRQpre: 1238 case AArch64::LDRQpost: 1239 case AArch64::STRQpost: 1240 case AArch64::LDRDpre: 1241 case AArch64::STRDpre: 1242 case AArch64::LDRDpost: 1243 case AArch64::STRDpost: 1244 case AArch64::LDRSpre: 1245 case AArch64::STRSpre: 1246 case AArch64::LDRSpost: 1247 case AArch64::STRSpost: 1248 case AArch64::LDRHpre: 1249 case AArch64::STRHpre: 1250 case AArch64::LDRHpost: 1251 case AArch64::STRHpost: 1252 case AArch64::LDRBpre: 1253 case AArch64::STRBpre: 1254 case AArch64::LDRBpost: 1255 case AArch64::STRBpost: 1256 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1257 break; 1258 } 1259 1260 switch (Inst.getOpcode()) { 1261 default: 1262 return Fail; 1263 case AArch64::PRFUMi: 1264 // Rt is an immediate in prefetch. 1265 Inst.addOperand(MCOperand::createImm(Rt)); 1266 break; 1267 case AArch64::STURBBi: 1268 case AArch64::LDURBBi: 1269 case AArch64::LDURSBWi: 1270 case AArch64::STURHHi: 1271 case AArch64::LDURHHi: 1272 case AArch64::LDURSHWi: 1273 case AArch64::STURWi: 1274 case AArch64::LDURWi: 1275 case AArch64::LDTRSBWi: 1276 case AArch64::LDTRSHWi: 1277 case AArch64::STTRWi: 1278 case AArch64::LDTRWi: 1279 case AArch64::STTRHi: 1280 case AArch64::LDTRHi: 1281 case AArch64::LDTRBi: 1282 case AArch64::STTRBi: 1283 case AArch64::LDRSBWpre: 1284 case AArch64::LDRSHWpre: 1285 case AArch64::STRBBpre: 1286 case AArch64::LDRBBpre: 1287 case AArch64::STRHHpre: 1288 case AArch64::LDRHHpre: 1289 case AArch64::STRWpre: 1290 case AArch64::LDRWpre: 1291 case AArch64::LDRSBWpost: 1292 case AArch64::LDRSHWpost: 1293 case AArch64::STRBBpost: 1294 case AArch64::LDRBBpost: 1295 case AArch64::STRHHpost: 1296 case AArch64::LDRHHpost: 1297 case AArch64::STRWpost: 1298 case AArch64::LDRWpost: 1299 case AArch64::STLURBi: 1300 case AArch64::STLURHi: 1301 case AArch64::STLURWi: 1302 case AArch64::LDAPURBi: 1303 case AArch64::LDAPURSBWi: 1304 case AArch64::LDAPURHi: 1305 case AArch64::LDAPURSHWi: 1306 case AArch64::LDAPURi: 1307 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1308 break; 1309 case AArch64::LDURSBXi: 1310 case AArch64::LDURSHXi: 1311 case AArch64::LDURSWi: 1312 case AArch64::STURXi: 1313 case AArch64::LDURXi: 1314 case AArch64::LDTRSBXi: 1315 case AArch64::LDTRSHXi: 1316 case AArch64::LDTRSWi: 1317 case AArch64::STTRXi: 1318 case AArch64::LDTRXi: 1319 case AArch64::LDRSBXpre: 1320 case AArch64::LDRSHXpre: 1321 case AArch64::STRXpre: 1322 case AArch64::LDRSWpre: 1323 case AArch64::LDRXpre: 1324 case AArch64::LDRSBXpost: 1325 case AArch64::LDRSHXpost: 1326 case AArch64::STRXpost: 1327 case AArch64::LDRSWpost: 1328 case AArch64::LDRXpost: 1329 case AArch64::LDAPURSWi: 1330 case AArch64::LDAPURSHXi: 1331 case AArch64::LDAPURSBXi: 1332 case AArch64::STLURXi: 1333 case AArch64::LDAPURXi: 1334 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1335 break; 1336 case AArch64::LDURQi: 1337 case AArch64::STURQi: 1338 case AArch64::LDRQpre: 1339 case AArch64::STRQpre: 1340 case AArch64::LDRQpost: 1341 case AArch64::STRQpost: 1342 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1343 break; 1344 case AArch64::LDURDi: 1345 case AArch64::STURDi: 1346 case AArch64::LDRDpre: 1347 case AArch64::STRDpre: 1348 case AArch64::LDRDpost: 1349 case AArch64::STRDpost: 1350 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1351 break; 1352 case AArch64::LDURSi: 1353 case AArch64::STURSi: 1354 case AArch64::LDRSpre: 1355 case AArch64::STRSpre: 1356 case AArch64::LDRSpost: 1357 case AArch64::STRSpost: 1358 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1359 break; 1360 case AArch64::LDURHi: 1361 case AArch64::STURHi: 1362 case AArch64::LDRHpre: 1363 case AArch64::STRHpre: 1364 case AArch64::LDRHpost: 1365 case AArch64::STRHpost: 1366 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1367 break; 1368 case AArch64::LDURBi: 1369 case AArch64::STURBi: 1370 case AArch64::LDRBpre: 1371 case AArch64::STRBpre: 1372 case AArch64::LDRBpost: 1373 case AArch64::STRBpost: 1374 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1375 break; 1376 } 1377 1378 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1379 Inst.addOperand(MCOperand::createImm(offset)); 1380 1381 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1382 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1383 bool IsFP = fieldFromInstruction(insn, 26, 1); 1384 1385 // Cannot write back to a transfer register (but xzr != sp). 1386 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1387 return SoftFail; 1388 1389 return Success; 1390 } 1391 1392 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1393 uint64_t Addr, 1394 const void *Decoder) { 1395 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1396 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1397 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1398 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1399 1400 unsigned Opcode = Inst.getOpcode(); 1401 switch (Opcode) { 1402 default: 1403 return Fail; 1404 case AArch64::STLXRW: 1405 case AArch64::STLXRB: 1406 case AArch64::STLXRH: 1407 case AArch64::STXRW: 1408 case AArch64::STXRB: 1409 case AArch64::STXRH: 1410 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1411 LLVM_FALLTHROUGH; 1412 case AArch64::LDARW: 1413 case AArch64::LDARB: 1414 case AArch64::LDARH: 1415 case AArch64::LDAXRW: 1416 case AArch64::LDAXRB: 1417 case AArch64::LDAXRH: 1418 case AArch64::LDXRW: 1419 case AArch64::LDXRB: 1420 case AArch64::LDXRH: 1421 case AArch64::STLRW: 1422 case AArch64::STLRB: 1423 case AArch64::STLRH: 1424 case AArch64::STLLRW: 1425 case AArch64::STLLRB: 1426 case AArch64::STLLRH: 1427 case AArch64::LDLARW: 1428 case AArch64::LDLARB: 1429 case AArch64::LDLARH: 1430 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1431 break; 1432 case AArch64::STLXRX: 1433 case AArch64::STXRX: 1434 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1435 LLVM_FALLTHROUGH; 1436 case AArch64::LDARX: 1437 case AArch64::LDAXRX: 1438 case AArch64::LDXRX: 1439 case AArch64::STLRX: 1440 case AArch64::LDLARX: 1441 case AArch64::STLLRX: 1442 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1443 break; 1444 case AArch64::STLXPW: 1445 case AArch64::STXPW: 1446 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1447 LLVM_FALLTHROUGH; 1448 case AArch64::LDAXPW: 1449 case AArch64::LDXPW: 1450 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1451 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1452 break; 1453 case AArch64::STLXPX: 1454 case AArch64::STXPX: 1455 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1456 LLVM_FALLTHROUGH; 1457 case AArch64::LDAXPX: 1458 case AArch64::LDXPX: 1459 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1460 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1461 break; 1462 } 1463 1464 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1465 1466 // You shouldn't load to the same register twice in an instruction... 1467 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1468 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1469 Rt == Rt2) 1470 return SoftFail; 1471 1472 return Success; 1473 } 1474 1475 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1476 uint64_t Addr, 1477 const void *Decoder) { 1478 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1479 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1480 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1481 int64_t offset = fieldFromInstruction(insn, 15, 7); 1482 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1483 1484 // offset is a 7-bit signed immediate, so sign extend it to 1485 // fill the unsigned. 1486 if (offset & (1 << (7 - 1))) 1487 offset |= ~((1LL << 7) - 1); 1488 1489 unsigned Opcode = Inst.getOpcode(); 1490 bool NeedsDisjointWritebackTransfer = false; 1491 1492 // First operand is always writeback of base register. 1493 switch (Opcode) { 1494 default: 1495 break; 1496 case AArch64::LDPXpost: 1497 case AArch64::STPXpost: 1498 case AArch64::LDPSWpost: 1499 case AArch64::LDPXpre: 1500 case AArch64::STPXpre: 1501 case AArch64::LDPSWpre: 1502 case AArch64::LDPWpost: 1503 case AArch64::STPWpost: 1504 case AArch64::LDPWpre: 1505 case AArch64::STPWpre: 1506 case AArch64::LDPQpost: 1507 case AArch64::STPQpost: 1508 case AArch64::LDPQpre: 1509 case AArch64::STPQpre: 1510 case AArch64::LDPDpost: 1511 case AArch64::STPDpost: 1512 case AArch64::LDPDpre: 1513 case AArch64::STPDpre: 1514 case AArch64::LDPSpost: 1515 case AArch64::STPSpost: 1516 case AArch64::LDPSpre: 1517 case AArch64::STPSpre: 1518 case AArch64::STGPpre: 1519 case AArch64::STGPpost: 1520 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1521 break; 1522 } 1523 1524 switch (Opcode) { 1525 default: 1526 return Fail; 1527 case AArch64::LDPXpost: 1528 case AArch64::STPXpost: 1529 case AArch64::LDPSWpost: 1530 case AArch64::LDPXpre: 1531 case AArch64::STPXpre: 1532 case AArch64::LDPSWpre: 1533 case AArch64::STGPpre: 1534 case AArch64::STGPpost: 1535 NeedsDisjointWritebackTransfer = true; 1536 LLVM_FALLTHROUGH; 1537 case AArch64::LDNPXi: 1538 case AArch64::STNPXi: 1539 case AArch64::LDPXi: 1540 case AArch64::STPXi: 1541 case AArch64::LDPSWi: 1542 case AArch64::STGPi: 1543 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1544 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1545 break; 1546 case AArch64::LDPWpost: 1547 case AArch64::STPWpost: 1548 case AArch64::LDPWpre: 1549 case AArch64::STPWpre: 1550 NeedsDisjointWritebackTransfer = true; 1551 LLVM_FALLTHROUGH; 1552 case AArch64::LDNPWi: 1553 case AArch64::STNPWi: 1554 case AArch64::LDPWi: 1555 case AArch64::STPWi: 1556 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1557 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1558 break; 1559 case AArch64::LDNPQi: 1560 case AArch64::STNPQi: 1561 case AArch64::LDPQpost: 1562 case AArch64::STPQpost: 1563 case AArch64::LDPQi: 1564 case AArch64::STPQi: 1565 case AArch64::LDPQpre: 1566 case AArch64::STPQpre: 1567 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1568 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1569 break; 1570 case AArch64::LDNPDi: 1571 case AArch64::STNPDi: 1572 case AArch64::LDPDpost: 1573 case AArch64::STPDpost: 1574 case AArch64::LDPDi: 1575 case AArch64::STPDi: 1576 case AArch64::LDPDpre: 1577 case AArch64::STPDpre: 1578 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1579 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1580 break; 1581 case AArch64::LDNPSi: 1582 case AArch64::STNPSi: 1583 case AArch64::LDPSpost: 1584 case AArch64::STPSpost: 1585 case AArch64::LDPSi: 1586 case AArch64::STPSi: 1587 case AArch64::LDPSpre: 1588 case AArch64::STPSpre: 1589 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1590 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1591 break; 1592 } 1593 1594 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1595 Inst.addOperand(MCOperand::createImm(offset)); 1596 1597 // You shouldn't load to the same register twice in an instruction... 1598 if (IsLoad && Rt == Rt2) 1599 return SoftFail; 1600 1601 // ... or do any operation that writes-back to a transfer register. But note 1602 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1603 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1604 return SoftFail; 1605 1606 return Success; 1607 } 1608 1609 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1610 uint64_t Addr, 1611 const void *Decoder) { 1612 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1613 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1614 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1615 fieldFromInstruction(insn, 12, 9); 1616 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1617 1618 switch (Inst.getOpcode()) { 1619 default: 1620 return Fail; 1621 case AArch64::LDRAAwriteback: 1622 case AArch64::LDRABwriteback: 1623 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1624 Decoder); 1625 break; 1626 case AArch64::LDRAAindexed: 1627 case AArch64::LDRABindexed: 1628 break; 1629 } 1630 1631 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1632 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1633 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1634 1635 if (writeback && Rt == Rn && Rn != 31) { 1636 return SoftFail; 1637 } 1638 1639 return Success; 1640 } 1641 1642 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1643 uint64_t Addr, 1644 const void *Decoder) { 1645 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1646 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1647 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1648 unsigned extend = fieldFromInstruction(insn, 10, 6); 1649 1650 unsigned shift = extend & 0x7; 1651 if (shift > 4) 1652 return Fail; 1653 1654 switch (Inst.getOpcode()) { 1655 default: 1656 return Fail; 1657 case AArch64::ADDWrx: 1658 case AArch64::SUBWrx: 1659 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1660 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1661 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1662 break; 1663 case AArch64::ADDSWrx: 1664 case AArch64::SUBSWrx: 1665 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1666 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1667 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1668 break; 1669 case AArch64::ADDXrx: 1670 case AArch64::SUBXrx: 1671 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1672 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1673 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1674 break; 1675 case AArch64::ADDSXrx: 1676 case AArch64::SUBSXrx: 1677 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1678 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1679 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1680 break; 1681 case AArch64::ADDXrx64: 1682 case AArch64::SUBXrx64: 1683 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1684 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1685 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1686 break; 1687 case AArch64::SUBSXrx64: 1688 case AArch64::ADDSXrx64: 1689 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1690 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1691 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1692 break; 1693 } 1694 1695 Inst.addOperand(MCOperand::createImm(extend)); 1696 return Success; 1697 } 1698 1699 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1700 uint64_t Addr, 1701 const void *Decoder) { 1702 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1703 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1704 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1705 unsigned imm; 1706 1707 if (Datasize) { 1708 if (Inst.getOpcode() == AArch64::ANDSXri) 1709 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1710 else 1711 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1712 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1713 imm = fieldFromInstruction(insn, 10, 13); 1714 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1715 return Fail; 1716 } else { 1717 if (Inst.getOpcode() == AArch64::ANDSWri) 1718 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1719 else 1720 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1721 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1722 imm = fieldFromInstruction(insn, 10, 12); 1723 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1724 return Fail; 1725 } 1726 Inst.addOperand(MCOperand::createImm(imm)); 1727 return Success; 1728 } 1729 1730 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1731 uint64_t Addr, 1732 const void *Decoder) { 1733 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1734 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1735 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1736 imm |= fieldFromInstruction(insn, 5, 5); 1737 1738 if (Inst.getOpcode() == AArch64::MOVID) 1739 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1740 else 1741 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1742 1743 Inst.addOperand(MCOperand::createImm(imm)); 1744 1745 switch (Inst.getOpcode()) { 1746 default: 1747 break; 1748 case AArch64::MOVIv4i16: 1749 case AArch64::MOVIv8i16: 1750 case AArch64::MVNIv4i16: 1751 case AArch64::MVNIv8i16: 1752 case AArch64::MOVIv2i32: 1753 case AArch64::MOVIv4i32: 1754 case AArch64::MVNIv2i32: 1755 case AArch64::MVNIv4i32: 1756 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1757 break; 1758 case AArch64::MOVIv2s_msl: 1759 case AArch64::MOVIv4s_msl: 1760 case AArch64::MVNIv2s_msl: 1761 case AArch64::MVNIv4s_msl: 1762 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1763 break; 1764 } 1765 1766 return Success; 1767 } 1768 1769 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1770 uint64_t Addr, 1771 const void *Decoder) { 1772 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1773 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1774 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1775 imm |= fieldFromInstruction(insn, 5, 5); 1776 1777 // Tied operands added twice. 1778 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1779 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1780 1781 Inst.addOperand(MCOperand::createImm(imm)); 1782 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1783 1784 return Success; 1785 } 1786 1787 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1788 uint64_t Addr, const void *Decoder) { 1789 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1790 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1791 imm |= fieldFromInstruction(insn, 29, 2); 1792 const AArch64Disassembler *Dis = 1793 static_cast<const AArch64Disassembler *>(Decoder); 1794 1795 // Sign-extend the 21-bit immediate. 1796 if (imm & (1 << (21 - 1))) 1797 imm |= ~((1LL << 21) - 1); 1798 1799 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1800 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1801 Inst.addOperand(MCOperand::createImm(imm)); 1802 1803 return Success; 1804 } 1805 1806 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1807 uint64_t Addr, const void *Decoder) { 1808 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1809 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1810 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1811 unsigned S = fieldFromInstruction(insn, 29, 1); 1812 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1813 1814 unsigned ShifterVal = (Imm >> 12) & 3; 1815 unsigned ImmVal = Imm & 0xFFF; 1816 const AArch64Disassembler *Dis = 1817 static_cast<const AArch64Disassembler *>(Decoder); 1818 1819 if (ShifterVal != 0 && ShifterVal != 1) 1820 return Fail; 1821 1822 if (Datasize) { 1823 if (Rd == 31 && !S) 1824 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1825 else 1826 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1827 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1828 } else { 1829 if (Rd == 31 && !S) 1830 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1831 else 1832 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1833 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1834 } 1835 1836 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1837 Inst.addOperand(MCOperand::createImm(ImmVal)); 1838 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1839 return Success; 1840 } 1841 1842 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1843 uint64_t Addr, 1844 const void *Decoder) { 1845 int64_t imm = fieldFromInstruction(insn, 0, 26); 1846 const AArch64Disassembler *Dis = 1847 static_cast<const AArch64Disassembler *>(Decoder); 1848 1849 // Sign-extend the 26-bit immediate. 1850 if (imm & (1 << (26 - 1))) 1851 imm |= ~((1LL << 26) - 1); 1852 1853 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1854 Inst.addOperand(MCOperand::createImm(imm)); 1855 1856 return Success; 1857 } 1858 1859 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1860 uint64_t Addr, 1861 const void *Decoder) { 1862 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1863 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1864 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1865 uint64_t pstate_field = (op1 << 3) | op2; 1866 1867 switch (pstate_field) { 1868 case 0x01: // XAFlag 1869 case 0x02: // AXFlag 1870 return Fail; 1871 } 1872 1873 if ((pstate_field == AArch64PState::PAN || 1874 pstate_field == AArch64PState::UAO || 1875 pstate_field == AArch64PState::SSBS) && crm > 1) 1876 return Fail; 1877 1878 Inst.addOperand(MCOperand::createImm(pstate_field)); 1879 Inst.addOperand(MCOperand::createImm(crm)); 1880 1881 const AArch64Disassembler *Dis = 1882 static_cast<const AArch64Disassembler *>(Decoder); 1883 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1884 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1885 return Success; 1886 return Fail; 1887 } 1888 1889 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1890 uint64_t Addr, const void *Decoder) { 1891 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1892 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1893 bit |= fieldFromInstruction(insn, 19, 5); 1894 int64_t dst = fieldFromInstruction(insn, 5, 14); 1895 const AArch64Disassembler *Dis = 1896 static_cast<const AArch64Disassembler *>(Decoder); 1897 1898 // Sign-extend 14-bit immediate. 1899 if (dst & (1 << (14 - 1))) 1900 dst |= ~((1LL << 14) - 1); 1901 1902 if (fieldFromInstruction(insn, 31, 1) == 0) 1903 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1904 else 1905 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1906 Inst.addOperand(MCOperand::createImm(bit)); 1907 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1908 Inst.addOperand(MCOperand::createImm(dst)); 1909 1910 return Success; 1911 } 1912 1913 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1914 unsigned RegClassID, 1915 unsigned RegNo, 1916 uint64_t Addr, 1917 const void *Decoder) { 1918 // Register number must be even (see CASP instruction) 1919 if (RegNo & 0x1) 1920 return Fail; 1921 1922 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1923 Inst.addOperand(MCOperand::createReg(Reg)); 1924 return Success; 1925 } 1926 1927 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1928 unsigned RegNo, 1929 uint64_t Addr, 1930 const void *Decoder) { 1931 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1932 AArch64::WSeqPairsClassRegClassID, 1933 RegNo, Addr, Decoder); 1934 } 1935 1936 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1937 unsigned RegNo, 1938 uint64_t Addr, 1939 const void *Decoder) { 1940 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1941 AArch64::XSeqPairsClassRegClassID, 1942 RegNo, Addr, Decoder); 1943 } 1944 1945 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1946 uint32_t insn, 1947 uint64_t Addr, 1948 const void *Decoder) { 1949 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1950 unsigned imm = fieldFromInstruction(insn, 5, 13); 1951 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1952 return Fail; 1953 1954 // The same (tied) operand is added twice to the instruction. 1955 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1956 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1957 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1958 Inst.addOperand(MCOperand::createImm(imm)); 1959 return Success; 1960 } 1961 1962 template<int Bits> 1963 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1964 uint64_t Address, const void *Decoder) { 1965 if (Imm & ~((1LL << Bits) - 1)) 1966 return Fail; 1967 1968 // Imm is a signed immediate, so sign extend it. 1969 if (Imm & (1 << (Bits - 1))) 1970 Imm |= ~((1LL << Bits) - 1); 1971 1972 Inst.addOperand(MCOperand::createImm(Imm)); 1973 return Success; 1974 } 1975 1976 // Decode 8-bit signed/unsigned immediate for a given element width. 1977 template <int ElementWidth> 1978 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1979 uint64_t Addr, const void *Decoder) { 1980 unsigned Val = (uint8_t)Imm; 1981 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1982 if (ElementWidth == 8 && Shift) 1983 return Fail; 1984 Inst.addOperand(MCOperand::createImm(Val)); 1985 Inst.addOperand(MCOperand::createImm(Shift)); 1986 return Success; 1987 } 1988 1989 // Decode uimm4 ranged from 1-16. 1990 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1991 uint64_t Addr, const void *Decoder) { 1992 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1993 return Success; 1994 } 1995