1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the functions necessary to decode AArch64 instruction 11 // bitpatterns into MCInsts (with the help of TableGenerated information from 12 // the instruction definitions). 13 // 14 //===----------------------------------------------------------------------===// 15 16 #define DEBUG_TYPE "arm-disassembler" 17 18 #include "AArch64.h" 19 #include "AArch64RegisterInfo.h" 20 #include "AArch64Subtarget.h" 21 #include "Utils/AArch64BaseInfo.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrDesc.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCDisassembler.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/MemoryObject.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetRegistry.h" 32 #include "llvm/Support/raw_ostream.h" 33 34 using namespace llvm; 35 36 typedef MCDisassembler::DecodeStatus DecodeStatus; 37 38 namespace { 39 /// AArch64 disassembler for all AArch64 platforms. 40 class AArch64Disassembler : public MCDisassembler { 41 OwningPtr<const MCRegisterInfo> RegInfo; 42 public: 43 /// Initializes the disassembler. 44 /// 45 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) 46 : MCDisassembler(STI), RegInfo(Info) { 47 } 48 49 ~AArch64Disassembler() {} 50 51 /// See MCDisassembler. 52 DecodeStatus getInstruction(MCInst &instr, 53 uint64_t &size, 54 const MemoryObject ®ion, 55 uint64_t address, 56 raw_ostream &vStream, 57 raw_ostream &cStream) const; 58 59 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } 60 }; 61 62 } 63 64 // Forward-declarations used in the auto-generated files. 65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 66 uint64_t Address, const void *Decoder); 67 static DecodeStatus 68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 uint64_t Address, const void *Decoder); 70 71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 uint64_t Address, const void *Decoder); 73 static DecodeStatus 74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 uint64_t Address, const void *Decoder); 76 77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 78 uint64_t Address, const void *Decoder); 79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 80 uint64_t Address, const void *Decoder); 81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 82 uint64_t Address, const void *Decoder); 83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 84 uint64_t Address, const void *Decoder); 85 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 86 unsigned RegNo, uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, 89 unsigned RegNo, uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 93 unsigned OptionHiS, 94 uint64_t Address, 95 const void *Decoder); 96 97 98 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 99 unsigned Imm6Bits, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 104 unsigned Imm6Bits, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 109 unsigned RmBits, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 116 uint64_t Address, 117 const void *Decoder); 118 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 122 uint64_t Address, 123 const void *Decoder); 124 125 template<int RegWidth> 126 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 127 unsigned FullImm, 128 uint64_t Address, 129 const void *Decoder); 130 131 template<int RegWidth> 132 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 133 unsigned Bits, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 138 unsigned ShiftAmount, 139 uint64_t Address, 140 const void *Decoder); 141 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 142 static DecodeStatus 143 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 144 uint64_t Address, const void *Decoder); 145 146 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 147 unsigned ShiftAmount, 148 uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, 152 const void *Decoder); 153 154 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, 156 const void *Decoder); 157 158 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 159 unsigned Insn, 160 uint64_t Address, 161 const void *Decoder); 162 163 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 164 unsigned Val, 165 uint64_t Address, 166 const void *Decoder); 167 168 template<typename SomeNamedImmMapper> 169 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 170 unsigned Val, 171 uint64_t Address, 172 const void *Decoder); 173 174 static DecodeStatus 175 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper, 176 llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 179 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 180 unsigned Val, 181 uint64_t Address, 182 const void *Decoder); 183 184 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 185 unsigned Val, 186 uint64_t Address, 187 const void *Decoder); 188 189 190 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 191 unsigned Val, 192 uint64_t Address, 193 const void *Decoder); 194 195 196 static bool Check(DecodeStatus &Out, DecodeStatus In); 197 198 #include "AArch64GenDisassemblerTables.inc" 199 #include "AArch64GenInstrInfo.inc" 200 201 static bool Check(DecodeStatus &Out, DecodeStatus In) { 202 switch (In) { 203 case MCDisassembler::Success: 204 // Out stays the same. 205 return true; 206 case MCDisassembler::SoftFail: 207 Out = In; 208 return true; 209 case MCDisassembler::Fail: 210 Out = In; 211 return false; 212 } 213 llvm_unreachable("Invalid DecodeStatus!"); 214 } 215 216 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 217 const MemoryObject &Region, 218 uint64_t Address, 219 raw_ostream &os, 220 raw_ostream &cs) const { 221 CommentStream = &cs; 222 223 uint8_t bytes[4]; 224 225 // We want to read exactly 4 bytes of data. 226 if (Region.readBytes(Address, 4, bytes) == -1) { 227 Size = 0; 228 return MCDisassembler::Fail; 229 } 230 231 // Encoded as a small-endian 32-bit word in the stream. 232 uint32_t insn = (bytes[3] << 24) | 233 (bytes[2] << 16) | 234 (bytes[1] << 8) | 235 (bytes[0] << 0); 236 237 // Calling the auto-generated decoder function. 238 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, 239 this, STI); 240 if (result != MCDisassembler::Fail) { 241 Size = 4; 242 return result; 243 } 244 245 MI.clear(); 246 Size = 0; 247 return MCDisassembler::Fail; 248 } 249 250 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 251 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D); 252 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo); 253 } 254 255 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 256 uint64_t Address, const void *Decoder) { 257 if (RegNo > 31) 258 return MCDisassembler::Fail; 259 260 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo); 261 Inst.addOperand(MCOperand::CreateReg(Register)); 262 return MCDisassembler::Success; 263 } 264 265 static DecodeStatus 266 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 267 uint64_t Address, const void *Decoder) { 268 if (RegNo > 31) 269 return MCDisassembler::Fail; 270 271 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo); 272 Inst.addOperand(MCOperand::CreateReg(Register)); 273 return MCDisassembler::Success; 274 } 275 276 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 277 uint64_t Address, 278 const void *Decoder) { 279 if (RegNo > 31) 280 return MCDisassembler::Fail; 281 282 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo); 283 Inst.addOperand(MCOperand::CreateReg(Register)); 284 return MCDisassembler::Success; 285 } 286 287 static DecodeStatus 288 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 289 uint64_t Address, const void *Decoder) { 290 if (RegNo > 31) 291 return MCDisassembler::Fail; 292 293 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo); 294 Inst.addOperand(MCOperand::CreateReg(Register)); 295 return MCDisassembler::Success; 296 } 297 298 static DecodeStatus 299 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 300 uint64_t Address, const void *Decoder) { 301 if (RegNo > 31) 302 return MCDisassembler::Fail; 303 304 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo); 305 Inst.addOperand(MCOperand::CreateReg(Register)); 306 return MCDisassembler::Success; 307 } 308 309 static DecodeStatus 310 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 311 uint64_t Address, const void *Decoder) { 312 if (RegNo > 31) 313 return MCDisassembler::Fail; 314 315 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo); 316 Inst.addOperand(MCOperand::CreateReg(Register)); 317 return MCDisassembler::Success; 318 } 319 320 321 static DecodeStatus 322 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 323 uint64_t Address, const void *Decoder) { 324 if (RegNo > 31) 325 return MCDisassembler::Fail; 326 327 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo); 328 Inst.addOperand(MCOperand::CreateReg(Register)); 329 return MCDisassembler::Success; 330 } 331 332 static DecodeStatus 333 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 334 uint64_t Address, const void *Decoder) { 335 if (RegNo > 31) 336 return MCDisassembler::Fail; 337 338 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo); 339 Inst.addOperand(MCOperand::CreateReg(Register)); 340 return MCDisassembler::Success; 341 } 342 343 344 static DecodeStatus 345 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 346 uint64_t Address, const void *Decoder) { 347 if (RegNo > 31) 348 return MCDisassembler::Fail; 349 350 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo); 351 Inst.addOperand(MCOperand::CreateReg(Register)); 352 return MCDisassembler::Success; 353 } 354 355 static DecodeStatus 356 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 357 uint64_t Address, const void *Decoder) { 358 if (RegNo > 15) 359 return MCDisassembler::Fail; 360 361 return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder); 362 } 363 364 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 365 unsigned OptionHiS, 366 uint64_t Address, 367 const void *Decoder) { 368 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1}, 369 // S}. Hence we want to check bit 1. 370 if (!(OptionHiS & 2)) 371 return MCDisassembler::Fail; 372 373 Inst.addOperand(MCOperand::CreateImm(OptionHiS)); 374 return MCDisassembler::Success; 375 } 376 377 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 378 unsigned Imm6Bits, 379 uint64_t Address, 380 const void *Decoder) { 381 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be 382 // between 0 and 31. 383 if (Imm6Bits > 31) 384 return MCDisassembler::Fail; 385 386 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 387 return MCDisassembler::Success; 388 } 389 390 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 391 unsigned Imm6Bits, 392 uint64_t Address, 393 const void *Decoder) { 394 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32. 395 if (Imm6Bits < 32) 396 return MCDisassembler::Fail; 397 398 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 399 return MCDisassembler::Success; 400 } 401 402 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 403 unsigned RmBits, 404 uint64_t Address, 405 const void *Decoder) { 406 // Any bits are valid in the instruction (they're architecturally ignored), 407 // but a code generator should insert 0. 408 Inst.addOperand(MCOperand::CreateImm(0)); 409 return MCDisassembler::Success; 410 } 411 412 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 413 uint64_t Address, 414 const void *Decoder) { 415 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 416 return MCDisassembler::Success; 417 } 418 419 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 420 uint64_t Address, 421 const void *Decoder) { 422 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 423 return MCDisassembler::Success; 424 } 425 426 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 427 uint64_t Address, 428 const void *Decoder) { 429 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 430 return MCDisassembler::Success; 431 } 432 433 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 434 uint64_t Address, 435 const void *Decoder) { 436 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 437 return MCDisassembler::Success; 438 } 439 440 template<int RegWidth> 441 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 442 unsigned FullImm, 443 uint64_t Address, 444 const void *Decoder) { 445 unsigned Imm16 = FullImm & 0xffff; 446 unsigned Shift = FullImm >> 16; 447 448 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail; 449 450 Inst.addOperand(MCOperand::CreateImm(Imm16)); 451 Inst.addOperand(MCOperand::CreateImm(Shift)); 452 return MCDisassembler::Success; 453 } 454 455 template<int RegWidth> 456 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 457 unsigned Bits, 458 uint64_t Address, 459 const void *Decoder) { 460 uint64_t Imm; 461 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm)) 462 return MCDisassembler::Fail; 463 464 Inst.addOperand(MCOperand::CreateImm(Bits)); 465 return MCDisassembler::Success; 466 } 467 468 469 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 470 unsigned ShiftAmount, 471 uint64_t Address, 472 const void *Decoder) { 473 // Only values 0-4 are valid for this 3-bit field 474 if (ShiftAmount > 4) 475 return MCDisassembler::Fail; 476 477 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 478 return MCDisassembler::Success; 479 } 480 481 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 482 unsigned ShiftAmount, 483 uint64_t Address, 484 const void *Decoder) { 485 // Only values below 32 are valid for a 32-bit register 486 if (ShiftAmount > 31) 487 return MCDisassembler::Fail; 488 489 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 490 return MCDisassembler::Success; 491 } 492 493 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 494 uint64_t Address, 495 const void *Decoder) { 496 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 497 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 498 unsigned ImmS = fieldFromInstruction(Insn, 10, 6); 499 unsigned ImmR = fieldFromInstruction(Insn, 16, 6); 500 unsigned SF = fieldFromInstruction(Insn, 31, 1); 501 502 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise 503 // out assertions that it thinks should never be hit. 504 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; 505 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); 506 507 if (!SF) { 508 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions. 509 if (ImmR > 31 || ImmS > 31) 510 return MCDisassembler::Fail; 511 } 512 513 if (SF) { 514 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 515 // BFM MCInsts use Rd as a source too. 516 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 517 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 518 } else { 519 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 520 // BFM MCInsts use Rd as a source too. 521 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 522 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder); 523 } 524 525 // ASR and LSR have more specific patterns so they won't get here: 526 assert(!(ImmS == 31 && !SF && Opc != BFM) 527 && "shift should have used auto decode"); 528 assert(!(ImmS == 63 && SF && Opc != BFM) 529 && "shift should have used auto decode"); 530 531 // Extension instructions similarly: 532 if (Opc == SBFM && ImmR == 0) { 533 assert((ImmS != 7 && ImmS != 15) && "extension got here"); 534 assert((ImmS != 31 || SF == 0) && "extension got here"); 535 } else if (Opc == UBFM && ImmR == 0) { 536 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here"); 537 } 538 539 if (Opc == UBFM) { 540 // It might be a LSL instruction, which actually takes the shift amount 541 // itself as an MCInst operand. 542 if (SF && (ImmS + 1) % 64 == ImmR) { 543 Inst.setOpcode(AArch64::LSLxxi); 544 Inst.addOperand(MCOperand::CreateImm(63 - ImmS)); 545 return MCDisassembler::Success; 546 } else if (!SF && (ImmS + 1) % 32 == ImmR) { 547 Inst.setOpcode(AArch64::LSLwwi); 548 Inst.addOperand(MCOperand::CreateImm(31 - ImmS)); 549 return MCDisassembler::Success; 550 } 551 } 552 553 // Otherwise it's definitely either an extract or an insert depending on which 554 // of ImmR or ImmS is larger. 555 unsigned ExtractOp, InsertOp; 556 switch (Opc) { 557 default: llvm_unreachable("unexpected instruction trying to decode bitfield"); 558 case SBFM: 559 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii; 560 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii; 561 break; 562 case BFM: 563 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii; 564 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii; 565 break; 566 case UBFM: 567 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii; 568 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii; 569 break; 570 } 571 572 // Otherwise it's a boring insert or extract 573 Inst.addOperand(MCOperand::CreateImm(ImmR)); 574 Inst.addOperand(MCOperand::CreateImm(ImmS)); 575 576 577 if (ImmS < ImmR) 578 Inst.setOpcode(InsertOp); 579 else 580 Inst.setOpcode(ExtractOp); 581 582 return MCDisassembler::Success; 583 } 584 585 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 586 uint64_t Address, 587 const void *Decoder) { 588 // This decoder exists to add the dummy Lane operand to the MCInst, which must 589 // be 1 in assembly but has no other real manifestation. 590 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 591 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 592 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 593 594 if (IsToVec) { 595 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 596 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 597 } else { 598 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 599 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 600 } 601 602 // Add the lane 603 Inst.addOperand(MCOperand::CreateImm(1)); 604 605 return MCDisassembler::Success; 606 } 607 608 609 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 610 unsigned Insn, 611 uint64_t Address, 612 const void *Decoder) { 613 DecodeStatus Result = MCDisassembler::Success; 614 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 615 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 616 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5); 617 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7); 618 unsigned L = fieldFromInstruction(Insn, 22, 1); 619 unsigned V = fieldFromInstruction(Insn, 26, 1); 620 unsigned Opc = fieldFromInstruction(Insn, 30, 2); 621 622 // Not an official name, but it turns out that bit 23 distinguishes indexed 623 // from non-indexed operations. 624 unsigned Indexed = fieldFromInstruction(Insn, 23, 1); 625 626 if (Indexed && L == 0) { 627 // The MCInst for an indexed store has an out operand and 4 ins: 628 // Rn_wb, Rt, Rt2, Rn, Imm 629 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 630 } 631 632 // You shouldn't load to the same register twice in an instruction... 633 if (L && Rt == Rt2) 634 Result = MCDisassembler::SoftFail; 635 636 // ... or do any operation that writes-back to a transfer register. But note 637 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 638 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 639 Result = MCDisassembler::SoftFail; 640 641 // Exactly how we decode the MCInst's registers depends on the Opc and V 642 // fields of the instruction. These also obviously determine the size of the 643 // operation so we can fill in that information while we're at it. 644 if (V) { 645 // The instruction operates on the FP/SIMD registers 646 switch (Opc) { 647 default: return MCDisassembler::Fail; 648 case 0: 649 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 650 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder); 651 break; 652 case 1: 653 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 654 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder); 655 break; 656 case 2: 657 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 658 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder); 659 break; 660 } 661 } else { 662 switch (Opc) { 663 default: return MCDisassembler::Fail; 664 case 0: 665 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 666 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder); 667 break; 668 case 1: 669 assert(L && "unexpected \"store signed\" attempt"); 670 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 671 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 672 break; 673 case 2: 674 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 675 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 676 break; 677 } 678 } 679 680 if (Indexed && L == 1) { 681 // The MCInst for an indexed load has 3 out operands and an 3 ins: 682 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm 683 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 684 } 685 686 687 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 688 Inst.addOperand(MCOperand::CreateImm(SImm7)); 689 690 return Result; 691 } 692 693 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 694 uint32_t Val, 695 uint64_t Address, 696 const void *Decoder) { 697 unsigned Rt = fieldFromInstruction(Val, 0, 5); 698 unsigned Rn = fieldFromInstruction(Val, 5, 5); 699 unsigned Rt2 = fieldFromInstruction(Val, 10, 5); 700 unsigned MemSize = fieldFromInstruction(Val, 30, 2); 701 702 DecodeStatus S = MCDisassembler::Success; 703 if (Rt == Rt2) S = MCDisassembler::SoftFail; 704 705 switch (MemSize) { 706 case 2: 707 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder))) 708 return MCDisassembler::Fail; 709 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder))) 710 return MCDisassembler::Fail; 711 break; 712 case 3: 713 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder))) 714 return MCDisassembler::Fail; 715 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder))) 716 return MCDisassembler::Fail; 717 break; 718 default: 719 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction"); 720 } 721 722 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder))) 723 return MCDisassembler::Fail; 724 725 return S; 726 } 727 728 template<typename SomeNamedImmMapper> 729 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 730 unsigned Val, 731 uint64_t Address, 732 const void *Decoder) { 733 SomeNamedImmMapper Mapper; 734 bool ValidNamed; 735 Mapper.toString(Val, ValidNamed); 736 if (ValidNamed || Mapper.validImm(Val)) { 737 Inst.addOperand(MCOperand::CreateImm(Val)); 738 return MCDisassembler::Success; 739 } 740 741 return MCDisassembler::Fail; 742 } 743 744 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, 745 llvm::MCInst &Inst, 746 unsigned Val, 747 uint64_t Address, 748 const void *Decoder) { 749 bool ValidNamed; 750 Mapper.toString(Val, ValidNamed); 751 752 Inst.addOperand(MCOperand::CreateImm(Val)); 753 754 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail; 755 } 756 757 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 758 unsigned Val, 759 uint64_t Address, 760 const void *Decoder) { 761 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address, 762 Decoder); 763 } 764 765 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 766 unsigned Val, 767 uint64_t Address, 768 const void *Decoder) { 769 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address, 770 Decoder); 771 } 772 773 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 774 unsigned Insn, 775 uint64_t Address, 776 const void *Decoder) { 777 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 778 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 779 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9); 780 781 unsigned Opc = fieldFromInstruction(Insn, 22, 2); 782 unsigned V = fieldFromInstruction(Insn, 26, 1); 783 unsigned Size = fieldFromInstruction(Insn, 30, 2); 784 785 if (Opc == 0 || (V == 1 && Opc == 2)) { 786 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm 787 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 788 } 789 790 if (V == 0 && (Opc == 2 || Size == 3)) { 791 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 792 } else if (V == 0) { 793 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 794 } else if (V == 1 && (Opc & 2)) { 795 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 796 } else { 797 switch (Size) { 798 case 0: 799 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder); 800 break; 801 case 1: 802 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder); 803 break; 804 case 2: 805 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 806 break; 807 case 3: 808 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 809 break; 810 } 811 } 812 813 if (Opc != 0 && (V != 1 || Opc != 2)) { 814 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm 815 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 816 } 817 818 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 819 820 Inst.addOperand(MCOperand::CreateImm(Imm9)); 821 822 // N.b. The official documentation says undpredictable if Rt == Rn, but this 823 // takes place at the architectural rather than encoding level: 824 // 825 // "STR xzr, [sp], #4" is perfectly valid. 826 if (V == 0 && Rt == Rn && Rn != 31) 827 return MCDisassembler::SoftFail; 828 else 829 return MCDisassembler::Success; 830 } 831 832 static MCDisassembler *createAArch64Disassembler(const Target &T, 833 const MCSubtargetInfo &STI) { 834 return new AArch64Disassembler(STI, T.createMCRegInfo("")); 835 } 836 837 extern "C" void LLVMInitializeAArch64Disassembler() { 838 TargetRegistry::RegisterMCDisassembler(TheAArch64Target, 839 createAArch64Disassembler); 840 } 841 842 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 843 static DecodeStatus 844 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 845 uint64_t Address, const void *Decoder) { 846 bool IsLSL = false; 847 if (Ext == A64SE::LSL) 848 IsLSL = true; 849 else if (Ext != A64SE::MSL) 850 return MCDisassembler::Fail; 851 852 // MSL and LSLH accepts encoded shift amount 0 or 1. 853 if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1) 854 return MCDisassembler::Fail; 855 856 // LSL accepts encoded shift amount 0, 1, 2 or 3. 857 if (IsLSL && ShiftAmount > 3) 858 return MCDisassembler::Fail; 859 860 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 861 return MCDisassembler::Success; 862 } 863