1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm-c/Disassembler.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include <algorithm> 28 #include <memory> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "aarch64-disassembler" 33 34 // Pull DecodeStatus and its enum values into the global namespace. 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 // Forward declare these because the autogenerated code will reference them. 38 // Definitions are further down. 39 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 40 unsigned RegNo, uint64_t Address, 41 const void *Decoder); 42 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 43 unsigned RegNo, 44 uint64_t Address, 45 const void *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const void *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const void *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const void *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const void *Decoder); 58 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 59 uint64_t Address, 60 const void *Decoder); 61 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 62 unsigned RegNo, uint64_t Address, 63 const void *Decoder); 64 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 65 uint64_t Address, 66 const void *Decoder); 67 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 68 unsigned RegNo, uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decode); 91 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decode); 94 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decode); 97 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decode); 100 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decode); 103 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decode); 106 107 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 108 uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 111 uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 134 uint64_t Address, 135 const void *Decoder); 136 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 137 uint64_t Address, 138 const void *Decoder); 139 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 140 uint64_t Address, 141 const void *Decoder); 142 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 143 uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 162 uint64_t Address, const void *Decoder); 163 164 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 168 uint64_t Addr, const void *Decoder); 169 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 170 uint64_t Addr, 171 const void *Decoder); 172 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 173 uint64_t Addr, const void *Decoder); 174 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 175 uint64_t Addr, 176 const void *Decoder); 177 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, const void *Decoder); 179 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 180 uint64_t Addr, 181 const void *Decoder); 182 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 183 uint64_t Addr, const void *Decoder); 184 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, const void *Decoder); 186 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 187 uint64_t Addr, const void *Decoder); 188 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 189 uint64_t Addr, const void *Decoder); 190 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 191 uint64_t Addr, const void *Decoder); 192 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 193 unsigned RegNo, 194 uint64_t Addr, 195 const void *Decoder); 196 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 197 unsigned RegNo, 198 uint64_t Addr, 199 const void *Decoder); 200 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 201 uint32_t insn, 202 uint64_t Address, 203 const void *Decoder); 204 template<int Bits> 205 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 206 uint64_t Address, const void *Decoder); 207 208 static bool Check(DecodeStatus &Out, DecodeStatus In) { 209 switch (In) { 210 case MCDisassembler::Success: 211 // Out stays the same. 212 return true; 213 case MCDisassembler::SoftFail: 214 Out = In; 215 return true; 216 case MCDisassembler::Fail: 217 Out = In; 218 return false; 219 } 220 llvm_unreachable("Invalid DecodeStatus!"); 221 } 222 223 #include "AArch64GenDisassemblerTables.inc" 224 #include "AArch64GenInstrInfo.inc" 225 226 #define Success MCDisassembler::Success 227 #define Fail MCDisassembler::Fail 228 #define SoftFail MCDisassembler::SoftFail 229 230 static MCDisassembler *createAArch64Disassembler(const Target &T, 231 const MCSubtargetInfo &STI, 232 MCContext &Ctx) { 233 return new AArch64Disassembler(STI, Ctx); 234 } 235 236 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 237 ArrayRef<uint8_t> Bytes, 238 uint64_t Address, 239 raw_ostream &OS, 240 raw_ostream &CS) const { 241 CommentStream = &CS; 242 243 Size = 0; 244 // We want to read exactly 4 bytes of data. 245 if (Bytes.size() < 4) 246 return Fail; 247 Size = 4; 248 249 // Encoded as a small-endian 32-bit word in the stream. 250 uint32_t Insn = 251 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 252 253 // Calling the auto-generated decoder function. 254 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 255 } 256 257 static MCSymbolizer * 258 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 259 LLVMSymbolLookupCallback SymbolLookUp, 260 void *DisInfo, MCContext *Ctx, 261 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 262 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 263 SymbolLookUp, DisInfo); 264 } 265 266 extern "C" void LLVMInitializeAArch64Disassembler() { 267 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 268 createAArch64Disassembler); 269 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 270 createAArch64Disassembler); 271 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 272 createAArch64ExternalSymbolizer); 273 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 274 createAArch64ExternalSymbolizer); 275 276 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 277 createAArch64Disassembler); 278 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 279 createAArch64ExternalSymbolizer); 280 } 281 282 static const unsigned FPR128DecoderTable[] = { 283 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 284 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 285 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 286 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 287 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 288 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 289 AArch64::Q30, AArch64::Q31 290 }; 291 292 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 293 uint64_t Addr, 294 const void *Decoder) { 295 if (RegNo > 31) 296 return Fail; 297 298 unsigned Register = FPR128DecoderTable[RegNo]; 299 Inst.addOperand(MCOperand::createReg(Register)); 300 return Success; 301 } 302 303 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 304 uint64_t Addr, 305 const void *Decoder) { 306 if (RegNo > 15) 307 return Fail; 308 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 309 } 310 311 static const unsigned FPR64DecoderTable[] = { 312 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 313 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 314 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 315 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 316 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 317 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 318 AArch64::D30, AArch64::D31 319 }; 320 321 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 322 uint64_t Addr, 323 const void *Decoder) { 324 if (RegNo > 31) 325 return Fail; 326 327 unsigned Register = FPR64DecoderTable[RegNo]; 328 Inst.addOperand(MCOperand::createReg(Register)); 329 return Success; 330 } 331 332 static const unsigned FPR32DecoderTable[] = { 333 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 334 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 335 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 336 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 337 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 338 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 339 AArch64::S30, AArch64::S31 340 }; 341 342 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 343 uint64_t Addr, 344 const void *Decoder) { 345 if (RegNo > 31) 346 return Fail; 347 348 unsigned Register = FPR32DecoderTable[RegNo]; 349 Inst.addOperand(MCOperand::createReg(Register)); 350 return Success; 351 } 352 353 static const unsigned FPR16DecoderTable[] = { 354 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 355 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 356 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 357 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 358 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 359 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 360 AArch64::H30, AArch64::H31 361 }; 362 363 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 364 uint64_t Addr, 365 const void *Decoder) { 366 if (RegNo > 31) 367 return Fail; 368 369 unsigned Register = FPR16DecoderTable[RegNo]; 370 Inst.addOperand(MCOperand::createReg(Register)); 371 return Success; 372 } 373 374 static const unsigned FPR8DecoderTable[] = { 375 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 376 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 377 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 378 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 379 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 380 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 381 AArch64::B30, AArch64::B31 382 }; 383 384 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 385 uint64_t Addr, 386 const void *Decoder) { 387 if (RegNo > 31) 388 return Fail; 389 390 unsigned Register = FPR8DecoderTable[RegNo]; 391 Inst.addOperand(MCOperand::createReg(Register)); 392 return Success; 393 } 394 395 static const unsigned GPR64DecoderTable[] = { 396 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 397 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 398 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 399 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 400 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 401 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 402 AArch64::LR, AArch64::XZR 403 }; 404 405 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 406 uint64_t Addr, 407 const void *Decoder) { 408 if (RegNo > 31) 409 return Fail; 410 411 unsigned Register = GPR64DecoderTable[RegNo]; 412 Inst.addOperand(MCOperand::createReg(Register)); 413 return Success; 414 } 415 416 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 417 uint64_t Addr, 418 const void *Decoder) { 419 if (RegNo > 31) 420 return Fail; 421 unsigned Register = GPR64DecoderTable[RegNo]; 422 if (Register == AArch64::XZR) 423 Register = AArch64::SP; 424 Inst.addOperand(MCOperand::createReg(Register)); 425 return Success; 426 } 427 428 static const unsigned GPR32DecoderTable[] = { 429 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 430 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 431 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 432 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 433 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 434 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 435 AArch64::W30, AArch64::WZR 436 }; 437 438 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 439 uint64_t Addr, 440 const void *Decoder) { 441 if (RegNo > 31) 442 return Fail; 443 444 unsigned Register = GPR32DecoderTable[RegNo]; 445 Inst.addOperand(MCOperand::createReg(Register)); 446 return Success; 447 } 448 449 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 450 uint64_t Addr, 451 const void *Decoder) { 452 if (RegNo > 31) 453 return Fail; 454 455 unsigned Register = GPR32DecoderTable[RegNo]; 456 if (Register == AArch64::WZR) 457 Register = AArch64::WSP; 458 Inst.addOperand(MCOperand::createReg(Register)); 459 return Success; 460 } 461 static const unsigned ZPRDecoderTable[] = { 462 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 463 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 464 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 465 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 466 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 467 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 468 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 469 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 470 }; 471 472 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 473 uint64_t Address, 474 const void* Decoder) { 475 if (RegNo > 31) 476 return Fail; 477 478 unsigned Register = ZPRDecoderTable[RegNo]; 479 Inst.addOperand(MCOperand::createReg(Register)); 480 return Success; 481 } 482 483 static const unsigned ZZDecoderTable[] = { 484 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 485 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 486 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 487 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 488 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 489 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 490 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 491 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 492 }; 493 494 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 495 uint64_t Address, 496 const void* Decoder) { 497 if (RegNo > 31) 498 return Fail; 499 unsigned Register = ZZDecoderTable[RegNo]; 500 Inst.addOperand(MCOperand::createReg(Register)); 501 return Success; 502 } 503 504 static const unsigned ZZZDecoderTable[] = { 505 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 506 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 507 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 508 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 509 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 510 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 511 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 512 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 513 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 514 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 515 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 516 }; 517 518 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 519 uint64_t Address, 520 const void* Decoder) { 521 if (RegNo > 31) 522 return Fail; 523 unsigned Register = ZZZDecoderTable[RegNo]; 524 Inst.addOperand(MCOperand::createReg(Register)); 525 return Success; 526 } 527 528 static const unsigned ZZZZDecoderTable[] = { 529 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 530 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 531 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 532 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 533 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 534 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 535 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 536 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 537 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 538 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 539 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 540 }; 541 542 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 543 uint64_t Address, 544 const void* Decoder) { 545 if (RegNo > 31) 546 return Fail; 547 unsigned Register = ZZZZDecoderTable[RegNo]; 548 Inst.addOperand(MCOperand::createReg(Register)); 549 return Success; 550 } 551 552 static const unsigned PPRDecoderTable[] = { 553 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 554 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 555 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 556 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 557 }; 558 559 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 560 uint64_t Addr, const void *Decoder) { 561 if (RegNo > 15) 562 return Fail; 563 564 unsigned Register = PPRDecoderTable[RegNo]; 565 Inst.addOperand(MCOperand::createReg(Register)); 566 return Success; 567 } 568 569 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 570 uint64_t Addr, 571 const void* Decoder) { 572 if (RegNo > 7) 573 return Fail; 574 575 // Just reuse the PPR decode table 576 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 577 } 578 579 static const unsigned VectorDecoderTable[] = { 580 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 581 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 582 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 583 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 584 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 585 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 586 AArch64::Q30, AArch64::Q31 587 }; 588 589 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 590 uint64_t Addr, 591 const void *Decoder) { 592 if (RegNo > 31) 593 return Fail; 594 595 unsigned Register = VectorDecoderTable[RegNo]; 596 Inst.addOperand(MCOperand::createReg(Register)); 597 return Success; 598 } 599 600 static const unsigned QQDecoderTable[] = { 601 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 602 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 603 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 604 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 605 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 606 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 607 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 608 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 609 }; 610 611 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 612 uint64_t Addr, const void *Decoder) { 613 if (RegNo > 31) 614 return Fail; 615 unsigned Register = QQDecoderTable[RegNo]; 616 Inst.addOperand(MCOperand::createReg(Register)); 617 return Success; 618 } 619 620 static const unsigned QQQDecoderTable[] = { 621 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 622 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 623 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 624 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 625 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 626 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 627 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 628 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 629 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 630 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 631 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 632 }; 633 634 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 635 uint64_t Addr, const void *Decoder) { 636 if (RegNo > 31) 637 return Fail; 638 unsigned Register = QQQDecoderTable[RegNo]; 639 Inst.addOperand(MCOperand::createReg(Register)); 640 return Success; 641 } 642 643 static const unsigned QQQQDecoderTable[] = { 644 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 645 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 646 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 647 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 648 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 649 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 650 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 651 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 652 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 653 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 654 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 655 }; 656 657 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 658 uint64_t Addr, 659 const void *Decoder) { 660 if (RegNo > 31) 661 return Fail; 662 unsigned Register = QQQQDecoderTable[RegNo]; 663 Inst.addOperand(MCOperand::createReg(Register)); 664 return Success; 665 } 666 667 static const unsigned DDDecoderTable[] = { 668 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 669 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 670 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 671 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 672 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 673 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 674 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 675 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 676 }; 677 678 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 679 uint64_t Addr, const void *Decoder) { 680 if (RegNo > 31) 681 return Fail; 682 unsigned Register = DDDecoderTable[RegNo]; 683 Inst.addOperand(MCOperand::createReg(Register)); 684 return Success; 685 } 686 687 static const unsigned DDDDecoderTable[] = { 688 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 689 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 690 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 691 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 692 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 693 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 694 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 695 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 696 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 697 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 698 AArch64::D30_D31_D0, AArch64::D31_D0_D1 699 }; 700 701 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 702 uint64_t Addr, const void *Decoder) { 703 if (RegNo > 31) 704 return Fail; 705 unsigned Register = DDDDecoderTable[RegNo]; 706 Inst.addOperand(MCOperand::createReg(Register)); 707 return Success; 708 } 709 710 static const unsigned DDDDDecoderTable[] = { 711 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 712 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 713 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 714 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 715 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 716 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 717 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 718 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 719 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 720 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 721 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 722 }; 723 724 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 725 uint64_t Addr, 726 const void *Decoder) { 727 if (RegNo > 31) 728 return Fail; 729 unsigned Register = DDDDDecoderTable[RegNo]; 730 Inst.addOperand(MCOperand::createReg(Register)); 731 return Success; 732 } 733 734 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 735 uint64_t Addr, 736 const void *Decoder) { 737 // scale{5} is asserted as 1 in tblgen. 738 Imm |= 0x20; 739 Inst.addOperand(MCOperand::createImm(64 - Imm)); 740 return Success; 741 } 742 743 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 744 uint64_t Addr, 745 const void *Decoder) { 746 Inst.addOperand(MCOperand::createImm(64 - Imm)); 747 return Success; 748 } 749 750 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 751 uint64_t Addr, const void *Decoder) { 752 int64_t ImmVal = Imm; 753 const AArch64Disassembler *Dis = 754 static_cast<const AArch64Disassembler *>(Decoder); 755 756 // Sign-extend 19-bit immediate. 757 if (ImmVal & (1 << (19 - 1))) 758 ImmVal |= ~((1LL << 19) - 1); 759 760 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 761 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 762 Inst.addOperand(MCOperand::createImm(ImmVal)); 763 return Success; 764 } 765 766 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 767 uint64_t Address, const void *Decoder) { 768 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 769 Inst.addOperand(MCOperand::createImm(Imm & 1)); 770 return Success; 771 } 772 773 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 774 uint64_t Address, 775 const void *Decoder) { 776 Inst.addOperand(MCOperand::createImm(Imm)); 777 778 // Every system register in the encoding space is valid with the syntax 779 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 780 return Success; 781 } 782 783 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 784 uint64_t Address, 785 const void *Decoder) { 786 Inst.addOperand(MCOperand::createImm(Imm)); 787 788 return Success; 789 } 790 791 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 792 uint64_t Address, 793 const void *Decoder) { 794 // This decoder exists to add the dummy Lane operand to the MCInst, which must 795 // be 1 in assembly but has no other real manifestation. 796 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 797 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 798 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 799 800 if (IsToVec) { 801 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 802 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 803 } else { 804 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 805 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 806 } 807 808 // Add the lane 809 Inst.addOperand(MCOperand::createImm(1)); 810 811 return Success; 812 } 813 814 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 815 unsigned Add) { 816 Inst.addOperand(MCOperand::createImm(Add - Imm)); 817 return Success; 818 } 819 820 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 821 unsigned Add) { 822 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 823 return Success; 824 } 825 826 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 827 uint64_t Addr, const void *Decoder) { 828 return DecodeVecShiftRImm(Inst, Imm, 64); 829 } 830 831 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 832 uint64_t Addr, 833 const void *Decoder) { 834 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 835 } 836 837 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 838 uint64_t Addr, const void *Decoder) { 839 return DecodeVecShiftRImm(Inst, Imm, 32); 840 } 841 842 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 843 uint64_t Addr, 844 const void *Decoder) { 845 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 846 } 847 848 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 849 uint64_t Addr, const void *Decoder) { 850 return DecodeVecShiftRImm(Inst, Imm, 16); 851 } 852 853 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 854 uint64_t Addr, 855 const void *Decoder) { 856 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 857 } 858 859 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 860 uint64_t Addr, const void *Decoder) { 861 return DecodeVecShiftRImm(Inst, Imm, 8); 862 } 863 864 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 865 uint64_t Addr, const void *Decoder) { 866 return DecodeVecShiftLImm(Inst, Imm, 64); 867 } 868 869 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 870 uint64_t Addr, const void *Decoder) { 871 return DecodeVecShiftLImm(Inst, Imm, 32); 872 } 873 874 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 875 uint64_t Addr, const void *Decoder) { 876 return DecodeVecShiftLImm(Inst, Imm, 16); 877 } 878 879 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 880 uint64_t Addr, const void *Decoder) { 881 return DecodeVecShiftLImm(Inst, Imm, 8); 882 } 883 884 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 885 uint64_t Addr, 886 const void *Decoder) { 887 unsigned Rd = fieldFromInstruction(insn, 0, 5); 888 unsigned Rn = fieldFromInstruction(insn, 5, 5); 889 unsigned Rm = fieldFromInstruction(insn, 16, 5); 890 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 891 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 892 unsigned shift = (shiftHi << 6) | shiftLo; 893 switch (Inst.getOpcode()) { 894 default: 895 return Fail; 896 case AArch64::ADDWrs: 897 case AArch64::ADDSWrs: 898 case AArch64::SUBWrs: 899 case AArch64::SUBSWrs: 900 // if shift == '11' then ReservedValue() 901 if (shiftHi == 0x3) 902 return Fail; 903 LLVM_FALLTHROUGH; 904 case AArch64::ANDWrs: 905 case AArch64::ANDSWrs: 906 case AArch64::BICWrs: 907 case AArch64::BICSWrs: 908 case AArch64::ORRWrs: 909 case AArch64::ORNWrs: 910 case AArch64::EORWrs: 911 case AArch64::EONWrs: { 912 // if sf == '0' and imm6<5> == '1' then ReservedValue() 913 if (shiftLo >> 5 == 1) 914 return Fail; 915 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 916 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 917 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 918 break; 919 } 920 case AArch64::ADDXrs: 921 case AArch64::ADDSXrs: 922 case AArch64::SUBXrs: 923 case AArch64::SUBSXrs: 924 // if shift == '11' then ReservedValue() 925 if (shiftHi == 0x3) 926 return Fail; 927 LLVM_FALLTHROUGH; 928 case AArch64::ANDXrs: 929 case AArch64::ANDSXrs: 930 case AArch64::BICXrs: 931 case AArch64::BICSXrs: 932 case AArch64::ORRXrs: 933 case AArch64::ORNXrs: 934 case AArch64::EORXrs: 935 case AArch64::EONXrs: 936 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 937 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 938 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 939 break; 940 } 941 942 Inst.addOperand(MCOperand::createImm(shift)); 943 return Success; 944 } 945 946 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 947 uint64_t Addr, 948 const void *Decoder) { 949 unsigned Rd = fieldFromInstruction(insn, 0, 5); 950 unsigned imm = fieldFromInstruction(insn, 5, 16); 951 unsigned shift = fieldFromInstruction(insn, 21, 2); 952 shift <<= 4; 953 switch (Inst.getOpcode()) { 954 default: 955 return Fail; 956 case AArch64::MOVZWi: 957 case AArch64::MOVNWi: 958 case AArch64::MOVKWi: 959 if (shift & (1U << 5)) 960 return Fail; 961 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 962 break; 963 case AArch64::MOVZXi: 964 case AArch64::MOVNXi: 965 case AArch64::MOVKXi: 966 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 967 break; 968 } 969 970 if (Inst.getOpcode() == AArch64::MOVKWi || 971 Inst.getOpcode() == AArch64::MOVKXi) 972 Inst.addOperand(Inst.getOperand(0)); 973 974 Inst.addOperand(MCOperand::createImm(imm)); 975 Inst.addOperand(MCOperand::createImm(shift)); 976 return Success; 977 } 978 979 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 980 uint64_t Addr, 981 const void *Decoder) { 982 unsigned Rt = fieldFromInstruction(insn, 0, 5); 983 unsigned Rn = fieldFromInstruction(insn, 5, 5); 984 unsigned offset = fieldFromInstruction(insn, 10, 12); 985 const AArch64Disassembler *Dis = 986 static_cast<const AArch64Disassembler *>(Decoder); 987 988 switch (Inst.getOpcode()) { 989 default: 990 return Fail; 991 case AArch64::PRFMui: 992 // Rt is an immediate in prefetch. 993 Inst.addOperand(MCOperand::createImm(Rt)); 994 break; 995 case AArch64::STRBBui: 996 case AArch64::LDRBBui: 997 case AArch64::LDRSBWui: 998 case AArch64::STRHHui: 999 case AArch64::LDRHHui: 1000 case AArch64::LDRSHWui: 1001 case AArch64::STRWui: 1002 case AArch64::LDRWui: 1003 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1004 break; 1005 case AArch64::LDRSBXui: 1006 case AArch64::LDRSHXui: 1007 case AArch64::LDRSWui: 1008 case AArch64::STRXui: 1009 case AArch64::LDRXui: 1010 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1011 break; 1012 case AArch64::LDRQui: 1013 case AArch64::STRQui: 1014 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1015 break; 1016 case AArch64::LDRDui: 1017 case AArch64::STRDui: 1018 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1019 break; 1020 case AArch64::LDRSui: 1021 case AArch64::STRSui: 1022 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1023 break; 1024 case AArch64::LDRHui: 1025 case AArch64::STRHui: 1026 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1027 break; 1028 case AArch64::LDRBui: 1029 case AArch64::STRBui: 1030 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1031 break; 1032 } 1033 1034 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1035 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1036 Inst.addOperand(MCOperand::createImm(offset)); 1037 return Success; 1038 } 1039 1040 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1041 uint64_t Addr, 1042 const void *Decoder) { 1043 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1044 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1045 int64_t offset = fieldFromInstruction(insn, 12, 9); 1046 1047 // offset is a 9-bit signed immediate, so sign extend it to 1048 // fill the unsigned. 1049 if (offset & (1 << (9 - 1))) 1050 offset |= ~((1LL << 9) - 1); 1051 1052 // First operand is always the writeback to the address register, if needed. 1053 switch (Inst.getOpcode()) { 1054 default: 1055 break; 1056 case AArch64::LDRSBWpre: 1057 case AArch64::LDRSHWpre: 1058 case AArch64::STRBBpre: 1059 case AArch64::LDRBBpre: 1060 case AArch64::STRHHpre: 1061 case AArch64::LDRHHpre: 1062 case AArch64::STRWpre: 1063 case AArch64::LDRWpre: 1064 case AArch64::LDRSBWpost: 1065 case AArch64::LDRSHWpost: 1066 case AArch64::STRBBpost: 1067 case AArch64::LDRBBpost: 1068 case AArch64::STRHHpost: 1069 case AArch64::LDRHHpost: 1070 case AArch64::STRWpost: 1071 case AArch64::LDRWpost: 1072 case AArch64::LDRSBXpre: 1073 case AArch64::LDRSHXpre: 1074 case AArch64::STRXpre: 1075 case AArch64::LDRSWpre: 1076 case AArch64::LDRXpre: 1077 case AArch64::LDRSBXpost: 1078 case AArch64::LDRSHXpost: 1079 case AArch64::STRXpost: 1080 case AArch64::LDRSWpost: 1081 case AArch64::LDRXpost: 1082 case AArch64::LDRQpre: 1083 case AArch64::STRQpre: 1084 case AArch64::LDRQpost: 1085 case AArch64::STRQpost: 1086 case AArch64::LDRDpre: 1087 case AArch64::STRDpre: 1088 case AArch64::LDRDpost: 1089 case AArch64::STRDpost: 1090 case AArch64::LDRSpre: 1091 case AArch64::STRSpre: 1092 case AArch64::LDRSpost: 1093 case AArch64::STRSpost: 1094 case AArch64::LDRHpre: 1095 case AArch64::STRHpre: 1096 case AArch64::LDRHpost: 1097 case AArch64::STRHpost: 1098 case AArch64::LDRBpre: 1099 case AArch64::STRBpre: 1100 case AArch64::LDRBpost: 1101 case AArch64::STRBpost: 1102 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1103 break; 1104 } 1105 1106 switch (Inst.getOpcode()) { 1107 default: 1108 return Fail; 1109 case AArch64::PRFUMi: 1110 // Rt is an immediate in prefetch. 1111 Inst.addOperand(MCOperand::createImm(Rt)); 1112 break; 1113 case AArch64::STURBBi: 1114 case AArch64::LDURBBi: 1115 case AArch64::LDURSBWi: 1116 case AArch64::STURHHi: 1117 case AArch64::LDURHHi: 1118 case AArch64::LDURSHWi: 1119 case AArch64::STURWi: 1120 case AArch64::LDURWi: 1121 case AArch64::LDTRSBWi: 1122 case AArch64::LDTRSHWi: 1123 case AArch64::STTRWi: 1124 case AArch64::LDTRWi: 1125 case AArch64::STTRHi: 1126 case AArch64::LDTRHi: 1127 case AArch64::LDTRBi: 1128 case AArch64::STTRBi: 1129 case AArch64::LDRSBWpre: 1130 case AArch64::LDRSHWpre: 1131 case AArch64::STRBBpre: 1132 case AArch64::LDRBBpre: 1133 case AArch64::STRHHpre: 1134 case AArch64::LDRHHpre: 1135 case AArch64::STRWpre: 1136 case AArch64::LDRWpre: 1137 case AArch64::LDRSBWpost: 1138 case AArch64::LDRSHWpost: 1139 case AArch64::STRBBpost: 1140 case AArch64::LDRBBpost: 1141 case AArch64::STRHHpost: 1142 case AArch64::LDRHHpost: 1143 case AArch64::STRWpost: 1144 case AArch64::LDRWpost: 1145 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1146 break; 1147 case AArch64::LDURSBXi: 1148 case AArch64::LDURSHXi: 1149 case AArch64::LDURSWi: 1150 case AArch64::STURXi: 1151 case AArch64::LDURXi: 1152 case AArch64::LDTRSBXi: 1153 case AArch64::LDTRSHXi: 1154 case AArch64::LDTRSWi: 1155 case AArch64::STTRXi: 1156 case AArch64::LDTRXi: 1157 case AArch64::LDRSBXpre: 1158 case AArch64::LDRSHXpre: 1159 case AArch64::STRXpre: 1160 case AArch64::LDRSWpre: 1161 case AArch64::LDRXpre: 1162 case AArch64::LDRSBXpost: 1163 case AArch64::LDRSHXpost: 1164 case AArch64::STRXpost: 1165 case AArch64::LDRSWpost: 1166 case AArch64::LDRXpost: 1167 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1168 break; 1169 case AArch64::LDURQi: 1170 case AArch64::STURQi: 1171 case AArch64::LDRQpre: 1172 case AArch64::STRQpre: 1173 case AArch64::LDRQpost: 1174 case AArch64::STRQpost: 1175 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1176 break; 1177 case AArch64::LDURDi: 1178 case AArch64::STURDi: 1179 case AArch64::LDRDpre: 1180 case AArch64::STRDpre: 1181 case AArch64::LDRDpost: 1182 case AArch64::STRDpost: 1183 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1184 break; 1185 case AArch64::LDURSi: 1186 case AArch64::STURSi: 1187 case AArch64::LDRSpre: 1188 case AArch64::STRSpre: 1189 case AArch64::LDRSpost: 1190 case AArch64::STRSpost: 1191 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1192 break; 1193 case AArch64::LDURHi: 1194 case AArch64::STURHi: 1195 case AArch64::LDRHpre: 1196 case AArch64::STRHpre: 1197 case AArch64::LDRHpost: 1198 case AArch64::STRHpost: 1199 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1200 break; 1201 case AArch64::LDURBi: 1202 case AArch64::STURBi: 1203 case AArch64::LDRBpre: 1204 case AArch64::STRBpre: 1205 case AArch64::LDRBpost: 1206 case AArch64::STRBpost: 1207 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1208 break; 1209 } 1210 1211 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1212 Inst.addOperand(MCOperand::createImm(offset)); 1213 1214 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1215 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1216 bool IsFP = fieldFromInstruction(insn, 26, 1); 1217 1218 // Cannot write back to a transfer register (but xzr != sp). 1219 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1220 return SoftFail; 1221 1222 return Success; 1223 } 1224 1225 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1226 uint64_t Addr, 1227 const void *Decoder) { 1228 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1229 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1230 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1231 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1232 1233 unsigned Opcode = Inst.getOpcode(); 1234 switch (Opcode) { 1235 default: 1236 return Fail; 1237 case AArch64::STLXRW: 1238 case AArch64::STLXRB: 1239 case AArch64::STLXRH: 1240 case AArch64::STXRW: 1241 case AArch64::STXRB: 1242 case AArch64::STXRH: 1243 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1244 LLVM_FALLTHROUGH; 1245 case AArch64::LDARW: 1246 case AArch64::LDARB: 1247 case AArch64::LDARH: 1248 case AArch64::LDAXRW: 1249 case AArch64::LDAXRB: 1250 case AArch64::LDAXRH: 1251 case AArch64::LDXRW: 1252 case AArch64::LDXRB: 1253 case AArch64::LDXRH: 1254 case AArch64::STLRW: 1255 case AArch64::STLRB: 1256 case AArch64::STLRH: 1257 case AArch64::STLLRW: 1258 case AArch64::STLLRB: 1259 case AArch64::STLLRH: 1260 case AArch64::LDLARW: 1261 case AArch64::LDLARB: 1262 case AArch64::LDLARH: 1263 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1264 break; 1265 case AArch64::STLXRX: 1266 case AArch64::STXRX: 1267 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1268 LLVM_FALLTHROUGH; 1269 case AArch64::LDARX: 1270 case AArch64::LDAXRX: 1271 case AArch64::LDXRX: 1272 case AArch64::STLRX: 1273 case AArch64::LDLARX: 1274 case AArch64::STLLRX: 1275 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1276 break; 1277 case AArch64::STLXPW: 1278 case AArch64::STXPW: 1279 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1280 LLVM_FALLTHROUGH; 1281 case AArch64::LDAXPW: 1282 case AArch64::LDXPW: 1283 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1284 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1285 break; 1286 case AArch64::STLXPX: 1287 case AArch64::STXPX: 1288 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1289 LLVM_FALLTHROUGH; 1290 case AArch64::LDAXPX: 1291 case AArch64::LDXPX: 1292 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1293 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1294 break; 1295 } 1296 1297 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1298 1299 // You shouldn't load to the same register twice in an instruction... 1300 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1301 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1302 Rt == Rt2) 1303 return SoftFail; 1304 1305 return Success; 1306 } 1307 1308 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1309 uint64_t Addr, 1310 const void *Decoder) { 1311 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1312 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1313 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1314 int64_t offset = fieldFromInstruction(insn, 15, 7); 1315 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1316 1317 // offset is a 7-bit signed immediate, so sign extend it to 1318 // fill the unsigned. 1319 if (offset & (1 << (7 - 1))) 1320 offset |= ~((1LL << 7) - 1); 1321 1322 unsigned Opcode = Inst.getOpcode(); 1323 bool NeedsDisjointWritebackTransfer = false; 1324 1325 // First operand is always writeback of base register. 1326 switch (Opcode) { 1327 default: 1328 break; 1329 case AArch64::LDPXpost: 1330 case AArch64::STPXpost: 1331 case AArch64::LDPSWpost: 1332 case AArch64::LDPXpre: 1333 case AArch64::STPXpre: 1334 case AArch64::LDPSWpre: 1335 case AArch64::LDPWpost: 1336 case AArch64::STPWpost: 1337 case AArch64::LDPWpre: 1338 case AArch64::STPWpre: 1339 case AArch64::LDPQpost: 1340 case AArch64::STPQpost: 1341 case AArch64::LDPQpre: 1342 case AArch64::STPQpre: 1343 case AArch64::LDPDpost: 1344 case AArch64::STPDpost: 1345 case AArch64::LDPDpre: 1346 case AArch64::STPDpre: 1347 case AArch64::LDPSpost: 1348 case AArch64::STPSpost: 1349 case AArch64::LDPSpre: 1350 case AArch64::STPSpre: 1351 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1352 break; 1353 } 1354 1355 switch (Opcode) { 1356 default: 1357 return Fail; 1358 case AArch64::LDPXpost: 1359 case AArch64::STPXpost: 1360 case AArch64::LDPSWpost: 1361 case AArch64::LDPXpre: 1362 case AArch64::STPXpre: 1363 case AArch64::LDPSWpre: 1364 NeedsDisjointWritebackTransfer = true; 1365 LLVM_FALLTHROUGH; 1366 case AArch64::LDNPXi: 1367 case AArch64::STNPXi: 1368 case AArch64::LDPXi: 1369 case AArch64::STPXi: 1370 case AArch64::LDPSWi: 1371 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1372 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1373 break; 1374 case AArch64::LDPWpost: 1375 case AArch64::STPWpost: 1376 case AArch64::LDPWpre: 1377 case AArch64::STPWpre: 1378 NeedsDisjointWritebackTransfer = true; 1379 LLVM_FALLTHROUGH; 1380 case AArch64::LDNPWi: 1381 case AArch64::STNPWi: 1382 case AArch64::LDPWi: 1383 case AArch64::STPWi: 1384 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1385 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1386 break; 1387 case AArch64::LDNPQi: 1388 case AArch64::STNPQi: 1389 case AArch64::LDPQpost: 1390 case AArch64::STPQpost: 1391 case AArch64::LDPQi: 1392 case AArch64::STPQi: 1393 case AArch64::LDPQpre: 1394 case AArch64::STPQpre: 1395 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1396 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1397 break; 1398 case AArch64::LDNPDi: 1399 case AArch64::STNPDi: 1400 case AArch64::LDPDpost: 1401 case AArch64::STPDpost: 1402 case AArch64::LDPDi: 1403 case AArch64::STPDi: 1404 case AArch64::LDPDpre: 1405 case AArch64::STPDpre: 1406 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1407 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1408 break; 1409 case AArch64::LDNPSi: 1410 case AArch64::STNPSi: 1411 case AArch64::LDPSpost: 1412 case AArch64::STPSpost: 1413 case AArch64::LDPSi: 1414 case AArch64::STPSi: 1415 case AArch64::LDPSpre: 1416 case AArch64::STPSpre: 1417 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1418 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1419 break; 1420 } 1421 1422 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1423 Inst.addOperand(MCOperand::createImm(offset)); 1424 1425 // You shouldn't load to the same register twice in an instruction... 1426 if (IsLoad && Rt == Rt2) 1427 return SoftFail; 1428 1429 // ... or do any operation that writes-back to a transfer register. But note 1430 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1431 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1432 return SoftFail; 1433 1434 return Success; 1435 } 1436 1437 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1438 uint64_t Addr, 1439 const void *Decoder) { 1440 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1441 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1442 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1443 unsigned extend = fieldFromInstruction(insn, 10, 6); 1444 1445 unsigned shift = extend & 0x7; 1446 if (shift > 4) 1447 return Fail; 1448 1449 switch (Inst.getOpcode()) { 1450 default: 1451 return Fail; 1452 case AArch64::ADDWrx: 1453 case AArch64::SUBWrx: 1454 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1455 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1456 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1457 break; 1458 case AArch64::ADDSWrx: 1459 case AArch64::SUBSWrx: 1460 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1461 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1462 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1463 break; 1464 case AArch64::ADDXrx: 1465 case AArch64::SUBXrx: 1466 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1467 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1468 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1469 break; 1470 case AArch64::ADDSXrx: 1471 case AArch64::SUBSXrx: 1472 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1473 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1474 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1475 break; 1476 case AArch64::ADDXrx64: 1477 case AArch64::SUBXrx64: 1478 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1479 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1480 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1481 break; 1482 case AArch64::SUBSXrx64: 1483 case AArch64::ADDSXrx64: 1484 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1485 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1486 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1487 break; 1488 } 1489 1490 Inst.addOperand(MCOperand::createImm(extend)); 1491 return Success; 1492 } 1493 1494 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1495 uint64_t Addr, 1496 const void *Decoder) { 1497 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1498 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1499 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1500 unsigned imm; 1501 1502 if (Datasize) { 1503 if (Inst.getOpcode() == AArch64::ANDSXri) 1504 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1505 else 1506 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1507 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1508 imm = fieldFromInstruction(insn, 10, 13); 1509 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1510 return Fail; 1511 } else { 1512 if (Inst.getOpcode() == AArch64::ANDSWri) 1513 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1514 else 1515 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1516 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1517 imm = fieldFromInstruction(insn, 10, 12); 1518 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1519 return Fail; 1520 } 1521 Inst.addOperand(MCOperand::createImm(imm)); 1522 return Success; 1523 } 1524 1525 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1526 uint64_t Addr, 1527 const void *Decoder) { 1528 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1529 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1530 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1531 imm |= fieldFromInstruction(insn, 5, 5); 1532 1533 if (Inst.getOpcode() == AArch64::MOVID) 1534 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1535 else 1536 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1537 1538 Inst.addOperand(MCOperand::createImm(imm)); 1539 1540 switch (Inst.getOpcode()) { 1541 default: 1542 break; 1543 case AArch64::MOVIv4i16: 1544 case AArch64::MOVIv8i16: 1545 case AArch64::MVNIv4i16: 1546 case AArch64::MVNIv8i16: 1547 case AArch64::MOVIv2i32: 1548 case AArch64::MOVIv4i32: 1549 case AArch64::MVNIv2i32: 1550 case AArch64::MVNIv4i32: 1551 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1552 break; 1553 case AArch64::MOVIv2s_msl: 1554 case AArch64::MOVIv4s_msl: 1555 case AArch64::MVNIv2s_msl: 1556 case AArch64::MVNIv4s_msl: 1557 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1558 break; 1559 } 1560 1561 return Success; 1562 } 1563 1564 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1565 uint64_t Addr, 1566 const void *Decoder) { 1567 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1568 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1569 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1570 imm |= fieldFromInstruction(insn, 5, 5); 1571 1572 // Tied operands added twice. 1573 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1574 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1575 1576 Inst.addOperand(MCOperand::createImm(imm)); 1577 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1578 1579 return Success; 1580 } 1581 1582 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1583 uint64_t Addr, const void *Decoder) { 1584 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1585 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1586 imm |= fieldFromInstruction(insn, 29, 2); 1587 const AArch64Disassembler *Dis = 1588 static_cast<const AArch64Disassembler *>(Decoder); 1589 1590 // Sign-extend the 21-bit immediate. 1591 if (imm & (1 << (21 - 1))) 1592 imm |= ~((1LL << 21) - 1); 1593 1594 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1595 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1596 Inst.addOperand(MCOperand::createImm(imm)); 1597 1598 return Success; 1599 } 1600 1601 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1602 uint64_t Addr, const void *Decoder) { 1603 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1604 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1605 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1606 unsigned S = fieldFromInstruction(insn, 29, 1); 1607 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1608 1609 unsigned ShifterVal = (Imm >> 12) & 3; 1610 unsigned ImmVal = Imm & 0xFFF; 1611 const AArch64Disassembler *Dis = 1612 static_cast<const AArch64Disassembler *>(Decoder); 1613 1614 if (ShifterVal != 0 && ShifterVal != 1) 1615 return Fail; 1616 1617 if (Datasize) { 1618 if (Rd == 31 && !S) 1619 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1620 else 1621 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1622 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1623 } else { 1624 if (Rd == 31 && !S) 1625 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1626 else 1627 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1628 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1629 } 1630 1631 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1632 Inst.addOperand(MCOperand::createImm(ImmVal)); 1633 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1634 return Success; 1635 } 1636 1637 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1638 uint64_t Addr, 1639 const void *Decoder) { 1640 int64_t imm = fieldFromInstruction(insn, 0, 26); 1641 const AArch64Disassembler *Dis = 1642 static_cast<const AArch64Disassembler *>(Decoder); 1643 1644 // Sign-extend the 26-bit immediate. 1645 if (imm & (1 << (26 - 1))) 1646 imm |= ~((1LL << 26) - 1); 1647 1648 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1649 Inst.addOperand(MCOperand::createImm(imm)); 1650 1651 return Success; 1652 } 1653 1654 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1655 uint64_t Addr, 1656 const void *Decoder) { 1657 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1658 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1659 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1660 1661 uint64_t pstate_field = (op1 << 3) | op2; 1662 1663 if ((pstate_field == AArch64PState::PAN || 1664 pstate_field == AArch64PState::UAO) && crm > 1) 1665 return Fail; 1666 1667 Inst.addOperand(MCOperand::createImm(pstate_field)); 1668 Inst.addOperand(MCOperand::createImm(crm)); 1669 1670 const AArch64Disassembler *Dis = 1671 static_cast<const AArch64Disassembler *>(Decoder); 1672 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1673 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1674 return Success; 1675 return Fail; 1676 } 1677 1678 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1679 uint64_t Addr, const void *Decoder) { 1680 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1681 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1682 bit |= fieldFromInstruction(insn, 19, 5); 1683 int64_t dst = fieldFromInstruction(insn, 5, 14); 1684 const AArch64Disassembler *Dis = 1685 static_cast<const AArch64Disassembler *>(Decoder); 1686 1687 // Sign-extend 14-bit immediate. 1688 if (dst & (1 << (14 - 1))) 1689 dst |= ~((1LL << 14) - 1); 1690 1691 if (fieldFromInstruction(insn, 31, 1) == 0) 1692 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1693 else 1694 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1695 Inst.addOperand(MCOperand::createImm(bit)); 1696 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1697 Inst.addOperand(MCOperand::createImm(dst)); 1698 1699 return Success; 1700 } 1701 1702 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1703 unsigned RegClassID, 1704 unsigned RegNo, 1705 uint64_t Addr, 1706 const void *Decoder) { 1707 // Register number must be even (see CASP instruction) 1708 if (RegNo & 0x1) 1709 return Fail; 1710 1711 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1712 Inst.addOperand(MCOperand::createReg(Register)); 1713 return Success; 1714 } 1715 1716 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1717 unsigned RegNo, 1718 uint64_t Addr, 1719 const void *Decoder) { 1720 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1721 AArch64::WSeqPairsClassRegClassID, 1722 RegNo, Addr, Decoder); 1723 } 1724 1725 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1726 unsigned RegNo, 1727 uint64_t Addr, 1728 const void *Decoder) { 1729 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1730 AArch64::XSeqPairsClassRegClassID, 1731 RegNo, Addr, Decoder); 1732 } 1733 1734 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1735 uint32_t insn, 1736 uint64_t Addr, 1737 const void *Decoder) { 1738 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1739 unsigned imm = fieldFromInstruction(insn, 5, 13); 1740 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1741 return Fail; 1742 1743 // The same (tied) operand is added twice to the instruction. 1744 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1745 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1746 Inst.addOperand(MCOperand::createImm(imm)); 1747 return Success; 1748 } 1749 1750 template<int Bits> 1751 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1752 uint64_t Address, const void *Decoder) { 1753 if (Imm & ~((1LL << Bits) - 1)) 1754 return Fail; 1755 1756 // Imm is a signed immediate, so sign extend it. 1757 if (Imm & (1 << (Bits - 1))) 1758 Imm |= ~((1LL << Bits) - 1); 1759 1760 Inst.addOperand(MCOperand::createImm(Imm)); 1761 return Success; 1762 } 1763 1764