1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 73 uint64_t Address, 74 const void *Decoder); 75 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 76 unsigned RegNo, uint64_t Address, 77 const void *Decoder); 78 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 82 uint64_t Address, 83 const void *Decoder); 84 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 91 uint64_t Address, 92 const void *Decoder); 93 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const void *Decoder); 99 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 139 uint64_t Address, 140 const void *Decoder); 141 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 142 uint64_t Address, 143 const void *Decoder); 144 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 145 uint64_t Address, 146 const void *Decoder); 147 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 148 uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 151 uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 154 uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 157 uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 160 uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 163 uint64_t Address, 164 const void *Decoder); 165 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 166 uint64_t Address, 167 const void *Decoder); 168 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 173 uint64_t Address, 174 const void *Decoder); 175 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 176 uint64_t Address, 177 const void *Decoder); 178 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 179 uint64_t Address, const void *Decoder); 180 181 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 182 uint64_t Address, 183 const void *Decoder); 184 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, const void *Decoder); 186 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 187 uint64_t Addr, 188 const void *Decoder); 189 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 190 uint64_t Addr, const void *Decoder); 191 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const void *Decoder); 194 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 195 uint64_t Addr, const void *Decoder); 196 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, 198 const void *Decoder); 199 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, const void *Decoder); 201 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 202 uint64_t Addr, const void *Decoder); 203 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, const void *Decoder); 205 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, const void *Decoder); 207 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 208 uint64_t Addr, const void *Decoder); 209 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 210 unsigned RegNo, 211 uint64_t Addr, 212 const void *Decoder); 213 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 214 unsigned RegNo, 215 uint64_t Addr, 216 const void *Decoder); 217 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 218 uint32_t insn, 219 uint64_t Address, 220 const void *Decoder); 221 template<int Bits> 222 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 223 uint64_t Address, const void *Decoder); 224 template <int ElementWidth> 225 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 226 uint64_t Addr, const void *Decoder); 227 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 228 uint64_t Addr, const void *Decoder); 229 230 static bool Check(DecodeStatus &Out, DecodeStatus In) { 231 switch (In) { 232 case MCDisassembler::Success: 233 // Out stays the same. 234 return true; 235 case MCDisassembler::SoftFail: 236 Out = In; 237 return true; 238 case MCDisassembler::Fail: 239 Out = In; 240 return false; 241 } 242 llvm_unreachable("Invalid DecodeStatus!"); 243 } 244 245 #include "AArch64GenDisassemblerTables.inc" 246 #include "AArch64GenInstrInfo.inc" 247 248 #define Success MCDisassembler::Success 249 #define Fail MCDisassembler::Fail 250 #define SoftFail MCDisassembler::SoftFail 251 252 static MCDisassembler *createAArch64Disassembler(const Target &T, 253 const MCSubtargetInfo &STI, 254 MCContext &Ctx) { 255 return new AArch64Disassembler(STI, Ctx); 256 } 257 258 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 259 ArrayRef<uint8_t> Bytes, 260 uint64_t Address, 261 raw_ostream &CS) const { 262 CommentStream = &CS; 263 264 Size = 0; 265 // We want to read exactly 4 bytes of data. 266 if (Bytes.size() < 4) 267 return Fail; 268 Size = 4; 269 270 // Encoded as a small-endian 32-bit word in the stream. 271 uint32_t Insn = 272 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 273 274 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 275 276 for (auto Table : Tables) { 277 DecodeStatus Result = 278 decodeInstruction(Table, MI, Insn, Address, this, STI); 279 if (Result != MCDisassembler::Fail) 280 return Result; 281 } 282 283 return MCDisassembler::Fail; 284 } 285 286 static MCSymbolizer * 287 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 288 LLVMSymbolLookupCallback SymbolLookUp, 289 void *DisInfo, MCContext *Ctx, 290 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 291 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 292 SymbolLookUp, DisInfo); 293 } 294 295 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 296 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 297 createAArch64Disassembler); 298 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 299 createAArch64Disassembler); 300 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 301 createAArch64ExternalSymbolizer); 302 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 303 createAArch64ExternalSymbolizer); 304 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 305 createAArch64Disassembler); 306 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 307 createAArch64ExternalSymbolizer); 308 309 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 310 createAArch64Disassembler); 311 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 312 createAArch64ExternalSymbolizer); 313 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 314 createAArch64Disassembler); 315 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 316 createAArch64ExternalSymbolizer); 317 } 318 319 static const unsigned FPR128DecoderTable[] = { 320 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 321 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 322 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 323 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 324 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 325 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 326 AArch64::Q30, AArch64::Q31 327 }; 328 329 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 330 uint64_t Addr, 331 const void *Decoder) { 332 if (RegNo > 31) 333 return Fail; 334 335 unsigned Register = FPR128DecoderTable[RegNo]; 336 Inst.addOperand(MCOperand::createReg(Register)); 337 return Success; 338 } 339 340 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 341 uint64_t Addr, 342 const void *Decoder) { 343 if (RegNo > 15) 344 return Fail; 345 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 346 } 347 348 static const unsigned FPR64DecoderTable[] = { 349 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 350 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 351 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 352 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 353 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 354 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 355 AArch64::D30, AArch64::D31 356 }; 357 358 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 359 uint64_t Addr, 360 const void *Decoder) { 361 if (RegNo > 31) 362 return Fail; 363 364 unsigned Register = FPR64DecoderTable[RegNo]; 365 Inst.addOperand(MCOperand::createReg(Register)); 366 return Success; 367 } 368 369 static const unsigned FPR32DecoderTable[] = { 370 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 371 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 372 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 373 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 374 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 375 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 376 AArch64::S30, AArch64::S31 377 }; 378 379 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 380 uint64_t Addr, 381 const void *Decoder) { 382 if (RegNo > 31) 383 return Fail; 384 385 unsigned Register = FPR32DecoderTable[RegNo]; 386 Inst.addOperand(MCOperand::createReg(Register)); 387 return Success; 388 } 389 390 static const unsigned FPR16DecoderTable[] = { 391 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 392 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 393 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 394 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 395 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 396 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 397 AArch64::H30, AArch64::H31 398 }; 399 400 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 401 uint64_t Addr, 402 const void *Decoder) { 403 if (RegNo > 31) 404 return Fail; 405 406 unsigned Register = FPR16DecoderTable[RegNo]; 407 Inst.addOperand(MCOperand::createReg(Register)); 408 return Success; 409 } 410 411 static const unsigned FPR8DecoderTable[] = { 412 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 413 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 414 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 415 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 416 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 417 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 418 AArch64::B30, AArch64::B31 419 }; 420 421 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 422 uint64_t Addr, 423 const void *Decoder) { 424 if (RegNo > 31) 425 return Fail; 426 427 unsigned Register = FPR8DecoderTable[RegNo]; 428 Inst.addOperand(MCOperand::createReg(Register)); 429 return Success; 430 } 431 432 static const unsigned GPR64DecoderTable[] = { 433 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 434 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 435 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 436 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 437 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 438 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 439 AArch64::LR, AArch64::XZR 440 }; 441 442 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 443 uint64_t Addr, 444 const void *Decoder) { 445 if (RegNo > 30) 446 return Fail; 447 448 unsigned Register = GPR64DecoderTable[RegNo]; 449 Inst.addOperand(MCOperand::createReg(Register)); 450 return Success; 451 } 452 453 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 454 uint64_t Addr, 455 const void *Decoder) { 456 if (RegNo > 31) 457 return Fail; 458 459 unsigned Register = GPR64DecoderTable[RegNo]; 460 Inst.addOperand(MCOperand::createReg(Register)); 461 return Success; 462 } 463 464 static const unsigned GPR64x8DecoderTable[] = { 465 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 466 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 467 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 468 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 469 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 470 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 471 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 472 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 473 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 474 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 475 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 476 }; 477 478 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 479 unsigned RegNo, 480 uint64_t Address, 481 const void *Decoder) { 482 if (RegNo > 22) 483 return Fail; 484 if (RegNo & 1) 485 return Fail; 486 487 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 488 Inst.addOperand(MCOperand::createReg(Register)); 489 return Success; 490 } 491 492 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 493 uint64_t Addr, 494 const void *Decoder) { 495 if (RegNo > 31) 496 return Fail; 497 unsigned Register = GPR64DecoderTable[RegNo]; 498 if (Register == AArch64::XZR) 499 Register = AArch64::SP; 500 Inst.addOperand(MCOperand::createReg(Register)); 501 return Success; 502 } 503 504 static const unsigned GPR32DecoderTable[] = { 505 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 506 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 507 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 508 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 509 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 510 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 511 AArch64::W30, AArch64::WZR 512 }; 513 514 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 515 uint64_t Addr, 516 const void *Decoder) { 517 if (RegNo > 31) 518 return Fail; 519 520 unsigned Register = GPR32DecoderTable[RegNo]; 521 Inst.addOperand(MCOperand::createReg(Register)); 522 return Success; 523 } 524 525 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 526 uint64_t Addr, 527 const void *Decoder) { 528 if (RegNo > 31) 529 return Fail; 530 531 unsigned Register = GPR32DecoderTable[RegNo]; 532 if (Register == AArch64::WZR) 533 Register = AArch64::WSP; 534 Inst.addOperand(MCOperand::createReg(Register)); 535 return Success; 536 } 537 static const unsigned ZPRDecoderTable[] = { 538 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 539 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 540 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 541 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 542 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 543 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 544 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 545 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 546 }; 547 548 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 549 uint64_t Address, 550 const void* Decoder) { 551 if (RegNo > 31) 552 return Fail; 553 554 unsigned Register = ZPRDecoderTable[RegNo]; 555 Inst.addOperand(MCOperand::createReg(Register)); 556 return Success; 557 } 558 559 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 560 uint64_t Address, 561 const void *Decoder) { 562 if (RegNo > 15) 563 return Fail; 564 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 565 } 566 567 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 568 uint64_t Address, 569 const void *Decoder) { 570 if (RegNo > 7) 571 return Fail; 572 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 573 } 574 575 static const unsigned ZZDecoderTable[] = { 576 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 577 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 578 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 579 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 580 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 581 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 582 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 583 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 584 }; 585 586 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 587 uint64_t Address, 588 const void* Decoder) { 589 if (RegNo > 31) 590 return Fail; 591 unsigned Register = ZZDecoderTable[RegNo]; 592 Inst.addOperand(MCOperand::createReg(Register)); 593 return Success; 594 } 595 596 static const unsigned ZZZDecoderTable[] = { 597 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 598 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 599 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 600 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 601 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 602 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 603 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 604 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 605 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 606 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 607 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 608 }; 609 610 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 611 uint64_t Address, 612 const void* Decoder) { 613 if (RegNo > 31) 614 return Fail; 615 unsigned Register = ZZZDecoderTable[RegNo]; 616 Inst.addOperand(MCOperand::createReg(Register)); 617 return Success; 618 } 619 620 static const unsigned ZZZZDecoderTable[] = { 621 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 622 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 623 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 624 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 625 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 626 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 627 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 628 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 629 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 630 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 631 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 632 }; 633 634 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 635 uint64_t Address, 636 const void* Decoder) { 637 if (RegNo > 31) 638 return Fail; 639 unsigned Register = ZZZZDecoderTable[RegNo]; 640 Inst.addOperand(MCOperand::createReg(Register)); 641 return Success; 642 } 643 644 static const unsigned PPRDecoderTable[] = { 645 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 646 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 647 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 648 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 649 }; 650 651 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 652 uint64_t Addr, const void *Decoder) { 653 if (RegNo > 15) 654 return Fail; 655 656 unsigned Register = PPRDecoderTable[RegNo]; 657 Inst.addOperand(MCOperand::createReg(Register)); 658 return Success; 659 } 660 661 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 662 uint64_t Addr, 663 const void* Decoder) { 664 if (RegNo > 7) 665 return Fail; 666 667 // Just reuse the PPR decode table 668 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 669 } 670 671 static const unsigned VectorDecoderTable[] = { 672 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 673 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 674 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 675 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 676 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 677 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 678 AArch64::Q30, AArch64::Q31 679 }; 680 681 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 682 uint64_t Addr, 683 const void *Decoder) { 684 if (RegNo > 31) 685 return Fail; 686 687 unsigned Register = VectorDecoderTable[RegNo]; 688 Inst.addOperand(MCOperand::createReg(Register)); 689 return Success; 690 } 691 692 static const unsigned QQDecoderTable[] = { 693 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 694 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 695 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 696 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 697 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 698 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 699 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 700 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 701 }; 702 703 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 704 uint64_t Addr, const void *Decoder) { 705 if (RegNo > 31) 706 return Fail; 707 unsigned Register = QQDecoderTable[RegNo]; 708 Inst.addOperand(MCOperand::createReg(Register)); 709 return Success; 710 } 711 712 static const unsigned QQQDecoderTable[] = { 713 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 714 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 715 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 716 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 717 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 718 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 719 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 720 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 721 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 722 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 723 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 724 }; 725 726 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 727 uint64_t Addr, const void *Decoder) { 728 if (RegNo > 31) 729 return Fail; 730 unsigned Register = QQQDecoderTable[RegNo]; 731 Inst.addOperand(MCOperand::createReg(Register)); 732 return Success; 733 } 734 735 static const unsigned QQQQDecoderTable[] = { 736 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 737 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 738 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 739 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 740 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 741 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 742 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 743 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 744 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 745 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 746 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 747 }; 748 749 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 750 uint64_t Addr, 751 const void *Decoder) { 752 if (RegNo > 31) 753 return Fail; 754 unsigned Register = QQQQDecoderTable[RegNo]; 755 Inst.addOperand(MCOperand::createReg(Register)); 756 return Success; 757 } 758 759 static const unsigned DDDecoderTable[] = { 760 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 761 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 762 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 763 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 764 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 765 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 766 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 767 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 768 }; 769 770 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 771 uint64_t Addr, const void *Decoder) { 772 if (RegNo > 31) 773 return Fail; 774 unsigned Register = DDDecoderTable[RegNo]; 775 Inst.addOperand(MCOperand::createReg(Register)); 776 return Success; 777 } 778 779 static const unsigned DDDDecoderTable[] = { 780 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 781 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 782 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 783 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 784 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 785 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 786 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 787 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 788 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 789 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 790 AArch64::D30_D31_D0, AArch64::D31_D0_D1 791 }; 792 793 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 794 uint64_t Addr, const void *Decoder) { 795 if (RegNo > 31) 796 return Fail; 797 unsigned Register = DDDDecoderTable[RegNo]; 798 Inst.addOperand(MCOperand::createReg(Register)); 799 return Success; 800 } 801 802 static const unsigned DDDDDecoderTable[] = { 803 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 804 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 805 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 806 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 807 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 808 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 809 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 810 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 811 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 812 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 813 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 814 }; 815 816 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 817 uint64_t Addr, 818 const void *Decoder) { 819 if (RegNo > 31) 820 return Fail; 821 unsigned Register = DDDDDecoderTable[RegNo]; 822 Inst.addOperand(MCOperand::createReg(Register)); 823 return Success; 824 } 825 826 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 827 uint64_t Addr, 828 const void *Decoder) { 829 // scale{5} is asserted as 1 in tblgen. 830 Imm |= 0x20; 831 Inst.addOperand(MCOperand::createImm(64 - Imm)); 832 return Success; 833 } 834 835 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 836 uint64_t Addr, 837 const void *Decoder) { 838 Inst.addOperand(MCOperand::createImm(64 - Imm)); 839 return Success; 840 } 841 842 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 843 uint64_t Addr, const void *Decoder) { 844 int64_t ImmVal = Imm; 845 const AArch64Disassembler *Dis = 846 static_cast<const AArch64Disassembler *>(Decoder); 847 848 // Sign-extend 19-bit immediate. 849 if (ImmVal & (1 << (19 - 1))) 850 ImmVal |= ~((1LL << 19) - 1); 851 852 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 853 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 854 Inst.addOperand(MCOperand::createImm(ImmVal)); 855 return Success; 856 } 857 858 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 859 uint64_t Address, const void *Decoder) { 860 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 861 Inst.addOperand(MCOperand::createImm(Imm & 1)); 862 return Success; 863 } 864 865 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 866 uint64_t Address, 867 const void *Decoder) { 868 Inst.addOperand(MCOperand::createImm(Imm)); 869 870 // Every system register in the encoding space is valid with the syntax 871 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 872 return Success; 873 } 874 875 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 876 uint64_t Address, 877 const void *Decoder) { 878 Inst.addOperand(MCOperand::createImm(Imm)); 879 880 return Success; 881 } 882 883 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 884 uint64_t Address, 885 const void *Decoder) { 886 // This decoder exists to add the dummy Lane operand to the MCInst, which must 887 // be 1 in assembly but has no other real manifestation. 888 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 889 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 890 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 891 892 if (IsToVec) { 893 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 894 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 895 } else { 896 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 897 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 898 } 899 900 // Add the lane 901 Inst.addOperand(MCOperand::createImm(1)); 902 903 return Success; 904 } 905 906 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 907 unsigned Add) { 908 Inst.addOperand(MCOperand::createImm(Add - Imm)); 909 return Success; 910 } 911 912 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 913 unsigned Add) { 914 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 915 return Success; 916 } 917 918 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 919 uint64_t Addr, const void *Decoder) { 920 return DecodeVecShiftRImm(Inst, Imm, 64); 921 } 922 923 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 924 uint64_t Addr, 925 const void *Decoder) { 926 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 927 } 928 929 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 930 uint64_t Addr, const void *Decoder) { 931 return DecodeVecShiftRImm(Inst, Imm, 32); 932 } 933 934 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 935 uint64_t Addr, 936 const void *Decoder) { 937 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 938 } 939 940 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 941 uint64_t Addr, const void *Decoder) { 942 return DecodeVecShiftRImm(Inst, Imm, 16); 943 } 944 945 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 946 uint64_t Addr, 947 const void *Decoder) { 948 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 949 } 950 951 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 952 uint64_t Addr, const void *Decoder) { 953 return DecodeVecShiftRImm(Inst, Imm, 8); 954 } 955 956 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 957 uint64_t Addr, const void *Decoder) { 958 return DecodeVecShiftLImm(Inst, Imm, 64); 959 } 960 961 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 962 uint64_t Addr, const void *Decoder) { 963 return DecodeVecShiftLImm(Inst, Imm, 32); 964 } 965 966 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 967 uint64_t Addr, const void *Decoder) { 968 return DecodeVecShiftLImm(Inst, Imm, 16); 969 } 970 971 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 972 uint64_t Addr, const void *Decoder) { 973 return DecodeVecShiftLImm(Inst, Imm, 8); 974 } 975 976 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 977 uint64_t Addr, 978 const void *Decoder) { 979 unsigned Rd = fieldFromInstruction(insn, 0, 5); 980 unsigned Rn = fieldFromInstruction(insn, 5, 5); 981 unsigned Rm = fieldFromInstruction(insn, 16, 5); 982 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 983 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 984 unsigned shift = (shiftHi << 6) | shiftLo; 985 switch (Inst.getOpcode()) { 986 default: 987 return Fail; 988 case AArch64::ADDWrs: 989 case AArch64::ADDSWrs: 990 case AArch64::SUBWrs: 991 case AArch64::SUBSWrs: 992 // if shift == '11' then ReservedValue() 993 if (shiftHi == 0x3) 994 return Fail; 995 LLVM_FALLTHROUGH; 996 case AArch64::ANDWrs: 997 case AArch64::ANDSWrs: 998 case AArch64::BICWrs: 999 case AArch64::BICSWrs: 1000 case AArch64::ORRWrs: 1001 case AArch64::ORNWrs: 1002 case AArch64::EORWrs: 1003 case AArch64::EONWrs: { 1004 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1005 if (shiftLo >> 5 == 1) 1006 return Fail; 1007 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1008 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1009 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1010 break; 1011 } 1012 case AArch64::ADDXrs: 1013 case AArch64::ADDSXrs: 1014 case AArch64::SUBXrs: 1015 case AArch64::SUBSXrs: 1016 // if shift == '11' then ReservedValue() 1017 if (shiftHi == 0x3) 1018 return Fail; 1019 LLVM_FALLTHROUGH; 1020 case AArch64::ANDXrs: 1021 case AArch64::ANDSXrs: 1022 case AArch64::BICXrs: 1023 case AArch64::BICSXrs: 1024 case AArch64::ORRXrs: 1025 case AArch64::ORNXrs: 1026 case AArch64::EORXrs: 1027 case AArch64::EONXrs: 1028 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1029 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1030 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1031 break; 1032 } 1033 1034 Inst.addOperand(MCOperand::createImm(shift)); 1035 return Success; 1036 } 1037 1038 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1039 uint64_t Addr, 1040 const void *Decoder) { 1041 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1042 unsigned imm = fieldFromInstruction(insn, 5, 16); 1043 unsigned shift = fieldFromInstruction(insn, 21, 2); 1044 shift <<= 4; 1045 switch (Inst.getOpcode()) { 1046 default: 1047 return Fail; 1048 case AArch64::MOVZWi: 1049 case AArch64::MOVNWi: 1050 case AArch64::MOVKWi: 1051 if (shift & (1U << 5)) 1052 return Fail; 1053 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1054 break; 1055 case AArch64::MOVZXi: 1056 case AArch64::MOVNXi: 1057 case AArch64::MOVKXi: 1058 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1059 break; 1060 } 1061 1062 if (Inst.getOpcode() == AArch64::MOVKWi || 1063 Inst.getOpcode() == AArch64::MOVKXi) 1064 Inst.addOperand(Inst.getOperand(0)); 1065 1066 Inst.addOperand(MCOperand::createImm(imm)); 1067 Inst.addOperand(MCOperand::createImm(shift)); 1068 return Success; 1069 } 1070 1071 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1072 uint64_t Addr, 1073 const void *Decoder) { 1074 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1075 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1076 unsigned offset = fieldFromInstruction(insn, 10, 12); 1077 const AArch64Disassembler *Dis = 1078 static_cast<const AArch64Disassembler *>(Decoder); 1079 1080 switch (Inst.getOpcode()) { 1081 default: 1082 return Fail; 1083 case AArch64::PRFMui: 1084 // Rt is an immediate in prefetch. 1085 Inst.addOperand(MCOperand::createImm(Rt)); 1086 break; 1087 case AArch64::STRBBui: 1088 case AArch64::LDRBBui: 1089 case AArch64::LDRSBWui: 1090 case AArch64::STRHHui: 1091 case AArch64::LDRHHui: 1092 case AArch64::LDRSHWui: 1093 case AArch64::STRWui: 1094 case AArch64::LDRWui: 1095 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1096 break; 1097 case AArch64::LDRSBXui: 1098 case AArch64::LDRSHXui: 1099 case AArch64::LDRSWui: 1100 case AArch64::STRXui: 1101 case AArch64::LDRXui: 1102 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1103 break; 1104 case AArch64::LDRQui: 1105 case AArch64::STRQui: 1106 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1107 break; 1108 case AArch64::LDRDui: 1109 case AArch64::STRDui: 1110 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1111 break; 1112 case AArch64::LDRSui: 1113 case AArch64::STRSui: 1114 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1115 break; 1116 case AArch64::LDRHui: 1117 case AArch64::STRHui: 1118 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1119 break; 1120 case AArch64::LDRBui: 1121 case AArch64::STRBui: 1122 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1123 break; 1124 } 1125 1126 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1127 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1128 Inst.addOperand(MCOperand::createImm(offset)); 1129 return Success; 1130 } 1131 1132 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1133 uint64_t Addr, 1134 const void *Decoder) { 1135 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1136 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1137 int64_t offset = fieldFromInstruction(insn, 12, 9); 1138 1139 // offset is a 9-bit signed immediate, so sign extend it to 1140 // fill the unsigned. 1141 if (offset & (1 << (9 - 1))) 1142 offset |= ~((1LL << 9) - 1); 1143 1144 // First operand is always the writeback to the address register, if needed. 1145 switch (Inst.getOpcode()) { 1146 default: 1147 break; 1148 case AArch64::LDRSBWpre: 1149 case AArch64::LDRSHWpre: 1150 case AArch64::STRBBpre: 1151 case AArch64::LDRBBpre: 1152 case AArch64::STRHHpre: 1153 case AArch64::LDRHHpre: 1154 case AArch64::STRWpre: 1155 case AArch64::LDRWpre: 1156 case AArch64::LDRSBWpost: 1157 case AArch64::LDRSHWpost: 1158 case AArch64::STRBBpost: 1159 case AArch64::LDRBBpost: 1160 case AArch64::STRHHpost: 1161 case AArch64::LDRHHpost: 1162 case AArch64::STRWpost: 1163 case AArch64::LDRWpost: 1164 case AArch64::LDRSBXpre: 1165 case AArch64::LDRSHXpre: 1166 case AArch64::STRXpre: 1167 case AArch64::LDRSWpre: 1168 case AArch64::LDRXpre: 1169 case AArch64::LDRSBXpost: 1170 case AArch64::LDRSHXpost: 1171 case AArch64::STRXpost: 1172 case AArch64::LDRSWpost: 1173 case AArch64::LDRXpost: 1174 case AArch64::LDRQpre: 1175 case AArch64::STRQpre: 1176 case AArch64::LDRQpost: 1177 case AArch64::STRQpost: 1178 case AArch64::LDRDpre: 1179 case AArch64::STRDpre: 1180 case AArch64::LDRDpost: 1181 case AArch64::STRDpost: 1182 case AArch64::LDRSpre: 1183 case AArch64::STRSpre: 1184 case AArch64::LDRSpost: 1185 case AArch64::STRSpost: 1186 case AArch64::LDRHpre: 1187 case AArch64::STRHpre: 1188 case AArch64::LDRHpost: 1189 case AArch64::STRHpost: 1190 case AArch64::LDRBpre: 1191 case AArch64::STRBpre: 1192 case AArch64::LDRBpost: 1193 case AArch64::STRBpost: 1194 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1195 break; 1196 } 1197 1198 switch (Inst.getOpcode()) { 1199 default: 1200 return Fail; 1201 case AArch64::PRFUMi: 1202 // Rt is an immediate in prefetch. 1203 Inst.addOperand(MCOperand::createImm(Rt)); 1204 break; 1205 case AArch64::STURBBi: 1206 case AArch64::LDURBBi: 1207 case AArch64::LDURSBWi: 1208 case AArch64::STURHHi: 1209 case AArch64::LDURHHi: 1210 case AArch64::LDURSHWi: 1211 case AArch64::STURWi: 1212 case AArch64::LDURWi: 1213 case AArch64::LDTRSBWi: 1214 case AArch64::LDTRSHWi: 1215 case AArch64::STTRWi: 1216 case AArch64::LDTRWi: 1217 case AArch64::STTRHi: 1218 case AArch64::LDTRHi: 1219 case AArch64::LDTRBi: 1220 case AArch64::STTRBi: 1221 case AArch64::LDRSBWpre: 1222 case AArch64::LDRSHWpre: 1223 case AArch64::STRBBpre: 1224 case AArch64::LDRBBpre: 1225 case AArch64::STRHHpre: 1226 case AArch64::LDRHHpre: 1227 case AArch64::STRWpre: 1228 case AArch64::LDRWpre: 1229 case AArch64::LDRSBWpost: 1230 case AArch64::LDRSHWpost: 1231 case AArch64::STRBBpost: 1232 case AArch64::LDRBBpost: 1233 case AArch64::STRHHpost: 1234 case AArch64::LDRHHpost: 1235 case AArch64::STRWpost: 1236 case AArch64::LDRWpost: 1237 case AArch64::STLURBi: 1238 case AArch64::STLURHi: 1239 case AArch64::STLURWi: 1240 case AArch64::LDAPURBi: 1241 case AArch64::LDAPURSBWi: 1242 case AArch64::LDAPURHi: 1243 case AArch64::LDAPURSHWi: 1244 case AArch64::LDAPURi: 1245 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1246 break; 1247 case AArch64::LDURSBXi: 1248 case AArch64::LDURSHXi: 1249 case AArch64::LDURSWi: 1250 case AArch64::STURXi: 1251 case AArch64::LDURXi: 1252 case AArch64::LDTRSBXi: 1253 case AArch64::LDTRSHXi: 1254 case AArch64::LDTRSWi: 1255 case AArch64::STTRXi: 1256 case AArch64::LDTRXi: 1257 case AArch64::LDRSBXpre: 1258 case AArch64::LDRSHXpre: 1259 case AArch64::STRXpre: 1260 case AArch64::LDRSWpre: 1261 case AArch64::LDRXpre: 1262 case AArch64::LDRSBXpost: 1263 case AArch64::LDRSHXpost: 1264 case AArch64::STRXpost: 1265 case AArch64::LDRSWpost: 1266 case AArch64::LDRXpost: 1267 case AArch64::LDAPURSWi: 1268 case AArch64::LDAPURSHXi: 1269 case AArch64::LDAPURSBXi: 1270 case AArch64::STLURXi: 1271 case AArch64::LDAPURXi: 1272 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1273 break; 1274 case AArch64::LDURQi: 1275 case AArch64::STURQi: 1276 case AArch64::LDRQpre: 1277 case AArch64::STRQpre: 1278 case AArch64::LDRQpost: 1279 case AArch64::STRQpost: 1280 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1281 break; 1282 case AArch64::LDURDi: 1283 case AArch64::STURDi: 1284 case AArch64::LDRDpre: 1285 case AArch64::STRDpre: 1286 case AArch64::LDRDpost: 1287 case AArch64::STRDpost: 1288 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1289 break; 1290 case AArch64::LDURSi: 1291 case AArch64::STURSi: 1292 case AArch64::LDRSpre: 1293 case AArch64::STRSpre: 1294 case AArch64::LDRSpost: 1295 case AArch64::STRSpost: 1296 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1297 break; 1298 case AArch64::LDURHi: 1299 case AArch64::STURHi: 1300 case AArch64::LDRHpre: 1301 case AArch64::STRHpre: 1302 case AArch64::LDRHpost: 1303 case AArch64::STRHpost: 1304 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1305 break; 1306 case AArch64::LDURBi: 1307 case AArch64::STURBi: 1308 case AArch64::LDRBpre: 1309 case AArch64::STRBpre: 1310 case AArch64::LDRBpost: 1311 case AArch64::STRBpost: 1312 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1313 break; 1314 } 1315 1316 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1317 Inst.addOperand(MCOperand::createImm(offset)); 1318 1319 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1320 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1321 bool IsFP = fieldFromInstruction(insn, 26, 1); 1322 1323 // Cannot write back to a transfer register (but xzr != sp). 1324 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1325 return SoftFail; 1326 1327 return Success; 1328 } 1329 1330 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1331 uint64_t Addr, 1332 const void *Decoder) { 1333 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1334 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1335 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1336 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1337 1338 unsigned Opcode = Inst.getOpcode(); 1339 switch (Opcode) { 1340 default: 1341 return Fail; 1342 case AArch64::STLXRW: 1343 case AArch64::STLXRB: 1344 case AArch64::STLXRH: 1345 case AArch64::STXRW: 1346 case AArch64::STXRB: 1347 case AArch64::STXRH: 1348 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1349 LLVM_FALLTHROUGH; 1350 case AArch64::LDARW: 1351 case AArch64::LDARB: 1352 case AArch64::LDARH: 1353 case AArch64::LDAXRW: 1354 case AArch64::LDAXRB: 1355 case AArch64::LDAXRH: 1356 case AArch64::LDXRW: 1357 case AArch64::LDXRB: 1358 case AArch64::LDXRH: 1359 case AArch64::STLRW: 1360 case AArch64::STLRB: 1361 case AArch64::STLRH: 1362 case AArch64::STLLRW: 1363 case AArch64::STLLRB: 1364 case AArch64::STLLRH: 1365 case AArch64::LDLARW: 1366 case AArch64::LDLARB: 1367 case AArch64::LDLARH: 1368 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1369 break; 1370 case AArch64::STLXRX: 1371 case AArch64::STXRX: 1372 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1373 LLVM_FALLTHROUGH; 1374 case AArch64::LDARX: 1375 case AArch64::LDAXRX: 1376 case AArch64::LDXRX: 1377 case AArch64::STLRX: 1378 case AArch64::LDLARX: 1379 case AArch64::STLLRX: 1380 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1381 break; 1382 case AArch64::STLXPW: 1383 case AArch64::STXPW: 1384 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1385 LLVM_FALLTHROUGH; 1386 case AArch64::LDAXPW: 1387 case AArch64::LDXPW: 1388 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1389 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1390 break; 1391 case AArch64::STLXPX: 1392 case AArch64::STXPX: 1393 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1394 LLVM_FALLTHROUGH; 1395 case AArch64::LDAXPX: 1396 case AArch64::LDXPX: 1397 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1398 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1399 break; 1400 } 1401 1402 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1403 1404 // You shouldn't load to the same register twice in an instruction... 1405 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1406 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1407 Rt == Rt2) 1408 return SoftFail; 1409 1410 return Success; 1411 } 1412 1413 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1414 uint64_t Addr, 1415 const void *Decoder) { 1416 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1417 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1418 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1419 int64_t offset = fieldFromInstruction(insn, 15, 7); 1420 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1421 1422 // offset is a 7-bit signed immediate, so sign extend it to 1423 // fill the unsigned. 1424 if (offset & (1 << (7 - 1))) 1425 offset |= ~((1LL << 7) - 1); 1426 1427 unsigned Opcode = Inst.getOpcode(); 1428 bool NeedsDisjointWritebackTransfer = false; 1429 1430 // First operand is always writeback of base register. 1431 switch (Opcode) { 1432 default: 1433 break; 1434 case AArch64::LDPXpost: 1435 case AArch64::STPXpost: 1436 case AArch64::LDPSWpost: 1437 case AArch64::LDPXpre: 1438 case AArch64::STPXpre: 1439 case AArch64::LDPSWpre: 1440 case AArch64::LDPWpost: 1441 case AArch64::STPWpost: 1442 case AArch64::LDPWpre: 1443 case AArch64::STPWpre: 1444 case AArch64::LDPQpost: 1445 case AArch64::STPQpost: 1446 case AArch64::LDPQpre: 1447 case AArch64::STPQpre: 1448 case AArch64::LDPDpost: 1449 case AArch64::STPDpost: 1450 case AArch64::LDPDpre: 1451 case AArch64::STPDpre: 1452 case AArch64::LDPSpost: 1453 case AArch64::STPSpost: 1454 case AArch64::LDPSpre: 1455 case AArch64::STPSpre: 1456 case AArch64::STGPpre: 1457 case AArch64::STGPpost: 1458 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1459 break; 1460 } 1461 1462 switch (Opcode) { 1463 default: 1464 return Fail; 1465 case AArch64::LDPXpost: 1466 case AArch64::STPXpost: 1467 case AArch64::LDPSWpost: 1468 case AArch64::LDPXpre: 1469 case AArch64::STPXpre: 1470 case AArch64::LDPSWpre: 1471 case AArch64::STGPpre: 1472 case AArch64::STGPpost: 1473 NeedsDisjointWritebackTransfer = true; 1474 LLVM_FALLTHROUGH; 1475 case AArch64::LDNPXi: 1476 case AArch64::STNPXi: 1477 case AArch64::LDPXi: 1478 case AArch64::STPXi: 1479 case AArch64::LDPSWi: 1480 case AArch64::STGPi: 1481 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1482 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1483 break; 1484 case AArch64::LDPWpost: 1485 case AArch64::STPWpost: 1486 case AArch64::LDPWpre: 1487 case AArch64::STPWpre: 1488 NeedsDisjointWritebackTransfer = true; 1489 LLVM_FALLTHROUGH; 1490 case AArch64::LDNPWi: 1491 case AArch64::STNPWi: 1492 case AArch64::LDPWi: 1493 case AArch64::STPWi: 1494 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1495 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1496 break; 1497 case AArch64::LDNPQi: 1498 case AArch64::STNPQi: 1499 case AArch64::LDPQpost: 1500 case AArch64::STPQpost: 1501 case AArch64::LDPQi: 1502 case AArch64::STPQi: 1503 case AArch64::LDPQpre: 1504 case AArch64::STPQpre: 1505 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1506 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1507 break; 1508 case AArch64::LDNPDi: 1509 case AArch64::STNPDi: 1510 case AArch64::LDPDpost: 1511 case AArch64::STPDpost: 1512 case AArch64::LDPDi: 1513 case AArch64::STPDi: 1514 case AArch64::LDPDpre: 1515 case AArch64::STPDpre: 1516 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1517 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1518 break; 1519 case AArch64::LDNPSi: 1520 case AArch64::STNPSi: 1521 case AArch64::LDPSpost: 1522 case AArch64::STPSpost: 1523 case AArch64::LDPSi: 1524 case AArch64::STPSi: 1525 case AArch64::LDPSpre: 1526 case AArch64::STPSpre: 1527 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1528 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1529 break; 1530 } 1531 1532 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1533 Inst.addOperand(MCOperand::createImm(offset)); 1534 1535 // You shouldn't load to the same register twice in an instruction... 1536 if (IsLoad && Rt == Rt2) 1537 return SoftFail; 1538 1539 // ... or do any operation that writes-back to a transfer register. But note 1540 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1541 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1542 return SoftFail; 1543 1544 return Success; 1545 } 1546 1547 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1548 uint64_t Addr, 1549 const void *Decoder) { 1550 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1551 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1552 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1553 fieldFromInstruction(insn, 12, 9); 1554 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1555 1556 switch (Inst.getOpcode()) { 1557 default: 1558 return Fail; 1559 case AArch64::LDRAAwriteback: 1560 case AArch64::LDRABwriteback: 1561 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1562 Decoder); 1563 break; 1564 case AArch64::LDRAAindexed: 1565 case AArch64::LDRABindexed: 1566 break; 1567 } 1568 1569 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1570 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1571 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1572 1573 if (writeback && Rt == Rn && Rn != 31) { 1574 return SoftFail; 1575 } 1576 1577 return Success; 1578 } 1579 1580 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1581 uint64_t Addr, 1582 const void *Decoder) { 1583 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1584 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1585 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1586 unsigned extend = fieldFromInstruction(insn, 10, 6); 1587 1588 unsigned shift = extend & 0x7; 1589 if (shift > 4) 1590 return Fail; 1591 1592 switch (Inst.getOpcode()) { 1593 default: 1594 return Fail; 1595 case AArch64::ADDWrx: 1596 case AArch64::SUBWrx: 1597 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1598 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1599 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1600 break; 1601 case AArch64::ADDSWrx: 1602 case AArch64::SUBSWrx: 1603 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1604 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1605 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1606 break; 1607 case AArch64::ADDXrx: 1608 case AArch64::SUBXrx: 1609 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1610 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1611 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1612 break; 1613 case AArch64::ADDSXrx: 1614 case AArch64::SUBSXrx: 1615 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1616 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1617 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1618 break; 1619 case AArch64::ADDXrx64: 1620 case AArch64::SUBXrx64: 1621 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1622 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1623 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1624 break; 1625 case AArch64::SUBSXrx64: 1626 case AArch64::ADDSXrx64: 1627 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1628 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1629 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1630 break; 1631 } 1632 1633 Inst.addOperand(MCOperand::createImm(extend)); 1634 return Success; 1635 } 1636 1637 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1638 uint64_t Addr, 1639 const void *Decoder) { 1640 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1641 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1642 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1643 unsigned imm; 1644 1645 if (Datasize) { 1646 if (Inst.getOpcode() == AArch64::ANDSXri) 1647 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1648 else 1649 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1650 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1651 imm = fieldFromInstruction(insn, 10, 13); 1652 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1653 return Fail; 1654 } else { 1655 if (Inst.getOpcode() == AArch64::ANDSWri) 1656 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1657 else 1658 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1659 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1660 imm = fieldFromInstruction(insn, 10, 12); 1661 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1662 return Fail; 1663 } 1664 Inst.addOperand(MCOperand::createImm(imm)); 1665 return Success; 1666 } 1667 1668 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1669 uint64_t Addr, 1670 const void *Decoder) { 1671 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1672 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1673 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1674 imm |= fieldFromInstruction(insn, 5, 5); 1675 1676 if (Inst.getOpcode() == AArch64::MOVID) 1677 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1678 else 1679 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1680 1681 Inst.addOperand(MCOperand::createImm(imm)); 1682 1683 switch (Inst.getOpcode()) { 1684 default: 1685 break; 1686 case AArch64::MOVIv4i16: 1687 case AArch64::MOVIv8i16: 1688 case AArch64::MVNIv4i16: 1689 case AArch64::MVNIv8i16: 1690 case AArch64::MOVIv2i32: 1691 case AArch64::MOVIv4i32: 1692 case AArch64::MVNIv2i32: 1693 case AArch64::MVNIv4i32: 1694 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1695 break; 1696 case AArch64::MOVIv2s_msl: 1697 case AArch64::MOVIv4s_msl: 1698 case AArch64::MVNIv2s_msl: 1699 case AArch64::MVNIv4s_msl: 1700 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1701 break; 1702 } 1703 1704 return Success; 1705 } 1706 1707 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1708 uint64_t Addr, 1709 const void *Decoder) { 1710 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1711 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1712 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1713 imm |= fieldFromInstruction(insn, 5, 5); 1714 1715 // Tied operands added twice. 1716 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1717 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1718 1719 Inst.addOperand(MCOperand::createImm(imm)); 1720 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1721 1722 return Success; 1723 } 1724 1725 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1726 uint64_t Addr, const void *Decoder) { 1727 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1728 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1729 imm |= fieldFromInstruction(insn, 29, 2); 1730 const AArch64Disassembler *Dis = 1731 static_cast<const AArch64Disassembler *>(Decoder); 1732 1733 // Sign-extend the 21-bit immediate. 1734 if (imm & (1 << (21 - 1))) 1735 imm |= ~((1LL << 21) - 1); 1736 1737 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1738 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1739 Inst.addOperand(MCOperand::createImm(imm)); 1740 1741 return Success; 1742 } 1743 1744 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1745 uint64_t Addr, const void *Decoder) { 1746 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1747 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1748 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1749 unsigned S = fieldFromInstruction(insn, 29, 1); 1750 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1751 1752 unsigned ShifterVal = (Imm >> 12) & 3; 1753 unsigned ImmVal = Imm & 0xFFF; 1754 const AArch64Disassembler *Dis = 1755 static_cast<const AArch64Disassembler *>(Decoder); 1756 1757 if (ShifterVal != 0 && ShifterVal != 1) 1758 return Fail; 1759 1760 if (Datasize) { 1761 if (Rd == 31 && !S) 1762 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1763 else 1764 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1765 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1766 } else { 1767 if (Rd == 31 && !S) 1768 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1769 else 1770 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1771 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1772 } 1773 1774 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1775 Inst.addOperand(MCOperand::createImm(ImmVal)); 1776 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1777 return Success; 1778 } 1779 1780 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1781 uint64_t Addr, 1782 const void *Decoder) { 1783 int64_t imm = fieldFromInstruction(insn, 0, 26); 1784 const AArch64Disassembler *Dis = 1785 static_cast<const AArch64Disassembler *>(Decoder); 1786 1787 // Sign-extend the 26-bit immediate. 1788 if (imm & (1 << (26 - 1))) 1789 imm |= ~((1LL << 26) - 1); 1790 1791 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1792 Inst.addOperand(MCOperand::createImm(imm)); 1793 1794 return Success; 1795 } 1796 1797 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1798 uint64_t Addr, 1799 const void *Decoder) { 1800 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1801 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1802 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1803 uint64_t pstate_field = (op1 << 3) | op2; 1804 1805 switch (pstate_field) { 1806 case 0x01: // XAFlag 1807 case 0x02: // AXFlag 1808 return Fail; 1809 } 1810 1811 if ((pstate_field == AArch64PState::PAN || 1812 pstate_field == AArch64PState::UAO || 1813 pstate_field == AArch64PState::SSBS) && crm > 1) 1814 return Fail; 1815 1816 Inst.addOperand(MCOperand::createImm(pstate_field)); 1817 Inst.addOperand(MCOperand::createImm(crm)); 1818 1819 const AArch64Disassembler *Dis = 1820 static_cast<const AArch64Disassembler *>(Decoder); 1821 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1822 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1823 return Success; 1824 return Fail; 1825 } 1826 1827 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1828 uint64_t Addr, const void *Decoder) { 1829 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1830 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1831 bit |= fieldFromInstruction(insn, 19, 5); 1832 int64_t dst = fieldFromInstruction(insn, 5, 14); 1833 const AArch64Disassembler *Dis = 1834 static_cast<const AArch64Disassembler *>(Decoder); 1835 1836 // Sign-extend 14-bit immediate. 1837 if (dst & (1 << (14 - 1))) 1838 dst |= ~((1LL << 14) - 1); 1839 1840 if (fieldFromInstruction(insn, 31, 1) == 0) 1841 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1842 else 1843 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1844 Inst.addOperand(MCOperand::createImm(bit)); 1845 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1846 Inst.addOperand(MCOperand::createImm(dst)); 1847 1848 return Success; 1849 } 1850 1851 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1852 unsigned RegClassID, 1853 unsigned RegNo, 1854 uint64_t Addr, 1855 const void *Decoder) { 1856 // Register number must be even (see CASP instruction) 1857 if (RegNo & 0x1) 1858 return Fail; 1859 1860 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1861 Inst.addOperand(MCOperand::createReg(Reg)); 1862 return Success; 1863 } 1864 1865 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1866 unsigned RegNo, 1867 uint64_t Addr, 1868 const void *Decoder) { 1869 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1870 AArch64::WSeqPairsClassRegClassID, 1871 RegNo, Addr, Decoder); 1872 } 1873 1874 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1875 unsigned RegNo, 1876 uint64_t Addr, 1877 const void *Decoder) { 1878 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1879 AArch64::XSeqPairsClassRegClassID, 1880 RegNo, Addr, Decoder); 1881 } 1882 1883 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1884 uint32_t insn, 1885 uint64_t Addr, 1886 const void *Decoder) { 1887 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1888 unsigned imm = fieldFromInstruction(insn, 5, 13); 1889 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1890 return Fail; 1891 1892 // The same (tied) operand is added twice to the instruction. 1893 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1894 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1895 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1896 Inst.addOperand(MCOperand::createImm(imm)); 1897 return Success; 1898 } 1899 1900 template<int Bits> 1901 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1902 uint64_t Address, const void *Decoder) { 1903 if (Imm & ~((1LL << Bits) - 1)) 1904 return Fail; 1905 1906 // Imm is a signed immediate, so sign extend it. 1907 if (Imm & (1 << (Bits - 1))) 1908 Imm |= ~((1LL << Bits) - 1); 1909 1910 Inst.addOperand(MCOperand::createImm(Imm)); 1911 return Success; 1912 } 1913 1914 // Decode 8-bit signed/unsigned immediate for a given element width. 1915 template <int ElementWidth> 1916 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1917 uint64_t Addr, const void *Decoder) { 1918 unsigned Val = (uint8_t)Imm; 1919 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1920 if (ElementWidth == 8 && Shift) 1921 return Fail; 1922 Inst.addOperand(MCOperand::createImm(Val)); 1923 Inst.addOperand(MCOperand::createImm(Shift)); 1924 return Success; 1925 } 1926 1927 // Decode uimm4 ranged from 1-16. 1928 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1929 uint64_t Addr, const void *Decoder) { 1930 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1931 return Success; 1932 } 1933