1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 80 unsigned RegNo, uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 template <unsigned NumBitsForTile> 119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 122 unsigned RegMask, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 133 uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 162 uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 168 uint64_t Address, 169 const void *Decoder); 170 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 171 uint64_t Address, 172 const void *Decoder); 173 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 174 uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 177 uint64_t Address, 178 const void *Decoder); 179 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 184 uint64_t Address, 185 const void *Decoder); 186 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 187 uint64_t Address, 188 const void *Decoder); 189 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 190 uint64_t Address, const void *Decoder); 191 192 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 193 uint64_t Address, 194 const void *Decoder); 195 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, const void *Decoder); 197 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 198 uint64_t Addr, 199 const void *Decoder); 200 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 201 uint64_t Addr, const void *Decoder); 202 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const void *Decoder); 205 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, const void *Decoder); 207 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 208 uint64_t Addr, 209 const void *Decoder); 210 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, const void *Decoder); 214 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, const void *Decoder); 216 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, const void *Decoder); 218 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 219 uint64_t Addr, const void *Decoder); 220 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Addr, 223 const void *Decoder); 224 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 225 unsigned RegNo, 226 uint64_t Addr, 227 const void *Decoder); 228 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, 229 uint64_t Address, 230 const void *Decoder); 231 template <int Bits> 232 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 233 const void *Decoder); 234 template <int ElementWidth> 235 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 236 uint64_t Addr, const void *Decoder); 237 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 238 uint64_t Addr, const void *Decoder); 239 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 240 const void *Decoder); 241 242 static bool Check(DecodeStatus &Out, DecodeStatus In) { 243 switch (In) { 244 case MCDisassembler::Success: 245 // Out stays the same. 246 return true; 247 case MCDisassembler::SoftFail: 248 Out = In; 249 return true; 250 case MCDisassembler::Fail: 251 Out = In; 252 return false; 253 } 254 llvm_unreachable("Invalid DecodeStatus!"); 255 } 256 257 #include "AArch64GenDisassemblerTables.inc" 258 #include "AArch64GenInstrInfo.inc" 259 260 #define Success MCDisassembler::Success 261 #define Fail MCDisassembler::Fail 262 #define SoftFail MCDisassembler::SoftFail 263 264 static MCDisassembler *createAArch64Disassembler(const Target &T, 265 const MCSubtargetInfo &STI, 266 MCContext &Ctx) { 267 return new AArch64Disassembler(STI, Ctx); 268 } 269 270 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 271 ArrayRef<uint8_t> Bytes, 272 uint64_t Address, 273 raw_ostream &CS) const { 274 CommentStream = &CS; 275 276 Size = 0; 277 // We want to read exactly 4 bytes of data. 278 if (Bytes.size() < 4) 279 return Fail; 280 Size = 4; 281 282 // Encoded as a small-endian 32-bit word in the stream. 283 uint32_t Insn = 284 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 285 286 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 287 288 for (auto Table : Tables) { 289 DecodeStatus Result = 290 decodeInstruction(Table, MI, Insn, Address, this, STI); 291 292 switch (MI.getOpcode()) { 293 default: 294 break; 295 // For Scalable Matrix Extension (SME) instructions that have an implicit 296 // operand for the accumulator (ZA) which isn't encoded, manually insert 297 // operand. 298 case AArch64::LDR_ZA: 299 case AArch64::STR_ZA: { 300 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA)); 301 // Spill and fill instructions have a single immediate used for both the 302 // vector select offset and optional memory offset. Replicate the decoded 303 // immediate. 304 const MCOperand &Imm4Op = MI.getOperand(2); 305 assert(Imm4Op.isImm() && "Unexpected operand type!"); 306 MI.addOperand(Imm4Op); 307 break; 308 } 309 case AArch64::LD1_MXIPXX_H_B: 310 case AArch64::LD1_MXIPXX_V_B: 311 case AArch64::ST1_MXIPXX_H_B: 312 case AArch64::ST1_MXIPXX_V_B: 313 case AArch64::INSERT_MXIPZ_H_B: 314 case AArch64::INSERT_MXIPZ_V_B: 315 // e.g. 316 // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B 317 // ^ insert implicit 8-bit element tile 318 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 319 break; 320 case AArch64::EXTRACT_ZPMXI_H_B: 321 case AArch64::EXTRACT_ZPMXI_V_B: 322 // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>] 323 // ^ insert implicit 8-bit element tile 324 MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0)); 325 break; 326 } 327 328 if (Result != MCDisassembler::Fail) 329 return Result; 330 } 331 332 return MCDisassembler::Fail; 333 } 334 335 static MCSymbolizer * 336 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 337 LLVMSymbolLookupCallback SymbolLookUp, 338 void *DisInfo, MCContext *Ctx, 339 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 340 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 341 SymbolLookUp, DisInfo); 342 } 343 344 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 345 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 346 createAArch64Disassembler); 347 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 348 createAArch64Disassembler); 349 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 350 createAArch64ExternalSymbolizer); 351 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 352 createAArch64ExternalSymbolizer); 353 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 354 createAArch64Disassembler); 355 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 356 createAArch64ExternalSymbolizer); 357 358 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 359 createAArch64Disassembler); 360 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 361 createAArch64ExternalSymbolizer); 362 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 363 createAArch64Disassembler); 364 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 365 createAArch64ExternalSymbolizer); 366 } 367 368 static const unsigned FPR128DecoderTable[] = { 369 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 370 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 371 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 372 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 373 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 374 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 375 AArch64::Q30, AArch64::Q31 376 }; 377 378 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 379 uint64_t Addr, 380 const void *Decoder) { 381 if (RegNo > 31) 382 return Fail; 383 384 unsigned Register = FPR128DecoderTable[RegNo]; 385 Inst.addOperand(MCOperand::createReg(Register)); 386 return Success; 387 } 388 389 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 390 uint64_t Addr, 391 const void *Decoder) { 392 if (RegNo > 15) 393 return Fail; 394 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 395 } 396 397 static const unsigned FPR64DecoderTable[] = { 398 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 399 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 400 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 401 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 402 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 403 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 404 AArch64::D30, AArch64::D31 405 }; 406 407 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 408 uint64_t Addr, 409 const void *Decoder) { 410 if (RegNo > 31) 411 return Fail; 412 413 unsigned Register = FPR64DecoderTable[RegNo]; 414 Inst.addOperand(MCOperand::createReg(Register)); 415 return Success; 416 } 417 418 static const unsigned FPR32DecoderTable[] = { 419 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 420 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 421 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 422 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 423 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 424 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 425 AArch64::S30, AArch64::S31 426 }; 427 428 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 429 uint64_t Addr, 430 const void *Decoder) { 431 if (RegNo > 31) 432 return Fail; 433 434 unsigned Register = FPR32DecoderTable[RegNo]; 435 Inst.addOperand(MCOperand::createReg(Register)); 436 return Success; 437 } 438 439 static const unsigned FPR16DecoderTable[] = { 440 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 441 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 442 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 443 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 444 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 445 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 446 AArch64::H30, AArch64::H31 447 }; 448 449 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 450 uint64_t Addr, 451 const void *Decoder) { 452 if (RegNo > 31) 453 return Fail; 454 455 unsigned Register = FPR16DecoderTable[RegNo]; 456 Inst.addOperand(MCOperand::createReg(Register)); 457 return Success; 458 } 459 460 static const unsigned FPR8DecoderTable[] = { 461 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 462 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 463 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 464 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 465 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 466 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 467 AArch64::B30, AArch64::B31 468 }; 469 470 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 471 uint64_t Addr, 472 const void *Decoder) { 473 if (RegNo > 31) 474 return Fail; 475 476 unsigned Register = FPR8DecoderTable[RegNo]; 477 Inst.addOperand(MCOperand::createReg(Register)); 478 return Success; 479 } 480 481 static const unsigned GPR64DecoderTable[] = { 482 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 483 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 484 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 485 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 486 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 487 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 488 AArch64::LR, AArch64::XZR 489 }; 490 491 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 492 uint64_t Addr, 493 const void *Decoder) { 494 if (RegNo > 30) 495 return Fail; 496 497 unsigned Register = GPR64DecoderTable[RegNo]; 498 Inst.addOperand(MCOperand::createReg(Register)); 499 return Success; 500 } 501 502 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 503 uint64_t Addr, 504 const void *Decoder) { 505 if (RegNo > 31) 506 return Fail; 507 508 unsigned Register = GPR64DecoderTable[RegNo]; 509 Inst.addOperand(MCOperand::createReg(Register)); 510 return Success; 511 } 512 513 static const unsigned GPR64x8DecoderTable[] = { 514 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 515 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 516 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 517 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 518 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 519 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 520 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 521 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 522 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 523 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 524 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 525 AArch64::X22_X23_X24_X25_X26_X27_X28_FP, 526 }; 527 528 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 529 unsigned RegNo, 530 uint64_t Address, 531 const void *Decoder) { 532 if (RegNo > 22) 533 return Fail; 534 if (RegNo & 1) 535 return Fail; 536 537 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 538 Inst.addOperand(MCOperand::createReg(Register)); 539 return Success; 540 } 541 542 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 543 uint64_t Addr, 544 const void *Decoder) { 545 if (RegNo > 31) 546 return Fail; 547 unsigned Register = GPR64DecoderTable[RegNo]; 548 if (Register == AArch64::XZR) 549 Register = AArch64::SP; 550 Inst.addOperand(MCOperand::createReg(Register)); 551 return Success; 552 } 553 554 static const unsigned MatrixIndexGPR32_12_15DecoderTable[] = { 555 AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15 556 }; 557 558 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 559 unsigned RegNo, 560 uint64_t Addr, 561 const void *Decoder) { 562 if (RegNo > 3) 563 return Fail; 564 565 unsigned Register = MatrixIndexGPR32_12_15DecoderTable[RegNo]; 566 Inst.addOperand(MCOperand::createReg(Register)); 567 return Success; 568 } 569 570 static const unsigned GPR32DecoderTable[] = { 571 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 572 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 573 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 574 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 575 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 576 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 577 AArch64::W30, AArch64::WZR 578 }; 579 580 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 581 uint64_t Addr, 582 const void *Decoder) { 583 if (RegNo > 31) 584 return Fail; 585 586 unsigned Register = GPR32DecoderTable[RegNo]; 587 Inst.addOperand(MCOperand::createReg(Register)); 588 return Success; 589 } 590 591 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 592 uint64_t Addr, 593 const void *Decoder) { 594 if (RegNo > 31) 595 return Fail; 596 597 unsigned Register = GPR32DecoderTable[RegNo]; 598 if (Register == AArch64::WZR) 599 Register = AArch64::WSP; 600 Inst.addOperand(MCOperand::createReg(Register)); 601 return Success; 602 } 603 static const unsigned ZPRDecoderTable[] = { 604 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 605 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 606 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 607 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 608 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 609 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 610 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 611 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 612 }; 613 614 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 615 uint64_t Address, 616 const void* Decoder) { 617 if (RegNo > 31) 618 return Fail; 619 620 unsigned Register = ZPRDecoderTable[RegNo]; 621 Inst.addOperand(MCOperand::createReg(Register)); 622 return Success; 623 } 624 625 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 626 uint64_t Address, 627 const void *Decoder) { 628 if (RegNo > 15) 629 return Fail; 630 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 631 } 632 633 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 634 uint64_t Address, 635 const void *Decoder) { 636 if (RegNo > 7) 637 return Fail; 638 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 639 } 640 641 static const unsigned ZZDecoderTable[] = { 642 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 643 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 644 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 645 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 646 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 647 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 648 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 649 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 650 }; 651 652 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 653 uint64_t Address, 654 const void* Decoder) { 655 if (RegNo > 31) 656 return Fail; 657 unsigned Register = ZZDecoderTable[RegNo]; 658 Inst.addOperand(MCOperand::createReg(Register)); 659 return Success; 660 } 661 662 static const unsigned ZZZDecoderTable[] = { 663 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 664 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 665 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 666 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 667 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 668 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 669 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 670 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 671 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 672 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 673 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 674 }; 675 676 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 677 uint64_t Address, 678 const void* Decoder) { 679 if (RegNo > 31) 680 return Fail; 681 unsigned Register = ZZZDecoderTable[RegNo]; 682 Inst.addOperand(MCOperand::createReg(Register)); 683 return Success; 684 } 685 686 static const unsigned ZZZZDecoderTable[] = { 687 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 688 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 689 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 690 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 691 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 692 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 693 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 694 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 695 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 696 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 697 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 698 }; 699 700 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 701 uint64_t Address, 702 const void* Decoder) { 703 if (RegNo > 31) 704 return Fail; 705 unsigned Register = ZZZZDecoderTable[RegNo]; 706 Inst.addOperand(MCOperand::createReg(Register)); 707 return Success; 708 } 709 710 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 711 unsigned RegMask, 712 uint64_t Address, 713 const void *Decoder) { 714 if (RegMask > 0xFF) 715 return Fail; 716 Inst.addOperand(MCOperand::createImm(RegMask)); 717 return Success; 718 } 719 720 static const SmallVector<SmallVector<unsigned, 16>, 5> 721 MatrixZATileDecoderTable = { 722 {AArch64::ZAB0}, 723 {AArch64::ZAH0, AArch64::ZAH1}, 724 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 725 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 726 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 727 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 728 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 729 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 730 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 731 732 template <unsigned NumBitsForTile> 733 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 734 uint64_t Address, const void *Decoder) { 735 unsigned LastReg = (1 << NumBitsForTile) - 1; 736 if (RegNo > LastReg) 737 return Fail; 738 Inst.addOperand( 739 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 740 return Success; 741 } 742 743 static const unsigned PPRDecoderTable[] = { 744 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 745 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 746 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 747 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 748 }; 749 750 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 751 uint64_t Addr, const void *Decoder) { 752 if (RegNo > 15) 753 return Fail; 754 755 unsigned Register = PPRDecoderTable[RegNo]; 756 Inst.addOperand(MCOperand::createReg(Register)); 757 return Success; 758 } 759 760 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 761 uint64_t Addr, 762 const void* Decoder) { 763 if (RegNo > 7) 764 return Fail; 765 766 // Just reuse the PPR decode table 767 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 768 } 769 770 static const unsigned QQDecoderTable[] = { 771 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 772 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 773 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 774 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 775 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 776 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 777 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 778 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 779 }; 780 781 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 782 uint64_t Addr, const void *Decoder) { 783 if (RegNo > 31) 784 return Fail; 785 unsigned Register = QQDecoderTable[RegNo]; 786 Inst.addOperand(MCOperand::createReg(Register)); 787 return Success; 788 } 789 790 static const unsigned QQQDecoderTable[] = { 791 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 792 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 793 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 794 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 795 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 796 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 797 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 798 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 799 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 800 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 801 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 802 }; 803 804 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 805 uint64_t Addr, const void *Decoder) { 806 if (RegNo > 31) 807 return Fail; 808 unsigned Register = QQQDecoderTable[RegNo]; 809 Inst.addOperand(MCOperand::createReg(Register)); 810 return Success; 811 } 812 813 static const unsigned QQQQDecoderTable[] = { 814 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 815 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 816 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 817 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 818 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 819 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 820 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 821 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 822 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 823 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 824 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 825 }; 826 827 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 828 uint64_t Addr, 829 const void *Decoder) { 830 if (RegNo > 31) 831 return Fail; 832 unsigned Register = QQQQDecoderTable[RegNo]; 833 Inst.addOperand(MCOperand::createReg(Register)); 834 return Success; 835 } 836 837 static const unsigned DDDecoderTable[] = { 838 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 839 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 840 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 841 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 842 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 843 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 844 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 845 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 846 }; 847 848 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 849 uint64_t Addr, const void *Decoder) { 850 if (RegNo > 31) 851 return Fail; 852 unsigned Register = DDDecoderTable[RegNo]; 853 Inst.addOperand(MCOperand::createReg(Register)); 854 return Success; 855 } 856 857 static const unsigned DDDDecoderTable[] = { 858 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 859 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 860 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 861 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 862 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 863 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 864 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 865 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 866 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 867 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 868 AArch64::D30_D31_D0, AArch64::D31_D0_D1 869 }; 870 871 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 872 uint64_t Addr, const void *Decoder) { 873 if (RegNo > 31) 874 return Fail; 875 unsigned Register = DDDDecoderTable[RegNo]; 876 Inst.addOperand(MCOperand::createReg(Register)); 877 return Success; 878 } 879 880 static const unsigned DDDDDecoderTable[] = { 881 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 882 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 883 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 884 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 885 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 886 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 887 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 888 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 889 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 890 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 891 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 892 }; 893 894 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 895 uint64_t Addr, 896 const void *Decoder) { 897 if (RegNo > 31) 898 return Fail; 899 unsigned Register = DDDDDecoderTable[RegNo]; 900 Inst.addOperand(MCOperand::createReg(Register)); 901 return Success; 902 } 903 904 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 905 uint64_t Addr, 906 const void *Decoder) { 907 // scale{5} is asserted as 1 in tblgen. 908 Imm |= 0x20; 909 Inst.addOperand(MCOperand::createImm(64 - Imm)); 910 return Success; 911 } 912 913 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 914 uint64_t Addr, 915 const void *Decoder) { 916 Inst.addOperand(MCOperand::createImm(64 - Imm)); 917 return Success; 918 } 919 920 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 921 uint64_t Addr, const void *Decoder) { 922 int64_t ImmVal = Imm; 923 const AArch64Disassembler *Dis = 924 static_cast<const AArch64Disassembler *>(Decoder); 925 926 // Sign-extend 19-bit immediate. 927 if (ImmVal & (1 << (19 - 1))) 928 ImmVal |= ~((1LL << 19) - 1); 929 930 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 931 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 932 Inst.addOperand(MCOperand::createImm(ImmVal)); 933 return Success; 934 } 935 936 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 937 uint64_t Address, const void *Decoder) { 938 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 939 Inst.addOperand(MCOperand::createImm(Imm & 1)); 940 return Success; 941 } 942 943 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 944 uint64_t Address, 945 const void *Decoder) { 946 Inst.addOperand(MCOperand::createImm(Imm)); 947 948 // Every system register in the encoding space is valid with the syntax 949 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 950 return Success; 951 } 952 953 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 954 uint64_t Address, 955 const void *Decoder) { 956 Inst.addOperand(MCOperand::createImm(Imm)); 957 958 return Success; 959 } 960 961 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 962 uint64_t Address, 963 const void *Decoder) { 964 // This decoder exists to add the dummy Lane operand to the MCInst, which must 965 // be 1 in assembly but has no other real manifestation. 966 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 967 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 968 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 969 970 if (IsToVec) { 971 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 972 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 973 } else { 974 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 975 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 976 } 977 978 // Add the lane 979 Inst.addOperand(MCOperand::createImm(1)); 980 981 return Success; 982 } 983 984 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 985 unsigned Add) { 986 Inst.addOperand(MCOperand::createImm(Add - Imm)); 987 return Success; 988 } 989 990 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 991 unsigned Add) { 992 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 993 return Success; 994 } 995 996 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 997 uint64_t Addr, const void *Decoder) { 998 return DecodeVecShiftRImm(Inst, Imm, 64); 999 } 1000 1001 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 1002 uint64_t Addr, 1003 const void *Decoder) { 1004 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 1005 } 1006 1007 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 1008 uint64_t Addr, const void *Decoder) { 1009 return DecodeVecShiftRImm(Inst, Imm, 32); 1010 } 1011 1012 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 1013 uint64_t Addr, 1014 const void *Decoder) { 1015 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 1016 } 1017 1018 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 1019 uint64_t Addr, const void *Decoder) { 1020 return DecodeVecShiftRImm(Inst, Imm, 16); 1021 } 1022 1023 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 1024 uint64_t Addr, 1025 const void *Decoder) { 1026 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 1027 } 1028 1029 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 1030 uint64_t Addr, const void *Decoder) { 1031 return DecodeVecShiftRImm(Inst, Imm, 8); 1032 } 1033 1034 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 1035 uint64_t Addr, const void *Decoder) { 1036 return DecodeVecShiftLImm(Inst, Imm, 64); 1037 } 1038 1039 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 1040 uint64_t Addr, const void *Decoder) { 1041 return DecodeVecShiftLImm(Inst, Imm, 32); 1042 } 1043 1044 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 1045 uint64_t Addr, const void *Decoder) { 1046 return DecodeVecShiftLImm(Inst, Imm, 16); 1047 } 1048 1049 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 1050 uint64_t Addr, const void *Decoder) { 1051 return DecodeVecShiftLImm(Inst, Imm, 8); 1052 } 1053 1054 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 1055 uint64_t Addr, 1056 const void *Decoder) { 1057 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1058 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1059 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1060 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 1061 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 1062 unsigned shift = (shiftHi << 6) | shiftLo; 1063 switch (Inst.getOpcode()) { 1064 default: 1065 return Fail; 1066 case AArch64::ADDWrs: 1067 case AArch64::ADDSWrs: 1068 case AArch64::SUBWrs: 1069 case AArch64::SUBSWrs: 1070 // if shift == '11' then ReservedValue() 1071 if (shiftHi == 0x3) 1072 return Fail; 1073 LLVM_FALLTHROUGH; 1074 case AArch64::ANDWrs: 1075 case AArch64::ANDSWrs: 1076 case AArch64::BICWrs: 1077 case AArch64::BICSWrs: 1078 case AArch64::ORRWrs: 1079 case AArch64::ORNWrs: 1080 case AArch64::EORWrs: 1081 case AArch64::EONWrs: { 1082 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1083 if (shiftLo >> 5 == 1) 1084 return Fail; 1085 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1086 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1087 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1088 break; 1089 } 1090 case AArch64::ADDXrs: 1091 case AArch64::ADDSXrs: 1092 case AArch64::SUBXrs: 1093 case AArch64::SUBSXrs: 1094 // if shift == '11' then ReservedValue() 1095 if (shiftHi == 0x3) 1096 return Fail; 1097 LLVM_FALLTHROUGH; 1098 case AArch64::ANDXrs: 1099 case AArch64::ANDSXrs: 1100 case AArch64::BICXrs: 1101 case AArch64::BICSXrs: 1102 case AArch64::ORRXrs: 1103 case AArch64::ORNXrs: 1104 case AArch64::EORXrs: 1105 case AArch64::EONXrs: 1106 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1107 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1108 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1109 break; 1110 } 1111 1112 Inst.addOperand(MCOperand::createImm(shift)); 1113 return Success; 1114 } 1115 1116 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1117 uint64_t Addr, 1118 const void *Decoder) { 1119 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1120 unsigned imm = fieldFromInstruction(insn, 5, 16); 1121 unsigned shift = fieldFromInstruction(insn, 21, 2); 1122 shift <<= 4; 1123 switch (Inst.getOpcode()) { 1124 default: 1125 return Fail; 1126 case AArch64::MOVZWi: 1127 case AArch64::MOVNWi: 1128 case AArch64::MOVKWi: 1129 if (shift & (1U << 5)) 1130 return Fail; 1131 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1132 break; 1133 case AArch64::MOVZXi: 1134 case AArch64::MOVNXi: 1135 case AArch64::MOVKXi: 1136 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1137 break; 1138 } 1139 1140 if (Inst.getOpcode() == AArch64::MOVKWi || 1141 Inst.getOpcode() == AArch64::MOVKXi) 1142 Inst.addOperand(Inst.getOperand(0)); 1143 1144 Inst.addOperand(MCOperand::createImm(imm)); 1145 Inst.addOperand(MCOperand::createImm(shift)); 1146 return Success; 1147 } 1148 1149 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1150 uint64_t Addr, 1151 const void *Decoder) { 1152 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1153 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1154 unsigned offset = fieldFromInstruction(insn, 10, 12); 1155 const AArch64Disassembler *Dis = 1156 static_cast<const AArch64Disassembler *>(Decoder); 1157 1158 switch (Inst.getOpcode()) { 1159 default: 1160 return Fail; 1161 case AArch64::PRFMui: 1162 // Rt is an immediate in prefetch. 1163 Inst.addOperand(MCOperand::createImm(Rt)); 1164 break; 1165 case AArch64::STRBBui: 1166 case AArch64::LDRBBui: 1167 case AArch64::LDRSBWui: 1168 case AArch64::STRHHui: 1169 case AArch64::LDRHHui: 1170 case AArch64::LDRSHWui: 1171 case AArch64::STRWui: 1172 case AArch64::LDRWui: 1173 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1174 break; 1175 case AArch64::LDRSBXui: 1176 case AArch64::LDRSHXui: 1177 case AArch64::LDRSWui: 1178 case AArch64::STRXui: 1179 case AArch64::LDRXui: 1180 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1181 break; 1182 case AArch64::LDRQui: 1183 case AArch64::STRQui: 1184 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1185 break; 1186 case AArch64::LDRDui: 1187 case AArch64::STRDui: 1188 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1189 break; 1190 case AArch64::LDRSui: 1191 case AArch64::STRSui: 1192 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1193 break; 1194 case AArch64::LDRHui: 1195 case AArch64::STRHui: 1196 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1197 break; 1198 case AArch64::LDRBui: 1199 case AArch64::STRBui: 1200 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1201 break; 1202 } 1203 1204 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1205 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1206 Inst.addOperand(MCOperand::createImm(offset)); 1207 return Success; 1208 } 1209 1210 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1211 uint64_t Addr, 1212 const void *Decoder) { 1213 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1214 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1215 int64_t offset = fieldFromInstruction(insn, 12, 9); 1216 1217 // offset is a 9-bit signed immediate, so sign extend it to 1218 // fill the unsigned. 1219 if (offset & (1 << (9 - 1))) 1220 offset |= ~((1LL << 9) - 1); 1221 1222 // First operand is always the writeback to the address register, if needed. 1223 switch (Inst.getOpcode()) { 1224 default: 1225 break; 1226 case AArch64::LDRSBWpre: 1227 case AArch64::LDRSHWpre: 1228 case AArch64::STRBBpre: 1229 case AArch64::LDRBBpre: 1230 case AArch64::STRHHpre: 1231 case AArch64::LDRHHpre: 1232 case AArch64::STRWpre: 1233 case AArch64::LDRWpre: 1234 case AArch64::LDRSBWpost: 1235 case AArch64::LDRSHWpost: 1236 case AArch64::STRBBpost: 1237 case AArch64::LDRBBpost: 1238 case AArch64::STRHHpost: 1239 case AArch64::LDRHHpost: 1240 case AArch64::STRWpost: 1241 case AArch64::LDRWpost: 1242 case AArch64::LDRSBXpre: 1243 case AArch64::LDRSHXpre: 1244 case AArch64::STRXpre: 1245 case AArch64::LDRSWpre: 1246 case AArch64::LDRXpre: 1247 case AArch64::LDRSBXpost: 1248 case AArch64::LDRSHXpost: 1249 case AArch64::STRXpost: 1250 case AArch64::LDRSWpost: 1251 case AArch64::LDRXpost: 1252 case AArch64::LDRQpre: 1253 case AArch64::STRQpre: 1254 case AArch64::LDRQpost: 1255 case AArch64::STRQpost: 1256 case AArch64::LDRDpre: 1257 case AArch64::STRDpre: 1258 case AArch64::LDRDpost: 1259 case AArch64::STRDpost: 1260 case AArch64::LDRSpre: 1261 case AArch64::STRSpre: 1262 case AArch64::LDRSpost: 1263 case AArch64::STRSpost: 1264 case AArch64::LDRHpre: 1265 case AArch64::STRHpre: 1266 case AArch64::LDRHpost: 1267 case AArch64::STRHpost: 1268 case AArch64::LDRBpre: 1269 case AArch64::STRBpre: 1270 case AArch64::LDRBpost: 1271 case AArch64::STRBpost: 1272 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1273 break; 1274 } 1275 1276 switch (Inst.getOpcode()) { 1277 default: 1278 return Fail; 1279 case AArch64::PRFUMi: 1280 // Rt is an immediate in prefetch. 1281 Inst.addOperand(MCOperand::createImm(Rt)); 1282 break; 1283 case AArch64::STURBBi: 1284 case AArch64::LDURBBi: 1285 case AArch64::LDURSBWi: 1286 case AArch64::STURHHi: 1287 case AArch64::LDURHHi: 1288 case AArch64::LDURSHWi: 1289 case AArch64::STURWi: 1290 case AArch64::LDURWi: 1291 case AArch64::LDTRSBWi: 1292 case AArch64::LDTRSHWi: 1293 case AArch64::STTRWi: 1294 case AArch64::LDTRWi: 1295 case AArch64::STTRHi: 1296 case AArch64::LDTRHi: 1297 case AArch64::LDTRBi: 1298 case AArch64::STTRBi: 1299 case AArch64::LDRSBWpre: 1300 case AArch64::LDRSHWpre: 1301 case AArch64::STRBBpre: 1302 case AArch64::LDRBBpre: 1303 case AArch64::STRHHpre: 1304 case AArch64::LDRHHpre: 1305 case AArch64::STRWpre: 1306 case AArch64::LDRWpre: 1307 case AArch64::LDRSBWpost: 1308 case AArch64::LDRSHWpost: 1309 case AArch64::STRBBpost: 1310 case AArch64::LDRBBpost: 1311 case AArch64::STRHHpost: 1312 case AArch64::LDRHHpost: 1313 case AArch64::STRWpost: 1314 case AArch64::LDRWpost: 1315 case AArch64::STLURBi: 1316 case AArch64::STLURHi: 1317 case AArch64::STLURWi: 1318 case AArch64::LDAPURBi: 1319 case AArch64::LDAPURSBWi: 1320 case AArch64::LDAPURHi: 1321 case AArch64::LDAPURSHWi: 1322 case AArch64::LDAPURi: 1323 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1324 break; 1325 case AArch64::LDURSBXi: 1326 case AArch64::LDURSHXi: 1327 case AArch64::LDURSWi: 1328 case AArch64::STURXi: 1329 case AArch64::LDURXi: 1330 case AArch64::LDTRSBXi: 1331 case AArch64::LDTRSHXi: 1332 case AArch64::LDTRSWi: 1333 case AArch64::STTRXi: 1334 case AArch64::LDTRXi: 1335 case AArch64::LDRSBXpre: 1336 case AArch64::LDRSHXpre: 1337 case AArch64::STRXpre: 1338 case AArch64::LDRSWpre: 1339 case AArch64::LDRXpre: 1340 case AArch64::LDRSBXpost: 1341 case AArch64::LDRSHXpost: 1342 case AArch64::STRXpost: 1343 case AArch64::LDRSWpost: 1344 case AArch64::LDRXpost: 1345 case AArch64::LDAPURSWi: 1346 case AArch64::LDAPURSHXi: 1347 case AArch64::LDAPURSBXi: 1348 case AArch64::STLURXi: 1349 case AArch64::LDAPURXi: 1350 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1351 break; 1352 case AArch64::LDURQi: 1353 case AArch64::STURQi: 1354 case AArch64::LDRQpre: 1355 case AArch64::STRQpre: 1356 case AArch64::LDRQpost: 1357 case AArch64::STRQpost: 1358 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1359 break; 1360 case AArch64::LDURDi: 1361 case AArch64::STURDi: 1362 case AArch64::LDRDpre: 1363 case AArch64::STRDpre: 1364 case AArch64::LDRDpost: 1365 case AArch64::STRDpost: 1366 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1367 break; 1368 case AArch64::LDURSi: 1369 case AArch64::STURSi: 1370 case AArch64::LDRSpre: 1371 case AArch64::STRSpre: 1372 case AArch64::LDRSpost: 1373 case AArch64::STRSpost: 1374 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1375 break; 1376 case AArch64::LDURHi: 1377 case AArch64::STURHi: 1378 case AArch64::LDRHpre: 1379 case AArch64::STRHpre: 1380 case AArch64::LDRHpost: 1381 case AArch64::STRHpost: 1382 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1383 break; 1384 case AArch64::LDURBi: 1385 case AArch64::STURBi: 1386 case AArch64::LDRBpre: 1387 case AArch64::STRBpre: 1388 case AArch64::LDRBpost: 1389 case AArch64::STRBpost: 1390 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1391 break; 1392 } 1393 1394 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1395 Inst.addOperand(MCOperand::createImm(offset)); 1396 1397 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1398 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1399 bool IsFP = fieldFromInstruction(insn, 26, 1); 1400 1401 // Cannot write back to a transfer register (but xzr != sp). 1402 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1403 return SoftFail; 1404 1405 return Success; 1406 } 1407 1408 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1409 uint64_t Addr, 1410 const void *Decoder) { 1411 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1412 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1413 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1414 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1415 1416 unsigned Opcode = Inst.getOpcode(); 1417 switch (Opcode) { 1418 default: 1419 return Fail; 1420 case AArch64::STLXRW: 1421 case AArch64::STLXRB: 1422 case AArch64::STLXRH: 1423 case AArch64::STXRW: 1424 case AArch64::STXRB: 1425 case AArch64::STXRH: 1426 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1427 LLVM_FALLTHROUGH; 1428 case AArch64::LDARW: 1429 case AArch64::LDARB: 1430 case AArch64::LDARH: 1431 case AArch64::LDAXRW: 1432 case AArch64::LDAXRB: 1433 case AArch64::LDAXRH: 1434 case AArch64::LDXRW: 1435 case AArch64::LDXRB: 1436 case AArch64::LDXRH: 1437 case AArch64::STLRW: 1438 case AArch64::STLRB: 1439 case AArch64::STLRH: 1440 case AArch64::STLLRW: 1441 case AArch64::STLLRB: 1442 case AArch64::STLLRH: 1443 case AArch64::LDLARW: 1444 case AArch64::LDLARB: 1445 case AArch64::LDLARH: 1446 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1447 break; 1448 case AArch64::STLXRX: 1449 case AArch64::STXRX: 1450 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1451 LLVM_FALLTHROUGH; 1452 case AArch64::LDARX: 1453 case AArch64::LDAXRX: 1454 case AArch64::LDXRX: 1455 case AArch64::STLRX: 1456 case AArch64::LDLARX: 1457 case AArch64::STLLRX: 1458 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1459 break; 1460 case AArch64::STLXPW: 1461 case AArch64::STXPW: 1462 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1463 LLVM_FALLTHROUGH; 1464 case AArch64::LDAXPW: 1465 case AArch64::LDXPW: 1466 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1467 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1468 break; 1469 case AArch64::STLXPX: 1470 case AArch64::STXPX: 1471 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1472 LLVM_FALLTHROUGH; 1473 case AArch64::LDAXPX: 1474 case AArch64::LDXPX: 1475 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1476 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1477 break; 1478 } 1479 1480 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1481 1482 // You shouldn't load to the same register twice in an instruction... 1483 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1484 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1485 Rt == Rt2) 1486 return SoftFail; 1487 1488 return Success; 1489 } 1490 1491 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1492 uint64_t Addr, 1493 const void *Decoder) { 1494 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1495 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1496 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1497 int64_t offset = fieldFromInstruction(insn, 15, 7); 1498 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1499 1500 // offset is a 7-bit signed immediate, so sign extend it to 1501 // fill the unsigned. 1502 if (offset & (1 << (7 - 1))) 1503 offset |= ~((1LL << 7) - 1); 1504 1505 unsigned Opcode = Inst.getOpcode(); 1506 bool NeedsDisjointWritebackTransfer = false; 1507 1508 // First operand is always writeback of base register. 1509 switch (Opcode) { 1510 default: 1511 break; 1512 case AArch64::LDPXpost: 1513 case AArch64::STPXpost: 1514 case AArch64::LDPSWpost: 1515 case AArch64::LDPXpre: 1516 case AArch64::STPXpre: 1517 case AArch64::LDPSWpre: 1518 case AArch64::LDPWpost: 1519 case AArch64::STPWpost: 1520 case AArch64::LDPWpre: 1521 case AArch64::STPWpre: 1522 case AArch64::LDPQpost: 1523 case AArch64::STPQpost: 1524 case AArch64::LDPQpre: 1525 case AArch64::STPQpre: 1526 case AArch64::LDPDpost: 1527 case AArch64::STPDpost: 1528 case AArch64::LDPDpre: 1529 case AArch64::STPDpre: 1530 case AArch64::LDPSpost: 1531 case AArch64::STPSpost: 1532 case AArch64::LDPSpre: 1533 case AArch64::STPSpre: 1534 case AArch64::STGPpre: 1535 case AArch64::STGPpost: 1536 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1537 break; 1538 } 1539 1540 switch (Opcode) { 1541 default: 1542 return Fail; 1543 case AArch64::LDPXpost: 1544 case AArch64::STPXpost: 1545 case AArch64::LDPSWpost: 1546 case AArch64::LDPXpre: 1547 case AArch64::STPXpre: 1548 case AArch64::LDPSWpre: 1549 case AArch64::STGPpre: 1550 case AArch64::STGPpost: 1551 NeedsDisjointWritebackTransfer = true; 1552 LLVM_FALLTHROUGH; 1553 case AArch64::LDNPXi: 1554 case AArch64::STNPXi: 1555 case AArch64::LDPXi: 1556 case AArch64::STPXi: 1557 case AArch64::LDPSWi: 1558 case AArch64::STGPi: 1559 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1560 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1561 break; 1562 case AArch64::LDPWpost: 1563 case AArch64::STPWpost: 1564 case AArch64::LDPWpre: 1565 case AArch64::STPWpre: 1566 NeedsDisjointWritebackTransfer = true; 1567 LLVM_FALLTHROUGH; 1568 case AArch64::LDNPWi: 1569 case AArch64::STNPWi: 1570 case AArch64::LDPWi: 1571 case AArch64::STPWi: 1572 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1573 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1574 break; 1575 case AArch64::LDNPQi: 1576 case AArch64::STNPQi: 1577 case AArch64::LDPQpost: 1578 case AArch64::STPQpost: 1579 case AArch64::LDPQi: 1580 case AArch64::STPQi: 1581 case AArch64::LDPQpre: 1582 case AArch64::STPQpre: 1583 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1584 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1585 break; 1586 case AArch64::LDNPDi: 1587 case AArch64::STNPDi: 1588 case AArch64::LDPDpost: 1589 case AArch64::STPDpost: 1590 case AArch64::LDPDi: 1591 case AArch64::STPDi: 1592 case AArch64::LDPDpre: 1593 case AArch64::STPDpre: 1594 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1595 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1596 break; 1597 case AArch64::LDNPSi: 1598 case AArch64::STNPSi: 1599 case AArch64::LDPSpost: 1600 case AArch64::STPSpost: 1601 case AArch64::LDPSi: 1602 case AArch64::STPSi: 1603 case AArch64::LDPSpre: 1604 case AArch64::STPSpre: 1605 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1606 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1607 break; 1608 } 1609 1610 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1611 Inst.addOperand(MCOperand::createImm(offset)); 1612 1613 // You shouldn't load to the same register twice in an instruction... 1614 if (IsLoad && Rt == Rt2) 1615 return SoftFail; 1616 1617 // ... or do any operation that writes-back to a transfer register. But note 1618 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1619 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1620 return SoftFail; 1621 1622 return Success; 1623 } 1624 1625 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1626 uint64_t Addr, 1627 const void *Decoder) { 1628 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1629 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1630 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1631 fieldFromInstruction(insn, 12, 9); 1632 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1633 1634 switch (Inst.getOpcode()) { 1635 default: 1636 return Fail; 1637 case AArch64::LDRAAwriteback: 1638 case AArch64::LDRABwriteback: 1639 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1640 Decoder); 1641 break; 1642 case AArch64::LDRAAindexed: 1643 case AArch64::LDRABindexed: 1644 break; 1645 } 1646 1647 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1648 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1649 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1650 1651 if (writeback && Rt == Rn && Rn != 31) { 1652 return SoftFail; 1653 } 1654 1655 return Success; 1656 } 1657 1658 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1659 uint64_t Addr, 1660 const void *Decoder) { 1661 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1662 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1663 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1664 unsigned extend = fieldFromInstruction(insn, 10, 6); 1665 1666 unsigned shift = extend & 0x7; 1667 if (shift > 4) 1668 return Fail; 1669 1670 switch (Inst.getOpcode()) { 1671 default: 1672 return Fail; 1673 case AArch64::ADDWrx: 1674 case AArch64::SUBWrx: 1675 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1676 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1677 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1678 break; 1679 case AArch64::ADDSWrx: 1680 case AArch64::SUBSWrx: 1681 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1682 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1683 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1684 break; 1685 case AArch64::ADDXrx: 1686 case AArch64::SUBXrx: 1687 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1688 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1689 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1690 break; 1691 case AArch64::ADDSXrx: 1692 case AArch64::SUBSXrx: 1693 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1694 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1695 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1696 break; 1697 case AArch64::ADDXrx64: 1698 case AArch64::SUBXrx64: 1699 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1700 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1701 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1702 break; 1703 case AArch64::SUBSXrx64: 1704 case AArch64::ADDSXrx64: 1705 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1706 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1707 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1708 break; 1709 } 1710 1711 Inst.addOperand(MCOperand::createImm(extend)); 1712 return Success; 1713 } 1714 1715 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1716 uint64_t Addr, 1717 const void *Decoder) { 1718 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1719 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1720 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1721 unsigned imm; 1722 1723 if (Datasize) { 1724 if (Inst.getOpcode() == AArch64::ANDSXri) 1725 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1726 else 1727 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1728 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1729 imm = fieldFromInstruction(insn, 10, 13); 1730 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1731 return Fail; 1732 } else { 1733 if (Inst.getOpcode() == AArch64::ANDSWri) 1734 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1735 else 1736 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1737 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1738 imm = fieldFromInstruction(insn, 10, 12); 1739 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1740 return Fail; 1741 } 1742 Inst.addOperand(MCOperand::createImm(imm)); 1743 return Success; 1744 } 1745 1746 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1747 uint64_t Addr, 1748 const void *Decoder) { 1749 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1750 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1751 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1752 imm |= fieldFromInstruction(insn, 5, 5); 1753 1754 if (Inst.getOpcode() == AArch64::MOVID) 1755 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1756 else 1757 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1758 1759 Inst.addOperand(MCOperand::createImm(imm)); 1760 1761 switch (Inst.getOpcode()) { 1762 default: 1763 break; 1764 case AArch64::MOVIv4i16: 1765 case AArch64::MOVIv8i16: 1766 case AArch64::MVNIv4i16: 1767 case AArch64::MVNIv8i16: 1768 case AArch64::MOVIv2i32: 1769 case AArch64::MOVIv4i32: 1770 case AArch64::MVNIv2i32: 1771 case AArch64::MVNIv4i32: 1772 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1773 break; 1774 case AArch64::MOVIv2s_msl: 1775 case AArch64::MOVIv4s_msl: 1776 case AArch64::MVNIv2s_msl: 1777 case AArch64::MVNIv4s_msl: 1778 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1779 break; 1780 } 1781 1782 return Success; 1783 } 1784 1785 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1786 uint64_t Addr, 1787 const void *Decoder) { 1788 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1789 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1790 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1791 imm |= fieldFromInstruction(insn, 5, 5); 1792 1793 // Tied operands added twice. 1794 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1795 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1796 1797 Inst.addOperand(MCOperand::createImm(imm)); 1798 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1799 1800 return Success; 1801 } 1802 1803 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1804 uint64_t Addr, const void *Decoder) { 1805 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1806 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1807 imm |= fieldFromInstruction(insn, 29, 2); 1808 const AArch64Disassembler *Dis = 1809 static_cast<const AArch64Disassembler *>(Decoder); 1810 1811 // Sign-extend the 21-bit immediate. 1812 if (imm & (1 << (21 - 1))) 1813 imm |= ~((1LL << 21) - 1); 1814 1815 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1816 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1817 Inst.addOperand(MCOperand::createImm(imm)); 1818 1819 return Success; 1820 } 1821 1822 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1823 uint64_t Addr, const void *Decoder) { 1824 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1825 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1826 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1827 unsigned S = fieldFromInstruction(insn, 29, 1); 1828 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1829 1830 unsigned ShifterVal = (Imm >> 12) & 3; 1831 unsigned ImmVal = Imm & 0xFFF; 1832 const AArch64Disassembler *Dis = 1833 static_cast<const AArch64Disassembler *>(Decoder); 1834 1835 if (ShifterVal != 0 && ShifterVal != 1) 1836 return Fail; 1837 1838 if (Datasize) { 1839 if (Rd == 31 && !S) 1840 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1841 else 1842 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1843 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1844 } else { 1845 if (Rd == 31 && !S) 1846 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1847 else 1848 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1849 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1850 } 1851 1852 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1853 Inst.addOperand(MCOperand::createImm(ImmVal)); 1854 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1855 return Success; 1856 } 1857 1858 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1859 uint64_t Addr, 1860 const void *Decoder) { 1861 int64_t imm = fieldFromInstruction(insn, 0, 26); 1862 const AArch64Disassembler *Dis = 1863 static_cast<const AArch64Disassembler *>(Decoder); 1864 1865 // Sign-extend the 26-bit immediate. 1866 if (imm & (1 << (26 - 1))) 1867 imm |= ~((1LL << 26) - 1); 1868 1869 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1870 Inst.addOperand(MCOperand::createImm(imm)); 1871 1872 return Success; 1873 } 1874 1875 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1876 uint64_t Addr, 1877 const void *Decoder) { 1878 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1879 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1880 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1881 uint64_t pstate_field = (op1 << 3) | op2; 1882 1883 switch (pstate_field) { 1884 case 0x01: // XAFlag 1885 case 0x02: // AXFlag 1886 return Fail; 1887 } 1888 1889 if ((pstate_field == AArch64PState::PAN || 1890 pstate_field == AArch64PState::UAO || 1891 pstate_field == AArch64PState::SSBS) && crm > 1) 1892 return Fail; 1893 1894 Inst.addOperand(MCOperand::createImm(pstate_field)); 1895 Inst.addOperand(MCOperand::createImm(crm)); 1896 1897 const AArch64Disassembler *Dis = 1898 static_cast<const AArch64Disassembler *>(Decoder); 1899 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1900 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1901 return Success; 1902 return Fail; 1903 } 1904 1905 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1906 uint64_t Addr, const void *Decoder) { 1907 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1908 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1909 bit |= fieldFromInstruction(insn, 19, 5); 1910 int64_t dst = fieldFromInstruction(insn, 5, 14); 1911 const AArch64Disassembler *Dis = 1912 static_cast<const AArch64Disassembler *>(Decoder); 1913 1914 // Sign-extend 14-bit immediate. 1915 if (dst & (1 << (14 - 1))) 1916 dst |= ~((1LL << 14) - 1); 1917 1918 if (fieldFromInstruction(insn, 31, 1) == 0) 1919 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1920 else 1921 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1922 Inst.addOperand(MCOperand::createImm(bit)); 1923 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1924 Inst.addOperand(MCOperand::createImm(dst)); 1925 1926 return Success; 1927 } 1928 1929 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1930 unsigned RegClassID, 1931 unsigned RegNo, 1932 uint64_t Addr, 1933 const void *Decoder) { 1934 // Register number must be even (see CASP instruction) 1935 if (RegNo & 0x1) 1936 return Fail; 1937 1938 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1939 Inst.addOperand(MCOperand::createReg(Reg)); 1940 return Success; 1941 } 1942 1943 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1944 unsigned RegNo, 1945 uint64_t Addr, 1946 const void *Decoder) { 1947 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1948 AArch64::WSeqPairsClassRegClassID, 1949 RegNo, Addr, Decoder); 1950 } 1951 1952 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1953 unsigned RegNo, 1954 uint64_t Addr, 1955 const void *Decoder) { 1956 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1957 AArch64::XSeqPairsClassRegClassID, 1958 RegNo, Addr, Decoder); 1959 } 1960 1961 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, 1962 uint64_t Addr, 1963 const void *Decoder) { 1964 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1965 unsigned imm = fieldFromInstruction(insn, 5, 13); 1966 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1967 return Fail; 1968 1969 // The same (tied) operand is added twice to the instruction. 1970 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1971 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1972 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1973 Inst.addOperand(MCOperand::createImm(imm)); 1974 return Success; 1975 } 1976 1977 template <int Bits> 1978 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 1979 const void *Decoder) { 1980 if (Imm & ~((1LL << Bits) - 1)) 1981 return Fail; 1982 1983 // Imm is a signed immediate, so sign extend it. 1984 if (Imm & (1 << (Bits - 1))) 1985 Imm |= ~((1LL << Bits) - 1); 1986 1987 Inst.addOperand(MCOperand::createImm(Imm)); 1988 return Success; 1989 } 1990 1991 // Decode 8-bit signed/unsigned immediate for a given element width. 1992 template <int ElementWidth> 1993 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1994 uint64_t Addr, const void *Decoder) { 1995 unsigned Val = (uint8_t)Imm; 1996 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1997 if (ElementWidth == 8 && Shift) 1998 return Fail; 1999 Inst.addOperand(MCOperand::createImm(Val)); 2000 Inst.addOperand(MCOperand::createImm(Shift)); 2001 return Success; 2002 } 2003 2004 // Decode uimm4 ranged from 1-16. 2005 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 2006 uint64_t Addr, const void *Decoder) { 2007 Inst.addOperand(MCOperand::createImm(Imm + 1)); 2008 return Success; 2009 } 2010 2011 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 2012 const void *Decoder) { 2013 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 2014 Inst.addOperand(MCOperand::createImm(Imm)); 2015 return Success; 2016 } 2017 return Fail; 2018 } 2019