1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm-c/Disassembler.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include <algorithm> 28 #include <memory> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "aarch64-disassembler" 33 34 // Pull DecodeStatus and its enum values into the global namespace. 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 // Forward declare these because the autogenerated code will reference them. 38 // Definitions are further down. 39 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 40 unsigned RegNo, uint64_t Address, 41 const void *Decoder); 42 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 43 unsigned RegNo, 44 uint64_t Address, 45 const void *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const void *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const void *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const void *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const void *Decoder); 58 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 59 uint64_t Address, 60 const void *Decoder); 61 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 62 unsigned RegNo, uint64_t Address, 63 const void *Decoder); 64 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 65 uint64_t Address, 66 const void *Decoder); 67 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 68 unsigned RegNo, uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decode); 91 92 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 93 uint64_t Address, 94 const void *Decoder); 95 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 96 uint64_t Address, 97 const void *Decoder); 98 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 99 uint64_t Address, const void *Decoder); 100 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 101 uint64_t Address, const void *Decoder); 102 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 103 uint64_t Address, const void *Decoder); 104 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 105 uint64_t Address, const void *Decoder); 106 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 116 uint64_t Address, 117 const void *Decoder); 118 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 134 uint64_t Address, 135 const void *Decoder); 136 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 141 uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 144 uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 147 uint64_t Address, const void *Decoder); 148 149 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 153 uint64_t Addr, const void *Decoder); 154 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 155 uint64_t Addr, 156 const void *Decoder); 157 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 158 uint64_t Addr, const void *Decoder); 159 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 160 uint64_t Addr, 161 const void *Decoder); 162 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 163 uint64_t Addr, const void *Decoder); 164 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 165 uint64_t Addr, 166 const void *Decoder); 167 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 168 uint64_t Addr, const void *Decoder); 169 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 170 uint64_t Addr, const void *Decoder); 171 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 172 uint64_t Addr, const void *Decoder); 173 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 174 uint64_t Addr, const void *Decoder); 175 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 176 uint64_t Addr, const void *Decoder); 177 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Addr, 180 const void *Decoder); 181 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Addr, 184 const void *Decoder); 185 template<int Bits> 186 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 187 uint64_t Address, const void *Decoder); 188 189 static bool Check(DecodeStatus &Out, DecodeStatus In) { 190 switch (In) { 191 case MCDisassembler::Success: 192 // Out stays the same. 193 return true; 194 case MCDisassembler::SoftFail: 195 Out = In; 196 return true; 197 case MCDisassembler::Fail: 198 Out = In; 199 return false; 200 } 201 llvm_unreachable("Invalid DecodeStatus!"); 202 } 203 204 #include "AArch64GenDisassemblerTables.inc" 205 #include "AArch64GenInstrInfo.inc" 206 207 #define Success MCDisassembler::Success 208 #define Fail MCDisassembler::Fail 209 #define SoftFail MCDisassembler::SoftFail 210 211 static MCDisassembler *createAArch64Disassembler(const Target &T, 212 const MCSubtargetInfo &STI, 213 MCContext &Ctx) { 214 return new AArch64Disassembler(STI, Ctx); 215 } 216 217 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 218 ArrayRef<uint8_t> Bytes, 219 uint64_t Address, 220 raw_ostream &OS, 221 raw_ostream &CS) const { 222 CommentStream = &CS; 223 224 Size = 0; 225 // We want to read exactly 4 bytes of data. 226 if (Bytes.size() < 4) 227 return Fail; 228 Size = 4; 229 230 // Encoded as a small-endian 32-bit word in the stream. 231 uint32_t Insn = 232 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 233 234 // Calling the auto-generated decoder function. 235 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 236 } 237 238 static MCSymbolizer * 239 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 240 LLVMSymbolLookupCallback SymbolLookUp, 241 void *DisInfo, MCContext *Ctx, 242 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 243 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 244 SymbolLookUp, DisInfo); 245 } 246 247 extern "C" void LLVMInitializeAArch64Disassembler() { 248 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 249 createAArch64Disassembler); 250 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 251 createAArch64Disassembler); 252 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 253 createAArch64ExternalSymbolizer); 254 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 255 createAArch64ExternalSymbolizer); 256 257 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 258 createAArch64Disassembler); 259 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 260 createAArch64ExternalSymbolizer); 261 } 262 263 static const unsigned FPR128DecoderTable[] = { 264 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 265 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 266 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 267 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 268 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 269 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 270 AArch64::Q30, AArch64::Q31 271 }; 272 273 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 274 uint64_t Addr, 275 const void *Decoder) { 276 if (RegNo > 31) 277 return Fail; 278 279 unsigned Register = FPR128DecoderTable[RegNo]; 280 Inst.addOperand(MCOperand::createReg(Register)); 281 return Success; 282 } 283 284 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 285 uint64_t Addr, 286 const void *Decoder) { 287 if (RegNo > 15) 288 return Fail; 289 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 290 } 291 292 static const unsigned FPR64DecoderTable[] = { 293 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 294 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 295 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 296 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 297 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 298 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 299 AArch64::D30, AArch64::D31 300 }; 301 302 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 303 uint64_t Addr, 304 const void *Decoder) { 305 if (RegNo > 31) 306 return Fail; 307 308 unsigned Register = FPR64DecoderTable[RegNo]; 309 Inst.addOperand(MCOperand::createReg(Register)); 310 return Success; 311 } 312 313 static const unsigned FPR32DecoderTable[] = { 314 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 315 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 316 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 317 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 318 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 319 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 320 AArch64::S30, AArch64::S31 321 }; 322 323 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 324 uint64_t Addr, 325 const void *Decoder) { 326 if (RegNo > 31) 327 return Fail; 328 329 unsigned Register = FPR32DecoderTable[RegNo]; 330 Inst.addOperand(MCOperand::createReg(Register)); 331 return Success; 332 } 333 334 static const unsigned FPR16DecoderTable[] = { 335 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 336 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 337 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 338 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 339 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 340 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 341 AArch64::H30, AArch64::H31 342 }; 343 344 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 345 uint64_t Addr, 346 const void *Decoder) { 347 if (RegNo > 31) 348 return Fail; 349 350 unsigned Register = FPR16DecoderTable[RegNo]; 351 Inst.addOperand(MCOperand::createReg(Register)); 352 return Success; 353 } 354 355 static const unsigned FPR8DecoderTable[] = { 356 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 357 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 358 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 359 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 360 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 361 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 362 AArch64::B30, AArch64::B31 363 }; 364 365 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 366 uint64_t Addr, 367 const void *Decoder) { 368 if (RegNo > 31) 369 return Fail; 370 371 unsigned Register = FPR8DecoderTable[RegNo]; 372 Inst.addOperand(MCOperand::createReg(Register)); 373 return Success; 374 } 375 376 static const unsigned GPR64DecoderTable[] = { 377 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 378 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 379 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 380 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 381 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 382 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 383 AArch64::LR, AArch64::XZR 384 }; 385 386 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 387 uint64_t Addr, 388 const void *Decoder) { 389 if (RegNo > 31) 390 return Fail; 391 392 unsigned Register = GPR64DecoderTable[RegNo]; 393 Inst.addOperand(MCOperand::createReg(Register)); 394 return Success; 395 } 396 397 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 398 uint64_t Addr, 399 const void *Decoder) { 400 if (RegNo > 31) 401 return Fail; 402 unsigned Register = GPR64DecoderTable[RegNo]; 403 if (Register == AArch64::XZR) 404 Register = AArch64::SP; 405 Inst.addOperand(MCOperand::createReg(Register)); 406 return Success; 407 } 408 409 static const unsigned GPR32DecoderTable[] = { 410 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 411 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 412 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 413 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 414 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 415 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 416 AArch64::W30, AArch64::WZR 417 }; 418 419 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 420 uint64_t Addr, 421 const void *Decoder) { 422 if (RegNo > 31) 423 return Fail; 424 425 unsigned Register = GPR32DecoderTable[RegNo]; 426 Inst.addOperand(MCOperand::createReg(Register)); 427 return Success; 428 } 429 430 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 431 uint64_t Addr, 432 const void *Decoder) { 433 if (RegNo > 31) 434 return Fail; 435 436 unsigned Register = GPR32DecoderTable[RegNo]; 437 if (Register == AArch64::WZR) 438 Register = AArch64::WSP; 439 Inst.addOperand(MCOperand::createReg(Register)); 440 return Success; 441 } 442 static const unsigned ZPRDecoderTable[] = { 443 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 444 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 445 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 446 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 447 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 448 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 449 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 450 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 451 }; 452 453 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 454 uint64_t Address, 455 const void* Decoder) { 456 if (RegNo > 31) 457 return Fail; 458 459 unsigned Register = ZPRDecoderTable[RegNo]; 460 Inst.addOperand(MCOperand::createReg(Register)); 461 return Success; 462 } 463 464 static const unsigned VectorDecoderTable[] = { 465 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 466 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 467 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 468 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 469 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 470 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 471 AArch64::Q30, AArch64::Q31 472 }; 473 474 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 475 uint64_t Addr, 476 const void *Decoder) { 477 if (RegNo > 31) 478 return Fail; 479 480 unsigned Register = VectorDecoderTable[RegNo]; 481 Inst.addOperand(MCOperand::createReg(Register)); 482 return Success; 483 } 484 485 static const unsigned QQDecoderTable[] = { 486 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 487 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 488 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 489 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 490 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 491 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 492 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 493 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 494 }; 495 496 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 497 uint64_t Addr, const void *Decoder) { 498 if (RegNo > 31) 499 return Fail; 500 unsigned Register = QQDecoderTable[RegNo]; 501 Inst.addOperand(MCOperand::createReg(Register)); 502 return Success; 503 } 504 505 static const unsigned QQQDecoderTable[] = { 506 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 507 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 508 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 509 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 510 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 511 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 512 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 513 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 514 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 515 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 516 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 517 }; 518 519 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 520 uint64_t Addr, const void *Decoder) { 521 if (RegNo > 31) 522 return Fail; 523 unsigned Register = QQQDecoderTable[RegNo]; 524 Inst.addOperand(MCOperand::createReg(Register)); 525 return Success; 526 } 527 528 static const unsigned QQQQDecoderTable[] = { 529 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 530 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 531 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 532 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 533 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 534 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 535 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 536 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 537 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 538 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 539 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 540 }; 541 542 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 543 uint64_t Addr, 544 const void *Decoder) { 545 if (RegNo > 31) 546 return Fail; 547 unsigned Register = QQQQDecoderTable[RegNo]; 548 Inst.addOperand(MCOperand::createReg(Register)); 549 return Success; 550 } 551 552 static const unsigned DDDecoderTable[] = { 553 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 554 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 555 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 556 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 557 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 558 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 559 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 560 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 561 }; 562 563 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 564 uint64_t Addr, const void *Decoder) { 565 if (RegNo > 31) 566 return Fail; 567 unsigned Register = DDDecoderTable[RegNo]; 568 Inst.addOperand(MCOperand::createReg(Register)); 569 return Success; 570 } 571 572 static const unsigned DDDDecoderTable[] = { 573 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 574 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 575 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 576 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 577 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 578 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 579 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 580 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 581 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 582 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 583 AArch64::D30_D31_D0, AArch64::D31_D0_D1 584 }; 585 586 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 587 uint64_t Addr, const void *Decoder) { 588 if (RegNo > 31) 589 return Fail; 590 unsigned Register = DDDDecoderTable[RegNo]; 591 Inst.addOperand(MCOperand::createReg(Register)); 592 return Success; 593 } 594 595 static const unsigned DDDDDecoderTable[] = { 596 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 597 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 598 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 599 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 600 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 601 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 602 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 603 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 604 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 605 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 606 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 607 }; 608 609 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 610 uint64_t Addr, 611 const void *Decoder) { 612 if (RegNo > 31) 613 return Fail; 614 unsigned Register = DDDDDecoderTable[RegNo]; 615 Inst.addOperand(MCOperand::createReg(Register)); 616 return Success; 617 } 618 619 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 620 uint64_t Addr, 621 const void *Decoder) { 622 // scale{5} is asserted as 1 in tblgen. 623 Imm |= 0x20; 624 Inst.addOperand(MCOperand::createImm(64 - Imm)); 625 return Success; 626 } 627 628 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 629 uint64_t Addr, 630 const void *Decoder) { 631 Inst.addOperand(MCOperand::createImm(64 - Imm)); 632 return Success; 633 } 634 635 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 636 uint64_t Addr, const void *Decoder) { 637 int64_t ImmVal = Imm; 638 const AArch64Disassembler *Dis = 639 static_cast<const AArch64Disassembler *>(Decoder); 640 641 // Sign-extend 19-bit immediate. 642 if (ImmVal & (1 << (19 - 1))) 643 ImmVal |= ~((1LL << 19) - 1); 644 645 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 646 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 647 Inst.addOperand(MCOperand::createImm(ImmVal)); 648 return Success; 649 } 650 651 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 652 uint64_t Address, const void *Decoder) { 653 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 654 Inst.addOperand(MCOperand::createImm(Imm & 1)); 655 return Success; 656 } 657 658 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 659 uint64_t Address, 660 const void *Decoder) { 661 Inst.addOperand(MCOperand::createImm(Imm)); 662 663 // Every system register in the encoding space is valid with the syntax 664 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 665 return Success; 666 } 667 668 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 669 uint64_t Address, 670 const void *Decoder) { 671 Inst.addOperand(MCOperand::createImm(Imm)); 672 673 return Success; 674 } 675 676 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 677 uint64_t Address, 678 const void *Decoder) { 679 // This decoder exists to add the dummy Lane operand to the MCInst, which must 680 // be 1 in assembly but has no other real manifestation. 681 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 682 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 683 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 684 685 if (IsToVec) { 686 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 687 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 688 } else { 689 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 690 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 691 } 692 693 // Add the lane 694 Inst.addOperand(MCOperand::createImm(1)); 695 696 return Success; 697 } 698 699 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 700 unsigned Add) { 701 Inst.addOperand(MCOperand::createImm(Add - Imm)); 702 return Success; 703 } 704 705 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 706 unsigned Add) { 707 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 708 return Success; 709 } 710 711 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 712 uint64_t Addr, const void *Decoder) { 713 return DecodeVecShiftRImm(Inst, Imm, 64); 714 } 715 716 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 717 uint64_t Addr, 718 const void *Decoder) { 719 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 720 } 721 722 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 723 uint64_t Addr, const void *Decoder) { 724 return DecodeVecShiftRImm(Inst, Imm, 32); 725 } 726 727 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 728 uint64_t Addr, 729 const void *Decoder) { 730 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 731 } 732 733 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 734 uint64_t Addr, const void *Decoder) { 735 return DecodeVecShiftRImm(Inst, Imm, 16); 736 } 737 738 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 739 uint64_t Addr, 740 const void *Decoder) { 741 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 742 } 743 744 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 745 uint64_t Addr, const void *Decoder) { 746 return DecodeVecShiftRImm(Inst, Imm, 8); 747 } 748 749 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 750 uint64_t Addr, const void *Decoder) { 751 return DecodeVecShiftLImm(Inst, Imm, 64); 752 } 753 754 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 755 uint64_t Addr, const void *Decoder) { 756 return DecodeVecShiftLImm(Inst, Imm, 32); 757 } 758 759 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 760 uint64_t Addr, const void *Decoder) { 761 return DecodeVecShiftLImm(Inst, Imm, 16); 762 } 763 764 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 765 uint64_t Addr, const void *Decoder) { 766 return DecodeVecShiftLImm(Inst, Imm, 8); 767 } 768 769 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 770 uint64_t Addr, 771 const void *Decoder) { 772 unsigned Rd = fieldFromInstruction(insn, 0, 5); 773 unsigned Rn = fieldFromInstruction(insn, 5, 5); 774 unsigned Rm = fieldFromInstruction(insn, 16, 5); 775 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 776 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 777 unsigned shift = (shiftHi << 6) | shiftLo; 778 switch (Inst.getOpcode()) { 779 default: 780 return Fail; 781 case AArch64::ADDWrs: 782 case AArch64::ADDSWrs: 783 case AArch64::SUBWrs: 784 case AArch64::SUBSWrs: 785 // if shift == '11' then ReservedValue() 786 if (shiftHi == 0x3) 787 return Fail; 788 LLVM_FALLTHROUGH; 789 case AArch64::ANDWrs: 790 case AArch64::ANDSWrs: 791 case AArch64::BICWrs: 792 case AArch64::BICSWrs: 793 case AArch64::ORRWrs: 794 case AArch64::ORNWrs: 795 case AArch64::EORWrs: 796 case AArch64::EONWrs: { 797 // if sf == '0' and imm6<5> == '1' then ReservedValue() 798 if (shiftLo >> 5 == 1) 799 return Fail; 800 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 801 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 802 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 803 break; 804 } 805 case AArch64::ADDXrs: 806 case AArch64::ADDSXrs: 807 case AArch64::SUBXrs: 808 case AArch64::SUBSXrs: 809 // if shift == '11' then ReservedValue() 810 if (shiftHi == 0x3) 811 return Fail; 812 LLVM_FALLTHROUGH; 813 case AArch64::ANDXrs: 814 case AArch64::ANDSXrs: 815 case AArch64::BICXrs: 816 case AArch64::BICSXrs: 817 case AArch64::ORRXrs: 818 case AArch64::ORNXrs: 819 case AArch64::EORXrs: 820 case AArch64::EONXrs: 821 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 822 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 823 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 824 break; 825 } 826 827 Inst.addOperand(MCOperand::createImm(shift)); 828 return Success; 829 } 830 831 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 832 uint64_t Addr, 833 const void *Decoder) { 834 unsigned Rd = fieldFromInstruction(insn, 0, 5); 835 unsigned imm = fieldFromInstruction(insn, 5, 16); 836 unsigned shift = fieldFromInstruction(insn, 21, 2); 837 shift <<= 4; 838 switch (Inst.getOpcode()) { 839 default: 840 return Fail; 841 case AArch64::MOVZWi: 842 case AArch64::MOVNWi: 843 case AArch64::MOVKWi: 844 if (shift & (1U << 5)) 845 return Fail; 846 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 847 break; 848 case AArch64::MOVZXi: 849 case AArch64::MOVNXi: 850 case AArch64::MOVKXi: 851 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 852 break; 853 } 854 855 if (Inst.getOpcode() == AArch64::MOVKWi || 856 Inst.getOpcode() == AArch64::MOVKXi) 857 Inst.addOperand(Inst.getOperand(0)); 858 859 Inst.addOperand(MCOperand::createImm(imm)); 860 Inst.addOperand(MCOperand::createImm(shift)); 861 return Success; 862 } 863 864 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 865 uint64_t Addr, 866 const void *Decoder) { 867 unsigned Rt = fieldFromInstruction(insn, 0, 5); 868 unsigned Rn = fieldFromInstruction(insn, 5, 5); 869 unsigned offset = fieldFromInstruction(insn, 10, 12); 870 const AArch64Disassembler *Dis = 871 static_cast<const AArch64Disassembler *>(Decoder); 872 873 switch (Inst.getOpcode()) { 874 default: 875 return Fail; 876 case AArch64::PRFMui: 877 // Rt is an immediate in prefetch. 878 Inst.addOperand(MCOperand::createImm(Rt)); 879 break; 880 case AArch64::STRBBui: 881 case AArch64::LDRBBui: 882 case AArch64::LDRSBWui: 883 case AArch64::STRHHui: 884 case AArch64::LDRHHui: 885 case AArch64::LDRSHWui: 886 case AArch64::STRWui: 887 case AArch64::LDRWui: 888 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 889 break; 890 case AArch64::LDRSBXui: 891 case AArch64::LDRSHXui: 892 case AArch64::LDRSWui: 893 case AArch64::STRXui: 894 case AArch64::LDRXui: 895 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 896 break; 897 case AArch64::LDRQui: 898 case AArch64::STRQui: 899 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 900 break; 901 case AArch64::LDRDui: 902 case AArch64::STRDui: 903 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 904 break; 905 case AArch64::LDRSui: 906 case AArch64::STRSui: 907 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 908 break; 909 case AArch64::LDRHui: 910 case AArch64::STRHui: 911 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 912 break; 913 case AArch64::LDRBui: 914 case AArch64::STRBui: 915 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 916 break; 917 } 918 919 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 920 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 921 Inst.addOperand(MCOperand::createImm(offset)); 922 return Success; 923 } 924 925 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 926 uint64_t Addr, 927 const void *Decoder) { 928 unsigned Rt = fieldFromInstruction(insn, 0, 5); 929 unsigned Rn = fieldFromInstruction(insn, 5, 5); 930 int64_t offset = fieldFromInstruction(insn, 12, 9); 931 932 // offset is a 9-bit signed immediate, so sign extend it to 933 // fill the unsigned. 934 if (offset & (1 << (9 - 1))) 935 offset |= ~((1LL << 9) - 1); 936 937 // First operand is always the writeback to the address register, if needed. 938 switch (Inst.getOpcode()) { 939 default: 940 break; 941 case AArch64::LDRSBWpre: 942 case AArch64::LDRSHWpre: 943 case AArch64::STRBBpre: 944 case AArch64::LDRBBpre: 945 case AArch64::STRHHpre: 946 case AArch64::LDRHHpre: 947 case AArch64::STRWpre: 948 case AArch64::LDRWpre: 949 case AArch64::LDRSBWpost: 950 case AArch64::LDRSHWpost: 951 case AArch64::STRBBpost: 952 case AArch64::LDRBBpost: 953 case AArch64::STRHHpost: 954 case AArch64::LDRHHpost: 955 case AArch64::STRWpost: 956 case AArch64::LDRWpost: 957 case AArch64::LDRSBXpre: 958 case AArch64::LDRSHXpre: 959 case AArch64::STRXpre: 960 case AArch64::LDRSWpre: 961 case AArch64::LDRXpre: 962 case AArch64::LDRSBXpost: 963 case AArch64::LDRSHXpost: 964 case AArch64::STRXpost: 965 case AArch64::LDRSWpost: 966 case AArch64::LDRXpost: 967 case AArch64::LDRQpre: 968 case AArch64::STRQpre: 969 case AArch64::LDRQpost: 970 case AArch64::STRQpost: 971 case AArch64::LDRDpre: 972 case AArch64::STRDpre: 973 case AArch64::LDRDpost: 974 case AArch64::STRDpost: 975 case AArch64::LDRSpre: 976 case AArch64::STRSpre: 977 case AArch64::LDRSpost: 978 case AArch64::STRSpost: 979 case AArch64::LDRHpre: 980 case AArch64::STRHpre: 981 case AArch64::LDRHpost: 982 case AArch64::STRHpost: 983 case AArch64::LDRBpre: 984 case AArch64::STRBpre: 985 case AArch64::LDRBpost: 986 case AArch64::STRBpost: 987 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 988 break; 989 } 990 991 switch (Inst.getOpcode()) { 992 default: 993 return Fail; 994 case AArch64::PRFUMi: 995 // Rt is an immediate in prefetch. 996 Inst.addOperand(MCOperand::createImm(Rt)); 997 break; 998 case AArch64::STURBBi: 999 case AArch64::LDURBBi: 1000 case AArch64::LDURSBWi: 1001 case AArch64::STURHHi: 1002 case AArch64::LDURHHi: 1003 case AArch64::LDURSHWi: 1004 case AArch64::STURWi: 1005 case AArch64::LDURWi: 1006 case AArch64::LDTRSBWi: 1007 case AArch64::LDTRSHWi: 1008 case AArch64::STTRWi: 1009 case AArch64::LDTRWi: 1010 case AArch64::STTRHi: 1011 case AArch64::LDTRHi: 1012 case AArch64::LDTRBi: 1013 case AArch64::STTRBi: 1014 case AArch64::LDRSBWpre: 1015 case AArch64::LDRSHWpre: 1016 case AArch64::STRBBpre: 1017 case AArch64::LDRBBpre: 1018 case AArch64::STRHHpre: 1019 case AArch64::LDRHHpre: 1020 case AArch64::STRWpre: 1021 case AArch64::LDRWpre: 1022 case AArch64::LDRSBWpost: 1023 case AArch64::LDRSHWpost: 1024 case AArch64::STRBBpost: 1025 case AArch64::LDRBBpost: 1026 case AArch64::STRHHpost: 1027 case AArch64::LDRHHpost: 1028 case AArch64::STRWpost: 1029 case AArch64::LDRWpost: 1030 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1031 break; 1032 case AArch64::LDURSBXi: 1033 case AArch64::LDURSHXi: 1034 case AArch64::LDURSWi: 1035 case AArch64::STURXi: 1036 case AArch64::LDURXi: 1037 case AArch64::LDTRSBXi: 1038 case AArch64::LDTRSHXi: 1039 case AArch64::LDTRSWi: 1040 case AArch64::STTRXi: 1041 case AArch64::LDTRXi: 1042 case AArch64::LDRSBXpre: 1043 case AArch64::LDRSHXpre: 1044 case AArch64::STRXpre: 1045 case AArch64::LDRSWpre: 1046 case AArch64::LDRXpre: 1047 case AArch64::LDRSBXpost: 1048 case AArch64::LDRSHXpost: 1049 case AArch64::STRXpost: 1050 case AArch64::LDRSWpost: 1051 case AArch64::LDRXpost: 1052 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1053 break; 1054 case AArch64::LDURQi: 1055 case AArch64::STURQi: 1056 case AArch64::LDRQpre: 1057 case AArch64::STRQpre: 1058 case AArch64::LDRQpost: 1059 case AArch64::STRQpost: 1060 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1061 break; 1062 case AArch64::LDURDi: 1063 case AArch64::STURDi: 1064 case AArch64::LDRDpre: 1065 case AArch64::STRDpre: 1066 case AArch64::LDRDpost: 1067 case AArch64::STRDpost: 1068 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1069 break; 1070 case AArch64::LDURSi: 1071 case AArch64::STURSi: 1072 case AArch64::LDRSpre: 1073 case AArch64::STRSpre: 1074 case AArch64::LDRSpost: 1075 case AArch64::STRSpost: 1076 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1077 break; 1078 case AArch64::LDURHi: 1079 case AArch64::STURHi: 1080 case AArch64::LDRHpre: 1081 case AArch64::STRHpre: 1082 case AArch64::LDRHpost: 1083 case AArch64::STRHpost: 1084 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1085 break; 1086 case AArch64::LDURBi: 1087 case AArch64::STURBi: 1088 case AArch64::LDRBpre: 1089 case AArch64::STRBpre: 1090 case AArch64::LDRBpost: 1091 case AArch64::STRBpost: 1092 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1093 break; 1094 } 1095 1096 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1097 Inst.addOperand(MCOperand::createImm(offset)); 1098 1099 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1100 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1101 bool IsFP = fieldFromInstruction(insn, 26, 1); 1102 1103 // Cannot write back to a transfer register (but xzr != sp). 1104 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1105 return SoftFail; 1106 1107 return Success; 1108 } 1109 1110 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1111 uint64_t Addr, 1112 const void *Decoder) { 1113 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1114 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1115 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1116 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1117 1118 unsigned Opcode = Inst.getOpcode(); 1119 switch (Opcode) { 1120 default: 1121 return Fail; 1122 case AArch64::STLXRW: 1123 case AArch64::STLXRB: 1124 case AArch64::STLXRH: 1125 case AArch64::STXRW: 1126 case AArch64::STXRB: 1127 case AArch64::STXRH: 1128 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1129 LLVM_FALLTHROUGH; 1130 case AArch64::LDARW: 1131 case AArch64::LDARB: 1132 case AArch64::LDARH: 1133 case AArch64::LDAXRW: 1134 case AArch64::LDAXRB: 1135 case AArch64::LDAXRH: 1136 case AArch64::LDXRW: 1137 case AArch64::LDXRB: 1138 case AArch64::LDXRH: 1139 case AArch64::STLRW: 1140 case AArch64::STLRB: 1141 case AArch64::STLRH: 1142 case AArch64::STLLRW: 1143 case AArch64::STLLRB: 1144 case AArch64::STLLRH: 1145 case AArch64::LDLARW: 1146 case AArch64::LDLARB: 1147 case AArch64::LDLARH: 1148 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1149 break; 1150 case AArch64::STLXRX: 1151 case AArch64::STXRX: 1152 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1153 LLVM_FALLTHROUGH; 1154 case AArch64::LDARX: 1155 case AArch64::LDAXRX: 1156 case AArch64::LDXRX: 1157 case AArch64::STLRX: 1158 case AArch64::LDLARX: 1159 case AArch64::STLLRX: 1160 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1161 break; 1162 case AArch64::STLXPW: 1163 case AArch64::STXPW: 1164 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1165 LLVM_FALLTHROUGH; 1166 case AArch64::LDAXPW: 1167 case AArch64::LDXPW: 1168 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1169 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1170 break; 1171 case AArch64::STLXPX: 1172 case AArch64::STXPX: 1173 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1174 LLVM_FALLTHROUGH; 1175 case AArch64::LDAXPX: 1176 case AArch64::LDXPX: 1177 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1178 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1179 break; 1180 } 1181 1182 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1183 1184 // You shouldn't load to the same register twice in an instruction... 1185 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1186 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1187 Rt == Rt2) 1188 return SoftFail; 1189 1190 return Success; 1191 } 1192 1193 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1194 uint64_t Addr, 1195 const void *Decoder) { 1196 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1197 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1198 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1199 int64_t offset = fieldFromInstruction(insn, 15, 7); 1200 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1201 1202 // offset is a 7-bit signed immediate, so sign extend it to 1203 // fill the unsigned. 1204 if (offset & (1 << (7 - 1))) 1205 offset |= ~((1LL << 7) - 1); 1206 1207 unsigned Opcode = Inst.getOpcode(); 1208 bool NeedsDisjointWritebackTransfer = false; 1209 1210 // First operand is always writeback of base register. 1211 switch (Opcode) { 1212 default: 1213 break; 1214 case AArch64::LDPXpost: 1215 case AArch64::STPXpost: 1216 case AArch64::LDPSWpost: 1217 case AArch64::LDPXpre: 1218 case AArch64::STPXpre: 1219 case AArch64::LDPSWpre: 1220 case AArch64::LDPWpost: 1221 case AArch64::STPWpost: 1222 case AArch64::LDPWpre: 1223 case AArch64::STPWpre: 1224 case AArch64::LDPQpost: 1225 case AArch64::STPQpost: 1226 case AArch64::LDPQpre: 1227 case AArch64::STPQpre: 1228 case AArch64::LDPDpost: 1229 case AArch64::STPDpost: 1230 case AArch64::LDPDpre: 1231 case AArch64::STPDpre: 1232 case AArch64::LDPSpost: 1233 case AArch64::STPSpost: 1234 case AArch64::LDPSpre: 1235 case AArch64::STPSpre: 1236 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1237 break; 1238 } 1239 1240 switch (Opcode) { 1241 default: 1242 return Fail; 1243 case AArch64::LDPXpost: 1244 case AArch64::STPXpost: 1245 case AArch64::LDPSWpost: 1246 case AArch64::LDPXpre: 1247 case AArch64::STPXpre: 1248 case AArch64::LDPSWpre: 1249 NeedsDisjointWritebackTransfer = true; 1250 LLVM_FALLTHROUGH; 1251 case AArch64::LDNPXi: 1252 case AArch64::STNPXi: 1253 case AArch64::LDPXi: 1254 case AArch64::STPXi: 1255 case AArch64::LDPSWi: 1256 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1257 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1258 break; 1259 case AArch64::LDPWpost: 1260 case AArch64::STPWpost: 1261 case AArch64::LDPWpre: 1262 case AArch64::STPWpre: 1263 NeedsDisjointWritebackTransfer = true; 1264 LLVM_FALLTHROUGH; 1265 case AArch64::LDNPWi: 1266 case AArch64::STNPWi: 1267 case AArch64::LDPWi: 1268 case AArch64::STPWi: 1269 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1270 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1271 break; 1272 case AArch64::LDNPQi: 1273 case AArch64::STNPQi: 1274 case AArch64::LDPQpost: 1275 case AArch64::STPQpost: 1276 case AArch64::LDPQi: 1277 case AArch64::STPQi: 1278 case AArch64::LDPQpre: 1279 case AArch64::STPQpre: 1280 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1281 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1282 break; 1283 case AArch64::LDNPDi: 1284 case AArch64::STNPDi: 1285 case AArch64::LDPDpost: 1286 case AArch64::STPDpost: 1287 case AArch64::LDPDi: 1288 case AArch64::STPDi: 1289 case AArch64::LDPDpre: 1290 case AArch64::STPDpre: 1291 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1292 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1293 break; 1294 case AArch64::LDNPSi: 1295 case AArch64::STNPSi: 1296 case AArch64::LDPSpost: 1297 case AArch64::STPSpost: 1298 case AArch64::LDPSi: 1299 case AArch64::STPSi: 1300 case AArch64::LDPSpre: 1301 case AArch64::STPSpre: 1302 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1303 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1304 break; 1305 } 1306 1307 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1308 Inst.addOperand(MCOperand::createImm(offset)); 1309 1310 // You shouldn't load to the same register twice in an instruction... 1311 if (IsLoad && Rt == Rt2) 1312 return SoftFail; 1313 1314 // ... or do any operation that writes-back to a transfer register. But note 1315 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1316 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1317 return SoftFail; 1318 1319 return Success; 1320 } 1321 1322 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1323 uint64_t Addr, 1324 const void *Decoder) { 1325 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1326 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1327 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1328 unsigned extend = fieldFromInstruction(insn, 10, 6); 1329 1330 unsigned shift = extend & 0x7; 1331 if (shift > 4) 1332 return Fail; 1333 1334 switch (Inst.getOpcode()) { 1335 default: 1336 return Fail; 1337 case AArch64::ADDWrx: 1338 case AArch64::SUBWrx: 1339 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1340 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1341 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1342 break; 1343 case AArch64::ADDSWrx: 1344 case AArch64::SUBSWrx: 1345 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1346 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1347 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1348 break; 1349 case AArch64::ADDXrx: 1350 case AArch64::SUBXrx: 1351 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1352 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1353 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1354 break; 1355 case AArch64::ADDSXrx: 1356 case AArch64::SUBSXrx: 1357 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1358 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1359 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1360 break; 1361 case AArch64::ADDXrx64: 1362 case AArch64::SUBXrx64: 1363 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1364 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1365 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1366 break; 1367 case AArch64::SUBSXrx64: 1368 case AArch64::ADDSXrx64: 1369 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1370 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1371 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1372 break; 1373 } 1374 1375 Inst.addOperand(MCOperand::createImm(extend)); 1376 return Success; 1377 } 1378 1379 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1380 uint64_t Addr, 1381 const void *Decoder) { 1382 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1383 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1384 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1385 unsigned imm; 1386 1387 if (Datasize) { 1388 if (Inst.getOpcode() == AArch64::ANDSXri) 1389 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1390 else 1391 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1392 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1393 imm = fieldFromInstruction(insn, 10, 13); 1394 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1395 return Fail; 1396 } else { 1397 if (Inst.getOpcode() == AArch64::ANDSWri) 1398 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1399 else 1400 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1401 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1402 imm = fieldFromInstruction(insn, 10, 12); 1403 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1404 return Fail; 1405 } 1406 Inst.addOperand(MCOperand::createImm(imm)); 1407 return Success; 1408 } 1409 1410 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1411 uint64_t Addr, 1412 const void *Decoder) { 1413 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1414 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1415 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1416 imm |= fieldFromInstruction(insn, 5, 5); 1417 1418 if (Inst.getOpcode() == AArch64::MOVID) 1419 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1420 else 1421 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1422 1423 Inst.addOperand(MCOperand::createImm(imm)); 1424 1425 switch (Inst.getOpcode()) { 1426 default: 1427 break; 1428 case AArch64::MOVIv4i16: 1429 case AArch64::MOVIv8i16: 1430 case AArch64::MVNIv4i16: 1431 case AArch64::MVNIv8i16: 1432 case AArch64::MOVIv2i32: 1433 case AArch64::MOVIv4i32: 1434 case AArch64::MVNIv2i32: 1435 case AArch64::MVNIv4i32: 1436 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1437 break; 1438 case AArch64::MOVIv2s_msl: 1439 case AArch64::MOVIv4s_msl: 1440 case AArch64::MVNIv2s_msl: 1441 case AArch64::MVNIv4s_msl: 1442 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1443 break; 1444 } 1445 1446 return Success; 1447 } 1448 1449 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1450 uint64_t Addr, 1451 const void *Decoder) { 1452 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1453 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1454 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1455 imm |= fieldFromInstruction(insn, 5, 5); 1456 1457 // Tied operands added twice. 1458 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1459 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1460 1461 Inst.addOperand(MCOperand::createImm(imm)); 1462 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1463 1464 return Success; 1465 } 1466 1467 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1468 uint64_t Addr, const void *Decoder) { 1469 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1470 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1471 imm |= fieldFromInstruction(insn, 29, 2); 1472 const AArch64Disassembler *Dis = 1473 static_cast<const AArch64Disassembler *>(Decoder); 1474 1475 // Sign-extend the 21-bit immediate. 1476 if (imm & (1 << (21 - 1))) 1477 imm |= ~((1LL << 21) - 1); 1478 1479 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1480 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1481 Inst.addOperand(MCOperand::createImm(imm)); 1482 1483 return Success; 1484 } 1485 1486 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1487 uint64_t Addr, const void *Decoder) { 1488 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1489 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1490 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1491 unsigned S = fieldFromInstruction(insn, 29, 1); 1492 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1493 1494 unsigned ShifterVal = (Imm >> 12) & 3; 1495 unsigned ImmVal = Imm & 0xFFF; 1496 const AArch64Disassembler *Dis = 1497 static_cast<const AArch64Disassembler *>(Decoder); 1498 1499 if (ShifterVal != 0 && ShifterVal != 1) 1500 return Fail; 1501 1502 if (Datasize) { 1503 if (Rd == 31 && !S) 1504 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1505 else 1506 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1507 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1508 } else { 1509 if (Rd == 31 && !S) 1510 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1511 else 1512 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1513 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1514 } 1515 1516 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1517 Inst.addOperand(MCOperand::createImm(ImmVal)); 1518 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1519 return Success; 1520 } 1521 1522 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1523 uint64_t Addr, 1524 const void *Decoder) { 1525 int64_t imm = fieldFromInstruction(insn, 0, 26); 1526 const AArch64Disassembler *Dis = 1527 static_cast<const AArch64Disassembler *>(Decoder); 1528 1529 // Sign-extend the 26-bit immediate. 1530 if (imm & (1 << (26 - 1))) 1531 imm |= ~((1LL << 26) - 1); 1532 1533 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1534 Inst.addOperand(MCOperand::createImm(imm)); 1535 1536 return Success; 1537 } 1538 1539 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1540 uint64_t Addr, 1541 const void *Decoder) { 1542 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1543 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1544 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1545 1546 uint64_t pstate_field = (op1 << 3) | op2; 1547 1548 if ((pstate_field == AArch64PState::PAN || 1549 pstate_field == AArch64PState::UAO) && crm > 1) 1550 return Fail; 1551 1552 Inst.addOperand(MCOperand::createImm(pstate_field)); 1553 Inst.addOperand(MCOperand::createImm(crm)); 1554 1555 const AArch64Disassembler *Dis = 1556 static_cast<const AArch64Disassembler *>(Decoder); 1557 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1558 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1559 return Success; 1560 return Fail; 1561 } 1562 1563 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1564 uint64_t Addr, const void *Decoder) { 1565 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1566 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1567 bit |= fieldFromInstruction(insn, 19, 5); 1568 int64_t dst = fieldFromInstruction(insn, 5, 14); 1569 const AArch64Disassembler *Dis = 1570 static_cast<const AArch64Disassembler *>(Decoder); 1571 1572 // Sign-extend 14-bit immediate. 1573 if (dst & (1 << (14 - 1))) 1574 dst |= ~((1LL << 14) - 1); 1575 1576 if (fieldFromInstruction(insn, 31, 1) == 0) 1577 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1578 else 1579 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1580 Inst.addOperand(MCOperand::createImm(bit)); 1581 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1582 Inst.addOperand(MCOperand::createImm(dst)); 1583 1584 return Success; 1585 } 1586 1587 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1588 unsigned RegClassID, 1589 unsigned RegNo, 1590 uint64_t Addr, 1591 const void *Decoder) { 1592 // Register number must be even (see CASP instruction) 1593 if (RegNo & 0x1) 1594 return Fail; 1595 1596 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1597 Inst.addOperand(MCOperand::createReg(Register)); 1598 return Success; 1599 } 1600 1601 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1602 unsigned RegNo, 1603 uint64_t Addr, 1604 const void *Decoder) { 1605 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1606 AArch64::WSeqPairsClassRegClassID, 1607 RegNo, Addr, Decoder); 1608 } 1609 1610 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1611 unsigned RegNo, 1612 uint64_t Addr, 1613 const void *Decoder) { 1614 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1615 AArch64::XSeqPairsClassRegClassID, 1616 RegNo, Addr, Decoder); 1617 } 1618 1619 template<int Bits> 1620 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1621 uint64_t Address, const void *Decoder) { 1622 if (Imm & ~((1LL << Bits) - 1)) 1623 return Fail; 1624 1625 // Imm is a signed immediate, so sign extend it. 1626 if (Imm & (1 << (Bits - 1))) 1627 Imm |= ~((1LL << Bits) - 1); 1628 1629 Inst.addOperand(MCOperand::createImm(Imm)); 1630 return Success; 1631 } 1632 1633