1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the functions necessary to decode AArch64 instruction 11 // bitpatterns into MCInsts (with the help of TableGenerated information from 12 // the instruction definitions). 13 // 14 //===----------------------------------------------------------------------===// 15 16 #define DEBUG_TYPE "arm-disassembler" 17 18 #include "AArch64.h" 19 #include "AArch64RegisterInfo.h" 20 #include "AArch64Subtarget.h" 21 #include "Utils/AArch64BaseInfo.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrDesc.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCDisassembler.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/MemoryObject.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetRegistry.h" 32 #include "llvm/Support/raw_ostream.h" 33 34 using namespace llvm; 35 36 typedef MCDisassembler::DecodeStatus DecodeStatus; 37 38 namespace { 39 /// AArch64 disassembler for all AArch64 platforms. 40 class AArch64Disassembler : public MCDisassembler { 41 OwningPtr<const MCRegisterInfo> RegInfo; 42 public: 43 /// Initializes the disassembler. 44 /// 45 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) 46 : MCDisassembler(STI), RegInfo(Info) { 47 } 48 49 ~AArch64Disassembler() {} 50 51 /// See MCDisassembler. 52 DecodeStatus getInstruction(MCInst &instr, 53 uint64_t &size, 54 const MemoryObject ®ion, 55 uint64_t address, 56 raw_ostream &vStream, 57 raw_ostream &cStream) const; 58 59 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } 60 }; 61 62 } 63 64 // Forward-declarations used in the auto-generated files. 65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 66 uint64_t Address, const void *Decoder); 67 static DecodeStatus 68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 uint64_t Address, const void *Decoder); 70 71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 uint64_t Address, const void *Decoder); 73 static DecodeStatus 74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 uint64_t Address, const void *Decoder); 76 77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 78 uint64_t Address, const void *Decoder); 79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 80 uint64_t Address, const void *Decoder); 81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 82 uint64_t Address, const void *Decoder); 83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 84 uint64_t Address, const void *Decoder); 85 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 86 unsigned RegNo, uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, 89 unsigned RegNo, uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 96 uint64_t Address, 97 const void *Decoder); 98 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 99 unsigned RegNo, uint64_t Address, 100 const void *Decoder); 101 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 102 unsigned RegNo, uint64_t Address, 103 const void *Decoder); 104 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 112 unsigned OptionHiS, 113 uint64_t Address, 114 const void *Decoder); 115 116 117 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 118 unsigned Imm6Bits, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 123 unsigned Imm6Bits, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 128 unsigned RmBits, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 135 uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 138 uint64_t Address, 139 const void *Decoder); 140 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 141 uint64_t Address, 142 const void *Decoder); 143 144 template<int RegWidth> 145 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 146 unsigned FullImm, 147 uint64_t Address, 148 const void *Decoder); 149 150 template<int RegWidth> 151 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 152 unsigned Bits, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 157 unsigned ShiftAmount, 158 uint64_t Address, 159 const void *Decoder); 160 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 161 static DecodeStatus 162 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 163 uint64_t Address, const void *Decoder); 164 165 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 166 unsigned ShiftAmount, 167 uint64_t Address, 168 const void *Decoder); 169 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 170 uint64_t Address, 171 const void *Decoder); 172 173 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 178 unsigned Insn, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 183 unsigned Val, 184 uint64_t Address, 185 const void *Decoder); 186 187 template<typename SomeNamedImmMapper> 188 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 189 unsigned Val, 190 uint64_t Address, 191 const void *Decoder); 192 193 static DecodeStatus 194 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper, 195 llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 198 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 199 unsigned Val, 200 uint64_t Address, 201 const void *Decoder); 202 203 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 204 unsigned Val, 205 uint64_t Address, 206 const void *Decoder); 207 208 209 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 210 unsigned Val, 211 uint64_t Address, 212 const void *Decoder); 213 214 215 static bool Check(DecodeStatus &Out, DecodeStatus In); 216 217 #include "AArch64GenDisassemblerTables.inc" 218 #include "AArch64GenInstrInfo.inc" 219 220 static bool Check(DecodeStatus &Out, DecodeStatus In) { 221 switch (In) { 222 case MCDisassembler::Success: 223 // Out stays the same. 224 return true; 225 case MCDisassembler::SoftFail: 226 Out = In; 227 return true; 228 case MCDisassembler::Fail: 229 Out = In; 230 return false; 231 } 232 llvm_unreachable("Invalid DecodeStatus!"); 233 } 234 235 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 236 const MemoryObject &Region, 237 uint64_t Address, 238 raw_ostream &os, 239 raw_ostream &cs) const { 240 CommentStream = &cs; 241 242 uint8_t bytes[4]; 243 244 // We want to read exactly 4 bytes of data. 245 if (Region.readBytes(Address, 4, bytes) == -1) { 246 Size = 0; 247 return MCDisassembler::Fail; 248 } 249 250 // Encoded as a small-endian 32-bit word in the stream. 251 uint32_t insn = (bytes[3] << 24) | 252 (bytes[2] << 16) | 253 (bytes[1] << 8) | 254 (bytes[0] << 0); 255 256 // Calling the auto-generated decoder function. 257 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, 258 this, STI); 259 if (result != MCDisassembler::Fail) { 260 Size = 4; 261 return result; 262 } 263 264 MI.clear(); 265 Size = 0; 266 return MCDisassembler::Fail; 267 } 268 269 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 270 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D); 271 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo); 272 } 273 274 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 275 uint64_t Address, const void *Decoder) { 276 if (RegNo > 31) 277 return MCDisassembler::Fail; 278 279 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo); 280 Inst.addOperand(MCOperand::CreateReg(Register)); 281 return MCDisassembler::Success; 282 } 283 284 static DecodeStatus 285 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 286 uint64_t Address, const void *Decoder) { 287 if (RegNo > 31) 288 return MCDisassembler::Fail; 289 290 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo); 291 Inst.addOperand(MCOperand::CreateReg(Register)); 292 return MCDisassembler::Success; 293 } 294 295 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 296 uint64_t Address, 297 const void *Decoder) { 298 if (RegNo > 31) 299 return MCDisassembler::Fail; 300 301 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo); 302 Inst.addOperand(MCOperand::CreateReg(Register)); 303 return MCDisassembler::Success; 304 } 305 306 static DecodeStatus 307 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 308 uint64_t Address, const void *Decoder) { 309 if (RegNo > 31) 310 return MCDisassembler::Fail; 311 312 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo); 313 Inst.addOperand(MCOperand::CreateReg(Register)); 314 return MCDisassembler::Success; 315 } 316 317 static DecodeStatus 318 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 319 uint64_t Address, const void *Decoder) { 320 if (RegNo > 31) 321 return MCDisassembler::Fail; 322 323 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo); 324 Inst.addOperand(MCOperand::CreateReg(Register)); 325 return MCDisassembler::Success; 326 } 327 328 static DecodeStatus 329 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 330 uint64_t Address, const void *Decoder) { 331 if (RegNo > 31) 332 return MCDisassembler::Fail; 333 334 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo); 335 Inst.addOperand(MCOperand::CreateReg(Register)); 336 return MCDisassembler::Success; 337 } 338 339 340 static DecodeStatus 341 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 342 uint64_t Address, const void *Decoder) { 343 if (RegNo > 31) 344 return MCDisassembler::Fail; 345 346 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo); 347 Inst.addOperand(MCOperand::CreateReg(Register)); 348 return MCDisassembler::Success; 349 } 350 351 static DecodeStatus 352 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 353 uint64_t Address, const void *Decoder) { 354 if (RegNo > 31) 355 return MCDisassembler::Fail; 356 357 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo); 358 Inst.addOperand(MCOperand::CreateReg(Register)); 359 return MCDisassembler::Success; 360 } 361 362 363 static DecodeStatus 364 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 365 uint64_t Address, const void *Decoder) { 366 if (RegNo > 31) 367 return MCDisassembler::Fail; 368 369 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo); 370 Inst.addOperand(MCOperand::CreateReg(Register)); 371 return MCDisassembler::Success; 372 } 373 374 static DecodeStatus 375 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 376 uint64_t Address, const void *Decoder) { 377 if (RegNo > 15) 378 return MCDisassembler::Fail; 379 380 return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder); 381 } 382 383 static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo, 384 unsigned RegID, 385 const void *Decoder) { 386 if (RegNo > 31) 387 return MCDisassembler::Fail; 388 389 uint16_t Register = getReg(Decoder, RegID, RegNo); 390 Inst.addOperand(MCOperand::CreateReg(Register)); 391 return MCDisassembler::Success; 392 } 393 394 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 395 uint64_t Address, 396 const void *Decoder) { 397 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID, 398 Decoder); 399 } 400 401 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 402 uint64_t Address, 403 const void *Decoder) { 404 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID, 405 Decoder); 406 } 407 408 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 409 unsigned RegNo, uint64_t Address, 410 const void *Decoder) { 411 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID, 412 Decoder); 413 } 414 415 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 416 unsigned RegNo, uint64_t Address, 417 const void *Decoder) { 418 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID, 419 Decoder); 420 } 421 422 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 423 uint64_t Address, 424 const void *Decoder) { 425 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID, 426 Decoder); 427 } 428 429 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 430 uint64_t Address, 431 const void *Decoder) { 432 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID, 433 Decoder); 434 } 435 436 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 437 unsigned OptionHiS, 438 uint64_t Address, 439 const void *Decoder) { 440 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1}, 441 // S}. Hence we want to check bit 1. 442 if (!(OptionHiS & 2)) 443 return MCDisassembler::Fail; 444 445 Inst.addOperand(MCOperand::CreateImm(OptionHiS)); 446 return MCDisassembler::Success; 447 } 448 449 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 450 unsigned Imm6Bits, 451 uint64_t Address, 452 const void *Decoder) { 453 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be 454 // between 0 and 31. 455 if (Imm6Bits > 31) 456 return MCDisassembler::Fail; 457 458 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 459 return MCDisassembler::Success; 460 } 461 462 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 463 unsigned Imm6Bits, 464 uint64_t Address, 465 const void *Decoder) { 466 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32. 467 if (Imm6Bits < 32) 468 return MCDisassembler::Fail; 469 470 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 471 return MCDisassembler::Success; 472 } 473 474 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 475 unsigned RmBits, 476 uint64_t Address, 477 const void *Decoder) { 478 // Any bits are valid in the instruction (they're architecturally ignored), 479 // but a code generator should insert 0. 480 Inst.addOperand(MCOperand::CreateImm(0)); 481 return MCDisassembler::Success; 482 } 483 484 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 485 uint64_t Address, 486 const void *Decoder) { 487 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 488 return MCDisassembler::Success; 489 } 490 491 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 492 uint64_t Address, 493 const void *Decoder) { 494 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 495 return MCDisassembler::Success; 496 } 497 498 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 499 uint64_t Address, 500 const void *Decoder) { 501 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 502 return MCDisassembler::Success; 503 } 504 505 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 506 uint64_t Address, 507 const void *Decoder) { 508 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 509 return MCDisassembler::Success; 510 } 511 512 template<int RegWidth> 513 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 514 unsigned FullImm, 515 uint64_t Address, 516 const void *Decoder) { 517 unsigned Imm16 = FullImm & 0xffff; 518 unsigned Shift = FullImm >> 16; 519 520 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail; 521 522 Inst.addOperand(MCOperand::CreateImm(Imm16)); 523 Inst.addOperand(MCOperand::CreateImm(Shift)); 524 return MCDisassembler::Success; 525 } 526 527 template<int RegWidth> 528 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 529 unsigned Bits, 530 uint64_t Address, 531 const void *Decoder) { 532 uint64_t Imm; 533 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm)) 534 return MCDisassembler::Fail; 535 536 Inst.addOperand(MCOperand::CreateImm(Bits)); 537 return MCDisassembler::Success; 538 } 539 540 541 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 542 unsigned ShiftAmount, 543 uint64_t Address, 544 const void *Decoder) { 545 // Only values 0-4 are valid for this 3-bit field 546 if (ShiftAmount > 4) 547 return MCDisassembler::Fail; 548 549 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 550 return MCDisassembler::Success; 551 } 552 553 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 554 unsigned ShiftAmount, 555 uint64_t Address, 556 const void *Decoder) { 557 // Only values below 32 are valid for a 32-bit register 558 if (ShiftAmount > 31) 559 return MCDisassembler::Fail; 560 561 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 562 return MCDisassembler::Success; 563 } 564 565 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 566 uint64_t Address, 567 const void *Decoder) { 568 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 569 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 570 unsigned ImmS = fieldFromInstruction(Insn, 10, 6); 571 unsigned ImmR = fieldFromInstruction(Insn, 16, 6); 572 unsigned SF = fieldFromInstruction(Insn, 31, 1); 573 574 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise 575 // out assertions that it thinks should never be hit. 576 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; 577 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); 578 579 if (!SF) { 580 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions. 581 if (ImmR > 31 || ImmS > 31) 582 return MCDisassembler::Fail; 583 } 584 585 if (SF) { 586 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 587 // BFM MCInsts use Rd as a source too. 588 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 589 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 590 } else { 591 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 592 // BFM MCInsts use Rd as a source too. 593 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 594 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder); 595 } 596 597 // ASR and LSR have more specific patterns so they won't get here: 598 assert(!(ImmS == 31 && !SF && Opc != BFM) 599 && "shift should have used auto decode"); 600 assert(!(ImmS == 63 && SF && Opc != BFM) 601 && "shift should have used auto decode"); 602 603 // Extension instructions similarly: 604 if (Opc == SBFM && ImmR == 0) { 605 assert((ImmS != 7 && ImmS != 15) && "extension got here"); 606 assert((ImmS != 31 || SF == 0) && "extension got here"); 607 } else if (Opc == UBFM && ImmR == 0) { 608 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here"); 609 } 610 611 if (Opc == UBFM) { 612 // It might be a LSL instruction, which actually takes the shift amount 613 // itself as an MCInst operand. 614 if (SF && (ImmS + 1) % 64 == ImmR) { 615 Inst.setOpcode(AArch64::LSLxxi); 616 Inst.addOperand(MCOperand::CreateImm(63 - ImmS)); 617 return MCDisassembler::Success; 618 } else if (!SF && (ImmS + 1) % 32 == ImmR) { 619 Inst.setOpcode(AArch64::LSLwwi); 620 Inst.addOperand(MCOperand::CreateImm(31 - ImmS)); 621 return MCDisassembler::Success; 622 } 623 } 624 625 // Otherwise it's definitely either an extract or an insert depending on which 626 // of ImmR or ImmS is larger. 627 unsigned ExtractOp, InsertOp; 628 switch (Opc) { 629 default: llvm_unreachable("unexpected instruction trying to decode bitfield"); 630 case SBFM: 631 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii; 632 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii; 633 break; 634 case BFM: 635 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii; 636 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii; 637 break; 638 case UBFM: 639 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii; 640 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii; 641 break; 642 } 643 644 // Otherwise it's a boring insert or extract 645 Inst.addOperand(MCOperand::CreateImm(ImmR)); 646 Inst.addOperand(MCOperand::CreateImm(ImmS)); 647 648 649 if (ImmS < ImmR) 650 Inst.setOpcode(InsertOp); 651 else 652 Inst.setOpcode(ExtractOp); 653 654 return MCDisassembler::Success; 655 } 656 657 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 658 uint64_t Address, 659 const void *Decoder) { 660 // This decoder exists to add the dummy Lane operand to the MCInst, which must 661 // be 1 in assembly but has no other real manifestation. 662 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 663 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 664 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 665 666 if (IsToVec) { 667 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 668 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 669 } else { 670 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 671 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 672 } 673 674 // Add the lane 675 Inst.addOperand(MCOperand::CreateImm(1)); 676 677 return MCDisassembler::Success; 678 } 679 680 681 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 682 unsigned Insn, 683 uint64_t Address, 684 const void *Decoder) { 685 DecodeStatus Result = MCDisassembler::Success; 686 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 687 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 688 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5); 689 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7); 690 unsigned L = fieldFromInstruction(Insn, 22, 1); 691 unsigned V = fieldFromInstruction(Insn, 26, 1); 692 unsigned Opc = fieldFromInstruction(Insn, 30, 2); 693 694 // Not an official name, but it turns out that bit 23 distinguishes indexed 695 // from non-indexed operations. 696 unsigned Indexed = fieldFromInstruction(Insn, 23, 1); 697 698 if (Indexed && L == 0) { 699 // The MCInst for an indexed store has an out operand and 4 ins: 700 // Rn_wb, Rt, Rt2, Rn, Imm 701 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 702 } 703 704 // You shouldn't load to the same register twice in an instruction... 705 if (L && Rt == Rt2) 706 Result = MCDisassembler::SoftFail; 707 708 // ... or do any operation that writes-back to a transfer register. But note 709 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 710 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 711 Result = MCDisassembler::SoftFail; 712 713 // Exactly how we decode the MCInst's registers depends on the Opc and V 714 // fields of the instruction. These also obviously determine the size of the 715 // operation so we can fill in that information while we're at it. 716 if (V) { 717 // The instruction operates on the FP/SIMD registers 718 switch (Opc) { 719 default: return MCDisassembler::Fail; 720 case 0: 721 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 722 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder); 723 break; 724 case 1: 725 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 726 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder); 727 break; 728 case 2: 729 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 730 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder); 731 break; 732 } 733 } else { 734 switch (Opc) { 735 default: return MCDisassembler::Fail; 736 case 0: 737 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 738 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder); 739 break; 740 case 1: 741 assert(L && "unexpected \"store signed\" attempt"); 742 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 743 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 744 break; 745 case 2: 746 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 747 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 748 break; 749 } 750 } 751 752 if (Indexed && L == 1) { 753 // The MCInst for an indexed load has 3 out operands and an 3 ins: 754 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm 755 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 756 } 757 758 759 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 760 Inst.addOperand(MCOperand::CreateImm(SImm7)); 761 762 return Result; 763 } 764 765 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 766 uint32_t Val, 767 uint64_t Address, 768 const void *Decoder) { 769 unsigned Rt = fieldFromInstruction(Val, 0, 5); 770 unsigned Rn = fieldFromInstruction(Val, 5, 5); 771 unsigned Rt2 = fieldFromInstruction(Val, 10, 5); 772 unsigned MemSize = fieldFromInstruction(Val, 30, 2); 773 774 DecodeStatus S = MCDisassembler::Success; 775 if (Rt == Rt2) S = MCDisassembler::SoftFail; 776 777 switch (MemSize) { 778 case 2: 779 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder))) 780 return MCDisassembler::Fail; 781 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder))) 782 return MCDisassembler::Fail; 783 break; 784 case 3: 785 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder))) 786 return MCDisassembler::Fail; 787 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder))) 788 return MCDisassembler::Fail; 789 break; 790 default: 791 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction"); 792 } 793 794 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder))) 795 return MCDisassembler::Fail; 796 797 return S; 798 } 799 800 template<typename SomeNamedImmMapper> 801 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 802 unsigned Val, 803 uint64_t Address, 804 const void *Decoder) { 805 SomeNamedImmMapper Mapper; 806 bool ValidNamed; 807 Mapper.toString(Val, ValidNamed); 808 if (ValidNamed || Mapper.validImm(Val)) { 809 Inst.addOperand(MCOperand::CreateImm(Val)); 810 return MCDisassembler::Success; 811 } 812 813 return MCDisassembler::Fail; 814 } 815 816 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, 817 llvm::MCInst &Inst, 818 unsigned Val, 819 uint64_t Address, 820 const void *Decoder) { 821 bool ValidNamed; 822 Mapper.toString(Val, ValidNamed); 823 824 Inst.addOperand(MCOperand::CreateImm(Val)); 825 826 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail; 827 } 828 829 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 830 unsigned Val, 831 uint64_t Address, 832 const void *Decoder) { 833 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address, 834 Decoder); 835 } 836 837 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 838 unsigned Val, 839 uint64_t Address, 840 const void *Decoder) { 841 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address, 842 Decoder); 843 } 844 845 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 846 unsigned Insn, 847 uint64_t Address, 848 const void *Decoder) { 849 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 850 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 851 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9); 852 853 unsigned Opc = fieldFromInstruction(Insn, 22, 2); 854 unsigned V = fieldFromInstruction(Insn, 26, 1); 855 unsigned Size = fieldFromInstruction(Insn, 30, 2); 856 857 if (Opc == 0 || (V == 1 && Opc == 2)) { 858 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm 859 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 860 } 861 862 if (V == 0 && (Opc == 2 || Size == 3)) { 863 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 864 } else if (V == 0) { 865 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 866 } else if (V == 1 && (Opc & 2)) { 867 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 868 } else { 869 switch (Size) { 870 case 0: 871 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder); 872 break; 873 case 1: 874 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder); 875 break; 876 case 2: 877 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 878 break; 879 case 3: 880 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 881 break; 882 } 883 } 884 885 if (Opc != 0 && (V != 1 || Opc != 2)) { 886 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm 887 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 888 } 889 890 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 891 892 Inst.addOperand(MCOperand::CreateImm(Imm9)); 893 894 // N.b. The official documentation says undpredictable if Rt == Rn, but this 895 // takes place at the architectural rather than encoding level: 896 // 897 // "STR xzr, [sp], #4" is perfectly valid. 898 if (V == 0 && Rt == Rn && Rn != 31) 899 return MCDisassembler::SoftFail; 900 else 901 return MCDisassembler::Success; 902 } 903 904 static MCDisassembler *createAArch64Disassembler(const Target &T, 905 const MCSubtargetInfo &STI) { 906 return new AArch64Disassembler(STI, T.createMCRegInfo("")); 907 } 908 909 extern "C" void LLVMInitializeAArch64Disassembler() { 910 TargetRegistry::RegisterMCDisassembler(TheAArch64Target, 911 createAArch64Disassembler); 912 } 913 914 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 915 static DecodeStatus 916 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 917 uint64_t Address, const void *Decoder) { 918 bool IsLSL = false; 919 if (Ext == A64SE::LSL) 920 IsLSL = true; 921 else if (Ext != A64SE::MSL) 922 return MCDisassembler::Fail; 923 924 // MSL and LSLH accepts encoded shift amount 0 or 1. 925 if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1) 926 return MCDisassembler::Fail; 927 928 // LSL accepts encoded shift amount 0, 1, 2 or 3. 929 if (IsLSL && ShiftAmount > 3) 930 return MCDisassembler::Fail; 931 932 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 933 return MCDisassembler::Success; 934 } 935