1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/MemoryObject.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "aarch64-disassembler" 28 29 // Pull DecodeStatus and its enum values into the global namespace. 30 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 31 32 // Forward declare these because the autogenerated code will reference them. 33 // Definitions are further down. 34 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 35 unsigned RegNo, uint64_t Address, 36 const void *Decoder); 37 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst, 38 unsigned RegNo, 39 uint64_t Address, 40 const void *Decoder); 41 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, 43 const void *Decoder); 44 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst, 57 unsigned RegNo, uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst, 63 unsigned RegNo, uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 66 uint64_t Address, 67 const void *Decoder); 68 static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 uint64_t Address, 73 const void *Decoder); 74 static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 81 uint64_t Address, 82 const void *Decoder); 83 84 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, 85 uint64_t Address, 86 const void *Decoder); 87 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, 88 uint64_t Address, 89 const void *Decoder); 90 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, 91 uint64_t Address, const void *Decoder); 92 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, 93 uint64_t Address, const void *Decoder); 94 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, 95 uint64_t Address, const void *Decoder); 96 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, 97 uint64_t Address, const void *Decoder); 98 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, 99 uint32_t insn, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, 103 uint64_t Address, 104 const void *Decoder); 105 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, 106 uint32_t insn, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst, 110 uint32_t insn, uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, 113 uint32_t insn, 114 uint64_t Address, 115 const void *Decoder); 116 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, 117 uint64_t Address, 118 const void *Decoder); 119 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst, 120 uint32_t insn, uint64_t Address, 121 const void *Decoder); 122 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst, 123 uint32_t insn, uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst, 129 uint32_t insn, uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst, 139 uint32_t insn, 140 uint64_t Address, 141 const void *Decoder); 142 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, 143 uint64_t Address, const void *Decoder); 144 145 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, 149 uint64_t Addr, const void *Decoder); 150 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 151 uint64_t Addr, 152 const void *Decoder); 153 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, 154 uint64_t Addr, const void *Decoder); 155 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 156 uint64_t Addr, 157 const void *Decoder); 158 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, 159 uint64_t Addr, const void *Decoder); 160 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 161 uint64_t Addr, 162 const void *Decoder); 163 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, 164 uint64_t Addr, const void *Decoder); 165 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, 166 uint64_t Addr, const void *Decoder); 167 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, 168 uint64_t Addr, const void *Decoder); 169 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, 170 uint64_t Addr, const void *Decoder); 171 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, 172 uint64_t Addr, const void *Decoder); 173 174 static bool Check(DecodeStatus &Out, DecodeStatus In) { 175 switch (In) { 176 case MCDisassembler::Success: 177 // Out stays the same. 178 return true; 179 case MCDisassembler::SoftFail: 180 Out = In; 181 return true; 182 case MCDisassembler::Fail: 183 Out = In; 184 return false; 185 } 186 llvm_unreachable("Invalid DecodeStatus!"); 187 } 188 189 #include "AArch64GenDisassemblerTables.inc" 190 #include "AArch64GenInstrInfo.inc" 191 192 #define Success llvm::MCDisassembler::Success 193 #define Fail llvm::MCDisassembler::Fail 194 #define SoftFail llvm::MCDisassembler::SoftFail 195 196 static MCDisassembler *createAArch64Disassembler(const Target &T, 197 const MCSubtargetInfo &STI, 198 MCContext &Ctx) { 199 return new AArch64Disassembler(STI, Ctx); 200 } 201 202 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 203 const MemoryObject &Region, 204 uint64_t Address, 205 raw_ostream &os, 206 raw_ostream &cs) const { 207 CommentStream = &cs; 208 209 uint8_t bytes[4]; 210 211 Size = 0; 212 // We want to read exactly 4 bytes of data. 213 if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1) 214 return Fail; 215 Size = 4; 216 217 // Encoded as a small-endian 32-bit word in the stream. 218 uint32_t insn = 219 (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0); 220 221 // Calling the auto-generated decoder function. 222 return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); 223 } 224 225 static MCSymbolizer * 226 createAArch64ExternalSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, 227 LLVMSymbolLookupCallback SymbolLookUp, 228 void *DisInfo, MCContext *Ctx, 229 MCRelocationInfo *RelInfo) { 230 return new llvm::AArch64ExternalSymbolizer( 231 *Ctx, 232 std::unique_ptr<MCRelocationInfo>(RelInfo), 233 GetOpInfo, SymbolLookUp, DisInfo); 234 } 235 236 extern "C" void LLVMInitializeAArch64Disassembler() { 237 TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget, 238 createAArch64Disassembler); 239 TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget, 240 createAArch64Disassembler); 241 TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget, 242 createAArch64ExternalSymbolizer); 243 TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget, 244 createAArch64ExternalSymbolizer); 245 246 TargetRegistry::RegisterMCDisassembler(TheARM64Target, 247 createAArch64Disassembler); 248 TargetRegistry::RegisterMCSymbolizer(TheARM64Target, 249 createAArch64ExternalSymbolizer); 250 } 251 252 static const unsigned FPR128DecoderTable[] = { 253 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 254 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 255 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 256 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 257 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 258 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 259 AArch64::Q30, AArch64::Q31 260 }; 261 262 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 263 uint64_t Addr, 264 const void *Decoder) { 265 if (RegNo > 31) 266 return Fail; 267 268 unsigned Register = FPR128DecoderTable[RegNo]; 269 Inst.addOperand(MCOperand::CreateReg(Register)); 270 return Success; 271 } 272 273 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 274 uint64_t Addr, 275 const void *Decoder) { 276 if (RegNo > 15) 277 return Fail; 278 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 279 } 280 281 static const unsigned FPR64DecoderTable[] = { 282 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 283 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 284 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 285 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 286 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 287 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 288 AArch64::D30, AArch64::D31 289 }; 290 291 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 292 uint64_t Addr, 293 const void *Decoder) { 294 if (RegNo > 31) 295 return Fail; 296 297 unsigned Register = FPR64DecoderTable[RegNo]; 298 Inst.addOperand(MCOperand::CreateReg(Register)); 299 return Success; 300 } 301 302 static const unsigned FPR32DecoderTable[] = { 303 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 304 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 305 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 306 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 307 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 308 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 309 AArch64::S30, AArch64::S31 310 }; 311 312 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 313 uint64_t Addr, 314 const void *Decoder) { 315 if (RegNo > 31) 316 return Fail; 317 318 unsigned Register = FPR32DecoderTable[RegNo]; 319 Inst.addOperand(MCOperand::CreateReg(Register)); 320 return Success; 321 } 322 323 static const unsigned FPR16DecoderTable[] = { 324 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 325 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 326 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 327 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 328 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 329 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 330 AArch64::H30, AArch64::H31 331 }; 332 333 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 334 uint64_t Addr, 335 const void *Decoder) { 336 if (RegNo > 31) 337 return Fail; 338 339 unsigned Register = FPR16DecoderTable[RegNo]; 340 Inst.addOperand(MCOperand::CreateReg(Register)); 341 return Success; 342 } 343 344 static const unsigned FPR8DecoderTable[] = { 345 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 346 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 347 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 348 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 349 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 350 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 351 AArch64::B30, AArch64::B31 352 }; 353 354 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 355 uint64_t Addr, 356 const void *Decoder) { 357 if (RegNo > 31) 358 return Fail; 359 360 unsigned Register = FPR8DecoderTable[RegNo]; 361 Inst.addOperand(MCOperand::CreateReg(Register)); 362 return Success; 363 } 364 365 static const unsigned GPR64DecoderTable[] = { 366 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 367 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 368 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 369 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 370 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 371 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 372 AArch64::LR, AArch64::XZR 373 }; 374 375 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 376 uint64_t Addr, 377 const void *Decoder) { 378 if (RegNo > 31) 379 return Fail; 380 381 unsigned Register = GPR64DecoderTable[RegNo]; 382 Inst.addOperand(MCOperand::CreateReg(Register)); 383 return Success; 384 } 385 386 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 387 uint64_t Addr, 388 const void *Decoder) { 389 if (RegNo > 31) 390 return Fail; 391 unsigned Register = GPR64DecoderTable[RegNo]; 392 if (Register == AArch64::XZR) 393 Register = AArch64::SP; 394 Inst.addOperand(MCOperand::CreateReg(Register)); 395 return Success; 396 } 397 398 static const unsigned GPR32DecoderTable[] = { 399 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 400 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 401 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 402 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 403 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 404 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 405 AArch64::W30, AArch64::WZR 406 }; 407 408 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 409 uint64_t Addr, 410 const void *Decoder) { 411 if (RegNo > 31) 412 return Fail; 413 414 unsigned Register = GPR32DecoderTable[RegNo]; 415 Inst.addOperand(MCOperand::CreateReg(Register)); 416 return Success; 417 } 418 419 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 420 uint64_t Addr, 421 const void *Decoder) { 422 if (RegNo > 31) 423 return Fail; 424 425 unsigned Register = GPR32DecoderTable[RegNo]; 426 if (Register == AArch64::WZR) 427 Register = AArch64::WSP; 428 Inst.addOperand(MCOperand::CreateReg(Register)); 429 return Success; 430 } 431 432 static const unsigned VectorDecoderTable[] = { 433 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 434 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 435 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 436 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 437 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 438 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 439 AArch64::Q30, AArch64::Q31 440 }; 441 442 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 443 uint64_t Addr, 444 const void *Decoder) { 445 if (RegNo > 31) 446 return Fail; 447 448 unsigned Register = VectorDecoderTable[RegNo]; 449 Inst.addOperand(MCOperand::CreateReg(Register)); 450 return Success; 451 } 452 453 static const unsigned QQDecoderTable[] = { 454 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 455 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 456 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 457 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 458 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 459 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 460 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 461 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 462 }; 463 464 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 465 uint64_t Addr, const void *Decoder) { 466 if (RegNo > 31) 467 return Fail; 468 unsigned Register = QQDecoderTable[RegNo]; 469 Inst.addOperand(MCOperand::CreateReg(Register)); 470 return Success; 471 } 472 473 static const unsigned QQQDecoderTable[] = { 474 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 475 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 476 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 477 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 478 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 479 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 480 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 481 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 482 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 483 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 484 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 485 }; 486 487 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 488 uint64_t Addr, const void *Decoder) { 489 if (RegNo > 31) 490 return Fail; 491 unsigned Register = QQQDecoderTable[RegNo]; 492 Inst.addOperand(MCOperand::CreateReg(Register)); 493 return Success; 494 } 495 496 static const unsigned QQQQDecoderTable[] = { 497 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 498 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 499 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 500 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 501 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 502 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 503 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 504 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 505 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 506 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 507 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 508 }; 509 510 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 511 uint64_t Addr, 512 const void *Decoder) { 513 if (RegNo > 31) 514 return Fail; 515 unsigned Register = QQQQDecoderTable[RegNo]; 516 Inst.addOperand(MCOperand::CreateReg(Register)); 517 return Success; 518 } 519 520 static const unsigned DDDecoderTable[] = { 521 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 522 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 523 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 524 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 525 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 526 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 527 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 528 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 529 }; 530 531 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 532 uint64_t Addr, const void *Decoder) { 533 if (RegNo > 31) 534 return Fail; 535 unsigned Register = DDDecoderTable[RegNo]; 536 Inst.addOperand(MCOperand::CreateReg(Register)); 537 return Success; 538 } 539 540 static const unsigned DDDDecoderTable[] = { 541 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 542 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 543 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 544 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 545 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 546 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 547 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 548 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 549 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 550 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 551 AArch64::D30_D31_D0, AArch64::D31_D0_D1 552 }; 553 554 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 555 uint64_t Addr, const void *Decoder) { 556 if (RegNo > 31) 557 return Fail; 558 unsigned Register = DDDDecoderTable[RegNo]; 559 Inst.addOperand(MCOperand::CreateReg(Register)); 560 return Success; 561 } 562 563 static const unsigned DDDDDecoderTable[] = { 564 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 565 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 566 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 567 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 568 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 569 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 570 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 571 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 572 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 573 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 574 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 575 }; 576 577 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 578 uint64_t Addr, 579 const void *Decoder) { 580 if (RegNo > 31) 581 return Fail; 582 unsigned Register = DDDDDecoderTable[RegNo]; 583 Inst.addOperand(MCOperand::CreateReg(Register)); 584 return Success; 585 } 586 587 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, 588 uint64_t Addr, 589 const void *Decoder) { 590 // scale{5} is asserted as 1 in tblgen. 591 Imm |= 0x20; 592 Inst.addOperand(MCOperand::CreateImm(64 - Imm)); 593 return Success; 594 } 595 596 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, 597 uint64_t Addr, 598 const void *Decoder) { 599 Inst.addOperand(MCOperand::CreateImm(64 - Imm)); 600 return Success; 601 } 602 603 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, 604 uint64_t Addr, const void *Decoder) { 605 int64_t ImmVal = Imm; 606 const AArch64Disassembler *Dis = 607 static_cast<const AArch64Disassembler *>(Decoder); 608 609 // Sign-extend 19-bit immediate. 610 if (ImmVal & (1 << (19 - 1))) 611 ImmVal |= ~((1LL << 19) - 1); 612 613 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal << 2, Addr, 614 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 615 Inst.addOperand(MCOperand::CreateImm(ImmVal)); 616 return Success; 617 } 618 619 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, 620 uint64_t Address, const void *Decoder) { 621 Inst.addOperand(MCOperand::CreateImm((Imm >> 1) & 1)); 622 Inst.addOperand(MCOperand::CreateImm(Imm & 1)); 623 return Success; 624 } 625 626 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, 627 uint64_t Address, 628 const void *Decoder) { 629 const AArch64Disassembler *Dis = 630 static_cast<const AArch64Disassembler *>(Decoder); 631 const MCSubtargetInfo &STI = Dis->getSubtargetInfo(); 632 633 Imm |= 0x8000; 634 Inst.addOperand(MCOperand::CreateImm(Imm)); 635 636 bool ValidNamed; 637 (void)AArch64SysReg::MRSMapper(STI.getFeatureBits()) 638 .toString(Imm, ValidNamed); 639 640 return ValidNamed ? Success : Fail; 641 } 642 643 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, 644 uint64_t Address, 645 const void *Decoder) { 646 const AArch64Disassembler *Dis = 647 static_cast<const AArch64Disassembler *>(Decoder); 648 const MCSubtargetInfo &STI = Dis->getSubtargetInfo(); 649 650 Imm |= 0x8000; 651 Inst.addOperand(MCOperand::CreateImm(Imm)); 652 653 bool ValidNamed; 654 (void)AArch64SysReg::MSRMapper(STI.getFeatureBits()) 655 .toString(Imm, ValidNamed); 656 657 return ValidNamed ? Success : Fail; 658 } 659 660 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 661 uint64_t Address, 662 const void *Decoder) { 663 // This decoder exists to add the dummy Lane operand to the MCInst, which must 664 // be 1 in assembly but has no other real manifestation. 665 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 666 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 667 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 668 669 if (IsToVec) { 670 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 671 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 672 } else { 673 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 674 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 675 } 676 677 // Add the lane 678 Inst.addOperand(MCOperand::CreateImm(1)); 679 680 return Success; 681 } 682 683 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm, 684 unsigned Add) { 685 Inst.addOperand(MCOperand::CreateImm(Add - Imm)); 686 return Success; 687 } 688 689 static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm, 690 unsigned Add) { 691 Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1))); 692 return Success; 693 } 694 695 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, 696 uint64_t Addr, const void *Decoder) { 697 return DecodeVecShiftRImm(Inst, Imm, 64); 698 } 699 700 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 701 uint64_t Addr, 702 const void *Decoder) { 703 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 704 } 705 706 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, 707 uint64_t Addr, const void *Decoder) { 708 return DecodeVecShiftRImm(Inst, Imm, 32); 709 } 710 711 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 712 uint64_t Addr, 713 const void *Decoder) { 714 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 715 } 716 717 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, 718 uint64_t Addr, const void *Decoder) { 719 return DecodeVecShiftRImm(Inst, Imm, 16); 720 } 721 722 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 723 uint64_t Addr, 724 const void *Decoder) { 725 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 726 } 727 728 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, 729 uint64_t Addr, const void *Decoder) { 730 return DecodeVecShiftRImm(Inst, Imm, 8); 731 } 732 733 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, 734 uint64_t Addr, const void *Decoder) { 735 return DecodeVecShiftLImm(Inst, Imm, 64); 736 } 737 738 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, 739 uint64_t Addr, const void *Decoder) { 740 return DecodeVecShiftLImm(Inst, Imm, 32); 741 } 742 743 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, 744 uint64_t Addr, const void *Decoder) { 745 return DecodeVecShiftLImm(Inst, Imm, 16); 746 } 747 748 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, 749 uint64_t Addr, const void *Decoder) { 750 return DecodeVecShiftLImm(Inst, Imm, 8); 751 } 752 753 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, 754 uint32_t insn, uint64_t Addr, 755 const void *Decoder) { 756 unsigned Rd = fieldFromInstruction(insn, 0, 5); 757 unsigned Rn = fieldFromInstruction(insn, 5, 5); 758 unsigned Rm = fieldFromInstruction(insn, 16, 5); 759 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 760 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 761 unsigned shift = (shiftHi << 6) | shiftLo; 762 switch (Inst.getOpcode()) { 763 default: 764 return Fail; 765 case AArch64::ADDWrs: 766 case AArch64::ADDSWrs: 767 case AArch64::SUBWrs: 768 case AArch64::SUBSWrs: 769 // if shift == '11' then ReservedValue() 770 if (shiftHi == 0x3) 771 return Fail; 772 // Deliberate fallthrough 773 case AArch64::ANDWrs: 774 case AArch64::ANDSWrs: 775 case AArch64::BICWrs: 776 case AArch64::BICSWrs: 777 case AArch64::ORRWrs: 778 case AArch64::ORNWrs: 779 case AArch64::EORWrs: 780 case AArch64::EONWrs: { 781 // if sf == '0' and imm6<5> == '1' then ReservedValue() 782 if (shiftLo >> 5 == 1) 783 return Fail; 784 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 785 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 786 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 787 break; 788 } 789 case AArch64::ADDXrs: 790 case AArch64::ADDSXrs: 791 case AArch64::SUBXrs: 792 case AArch64::SUBSXrs: 793 // if shift == '11' then ReservedValue() 794 if (shiftHi == 0x3) 795 return Fail; 796 // Deliberate fallthrough 797 case AArch64::ANDXrs: 798 case AArch64::ANDSXrs: 799 case AArch64::BICXrs: 800 case AArch64::BICSXrs: 801 case AArch64::ORRXrs: 802 case AArch64::ORNXrs: 803 case AArch64::EORXrs: 804 case AArch64::EONXrs: 805 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 806 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 807 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 808 break; 809 } 810 811 Inst.addOperand(MCOperand::CreateImm(shift)); 812 return Success; 813 } 814 815 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, 816 uint64_t Addr, 817 const void *Decoder) { 818 unsigned Rd = fieldFromInstruction(insn, 0, 5); 819 unsigned imm = fieldFromInstruction(insn, 5, 16); 820 unsigned shift = fieldFromInstruction(insn, 21, 2); 821 shift <<= 4; 822 switch (Inst.getOpcode()) { 823 default: 824 return Fail; 825 case AArch64::MOVZWi: 826 case AArch64::MOVNWi: 827 case AArch64::MOVKWi: 828 if (shift & (1U << 5)) 829 return Fail; 830 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 831 break; 832 case AArch64::MOVZXi: 833 case AArch64::MOVNXi: 834 case AArch64::MOVKXi: 835 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 836 break; 837 } 838 839 if (Inst.getOpcode() == AArch64::MOVKWi || 840 Inst.getOpcode() == AArch64::MOVKXi) 841 Inst.addOperand(Inst.getOperand(0)); 842 843 Inst.addOperand(MCOperand::CreateImm(imm)); 844 Inst.addOperand(MCOperand::CreateImm(shift)); 845 return Success; 846 } 847 848 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, 849 uint32_t insn, uint64_t Addr, 850 const void *Decoder) { 851 unsigned Rt = fieldFromInstruction(insn, 0, 5); 852 unsigned Rn = fieldFromInstruction(insn, 5, 5); 853 unsigned offset = fieldFromInstruction(insn, 10, 12); 854 const AArch64Disassembler *Dis = 855 static_cast<const AArch64Disassembler *>(Decoder); 856 857 switch (Inst.getOpcode()) { 858 default: 859 return Fail; 860 case AArch64::PRFMui: 861 // Rt is an immediate in prefetch. 862 Inst.addOperand(MCOperand::CreateImm(Rt)); 863 break; 864 case AArch64::STRBBui: 865 case AArch64::LDRBBui: 866 case AArch64::LDRSBWui: 867 case AArch64::STRHHui: 868 case AArch64::LDRHHui: 869 case AArch64::LDRSHWui: 870 case AArch64::STRWui: 871 case AArch64::LDRWui: 872 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 873 break; 874 case AArch64::LDRSBXui: 875 case AArch64::LDRSHXui: 876 case AArch64::LDRSWui: 877 case AArch64::STRXui: 878 case AArch64::LDRXui: 879 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 880 break; 881 case AArch64::LDRQui: 882 case AArch64::STRQui: 883 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 884 break; 885 case AArch64::LDRDui: 886 case AArch64::STRDui: 887 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 888 break; 889 case AArch64::LDRSui: 890 case AArch64::STRSui: 891 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 892 break; 893 case AArch64::LDRHui: 894 case AArch64::STRHui: 895 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 896 break; 897 case AArch64::LDRBui: 898 case AArch64::STRBui: 899 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 900 break; 901 } 902 903 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 904 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 905 Inst.addOperand(MCOperand::CreateImm(offset)); 906 return Success; 907 } 908 909 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst, 910 uint32_t insn, uint64_t Addr, 911 const void *Decoder) { 912 unsigned Rt = fieldFromInstruction(insn, 0, 5); 913 unsigned Rn = fieldFromInstruction(insn, 5, 5); 914 int64_t offset = fieldFromInstruction(insn, 12, 9); 915 916 // offset is a 9-bit signed immediate, so sign extend it to 917 // fill the unsigned. 918 if (offset & (1 << (9 - 1))) 919 offset |= ~((1LL << 9) - 1); 920 921 // First operand is always the writeback to the address register, if needed. 922 switch (Inst.getOpcode()) { 923 default: 924 break; 925 case AArch64::LDRSBWpre: 926 case AArch64::LDRSHWpre: 927 case AArch64::STRBBpre: 928 case AArch64::LDRBBpre: 929 case AArch64::STRHHpre: 930 case AArch64::LDRHHpre: 931 case AArch64::STRWpre: 932 case AArch64::LDRWpre: 933 case AArch64::LDRSBWpost: 934 case AArch64::LDRSHWpost: 935 case AArch64::STRBBpost: 936 case AArch64::LDRBBpost: 937 case AArch64::STRHHpost: 938 case AArch64::LDRHHpost: 939 case AArch64::STRWpost: 940 case AArch64::LDRWpost: 941 case AArch64::LDRSBXpre: 942 case AArch64::LDRSHXpre: 943 case AArch64::STRXpre: 944 case AArch64::LDRSWpre: 945 case AArch64::LDRXpre: 946 case AArch64::LDRSBXpost: 947 case AArch64::LDRSHXpost: 948 case AArch64::STRXpost: 949 case AArch64::LDRSWpost: 950 case AArch64::LDRXpost: 951 case AArch64::LDRQpre: 952 case AArch64::STRQpre: 953 case AArch64::LDRQpost: 954 case AArch64::STRQpost: 955 case AArch64::LDRDpre: 956 case AArch64::STRDpre: 957 case AArch64::LDRDpost: 958 case AArch64::STRDpost: 959 case AArch64::LDRSpre: 960 case AArch64::STRSpre: 961 case AArch64::LDRSpost: 962 case AArch64::STRSpost: 963 case AArch64::LDRHpre: 964 case AArch64::STRHpre: 965 case AArch64::LDRHpost: 966 case AArch64::STRHpost: 967 case AArch64::LDRBpre: 968 case AArch64::STRBpre: 969 case AArch64::LDRBpost: 970 case AArch64::STRBpost: 971 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 972 break; 973 } 974 975 switch (Inst.getOpcode()) { 976 default: 977 return Fail; 978 case AArch64::PRFUMi: 979 // Rt is an immediate in prefetch. 980 Inst.addOperand(MCOperand::CreateImm(Rt)); 981 break; 982 case AArch64::STURBBi: 983 case AArch64::LDURBBi: 984 case AArch64::LDURSBWi: 985 case AArch64::STURHHi: 986 case AArch64::LDURHHi: 987 case AArch64::LDURSHWi: 988 case AArch64::STURWi: 989 case AArch64::LDURWi: 990 case AArch64::LDTRSBWi: 991 case AArch64::LDTRSHWi: 992 case AArch64::STTRWi: 993 case AArch64::LDTRWi: 994 case AArch64::STTRHi: 995 case AArch64::LDTRHi: 996 case AArch64::LDTRBi: 997 case AArch64::STTRBi: 998 case AArch64::LDRSBWpre: 999 case AArch64::LDRSHWpre: 1000 case AArch64::STRBBpre: 1001 case AArch64::LDRBBpre: 1002 case AArch64::STRHHpre: 1003 case AArch64::LDRHHpre: 1004 case AArch64::STRWpre: 1005 case AArch64::LDRWpre: 1006 case AArch64::LDRSBWpost: 1007 case AArch64::LDRSHWpost: 1008 case AArch64::STRBBpost: 1009 case AArch64::LDRBBpost: 1010 case AArch64::STRHHpost: 1011 case AArch64::LDRHHpost: 1012 case AArch64::STRWpost: 1013 case AArch64::LDRWpost: 1014 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1015 break; 1016 case AArch64::LDURSBXi: 1017 case AArch64::LDURSHXi: 1018 case AArch64::LDURSWi: 1019 case AArch64::STURXi: 1020 case AArch64::LDURXi: 1021 case AArch64::LDTRSBXi: 1022 case AArch64::LDTRSHXi: 1023 case AArch64::LDTRSWi: 1024 case AArch64::STTRXi: 1025 case AArch64::LDTRXi: 1026 case AArch64::LDRSBXpre: 1027 case AArch64::LDRSHXpre: 1028 case AArch64::STRXpre: 1029 case AArch64::LDRSWpre: 1030 case AArch64::LDRXpre: 1031 case AArch64::LDRSBXpost: 1032 case AArch64::LDRSHXpost: 1033 case AArch64::STRXpost: 1034 case AArch64::LDRSWpost: 1035 case AArch64::LDRXpost: 1036 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1037 break; 1038 case AArch64::LDURQi: 1039 case AArch64::STURQi: 1040 case AArch64::LDRQpre: 1041 case AArch64::STRQpre: 1042 case AArch64::LDRQpost: 1043 case AArch64::STRQpost: 1044 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1045 break; 1046 case AArch64::LDURDi: 1047 case AArch64::STURDi: 1048 case AArch64::LDRDpre: 1049 case AArch64::STRDpre: 1050 case AArch64::LDRDpost: 1051 case AArch64::STRDpost: 1052 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1053 break; 1054 case AArch64::LDURSi: 1055 case AArch64::STURSi: 1056 case AArch64::LDRSpre: 1057 case AArch64::STRSpre: 1058 case AArch64::LDRSpost: 1059 case AArch64::STRSpost: 1060 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1061 break; 1062 case AArch64::LDURHi: 1063 case AArch64::STURHi: 1064 case AArch64::LDRHpre: 1065 case AArch64::STRHpre: 1066 case AArch64::LDRHpost: 1067 case AArch64::STRHpost: 1068 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1069 break; 1070 case AArch64::LDURBi: 1071 case AArch64::STURBi: 1072 case AArch64::LDRBpre: 1073 case AArch64::STRBpre: 1074 case AArch64::LDRBpost: 1075 case AArch64::STRBpost: 1076 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1077 break; 1078 } 1079 1080 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1081 Inst.addOperand(MCOperand::CreateImm(offset)); 1082 1083 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1084 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1085 bool IsFP = fieldFromInstruction(insn, 26, 1); 1086 1087 // Cannot write back to a transfer register (but xzr != sp). 1088 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1089 return SoftFail; 1090 1091 return Success; 1092 } 1093 1094 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, 1095 uint32_t insn, uint64_t Addr, 1096 const void *Decoder) { 1097 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1098 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1099 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1100 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1101 1102 unsigned Opcode = Inst.getOpcode(); 1103 switch (Opcode) { 1104 default: 1105 return Fail; 1106 case AArch64::STLXRW: 1107 case AArch64::STLXRB: 1108 case AArch64::STLXRH: 1109 case AArch64::STXRW: 1110 case AArch64::STXRB: 1111 case AArch64::STXRH: 1112 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1113 // FALLTHROUGH 1114 case AArch64::LDARW: 1115 case AArch64::LDARB: 1116 case AArch64::LDARH: 1117 case AArch64::LDAXRW: 1118 case AArch64::LDAXRB: 1119 case AArch64::LDAXRH: 1120 case AArch64::LDXRW: 1121 case AArch64::LDXRB: 1122 case AArch64::LDXRH: 1123 case AArch64::STLRW: 1124 case AArch64::STLRB: 1125 case AArch64::STLRH: 1126 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1127 break; 1128 case AArch64::STLXRX: 1129 case AArch64::STXRX: 1130 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1131 // FALLTHROUGH 1132 case AArch64::LDARX: 1133 case AArch64::LDAXRX: 1134 case AArch64::LDXRX: 1135 case AArch64::STLRX: 1136 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1137 break; 1138 case AArch64::STLXPW: 1139 case AArch64::STXPW: 1140 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1141 // FALLTHROUGH 1142 case AArch64::LDAXPW: 1143 case AArch64::LDXPW: 1144 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1145 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1146 break; 1147 case AArch64::STLXPX: 1148 case AArch64::STXPX: 1149 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1150 // FALLTHROUGH 1151 case AArch64::LDAXPX: 1152 case AArch64::LDXPX: 1153 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1154 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1155 break; 1156 } 1157 1158 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1159 1160 // You shouldn't load to the same register twice in an instruction... 1161 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1162 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1163 Rt == Rt2) 1164 return SoftFail; 1165 1166 return Success; 1167 } 1168 1169 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, 1170 uint64_t Addr, 1171 const void *Decoder) { 1172 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1173 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1174 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1175 int64_t offset = fieldFromInstruction(insn, 15, 7); 1176 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1177 1178 // offset is a 7-bit signed immediate, so sign extend it to 1179 // fill the unsigned. 1180 if (offset & (1 << (7 - 1))) 1181 offset |= ~((1LL << 7) - 1); 1182 1183 unsigned Opcode = Inst.getOpcode(); 1184 bool NeedsDisjointWritebackTransfer = false; 1185 1186 // First operand is always writeback of base register. 1187 switch (Opcode) { 1188 default: 1189 break; 1190 case AArch64::LDPXpost: 1191 case AArch64::STPXpost: 1192 case AArch64::LDPSWpost: 1193 case AArch64::LDPXpre: 1194 case AArch64::STPXpre: 1195 case AArch64::LDPSWpre: 1196 case AArch64::LDPWpost: 1197 case AArch64::STPWpost: 1198 case AArch64::LDPWpre: 1199 case AArch64::STPWpre: 1200 case AArch64::LDPQpost: 1201 case AArch64::STPQpost: 1202 case AArch64::LDPQpre: 1203 case AArch64::STPQpre: 1204 case AArch64::LDPDpost: 1205 case AArch64::STPDpost: 1206 case AArch64::LDPDpre: 1207 case AArch64::STPDpre: 1208 case AArch64::LDPSpost: 1209 case AArch64::STPSpost: 1210 case AArch64::LDPSpre: 1211 case AArch64::STPSpre: 1212 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1213 break; 1214 } 1215 1216 switch (Opcode) { 1217 default: 1218 return Fail; 1219 case AArch64::LDPXpost: 1220 case AArch64::STPXpost: 1221 case AArch64::LDPSWpost: 1222 case AArch64::LDPXpre: 1223 case AArch64::STPXpre: 1224 case AArch64::LDPSWpre: 1225 NeedsDisjointWritebackTransfer = true; 1226 // Fallthrough 1227 case AArch64::LDNPXi: 1228 case AArch64::STNPXi: 1229 case AArch64::LDPXi: 1230 case AArch64::STPXi: 1231 case AArch64::LDPSWi: 1232 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1233 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1234 break; 1235 case AArch64::LDPWpost: 1236 case AArch64::STPWpost: 1237 case AArch64::LDPWpre: 1238 case AArch64::STPWpre: 1239 NeedsDisjointWritebackTransfer = true; 1240 // Fallthrough 1241 case AArch64::LDNPWi: 1242 case AArch64::STNPWi: 1243 case AArch64::LDPWi: 1244 case AArch64::STPWi: 1245 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1246 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1247 break; 1248 case AArch64::LDNPQi: 1249 case AArch64::STNPQi: 1250 case AArch64::LDPQpost: 1251 case AArch64::STPQpost: 1252 case AArch64::LDPQi: 1253 case AArch64::STPQi: 1254 case AArch64::LDPQpre: 1255 case AArch64::STPQpre: 1256 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1257 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1258 break; 1259 case AArch64::LDNPDi: 1260 case AArch64::STNPDi: 1261 case AArch64::LDPDpost: 1262 case AArch64::STPDpost: 1263 case AArch64::LDPDi: 1264 case AArch64::STPDi: 1265 case AArch64::LDPDpre: 1266 case AArch64::STPDpre: 1267 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1268 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1269 break; 1270 case AArch64::LDNPSi: 1271 case AArch64::STNPSi: 1272 case AArch64::LDPSpost: 1273 case AArch64::STPSpost: 1274 case AArch64::LDPSi: 1275 case AArch64::STPSi: 1276 case AArch64::LDPSpre: 1277 case AArch64::STPSpre: 1278 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1279 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1280 break; 1281 } 1282 1283 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1284 Inst.addOperand(MCOperand::CreateImm(offset)); 1285 1286 // You shouldn't load to the same register twice in an instruction... 1287 if (IsLoad && Rt == Rt2) 1288 return SoftFail; 1289 1290 // ... or do any operation that writes-back to a transfer register. But note 1291 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1292 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1293 return SoftFail; 1294 1295 return Success; 1296 } 1297 1298 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst, 1299 uint32_t insn, uint64_t Addr, 1300 const void *Decoder) { 1301 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1302 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1303 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1304 unsigned extend = fieldFromInstruction(insn, 10, 6); 1305 1306 unsigned shift = extend & 0x7; 1307 if (shift > 4) 1308 return Fail; 1309 1310 switch (Inst.getOpcode()) { 1311 default: 1312 return Fail; 1313 case AArch64::ADDWrx: 1314 case AArch64::SUBWrx: 1315 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1316 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1317 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1318 break; 1319 case AArch64::ADDSWrx: 1320 case AArch64::SUBSWrx: 1321 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1322 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1323 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1324 break; 1325 case AArch64::ADDXrx: 1326 case AArch64::SUBXrx: 1327 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1328 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1329 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1330 break; 1331 case AArch64::ADDSXrx: 1332 case AArch64::SUBSXrx: 1333 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1334 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1335 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1336 break; 1337 case AArch64::ADDXrx64: 1338 case AArch64::SUBXrx64: 1339 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1340 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1341 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1342 break; 1343 case AArch64::SUBSXrx64: 1344 case AArch64::ADDSXrx64: 1345 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1346 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1347 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1348 break; 1349 } 1350 1351 Inst.addOperand(MCOperand::CreateImm(extend)); 1352 return Success; 1353 } 1354 1355 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst, 1356 uint32_t insn, uint64_t Addr, 1357 const void *Decoder) { 1358 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1359 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1360 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1361 unsigned imm; 1362 1363 if (Datasize) { 1364 if (Inst.getOpcode() == AArch64::ANDSXri) 1365 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1366 else 1367 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1368 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1369 imm = fieldFromInstruction(insn, 10, 13); 1370 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1371 return Fail; 1372 } else { 1373 if (Inst.getOpcode() == AArch64::ANDSWri) 1374 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1375 else 1376 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1377 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1378 imm = fieldFromInstruction(insn, 10, 12); 1379 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1380 return Fail; 1381 } 1382 Inst.addOperand(MCOperand::CreateImm(imm)); 1383 return Success; 1384 } 1385 1386 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, 1387 uint64_t Addr, 1388 const void *Decoder) { 1389 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1390 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1391 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1392 imm |= fieldFromInstruction(insn, 5, 5); 1393 1394 if (Inst.getOpcode() == AArch64::MOVID) 1395 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1396 else 1397 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1398 1399 Inst.addOperand(MCOperand::CreateImm(imm)); 1400 1401 switch (Inst.getOpcode()) { 1402 default: 1403 break; 1404 case AArch64::MOVIv4i16: 1405 case AArch64::MOVIv8i16: 1406 case AArch64::MVNIv4i16: 1407 case AArch64::MVNIv8i16: 1408 case AArch64::MOVIv2i32: 1409 case AArch64::MOVIv4i32: 1410 case AArch64::MVNIv2i32: 1411 case AArch64::MVNIv4i32: 1412 Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2)); 1413 break; 1414 case AArch64::MOVIv2s_msl: 1415 case AArch64::MOVIv4s_msl: 1416 case AArch64::MVNIv2s_msl: 1417 case AArch64::MVNIv4s_msl: 1418 Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108)); 1419 break; 1420 } 1421 1422 return Success; 1423 } 1424 1425 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst, 1426 uint32_t insn, uint64_t Addr, 1427 const void *Decoder) { 1428 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1429 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1430 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1431 imm |= fieldFromInstruction(insn, 5, 5); 1432 1433 // Tied operands added twice. 1434 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1435 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1436 1437 Inst.addOperand(MCOperand::CreateImm(imm)); 1438 Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2)); 1439 1440 return Success; 1441 } 1442 1443 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, 1444 uint64_t Addr, const void *Decoder) { 1445 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1446 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1447 imm |= fieldFromInstruction(insn, 29, 2); 1448 const AArch64Disassembler *Dis = 1449 static_cast<const AArch64Disassembler *>(Decoder); 1450 1451 // Sign-extend the 21-bit immediate. 1452 if (imm & (1 << (21 - 1))) 1453 imm |= ~((1LL << 21) - 1); 1454 1455 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1456 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1457 Inst.addOperand(MCOperand::CreateImm(imm)); 1458 1459 return Success; 1460 } 1461 1462 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, 1463 uint64_t Addr, const void *Decoder) { 1464 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1465 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1466 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1467 unsigned S = fieldFromInstruction(insn, 29, 1); 1468 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1469 1470 unsigned ShifterVal = (Imm >> 12) & 3; 1471 unsigned ImmVal = Imm & 0xFFF; 1472 const AArch64Disassembler *Dis = 1473 static_cast<const AArch64Disassembler *>(Decoder); 1474 1475 if (ShifterVal != 0 && ShifterVal != 1) 1476 return Fail; 1477 1478 if (Datasize) { 1479 if (Rd == 31 && !S) 1480 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1481 else 1482 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1483 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1484 } else { 1485 if (Rd == 31 && !S) 1486 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1487 else 1488 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1489 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1490 } 1491 1492 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1493 Inst.addOperand(MCOperand::CreateImm(ImmVal)); 1494 Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal)); 1495 return Success; 1496 } 1497 1498 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, 1499 uint64_t Addr, 1500 const void *Decoder) { 1501 int64_t imm = fieldFromInstruction(insn, 0, 26); 1502 const AArch64Disassembler *Dis = 1503 static_cast<const AArch64Disassembler *>(Decoder); 1504 1505 // Sign-extend the 26-bit immediate. 1506 if (imm & (1 << (26 - 1))) 1507 imm |= ~((1LL << 26) - 1); 1508 1509 if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4)) 1510 Inst.addOperand(MCOperand::CreateImm(imm)); 1511 1512 return Success; 1513 } 1514 1515 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst, 1516 uint32_t insn, uint64_t Addr, 1517 const void *Decoder) { 1518 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1519 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1520 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1521 1522 uint64_t pstate_field = (op1 << 3) | op2; 1523 1524 Inst.addOperand(MCOperand::CreateImm(pstate_field)); 1525 Inst.addOperand(MCOperand::CreateImm(crm)); 1526 1527 bool ValidNamed; 1528 (void)AArch64PState::PStateMapper().toString(pstate_field, ValidNamed); 1529 1530 return ValidNamed ? Success : Fail; 1531 } 1532 1533 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, 1534 uint64_t Addr, const void *Decoder) { 1535 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1536 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1537 bit |= fieldFromInstruction(insn, 19, 5); 1538 int64_t dst = fieldFromInstruction(insn, 5, 14); 1539 const AArch64Disassembler *Dis = 1540 static_cast<const AArch64Disassembler *>(Decoder); 1541 1542 // Sign-extend 14-bit immediate. 1543 if (dst & (1 << (14 - 1))) 1544 dst |= ~((1LL << 14) - 1); 1545 1546 if (fieldFromInstruction(insn, 31, 1) == 0) 1547 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1548 else 1549 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1550 Inst.addOperand(MCOperand::CreateImm(bit)); 1551 if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) 1552 Inst.addOperand(MCOperand::CreateImm(dst)); 1553 1554 return Success; 1555 } 1556