1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm-c/Disassembler.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include <algorithm> 28 #include <memory> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "aarch64-disassembler" 33 34 // Pull DecodeStatus and its enum values into the global namespace. 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 // Forward declare these because the autogenerated code will reference them. 38 // Definitions are further down. 39 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 40 unsigned RegNo, uint64_t Address, 41 const void *Decoder); 42 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 43 unsigned RegNo, 44 uint64_t Address, 45 const void *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const void *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const void *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const void *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const void *Decoder); 58 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 59 uint64_t Address, 60 const void *Decoder); 61 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 62 unsigned RegNo, uint64_t Address, 63 const void *Decoder); 64 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 65 uint64_t Address, 66 const void *Decoder); 67 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 68 unsigned RegNo, uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 89 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 90 uint64_t Address, 91 const void *Decoder); 92 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 93 uint64_t Address, 94 const void *Decoder); 95 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 96 uint64_t Address, const void *Decoder); 97 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 98 uint64_t Address, const void *Decoder); 99 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 100 uint64_t Address, const void *Decoder); 101 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 102 uint64_t Address, const void *Decoder); 103 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 116 uint64_t Address, 117 const void *Decoder); 118 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 138 uint64_t Address, 139 const void *Decoder); 140 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 141 uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 144 uint64_t Address, const void *Decoder); 145 146 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 150 uint64_t Addr, const void *Decoder); 151 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 152 uint64_t Addr, 153 const void *Decoder); 154 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 155 uint64_t Addr, const void *Decoder); 156 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 157 uint64_t Addr, 158 const void *Decoder); 159 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 160 uint64_t Addr, const void *Decoder); 161 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 162 uint64_t Addr, 163 const void *Decoder); 164 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 165 uint64_t Addr, const void *Decoder); 166 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 167 uint64_t Addr, const void *Decoder); 168 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 169 uint64_t Addr, const void *Decoder); 170 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, const void *Decoder); 172 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 173 uint64_t Addr, const void *Decoder); 174 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 175 unsigned RegNo, 176 uint64_t Addr, 177 const void *Decoder); 178 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 179 unsigned RegNo, 180 uint64_t Addr, 181 const void *Decoder); 182 183 static bool Check(DecodeStatus &Out, DecodeStatus In) { 184 switch (In) { 185 case MCDisassembler::Success: 186 // Out stays the same. 187 return true; 188 case MCDisassembler::SoftFail: 189 Out = In; 190 return true; 191 case MCDisassembler::Fail: 192 Out = In; 193 return false; 194 } 195 llvm_unreachable("Invalid DecodeStatus!"); 196 } 197 198 #include "AArch64GenDisassemblerTables.inc" 199 #include "AArch64GenInstrInfo.inc" 200 201 #define Success MCDisassembler::Success 202 #define Fail MCDisassembler::Fail 203 #define SoftFail MCDisassembler::SoftFail 204 205 static MCDisassembler *createAArch64Disassembler(const Target &T, 206 const MCSubtargetInfo &STI, 207 MCContext &Ctx) { 208 return new AArch64Disassembler(STI, Ctx); 209 } 210 211 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 212 ArrayRef<uint8_t> Bytes, 213 uint64_t Address, 214 raw_ostream &OS, 215 raw_ostream &CS) const { 216 CommentStream = &CS; 217 218 Size = 0; 219 // We want to read exactly 4 bytes of data. 220 if (Bytes.size() < 4) 221 return Fail; 222 Size = 4; 223 224 // Encoded as a small-endian 32-bit word in the stream. 225 uint32_t Insn = 226 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 227 228 // Calling the auto-generated decoder function. 229 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 230 } 231 232 static MCSymbolizer * 233 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 234 LLVMSymbolLookupCallback SymbolLookUp, 235 void *DisInfo, MCContext *Ctx, 236 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 237 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 238 SymbolLookUp, DisInfo); 239 } 240 241 extern "C" void LLVMInitializeAArch64Disassembler() { 242 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 243 createAArch64Disassembler); 244 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 245 createAArch64Disassembler); 246 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 247 createAArch64ExternalSymbolizer); 248 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 249 createAArch64ExternalSymbolizer); 250 251 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 252 createAArch64Disassembler); 253 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 254 createAArch64ExternalSymbolizer); 255 } 256 257 static const unsigned FPR128DecoderTable[] = { 258 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 259 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 260 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 261 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 262 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 263 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 264 AArch64::Q30, AArch64::Q31 265 }; 266 267 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 268 uint64_t Addr, 269 const void *Decoder) { 270 if (RegNo > 31) 271 return Fail; 272 273 unsigned Register = FPR128DecoderTable[RegNo]; 274 Inst.addOperand(MCOperand::createReg(Register)); 275 return Success; 276 } 277 278 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 279 uint64_t Addr, 280 const void *Decoder) { 281 if (RegNo > 15) 282 return Fail; 283 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 284 } 285 286 static const unsigned FPR64DecoderTable[] = { 287 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 288 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 289 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 290 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 291 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 292 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 293 AArch64::D30, AArch64::D31 294 }; 295 296 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 297 uint64_t Addr, 298 const void *Decoder) { 299 if (RegNo > 31) 300 return Fail; 301 302 unsigned Register = FPR64DecoderTable[RegNo]; 303 Inst.addOperand(MCOperand::createReg(Register)); 304 return Success; 305 } 306 307 static const unsigned FPR32DecoderTable[] = { 308 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 309 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 310 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 311 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 312 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 313 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 314 AArch64::S30, AArch64::S31 315 }; 316 317 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 318 uint64_t Addr, 319 const void *Decoder) { 320 if (RegNo > 31) 321 return Fail; 322 323 unsigned Register = FPR32DecoderTable[RegNo]; 324 Inst.addOperand(MCOperand::createReg(Register)); 325 return Success; 326 } 327 328 static const unsigned FPR16DecoderTable[] = { 329 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 330 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 331 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 332 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 333 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 334 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 335 AArch64::H30, AArch64::H31 336 }; 337 338 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 339 uint64_t Addr, 340 const void *Decoder) { 341 if (RegNo > 31) 342 return Fail; 343 344 unsigned Register = FPR16DecoderTable[RegNo]; 345 Inst.addOperand(MCOperand::createReg(Register)); 346 return Success; 347 } 348 349 static const unsigned FPR8DecoderTable[] = { 350 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 351 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 352 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 353 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 354 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 355 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 356 AArch64::B30, AArch64::B31 357 }; 358 359 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 360 uint64_t Addr, 361 const void *Decoder) { 362 if (RegNo > 31) 363 return Fail; 364 365 unsigned Register = FPR8DecoderTable[RegNo]; 366 Inst.addOperand(MCOperand::createReg(Register)); 367 return Success; 368 } 369 370 static const unsigned GPR64DecoderTable[] = { 371 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 372 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 373 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 374 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 375 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 376 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 377 AArch64::LR, AArch64::XZR 378 }; 379 380 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 381 uint64_t Addr, 382 const void *Decoder) { 383 if (RegNo > 31) 384 return Fail; 385 386 unsigned Register = GPR64DecoderTable[RegNo]; 387 Inst.addOperand(MCOperand::createReg(Register)); 388 return Success; 389 } 390 391 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 392 uint64_t Addr, 393 const void *Decoder) { 394 if (RegNo > 31) 395 return Fail; 396 unsigned Register = GPR64DecoderTable[RegNo]; 397 if (Register == AArch64::XZR) 398 Register = AArch64::SP; 399 Inst.addOperand(MCOperand::createReg(Register)); 400 return Success; 401 } 402 403 static const unsigned GPR32DecoderTable[] = { 404 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 405 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 406 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 407 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 408 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 409 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 410 AArch64::W30, AArch64::WZR 411 }; 412 413 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 414 uint64_t Addr, 415 const void *Decoder) { 416 if (RegNo > 31) 417 return Fail; 418 419 unsigned Register = GPR32DecoderTable[RegNo]; 420 Inst.addOperand(MCOperand::createReg(Register)); 421 return Success; 422 } 423 424 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 425 uint64_t Addr, 426 const void *Decoder) { 427 if (RegNo > 31) 428 return Fail; 429 430 unsigned Register = GPR32DecoderTable[RegNo]; 431 if (Register == AArch64::WZR) 432 Register = AArch64::WSP; 433 Inst.addOperand(MCOperand::createReg(Register)); 434 return Success; 435 } 436 437 static const unsigned VectorDecoderTable[] = { 438 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 439 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 440 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 441 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 442 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 443 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 444 AArch64::Q30, AArch64::Q31 445 }; 446 447 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 448 uint64_t Addr, 449 const void *Decoder) { 450 if (RegNo > 31) 451 return Fail; 452 453 unsigned Register = VectorDecoderTable[RegNo]; 454 Inst.addOperand(MCOperand::createReg(Register)); 455 return Success; 456 } 457 458 static const unsigned QQDecoderTable[] = { 459 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 460 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 461 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 462 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 463 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 464 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 465 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 466 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 467 }; 468 469 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 470 uint64_t Addr, const void *Decoder) { 471 if (RegNo > 31) 472 return Fail; 473 unsigned Register = QQDecoderTable[RegNo]; 474 Inst.addOperand(MCOperand::createReg(Register)); 475 return Success; 476 } 477 478 static const unsigned QQQDecoderTable[] = { 479 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 480 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 481 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 482 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 483 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 484 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 485 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 486 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 487 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 488 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 489 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 490 }; 491 492 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 493 uint64_t Addr, const void *Decoder) { 494 if (RegNo > 31) 495 return Fail; 496 unsigned Register = QQQDecoderTable[RegNo]; 497 Inst.addOperand(MCOperand::createReg(Register)); 498 return Success; 499 } 500 501 static const unsigned QQQQDecoderTable[] = { 502 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 503 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 504 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 505 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 506 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 507 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 508 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 509 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 510 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 511 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 512 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 513 }; 514 515 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 516 uint64_t Addr, 517 const void *Decoder) { 518 if (RegNo > 31) 519 return Fail; 520 unsigned Register = QQQQDecoderTable[RegNo]; 521 Inst.addOperand(MCOperand::createReg(Register)); 522 return Success; 523 } 524 525 static const unsigned DDDecoderTable[] = { 526 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 527 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 528 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 529 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 530 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 531 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 532 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 533 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 534 }; 535 536 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 537 uint64_t Addr, const void *Decoder) { 538 if (RegNo > 31) 539 return Fail; 540 unsigned Register = DDDecoderTable[RegNo]; 541 Inst.addOperand(MCOperand::createReg(Register)); 542 return Success; 543 } 544 545 static const unsigned DDDDecoderTable[] = { 546 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 547 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 548 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 549 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 550 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 551 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 552 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 553 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 554 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 555 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 556 AArch64::D30_D31_D0, AArch64::D31_D0_D1 557 }; 558 559 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 560 uint64_t Addr, const void *Decoder) { 561 if (RegNo > 31) 562 return Fail; 563 unsigned Register = DDDDecoderTable[RegNo]; 564 Inst.addOperand(MCOperand::createReg(Register)); 565 return Success; 566 } 567 568 static const unsigned DDDDDecoderTable[] = { 569 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 570 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 571 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 572 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 573 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 574 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 575 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 576 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 577 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 578 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 579 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 580 }; 581 582 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 583 uint64_t Addr, 584 const void *Decoder) { 585 if (RegNo > 31) 586 return Fail; 587 unsigned Register = DDDDDecoderTable[RegNo]; 588 Inst.addOperand(MCOperand::createReg(Register)); 589 return Success; 590 } 591 592 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 593 uint64_t Addr, 594 const void *Decoder) { 595 // scale{5} is asserted as 1 in tblgen. 596 Imm |= 0x20; 597 Inst.addOperand(MCOperand::createImm(64 - Imm)); 598 return Success; 599 } 600 601 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 602 uint64_t Addr, 603 const void *Decoder) { 604 Inst.addOperand(MCOperand::createImm(64 - Imm)); 605 return Success; 606 } 607 608 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 609 uint64_t Addr, const void *Decoder) { 610 int64_t ImmVal = Imm; 611 const AArch64Disassembler *Dis = 612 static_cast<const AArch64Disassembler *>(Decoder); 613 614 // Sign-extend 19-bit immediate. 615 if (ImmVal & (1 << (19 - 1))) 616 ImmVal |= ~((1LL << 19) - 1); 617 618 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 619 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 620 Inst.addOperand(MCOperand::createImm(ImmVal)); 621 return Success; 622 } 623 624 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 625 uint64_t Address, const void *Decoder) { 626 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 627 Inst.addOperand(MCOperand::createImm(Imm & 1)); 628 return Success; 629 } 630 631 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 632 uint64_t Address, 633 const void *Decoder) { 634 Inst.addOperand(MCOperand::createImm(Imm)); 635 636 // Every system register in the encoding space is valid with the syntax 637 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 638 return Success; 639 } 640 641 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 642 uint64_t Address, 643 const void *Decoder) { 644 Inst.addOperand(MCOperand::createImm(Imm)); 645 646 return Success; 647 } 648 649 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 650 uint64_t Address, 651 const void *Decoder) { 652 // This decoder exists to add the dummy Lane operand to the MCInst, which must 653 // be 1 in assembly but has no other real manifestation. 654 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 655 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 656 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 657 658 if (IsToVec) { 659 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 660 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 661 } else { 662 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 663 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 664 } 665 666 // Add the lane 667 Inst.addOperand(MCOperand::createImm(1)); 668 669 return Success; 670 } 671 672 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 673 unsigned Add) { 674 Inst.addOperand(MCOperand::createImm(Add - Imm)); 675 return Success; 676 } 677 678 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 679 unsigned Add) { 680 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 681 return Success; 682 } 683 684 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 685 uint64_t Addr, const void *Decoder) { 686 return DecodeVecShiftRImm(Inst, Imm, 64); 687 } 688 689 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 690 uint64_t Addr, 691 const void *Decoder) { 692 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 693 } 694 695 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 696 uint64_t Addr, const void *Decoder) { 697 return DecodeVecShiftRImm(Inst, Imm, 32); 698 } 699 700 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 701 uint64_t Addr, 702 const void *Decoder) { 703 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 704 } 705 706 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 707 uint64_t Addr, const void *Decoder) { 708 return DecodeVecShiftRImm(Inst, Imm, 16); 709 } 710 711 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 712 uint64_t Addr, 713 const void *Decoder) { 714 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 715 } 716 717 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 718 uint64_t Addr, const void *Decoder) { 719 return DecodeVecShiftRImm(Inst, Imm, 8); 720 } 721 722 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 723 uint64_t Addr, const void *Decoder) { 724 return DecodeVecShiftLImm(Inst, Imm, 64); 725 } 726 727 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 728 uint64_t Addr, const void *Decoder) { 729 return DecodeVecShiftLImm(Inst, Imm, 32); 730 } 731 732 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 733 uint64_t Addr, const void *Decoder) { 734 return DecodeVecShiftLImm(Inst, Imm, 16); 735 } 736 737 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 738 uint64_t Addr, const void *Decoder) { 739 return DecodeVecShiftLImm(Inst, Imm, 8); 740 } 741 742 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 743 uint64_t Addr, 744 const void *Decoder) { 745 unsigned Rd = fieldFromInstruction(insn, 0, 5); 746 unsigned Rn = fieldFromInstruction(insn, 5, 5); 747 unsigned Rm = fieldFromInstruction(insn, 16, 5); 748 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 749 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 750 unsigned shift = (shiftHi << 6) | shiftLo; 751 switch (Inst.getOpcode()) { 752 default: 753 return Fail; 754 case AArch64::ADDWrs: 755 case AArch64::ADDSWrs: 756 case AArch64::SUBWrs: 757 case AArch64::SUBSWrs: 758 // if shift == '11' then ReservedValue() 759 if (shiftHi == 0x3) 760 return Fail; 761 LLVM_FALLTHROUGH; 762 case AArch64::ANDWrs: 763 case AArch64::ANDSWrs: 764 case AArch64::BICWrs: 765 case AArch64::BICSWrs: 766 case AArch64::ORRWrs: 767 case AArch64::ORNWrs: 768 case AArch64::EORWrs: 769 case AArch64::EONWrs: { 770 // if sf == '0' and imm6<5> == '1' then ReservedValue() 771 if (shiftLo >> 5 == 1) 772 return Fail; 773 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 774 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 775 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 776 break; 777 } 778 case AArch64::ADDXrs: 779 case AArch64::ADDSXrs: 780 case AArch64::SUBXrs: 781 case AArch64::SUBSXrs: 782 // if shift == '11' then ReservedValue() 783 if (shiftHi == 0x3) 784 return Fail; 785 LLVM_FALLTHROUGH; 786 case AArch64::ANDXrs: 787 case AArch64::ANDSXrs: 788 case AArch64::BICXrs: 789 case AArch64::BICSXrs: 790 case AArch64::ORRXrs: 791 case AArch64::ORNXrs: 792 case AArch64::EORXrs: 793 case AArch64::EONXrs: 794 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 795 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 796 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 797 break; 798 } 799 800 Inst.addOperand(MCOperand::createImm(shift)); 801 return Success; 802 } 803 804 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 805 uint64_t Addr, 806 const void *Decoder) { 807 unsigned Rd = fieldFromInstruction(insn, 0, 5); 808 unsigned imm = fieldFromInstruction(insn, 5, 16); 809 unsigned shift = fieldFromInstruction(insn, 21, 2); 810 shift <<= 4; 811 switch (Inst.getOpcode()) { 812 default: 813 return Fail; 814 case AArch64::MOVZWi: 815 case AArch64::MOVNWi: 816 case AArch64::MOVKWi: 817 if (shift & (1U << 5)) 818 return Fail; 819 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 820 break; 821 case AArch64::MOVZXi: 822 case AArch64::MOVNXi: 823 case AArch64::MOVKXi: 824 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 825 break; 826 } 827 828 if (Inst.getOpcode() == AArch64::MOVKWi || 829 Inst.getOpcode() == AArch64::MOVKXi) 830 Inst.addOperand(Inst.getOperand(0)); 831 832 Inst.addOperand(MCOperand::createImm(imm)); 833 Inst.addOperand(MCOperand::createImm(shift)); 834 return Success; 835 } 836 837 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 838 uint64_t Addr, 839 const void *Decoder) { 840 unsigned Rt = fieldFromInstruction(insn, 0, 5); 841 unsigned Rn = fieldFromInstruction(insn, 5, 5); 842 unsigned offset = fieldFromInstruction(insn, 10, 12); 843 const AArch64Disassembler *Dis = 844 static_cast<const AArch64Disassembler *>(Decoder); 845 846 switch (Inst.getOpcode()) { 847 default: 848 return Fail; 849 case AArch64::PRFMui: 850 // Rt is an immediate in prefetch. 851 Inst.addOperand(MCOperand::createImm(Rt)); 852 break; 853 case AArch64::STRBBui: 854 case AArch64::LDRBBui: 855 case AArch64::LDRSBWui: 856 case AArch64::STRHHui: 857 case AArch64::LDRHHui: 858 case AArch64::LDRSHWui: 859 case AArch64::STRWui: 860 case AArch64::LDRWui: 861 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 862 break; 863 case AArch64::LDRSBXui: 864 case AArch64::LDRSHXui: 865 case AArch64::LDRSWui: 866 case AArch64::STRXui: 867 case AArch64::LDRXui: 868 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 869 break; 870 case AArch64::LDRQui: 871 case AArch64::STRQui: 872 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 873 break; 874 case AArch64::LDRDui: 875 case AArch64::STRDui: 876 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 877 break; 878 case AArch64::LDRSui: 879 case AArch64::STRSui: 880 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 881 break; 882 case AArch64::LDRHui: 883 case AArch64::STRHui: 884 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 885 break; 886 case AArch64::LDRBui: 887 case AArch64::STRBui: 888 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 889 break; 890 } 891 892 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 893 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 894 Inst.addOperand(MCOperand::createImm(offset)); 895 return Success; 896 } 897 898 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 899 uint64_t Addr, 900 const void *Decoder) { 901 unsigned Rt = fieldFromInstruction(insn, 0, 5); 902 unsigned Rn = fieldFromInstruction(insn, 5, 5); 903 int64_t offset = fieldFromInstruction(insn, 12, 9); 904 905 // offset is a 9-bit signed immediate, so sign extend it to 906 // fill the unsigned. 907 if (offset & (1 << (9 - 1))) 908 offset |= ~((1LL << 9) - 1); 909 910 // First operand is always the writeback to the address register, if needed. 911 switch (Inst.getOpcode()) { 912 default: 913 break; 914 case AArch64::LDRSBWpre: 915 case AArch64::LDRSHWpre: 916 case AArch64::STRBBpre: 917 case AArch64::LDRBBpre: 918 case AArch64::STRHHpre: 919 case AArch64::LDRHHpre: 920 case AArch64::STRWpre: 921 case AArch64::LDRWpre: 922 case AArch64::LDRSBWpost: 923 case AArch64::LDRSHWpost: 924 case AArch64::STRBBpost: 925 case AArch64::LDRBBpost: 926 case AArch64::STRHHpost: 927 case AArch64::LDRHHpost: 928 case AArch64::STRWpost: 929 case AArch64::LDRWpost: 930 case AArch64::LDRSBXpre: 931 case AArch64::LDRSHXpre: 932 case AArch64::STRXpre: 933 case AArch64::LDRSWpre: 934 case AArch64::LDRXpre: 935 case AArch64::LDRSBXpost: 936 case AArch64::LDRSHXpost: 937 case AArch64::STRXpost: 938 case AArch64::LDRSWpost: 939 case AArch64::LDRXpost: 940 case AArch64::LDRQpre: 941 case AArch64::STRQpre: 942 case AArch64::LDRQpost: 943 case AArch64::STRQpost: 944 case AArch64::LDRDpre: 945 case AArch64::STRDpre: 946 case AArch64::LDRDpost: 947 case AArch64::STRDpost: 948 case AArch64::LDRSpre: 949 case AArch64::STRSpre: 950 case AArch64::LDRSpost: 951 case AArch64::STRSpost: 952 case AArch64::LDRHpre: 953 case AArch64::STRHpre: 954 case AArch64::LDRHpost: 955 case AArch64::STRHpost: 956 case AArch64::LDRBpre: 957 case AArch64::STRBpre: 958 case AArch64::LDRBpost: 959 case AArch64::STRBpost: 960 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 961 break; 962 } 963 964 switch (Inst.getOpcode()) { 965 default: 966 return Fail; 967 case AArch64::PRFUMi: 968 // Rt is an immediate in prefetch. 969 Inst.addOperand(MCOperand::createImm(Rt)); 970 break; 971 case AArch64::STURBBi: 972 case AArch64::LDURBBi: 973 case AArch64::LDURSBWi: 974 case AArch64::STURHHi: 975 case AArch64::LDURHHi: 976 case AArch64::LDURSHWi: 977 case AArch64::STURWi: 978 case AArch64::LDURWi: 979 case AArch64::LDTRSBWi: 980 case AArch64::LDTRSHWi: 981 case AArch64::STTRWi: 982 case AArch64::LDTRWi: 983 case AArch64::STTRHi: 984 case AArch64::LDTRHi: 985 case AArch64::LDTRBi: 986 case AArch64::STTRBi: 987 case AArch64::LDRSBWpre: 988 case AArch64::LDRSHWpre: 989 case AArch64::STRBBpre: 990 case AArch64::LDRBBpre: 991 case AArch64::STRHHpre: 992 case AArch64::LDRHHpre: 993 case AArch64::STRWpre: 994 case AArch64::LDRWpre: 995 case AArch64::LDRSBWpost: 996 case AArch64::LDRSHWpost: 997 case AArch64::STRBBpost: 998 case AArch64::LDRBBpost: 999 case AArch64::STRHHpost: 1000 case AArch64::LDRHHpost: 1001 case AArch64::STRWpost: 1002 case AArch64::LDRWpost: 1003 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1004 break; 1005 case AArch64::LDURSBXi: 1006 case AArch64::LDURSHXi: 1007 case AArch64::LDURSWi: 1008 case AArch64::STURXi: 1009 case AArch64::LDURXi: 1010 case AArch64::LDTRSBXi: 1011 case AArch64::LDTRSHXi: 1012 case AArch64::LDTRSWi: 1013 case AArch64::STTRXi: 1014 case AArch64::LDTRXi: 1015 case AArch64::LDRSBXpre: 1016 case AArch64::LDRSHXpre: 1017 case AArch64::STRXpre: 1018 case AArch64::LDRSWpre: 1019 case AArch64::LDRXpre: 1020 case AArch64::LDRSBXpost: 1021 case AArch64::LDRSHXpost: 1022 case AArch64::STRXpost: 1023 case AArch64::LDRSWpost: 1024 case AArch64::LDRXpost: 1025 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1026 break; 1027 case AArch64::LDURQi: 1028 case AArch64::STURQi: 1029 case AArch64::LDRQpre: 1030 case AArch64::STRQpre: 1031 case AArch64::LDRQpost: 1032 case AArch64::STRQpost: 1033 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1034 break; 1035 case AArch64::LDURDi: 1036 case AArch64::STURDi: 1037 case AArch64::LDRDpre: 1038 case AArch64::STRDpre: 1039 case AArch64::LDRDpost: 1040 case AArch64::STRDpost: 1041 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1042 break; 1043 case AArch64::LDURSi: 1044 case AArch64::STURSi: 1045 case AArch64::LDRSpre: 1046 case AArch64::STRSpre: 1047 case AArch64::LDRSpost: 1048 case AArch64::STRSpost: 1049 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1050 break; 1051 case AArch64::LDURHi: 1052 case AArch64::STURHi: 1053 case AArch64::LDRHpre: 1054 case AArch64::STRHpre: 1055 case AArch64::LDRHpost: 1056 case AArch64::STRHpost: 1057 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1058 break; 1059 case AArch64::LDURBi: 1060 case AArch64::STURBi: 1061 case AArch64::LDRBpre: 1062 case AArch64::STRBpre: 1063 case AArch64::LDRBpost: 1064 case AArch64::STRBpost: 1065 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1066 break; 1067 } 1068 1069 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1070 Inst.addOperand(MCOperand::createImm(offset)); 1071 1072 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1073 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1074 bool IsFP = fieldFromInstruction(insn, 26, 1); 1075 1076 // Cannot write back to a transfer register (but xzr != sp). 1077 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1078 return SoftFail; 1079 1080 return Success; 1081 } 1082 1083 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1084 uint64_t Addr, 1085 const void *Decoder) { 1086 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1087 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1088 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1089 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1090 1091 unsigned Opcode = Inst.getOpcode(); 1092 switch (Opcode) { 1093 default: 1094 return Fail; 1095 case AArch64::STLXRW: 1096 case AArch64::STLXRB: 1097 case AArch64::STLXRH: 1098 case AArch64::STXRW: 1099 case AArch64::STXRB: 1100 case AArch64::STXRH: 1101 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1102 LLVM_FALLTHROUGH; 1103 case AArch64::LDARW: 1104 case AArch64::LDARB: 1105 case AArch64::LDARH: 1106 case AArch64::LDAXRW: 1107 case AArch64::LDAXRB: 1108 case AArch64::LDAXRH: 1109 case AArch64::LDXRW: 1110 case AArch64::LDXRB: 1111 case AArch64::LDXRH: 1112 case AArch64::STLRW: 1113 case AArch64::STLRB: 1114 case AArch64::STLRH: 1115 case AArch64::STLLRW: 1116 case AArch64::STLLRB: 1117 case AArch64::STLLRH: 1118 case AArch64::LDLARW: 1119 case AArch64::LDLARB: 1120 case AArch64::LDLARH: 1121 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1122 break; 1123 case AArch64::STLXRX: 1124 case AArch64::STXRX: 1125 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1126 LLVM_FALLTHROUGH; 1127 case AArch64::LDARX: 1128 case AArch64::LDAXRX: 1129 case AArch64::LDXRX: 1130 case AArch64::STLRX: 1131 case AArch64::LDLARX: 1132 case AArch64::STLLRX: 1133 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1134 break; 1135 case AArch64::STLXPW: 1136 case AArch64::STXPW: 1137 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1138 LLVM_FALLTHROUGH; 1139 case AArch64::LDAXPW: 1140 case AArch64::LDXPW: 1141 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1142 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1143 break; 1144 case AArch64::STLXPX: 1145 case AArch64::STXPX: 1146 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1147 LLVM_FALLTHROUGH; 1148 case AArch64::LDAXPX: 1149 case AArch64::LDXPX: 1150 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1151 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1152 break; 1153 } 1154 1155 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1156 1157 // You shouldn't load to the same register twice in an instruction... 1158 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1159 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1160 Rt == Rt2) 1161 return SoftFail; 1162 1163 return Success; 1164 } 1165 1166 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1167 uint64_t Addr, 1168 const void *Decoder) { 1169 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1170 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1171 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1172 int64_t offset = fieldFromInstruction(insn, 15, 7); 1173 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1174 1175 // offset is a 7-bit signed immediate, so sign extend it to 1176 // fill the unsigned. 1177 if (offset & (1 << (7 - 1))) 1178 offset |= ~((1LL << 7) - 1); 1179 1180 unsigned Opcode = Inst.getOpcode(); 1181 bool NeedsDisjointWritebackTransfer = false; 1182 1183 // First operand is always writeback of base register. 1184 switch (Opcode) { 1185 default: 1186 break; 1187 case AArch64::LDPXpost: 1188 case AArch64::STPXpost: 1189 case AArch64::LDPSWpost: 1190 case AArch64::LDPXpre: 1191 case AArch64::STPXpre: 1192 case AArch64::LDPSWpre: 1193 case AArch64::LDPWpost: 1194 case AArch64::STPWpost: 1195 case AArch64::LDPWpre: 1196 case AArch64::STPWpre: 1197 case AArch64::LDPQpost: 1198 case AArch64::STPQpost: 1199 case AArch64::LDPQpre: 1200 case AArch64::STPQpre: 1201 case AArch64::LDPDpost: 1202 case AArch64::STPDpost: 1203 case AArch64::LDPDpre: 1204 case AArch64::STPDpre: 1205 case AArch64::LDPSpost: 1206 case AArch64::STPSpost: 1207 case AArch64::LDPSpre: 1208 case AArch64::STPSpre: 1209 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1210 break; 1211 } 1212 1213 switch (Opcode) { 1214 default: 1215 return Fail; 1216 case AArch64::LDPXpost: 1217 case AArch64::STPXpost: 1218 case AArch64::LDPSWpost: 1219 case AArch64::LDPXpre: 1220 case AArch64::STPXpre: 1221 case AArch64::LDPSWpre: 1222 NeedsDisjointWritebackTransfer = true; 1223 LLVM_FALLTHROUGH; 1224 case AArch64::LDNPXi: 1225 case AArch64::STNPXi: 1226 case AArch64::LDPXi: 1227 case AArch64::STPXi: 1228 case AArch64::LDPSWi: 1229 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1230 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1231 break; 1232 case AArch64::LDPWpost: 1233 case AArch64::STPWpost: 1234 case AArch64::LDPWpre: 1235 case AArch64::STPWpre: 1236 NeedsDisjointWritebackTransfer = true; 1237 LLVM_FALLTHROUGH; 1238 case AArch64::LDNPWi: 1239 case AArch64::STNPWi: 1240 case AArch64::LDPWi: 1241 case AArch64::STPWi: 1242 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1243 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1244 break; 1245 case AArch64::LDNPQi: 1246 case AArch64::STNPQi: 1247 case AArch64::LDPQpost: 1248 case AArch64::STPQpost: 1249 case AArch64::LDPQi: 1250 case AArch64::STPQi: 1251 case AArch64::LDPQpre: 1252 case AArch64::STPQpre: 1253 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1254 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1255 break; 1256 case AArch64::LDNPDi: 1257 case AArch64::STNPDi: 1258 case AArch64::LDPDpost: 1259 case AArch64::STPDpost: 1260 case AArch64::LDPDi: 1261 case AArch64::STPDi: 1262 case AArch64::LDPDpre: 1263 case AArch64::STPDpre: 1264 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1265 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1266 break; 1267 case AArch64::LDNPSi: 1268 case AArch64::STNPSi: 1269 case AArch64::LDPSpost: 1270 case AArch64::STPSpost: 1271 case AArch64::LDPSi: 1272 case AArch64::STPSi: 1273 case AArch64::LDPSpre: 1274 case AArch64::STPSpre: 1275 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1276 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1277 break; 1278 } 1279 1280 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1281 Inst.addOperand(MCOperand::createImm(offset)); 1282 1283 // You shouldn't load to the same register twice in an instruction... 1284 if (IsLoad && Rt == Rt2) 1285 return SoftFail; 1286 1287 // ... or do any operation that writes-back to a transfer register. But note 1288 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1289 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1290 return SoftFail; 1291 1292 return Success; 1293 } 1294 1295 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1296 uint64_t Addr, 1297 const void *Decoder) { 1298 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1299 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1300 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1301 unsigned extend = fieldFromInstruction(insn, 10, 6); 1302 1303 unsigned shift = extend & 0x7; 1304 if (shift > 4) 1305 return Fail; 1306 1307 switch (Inst.getOpcode()) { 1308 default: 1309 return Fail; 1310 case AArch64::ADDWrx: 1311 case AArch64::SUBWrx: 1312 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1313 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1314 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1315 break; 1316 case AArch64::ADDSWrx: 1317 case AArch64::SUBSWrx: 1318 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1319 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1320 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1321 break; 1322 case AArch64::ADDXrx: 1323 case AArch64::SUBXrx: 1324 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1325 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1326 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1327 break; 1328 case AArch64::ADDSXrx: 1329 case AArch64::SUBSXrx: 1330 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1331 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1332 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1333 break; 1334 case AArch64::ADDXrx64: 1335 case AArch64::SUBXrx64: 1336 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1337 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1338 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1339 break; 1340 case AArch64::SUBSXrx64: 1341 case AArch64::ADDSXrx64: 1342 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1343 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1344 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1345 break; 1346 } 1347 1348 Inst.addOperand(MCOperand::createImm(extend)); 1349 return Success; 1350 } 1351 1352 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1353 uint64_t Addr, 1354 const void *Decoder) { 1355 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1356 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1357 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1358 unsigned imm; 1359 1360 if (Datasize) { 1361 if (Inst.getOpcode() == AArch64::ANDSXri) 1362 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1363 else 1364 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1365 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1366 imm = fieldFromInstruction(insn, 10, 13); 1367 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1368 return Fail; 1369 } else { 1370 if (Inst.getOpcode() == AArch64::ANDSWri) 1371 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1372 else 1373 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1374 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1375 imm = fieldFromInstruction(insn, 10, 12); 1376 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1377 return Fail; 1378 } 1379 Inst.addOperand(MCOperand::createImm(imm)); 1380 return Success; 1381 } 1382 1383 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1384 uint64_t Addr, 1385 const void *Decoder) { 1386 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1387 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1388 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1389 imm |= fieldFromInstruction(insn, 5, 5); 1390 1391 if (Inst.getOpcode() == AArch64::MOVID) 1392 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1393 else 1394 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1395 1396 Inst.addOperand(MCOperand::createImm(imm)); 1397 1398 switch (Inst.getOpcode()) { 1399 default: 1400 break; 1401 case AArch64::MOVIv4i16: 1402 case AArch64::MOVIv8i16: 1403 case AArch64::MVNIv4i16: 1404 case AArch64::MVNIv8i16: 1405 case AArch64::MOVIv2i32: 1406 case AArch64::MOVIv4i32: 1407 case AArch64::MVNIv2i32: 1408 case AArch64::MVNIv4i32: 1409 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1410 break; 1411 case AArch64::MOVIv2s_msl: 1412 case AArch64::MOVIv4s_msl: 1413 case AArch64::MVNIv2s_msl: 1414 case AArch64::MVNIv4s_msl: 1415 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1416 break; 1417 } 1418 1419 return Success; 1420 } 1421 1422 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1423 uint64_t Addr, 1424 const void *Decoder) { 1425 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1426 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1427 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1428 imm |= fieldFromInstruction(insn, 5, 5); 1429 1430 // Tied operands added twice. 1431 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1432 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1433 1434 Inst.addOperand(MCOperand::createImm(imm)); 1435 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1436 1437 return Success; 1438 } 1439 1440 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1441 uint64_t Addr, const void *Decoder) { 1442 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1443 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1444 imm |= fieldFromInstruction(insn, 29, 2); 1445 const AArch64Disassembler *Dis = 1446 static_cast<const AArch64Disassembler *>(Decoder); 1447 1448 // Sign-extend the 21-bit immediate. 1449 if (imm & (1 << (21 - 1))) 1450 imm |= ~((1LL << 21) - 1); 1451 1452 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1453 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1454 Inst.addOperand(MCOperand::createImm(imm)); 1455 1456 return Success; 1457 } 1458 1459 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1460 uint64_t Addr, const void *Decoder) { 1461 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1462 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1463 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1464 unsigned S = fieldFromInstruction(insn, 29, 1); 1465 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1466 1467 unsigned ShifterVal = (Imm >> 12) & 3; 1468 unsigned ImmVal = Imm & 0xFFF; 1469 const AArch64Disassembler *Dis = 1470 static_cast<const AArch64Disassembler *>(Decoder); 1471 1472 if (ShifterVal != 0 && ShifterVal != 1) 1473 return Fail; 1474 1475 if (Datasize) { 1476 if (Rd == 31 && !S) 1477 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1478 else 1479 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1480 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1481 } else { 1482 if (Rd == 31 && !S) 1483 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1484 else 1485 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1486 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1487 } 1488 1489 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1490 Inst.addOperand(MCOperand::createImm(ImmVal)); 1491 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1492 return Success; 1493 } 1494 1495 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1496 uint64_t Addr, 1497 const void *Decoder) { 1498 int64_t imm = fieldFromInstruction(insn, 0, 26); 1499 const AArch64Disassembler *Dis = 1500 static_cast<const AArch64Disassembler *>(Decoder); 1501 1502 // Sign-extend the 26-bit immediate. 1503 if (imm & (1 << (26 - 1))) 1504 imm |= ~((1LL << 26) - 1); 1505 1506 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1507 Inst.addOperand(MCOperand::createImm(imm)); 1508 1509 return Success; 1510 } 1511 1512 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1513 uint64_t Addr, 1514 const void *Decoder) { 1515 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1516 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1517 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1518 1519 uint64_t pstate_field = (op1 << 3) | op2; 1520 1521 if ((pstate_field == AArch64PState::PAN || 1522 pstate_field == AArch64PState::UAO) && crm > 1) 1523 return Fail; 1524 1525 Inst.addOperand(MCOperand::createImm(pstate_field)); 1526 Inst.addOperand(MCOperand::createImm(crm)); 1527 1528 const AArch64Disassembler *Dis = 1529 static_cast<const AArch64Disassembler *>(Decoder); 1530 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1531 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1532 return Success; 1533 return Fail; 1534 } 1535 1536 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1537 uint64_t Addr, const void *Decoder) { 1538 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1539 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1540 bit |= fieldFromInstruction(insn, 19, 5); 1541 int64_t dst = fieldFromInstruction(insn, 5, 14); 1542 const AArch64Disassembler *Dis = 1543 static_cast<const AArch64Disassembler *>(Decoder); 1544 1545 // Sign-extend 14-bit immediate. 1546 if (dst & (1 << (14 - 1))) 1547 dst |= ~((1LL << 14) - 1); 1548 1549 if (fieldFromInstruction(insn, 31, 1) == 0) 1550 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1551 else 1552 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1553 Inst.addOperand(MCOperand::createImm(bit)); 1554 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1555 Inst.addOperand(MCOperand::createImm(dst)); 1556 1557 return Success; 1558 } 1559 1560 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1561 unsigned RegClassID, 1562 unsigned RegNo, 1563 uint64_t Addr, 1564 const void *Decoder) { 1565 // Register number must be even (see CASP instruction) 1566 if (RegNo & 0x1) 1567 return Fail; 1568 1569 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1570 Inst.addOperand(MCOperand::createReg(Register)); 1571 return Success; 1572 } 1573 1574 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1575 unsigned RegNo, 1576 uint64_t Addr, 1577 const void *Decoder) { 1578 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1579 AArch64::WSeqPairsClassRegClassID, 1580 RegNo, Addr, Decoder); 1581 } 1582 1583 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1584 unsigned RegNo, 1585 uint64_t Addr, 1586 const void *Decoder) { 1587 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1588 AArch64::XSeqPairsClassRegClassID, 1589 RegNo, Addr, Decoder); 1590 } 1591