1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 80 unsigned RegNo, uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 template <unsigned NumBitsForTile> 119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 129 uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 132 uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 143 uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 152 uint64_t Address, 153 const void *Decoder); 154 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 155 uint64_t Address, 156 const void *Decoder); 157 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 158 uint64_t Address, 159 const void *Decoder); 160 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 161 uint64_t Address, 162 const void *Decoder); 163 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 164 uint64_t Address, 165 const void *Decoder); 166 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 167 uint64_t Address, 168 const void *Decoder); 169 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 170 uint64_t Address, 171 const void *Decoder); 172 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 173 uint64_t Address, 174 const void *Decoder); 175 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 180 uint64_t Address, 181 const void *Decoder); 182 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 183 uint64_t Address, 184 const void *Decoder); 185 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 186 uint64_t Address, const void *Decoder); 187 188 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 189 uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, const void *Decoder); 193 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 194 uint64_t Addr, 195 const void *Decoder); 196 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, const void *Decoder); 198 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const void *Decoder); 201 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 202 uint64_t Addr, const void *Decoder); 203 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, 205 const void *Decoder); 206 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 207 uint64_t Addr, const void *Decoder); 208 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 209 uint64_t Addr, const void *Decoder); 210 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, const void *Decoder); 214 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, const void *Decoder); 216 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 217 unsigned RegNo, 218 uint64_t Addr, 219 const void *Decoder); 220 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Addr, 223 const void *Decoder); 224 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 225 uint32_t insn, 226 uint64_t Address, 227 const void *Decoder); 228 template<int Bits> 229 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 230 uint64_t Address, const void *Decoder); 231 template <int ElementWidth> 232 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 233 uint64_t Addr, const void *Decoder); 234 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 235 uint64_t Addr, const void *Decoder); 236 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 237 const void *Decoder); 238 239 static bool Check(DecodeStatus &Out, DecodeStatus In) { 240 switch (In) { 241 case MCDisassembler::Success: 242 // Out stays the same. 243 return true; 244 case MCDisassembler::SoftFail: 245 Out = In; 246 return true; 247 case MCDisassembler::Fail: 248 Out = In; 249 return false; 250 } 251 llvm_unreachable("Invalid DecodeStatus!"); 252 } 253 254 #include "AArch64GenDisassemblerTables.inc" 255 #include "AArch64GenInstrInfo.inc" 256 257 #define Success MCDisassembler::Success 258 #define Fail MCDisassembler::Fail 259 #define SoftFail MCDisassembler::SoftFail 260 261 static MCDisassembler *createAArch64Disassembler(const Target &T, 262 const MCSubtargetInfo &STI, 263 MCContext &Ctx) { 264 return new AArch64Disassembler(STI, Ctx); 265 } 266 267 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 268 ArrayRef<uint8_t> Bytes, 269 uint64_t Address, 270 raw_ostream &CS) const { 271 CommentStream = &CS; 272 273 Size = 0; 274 // We want to read exactly 4 bytes of data. 275 if (Bytes.size() < 4) 276 return Fail; 277 Size = 4; 278 279 // Encoded as a small-endian 32-bit word in the stream. 280 uint32_t Insn = 281 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 282 283 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 284 285 for (auto Table : Tables) { 286 DecodeStatus Result = 287 decodeInstruction(Table, MI, Insn, Address, this, STI); 288 289 switch (MI.getOpcode()) { 290 default: 291 break; 292 // For Scalable Matrix Extension (SME) instructions that have an implicit 293 // operand for the accumulator (ZA) which isn't encoded, manually insert 294 // operand. 295 case AArch64::LDR_ZA: 296 case AArch64::STR_ZA: { 297 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA)); 298 // Spill and fill instructions have a single immediate used for both the 299 // vector select offset and optional memory offset. Replicate the decoded 300 // immediate. 301 const MCOperand &Imm4Op = MI.getOperand(2); 302 assert(Imm4Op.isImm() && "Unexpected operand type!"); 303 MI.addOperand(Imm4Op); 304 break; 305 } 306 case AArch64::LD1_MXIPXX_H_B: 307 case AArch64::LD1_MXIPXX_V_B: 308 case AArch64::ST1_MXIPXX_H_B: 309 case AArch64::ST1_MXIPXX_V_B: 310 case AArch64::INSERT_MXIPZ_H_B: 311 case AArch64::INSERT_MXIPZ_V_B: 312 // e.g. 313 // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B 314 // ^ insert implicit 8-bit element tile 315 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 316 break; 317 case AArch64::EXTRACT_ZPMXI_H_B: 318 case AArch64::EXTRACT_ZPMXI_V_B: 319 // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>] 320 // ^ insert implicit 8-bit element tile 321 MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0)); 322 break; 323 } 324 325 if (Result != MCDisassembler::Fail) 326 return Result; 327 } 328 329 return MCDisassembler::Fail; 330 } 331 332 static MCSymbolizer * 333 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 334 LLVMSymbolLookupCallback SymbolLookUp, 335 void *DisInfo, MCContext *Ctx, 336 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 337 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 338 SymbolLookUp, DisInfo); 339 } 340 341 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 342 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 343 createAArch64Disassembler); 344 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 345 createAArch64Disassembler); 346 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 347 createAArch64ExternalSymbolizer); 348 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 349 createAArch64ExternalSymbolizer); 350 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 351 createAArch64Disassembler); 352 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 353 createAArch64ExternalSymbolizer); 354 355 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 356 createAArch64Disassembler); 357 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 358 createAArch64ExternalSymbolizer); 359 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 360 createAArch64Disassembler); 361 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 362 createAArch64ExternalSymbolizer); 363 } 364 365 static const unsigned FPR128DecoderTable[] = { 366 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 367 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 368 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 369 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 370 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 371 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 372 AArch64::Q30, AArch64::Q31 373 }; 374 375 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 376 uint64_t Addr, 377 const void *Decoder) { 378 if (RegNo > 31) 379 return Fail; 380 381 unsigned Register = FPR128DecoderTable[RegNo]; 382 Inst.addOperand(MCOperand::createReg(Register)); 383 return Success; 384 } 385 386 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 387 uint64_t Addr, 388 const void *Decoder) { 389 if (RegNo > 15) 390 return Fail; 391 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 392 } 393 394 static const unsigned FPR64DecoderTable[] = { 395 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 396 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 397 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 398 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 399 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 400 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 401 AArch64::D30, AArch64::D31 402 }; 403 404 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 405 uint64_t Addr, 406 const void *Decoder) { 407 if (RegNo > 31) 408 return Fail; 409 410 unsigned Register = FPR64DecoderTable[RegNo]; 411 Inst.addOperand(MCOperand::createReg(Register)); 412 return Success; 413 } 414 415 static const unsigned FPR32DecoderTable[] = { 416 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 417 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 418 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 419 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 420 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 421 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 422 AArch64::S30, AArch64::S31 423 }; 424 425 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 426 uint64_t Addr, 427 const void *Decoder) { 428 if (RegNo > 31) 429 return Fail; 430 431 unsigned Register = FPR32DecoderTable[RegNo]; 432 Inst.addOperand(MCOperand::createReg(Register)); 433 return Success; 434 } 435 436 static const unsigned FPR16DecoderTable[] = { 437 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 438 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 439 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 440 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 441 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 442 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 443 AArch64::H30, AArch64::H31 444 }; 445 446 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 447 uint64_t Addr, 448 const void *Decoder) { 449 if (RegNo > 31) 450 return Fail; 451 452 unsigned Register = FPR16DecoderTable[RegNo]; 453 Inst.addOperand(MCOperand::createReg(Register)); 454 return Success; 455 } 456 457 static const unsigned FPR8DecoderTable[] = { 458 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 459 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 460 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 461 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 462 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 463 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 464 AArch64::B30, AArch64::B31 465 }; 466 467 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 468 uint64_t Addr, 469 const void *Decoder) { 470 if (RegNo > 31) 471 return Fail; 472 473 unsigned Register = FPR8DecoderTable[RegNo]; 474 Inst.addOperand(MCOperand::createReg(Register)); 475 return Success; 476 } 477 478 static const unsigned GPR64DecoderTable[] = { 479 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 480 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 481 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 482 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 483 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 484 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 485 AArch64::LR, AArch64::XZR 486 }; 487 488 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 489 uint64_t Addr, 490 const void *Decoder) { 491 if (RegNo > 30) 492 return Fail; 493 494 unsigned Register = GPR64DecoderTable[RegNo]; 495 Inst.addOperand(MCOperand::createReg(Register)); 496 return Success; 497 } 498 499 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 500 uint64_t Addr, 501 const void *Decoder) { 502 if (RegNo > 31) 503 return Fail; 504 505 unsigned Register = GPR64DecoderTable[RegNo]; 506 Inst.addOperand(MCOperand::createReg(Register)); 507 return Success; 508 } 509 510 static const unsigned GPR64x8DecoderTable[] = { 511 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 512 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 513 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 514 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 515 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 516 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 517 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 518 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 519 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 520 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 521 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 522 AArch64::X22_X23_X24_X25_X26_X27_X28_FP, 523 }; 524 525 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 526 unsigned RegNo, 527 uint64_t Address, 528 const void *Decoder) { 529 if (RegNo > 22) 530 return Fail; 531 if (RegNo & 1) 532 return Fail; 533 534 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 535 Inst.addOperand(MCOperand::createReg(Register)); 536 return Success; 537 } 538 539 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 540 uint64_t Addr, 541 const void *Decoder) { 542 if (RegNo > 31) 543 return Fail; 544 unsigned Register = GPR64DecoderTable[RegNo]; 545 if (Register == AArch64::XZR) 546 Register = AArch64::SP; 547 Inst.addOperand(MCOperand::createReg(Register)); 548 return Success; 549 } 550 551 static const unsigned MatrixIndexGPR32_12_15DecoderTable[] = { 552 AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15 553 }; 554 555 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 556 unsigned RegNo, 557 uint64_t Addr, 558 const void *Decoder) { 559 if (RegNo > 3) 560 return Fail; 561 562 unsigned Register = MatrixIndexGPR32_12_15DecoderTable[RegNo]; 563 Inst.addOperand(MCOperand::createReg(Register)); 564 return Success; 565 } 566 567 static const unsigned GPR32DecoderTable[] = { 568 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 569 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 570 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 571 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 572 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 573 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 574 AArch64::W30, AArch64::WZR 575 }; 576 577 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 578 uint64_t Addr, 579 const void *Decoder) { 580 if (RegNo > 31) 581 return Fail; 582 583 unsigned Register = GPR32DecoderTable[RegNo]; 584 Inst.addOperand(MCOperand::createReg(Register)); 585 return Success; 586 } 587 588 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 589 uint64_t Addr, 590 const void *Decoder) { 591 if (RegNo > 31) 592 return Fail; 593 594 unsigned Register = GPR32DecoderTable[RegNo]; 595 if (Register == AArch64::WZR) 596 Register = AArch64::WSP; 597 Inst.addOperand(MCOperand::createReg(Register)); 598 return Success; 599 } 600 static const unsigned ZPRDecoderTable[] = { 601 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 602 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 603 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 604 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 605 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 606 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 607 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 608 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 609 }; 610 611 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 612 uint64_t Address, 613 const void* Decoder) { 614 if (RegNo > 31) 615 return Fail; 616 617 unsigned Register = ZPRDecoderTable[RegNo]; 618 Inst.addOperand(MCOperand::createReg(Register)); 619 return Success; 620 } 621 622 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 623 uint64_t Address, 624 const void *Decoder) { 625 if (RegNo > 15) 626 return Fail; 627 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 628 } 629 630 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 631 uint64_t Address, 632 const void *Decoder) { 633 if (RegNo > 7) 634 return Fail; 635 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 636 } 637 638 static const unsigned ZZDecoderTable[] = { 639 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 640 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 641 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 642 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 643 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 644 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 645 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 646 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 647 }; 648 649 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 650 uint64_t Address, 651 const void* Decoder) { 652 if (RegNo > 31) 653 return Fail; 654 unsigned Register = ZZDecoderTable[RegNo]; 655 Inst.addOperand(MCOperand::createReg(Register)); 656 return Success; 657 } 658 659 static const unsigned ZZZDecoderTable[] = { 660 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 661 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 662 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 663 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 664 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 665 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 666 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 667 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 668 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 669 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 670 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 671 }; 672 673 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 674 uint64_t Address, 675 const void* Decoder) { 676 if (RegNo > 31) 677 return Fail; 678 unsigned Register = ZZZDecoderTable[RegNo]; 679 Inst.addOperand(MCOperand::createReg(Register)); 680 return Success; 681 } 682 683 static const unsigned ZZZZDecoderTable[] = { 684 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 685 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 686 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 687 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 688 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 689 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 690 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 691 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 692 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 693 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 694 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 695 }; 696 697 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 698 uint64_t Address, 699 const void* Decoder) { 700 if (RegNo > 31) 701 return Fail; 702 unsigned Register = ZZZZDecoderTable[RegNo]; 703 Inst.addOperand(MCOperand::createReg(Register)); 704 return Success; 705 } 706 707 static const SmallVector<SmallVector<unsigned, 16>, 5> 708 MatrixZATileDecoderTable = { 709 {AArch64::ZAB0}, 710 {AArch64::ZAH0, AArch64::ZAH1}, 711 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 712 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 713 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 714 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 715 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 716 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 717 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 718 719 template <unsigned NumBitsForTile> 720 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 721 uint64_t Address, const void *Decoder) { 722 unsigned LastReg = (1 << NumBitsForTile) - 1; 723 if (RegNo > LastReg) 724 return Fail; 725 Inst.addOperand( 726 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 727 return Success; 728 } 729 730 static const unsigned PPRDecoderTable[] = { 731 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 732 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 733 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 734 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 735 }; 736 737 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 738 uint64_t Addr, const void *Decoder) { 739 if (RegNo > 15) 740 return Fail; 741 742 unsigned Register = PPRDecoderTable[RegNo]; 743 Inst.addOperand(MCOperand::createReg(Register)); 744 return Success; 745 } 746 747 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 748 uint64_t Addr, 749 const void* Decoder) { 750 if (RegNo > 7) 751 return Fail; 752 753 // Just reuse the PPR decode table 754 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 755 } 756 757 static const unsigned VectorDecoderTable[] = { 758 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 759 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 760 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 761 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 762 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 763 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 764 AArch64::Q30, AArch64::Q31 765 }; 766 767 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 768 uint64_t Addr, 769 const void *Decoder) { 770 if (RegNo > 31) 771 return Fail; 772 773 unsigned Register = VectorDecoderTable[RegNo]; 774 Inst.addOperand(MCOperand::createReg(Register)); 775 return Success; 776 } 777 778 static const unsigned QQDecoderTable[] = { 779 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 780 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 781 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 782 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 783 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 784 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 785 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 786 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 787 }; 788 789 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 790 uint64_t Addr, const void *Decoder) { 791 if (RegNo > 31) 792 return Fail; 793 unsigned Register = QQDecoderTable[RegNo]; 794 Inst.addOperand(MCOperand::createReg(Register)); 795 return Success; 796 } 797 798 static const unsigned QQQDecoderTable[] = { 799 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 800 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 801 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 802 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 803 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 804 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 805 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 806 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 807 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 808 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 809 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 810 }; 811 812 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 813 uint64_t Addr, const void *Decoder) { 814 if (RegNo > 31) 815 return Fail; 816 unsigned Register = QQQDecoderTable[RegNo]; 817 Inst.addOperand(MCOperand::createReg(Register)); 818 return Success; 819 } 820 821 static const unsigned QQQQDecoderTable[] = { 822 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 823 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 824 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 825 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 826 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 827 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 828 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 829 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 830 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 831 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 832 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 833 }; 834 835 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 836 uint64_t Addr, 837 const void *Decoder) { 838 if (RegNo > 31) 839 return Fail; 840 unsigned Register = QQQQDecoderTable[RegNo]; 841 Inst.addOperand(MCOperand::createReg(Register)); 842 return Success; 843 } 844 845 static const unsigned DDDecoderTable[] = { 846 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 847 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 848 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 849 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 850 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 851 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 852 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 853 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 854 }; 855 856 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 857 uint64_t Addr, const void *Decoder) { 858 if (RegNo > 31) 859 return Fail; 860 unsigned Register = DDDecoderTable[RegNo]; 861 Inst.addOperand(MCOperand::createReg(Register)); 862 return Success; 863 } 864 865 static const unsigned DDDDecoderTable[] = { 866 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 867 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 868 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 869 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 870 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 871 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 872 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 873 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 874 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 875 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 876 AArch64::D30_D31_D0, AArch64::D31_D0_D1 877 }; 878 879 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 880 uint64_t Addr, const void *Decoder) { 881 if (RegNo > 31) 882 return Fail; 883 unsigned Register = DDDDecoderTable[RegNo]; 884 Inst.addOperand(MCOperand::createReg(Register)); 885 return Success; 886 } 887 888 static const unsigned DDDDDecoderTable[] = { 889 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 890 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 891 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 892 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 893 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 894 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 895 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 896 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 897 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 898 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 899 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 900 }; 901 902 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 903 uint64_t Addr, 904 const void *Decoder) { 905 if (RegNo > 31) 906 return Fail; 907 unsigned Register = DDDDDecoderTable[RegNo]; 908 Inst.addOperand(MCOperand::createReg(Register)); 909 return Success; 910 } 911 912 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 913 uint64_t Addr, 914 const void *Decoder) { 915 // scale{5} is asserted as 1 in tblgen. 916 Imm |= 0x20; 917 Inst.addOperand(MCOperand::createImm(64 - Imm)); 918 return Success; 919 } 920 921 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 922 uint64_t Addr, 923 const void *Decoder) { 924 Inst.addOperand(MCOperand::createImm(64 - Imm)); 925 return Success; 926 } 927 928 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 929 uint64_t Addr, const void *Decoder) { 930 int64_t ImmVal = Imm; 931 const AArch64Disassembler *Dis = 932 static_cast<const AArch64Disassembler *>(Decoder); 933 934 // Sign-extend 19-bit immediate. 935 if (ImmVal & (1 << (19 - 1))) 936 ImmVal |= ~((1LL << 19) - 1); 937 938 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 939 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 940 Inst.addOperand(MCOperand::createImm(ImmVal)); 941 return Success; 942 } 943 944 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 945 uint64_t Address, const void *Decoder) { 946 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 947 Inst.addOperand(MCOperand::createImm(Imm & 1)); 948 return Success; 949 } 950 951 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 952 uint64_t Address, 953 const void *Decoder) { 954 Inst.addOperand(MCOperand::createImm(Imm)); 955 956 // Every system register in the encoding space is valid with the syntax 957 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 958 return Success; 959 } 960 961 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 962 uint64_t Address, 963 const void *Decoder) { 964 Inst.addOperand(MCOperand::createImm(Imm)); 965 966 return Success; 967 } 968 969 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 970 uint64_t Address, 971 const void *Decoder) { 972 // This decoder exists to add the dummy Lane operand to the MCInst, which must 973 // be 1 in assembly but has no other real manifestation. 974 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 975 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 976 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 977 978 if (IsToVec) { 979 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 980 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 981 } else { 982 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 983 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 984 } 985 986 // Add the lane 987 Inst.addOperand(MCOperand::createImm(1)); 988 989 return Success; 990 } 991 992 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 993 unsigned Add) { 994 Inst.addOperand(MCOperand::createImm(Add - Imm)); 995 return Success; 996 } 997 998 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 999 unsigned Add) { 1000 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 1001 return Success; 1002 } 1003 1004 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 1005 uint64_t Addr, const void *Decoder) { 1006 return DecodeVecShiftRImm(Inst, Imm, 64); 1007 } 1008 1009 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 1010 uint64_t Addr, 1011 const void *Decoder) { 1012 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 1013 } 1014 1015 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 1016 uint64_t Addr, const void *Decoder) { 1017 return DecodeVecShiftRImm(Inst, Imm, 32); 1018 } 1019 1020 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 1021 uint64_t Addr, 1022 const void *Decoder) { 1023 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 1024 } 1025 1026 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 1027 uint64_t Addr, const void *Decoder) { 1028 return DecodeVecShiftRImm(Inst, Imm, 16); 1029 } 1030 1031 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 1032 uint64_t Addr, 1033 const void *Decoder) { 1034 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 1035 } 1036 1037 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 1038 uint64_t Addr, const void *Decoder) { 1039 return DecodeVecShiftRImm(Inst, Imm, 8); 1040 } 1041 1042 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 1043 uint64_t Addr, const void *Decoder) { 1044 return DecodeVecShiftLImm(Inst, Imm, 64); 1045 } 1046 1047 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 1048 uint64_t Addr, const void *Decoder) { 1049 return DecodeVecShiftLImm(Inst, Imm, 32); 1050 } 1051 1052 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 1053 uint64_t Addr, const void *Decoder) { 1054 return DecodeVecShiftLImm(Inst, Imm, 16); 1055 } 1056 1057 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 1058 uint64_t Addr, const void *Decoder) { 1059 return DecodeVecShiftLImm(Inst, Imm, 8); 1060 } 1061 1062 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 1063 uint64_t Addr, 1064 const void *Decoder) { 1065 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1066 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1067 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1068 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 1069 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 1070 unsigned shift = (shiftHi << 6) | shiftLo; 1071 switch (Inst.getOpcode()) { 1072 default: 1073 return Fail; 1074 case AArch64::ADDWrs: 1075 case AArch64::ADDSWrs: 1076 case AArch64::SUBWrs: 1077 case AArch64::SUBSWrs: 1078 // if shift == '11' then ReservedValue() 1079 if (shiftHi == 0x3) 1080 return Fail; 1081 LLVM_FALLTHROUGH; 1082 case AArch64::ANDWrs: 1083 case AArch64::ANDSWrs: 1084 case AArch64::BICWrs: 1085 case AArch64::BICSWrs: 1086 case AArch64::ORRWrs: 1087 case AArch64::ORNWrs: 1088 case AArch64::EORWrs: 1089 case AArch64::EONWrs: { 1090 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1091 if (shiftLo >> 5 == 1) 1092 return Fail; 1093 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1094 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1095 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1096 break; 1097 } 1098 case AArch64::ADDXrs: 1099 case AArch64::ADDSXrs: 1100 case AArch64::SUBXrs: 1101 case AArch64::SUBSXrs: 1102 // if shift == '11' then ReservedValue() 1103 if (shiftHi == 0x3) 1104 return Fail; 1105 LLVM_FALLTHROUGH; 1106 case AArch64::ANDXrs: 1107 case AArch64::ANDSXrs: 1108 case AArch64::BICXrs: 1109 case AArch64::BICSXrs: 1110 case AArch64::ORRXrs: 1111 case AArch64::ORNXrs: 1112 case AArch64::EORXrs: 1113 case AArch64::EONXrs: 1114 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1115 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1116 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1117 break; 1118 } 1119 1120 Inst.addOperand(MCOperand::createImm(shift)); 1121 return Success; 1122 } 1123 1124 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1125 uint64_t Addr, 1126 const void *Decoder) { 1127 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1128 unsigned imm = fieldFromInstruction(insn, 5, 16); 1129 unsigned shift = fieldFromInstruction(insn, 21, 2); 1130 shift <<= 4; 1131 switch (Inst.getOpcode()) { 1132 default: 1133 return Fail; 1134 case AArch64::MOVZWi: 1135 case AArch64::MOVNWi: 1136 case AArch64::MOVKWi: 1137 if (shift & (1U << 5)) 1138 return Fail; 1139 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1140 break; 1141 case AArch64::MOVZXi: 1142 case AArch64::MOVNXi: 1143 case AArch64::MOVKXi: 1144 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1145 break; 1146 } 1147 1148 if (Inst.getOpcode() == AArch64::MOVKWi || 1149 Inst.getOpcode() == AArch64::MOVKXi) 1150 Inst.addOperand(Inst.getOperand(0)); 1151 1152 Inst.addOperand(MCOperand::createImm(imm)); 1153 Inst.addOperand(MCOperand::createImm(shift)); 1154 return Success; 1155 } 1156 1157 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1158 uint64_t Addr, 1159 const void *Decoder) { 1160 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1161 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1162 unsigned offset = fieldFromInstruction(insn, 10, 12); 1163 const AArch64Disassembler *Dis = 1164 static_cast<const AArch64Disassembler *>(Decoder); 1165 1166 switch (Inst.getOpcode()) { 1167 default: 1168 return Fail; 1169 case AArch64::PRFMui: 1170 // Rt is an immediate in prefetch. 1171 Inst.addOperand(MCOperand::createImm(Rt)); 1172 break; 1173 case AArch64::STRBBui: 1174 case AArch64::LDRBBui: 1175 case AArch64::LDRSBWui: 1176 case AArch64::STRHHui: 1177 case AArch64::LDRHHui: 1178 case AArch64::LDRSHWui: 1179 case AArch64::STRWui: 1180 case AArch64::LDRWui: 1181 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1182 break; 1183 case AArch64::LDRSBXui: 1184 case AArch64::LDRSHXui: 1185 case AArch64::LDRSWui: 1186 case AArch64::STRXui: 1187 case AArch64::LDRXui: 1188 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1189 break; 1190 case AArch64::LDRQui: 1191 case AArch64::STRQui: 1192 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1193 break; 1194 case AArch64::LDRDui: 1195 case AArch64::STRDui: 1196 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1197 break; 1198 case AArch64::LDRSui: 1199 case AArch64::STRSui: 1200 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1201 break; 1202 case AArch64::LDRHui: 1203 case AArch64::STRHui: 1204 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1205 break; 1206 case AArch64::LDRBui: 1207 case AArch64::STRBui: 1208 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1209 break; 1210 } 1211 1212 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1213 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1214 Inst.addOperand(MCOperand::createImm(offset)); 1215 return Success; 1216 } 1217 1218 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1219 uint64_t Addr, 1220 const void *Decoder) { 1221 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1222 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1223 int64_t offset = fieldFromInstruction(insn, 12, 9); 1224 1225 // offset is a 9-bit signed immediate, so sign extend it to 1226 // fill the unsigned. 1227 if (offset & (1 << (9 - 1))) 1228 offset |= ~((1LL << 9) - 1); 1229 1230 // First operand is always the writeback to the address register, if needed. 1231 switch (Inst.getOpcode()) { 1232 default: 1233 break; 1234 case AArch64::LDRSBWpre: 1235 case AArch64::LDRSHWpre: 1236 case AArch64::STRBBpre: 1237 case AArch64::LDRBBpre: 1238 case AArch64::STRHHpre: 1239 case AArch64::LDRHHpre: 1240 case AArch64::STRWpre: 1241 case AArch64::LDRWpre: 1242 case AArch64::LDRSBWpost: 1243 case AArch64::LDRSHWpost: 1244 case AArch64::STRBBpost: 1245 case AArch64::LDRBBpost: 1246 case AArch64::STRHHpost: 1247 case AArch64::LDRHHpost: 1248 case AArch64::STRWpost: 1249 case AArch64::LDRWpost: 1250 case AArch64::LDRSBXpre: 1251 case AArch64::LDRSHXpre: 1252 case AArch64::STRXpre: 1253 case AArch64::LDRSWpre: 1254 case AArch64::LDRXpre: 1255 case AArch64::LDRSBXpost: 1256 case AArch64::LDRSHXpost: 1257 case AArch64::STRXpost: 1258 case AArch64::LDRSWpost: 1259 case AArch64::LDRXpost: 1260 case AArch64::LDRQpre: 1261 case AArch64::STRQpre: 1262 case AArch64::LDRQpost: 1263 case AArch64::STRQpost: 1264 case AArch64::LDRDpre: 1265 case AArch64::STRDpre: 1266 case AArch64::LDRDpost: 1267 case AArch64::STRDpost: 1268 case AArch64::LDRSpre: 1269 case AArch64::STRSpre: 1270 case AArch64::LDRSpost: 1271 case AArch64::STRSpost: 1272 case AArch64::LDRHpre: 1273 case AArch64::STRHpre: 1274 case AArch64::LDRHpost: 1275 case AArch64::STRHpost: 1276 case AArch64::LDRBpre: 1277 case AArch64::STRBpre: 1278 case AArch64::LDRBpost: 1279 case AArch64::STRBpost: 1280 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1281 break; 1282 } 1283 1284 switch (Inst.getOpcode()) { 1285 default: 1286 return Fail; 1287 case AArch64::PRFUMi: 1288 // Rt is an immediate in prefetch. 1289 Inst.addOperand(MCOperand::createImm(Rt)); 1290 break; 1291 case AArch64::STURBBi: 1292 case AArch64::LDURBBi: 1293 case AArch64::LDURSBWi: 1294 case AArch64::STURHHi: 1295 case AArch64::LDURHHi: 1296 case AArch64::LDURSHWi: 1297 case AArch64::STURWi: 1298 case AArch64::LDURWi: 1299 case AArch64::LDTRSBWi: 1300 case AArch64::LDTRSHWi: 1301 case AArch64::STTRWi: 1302 case AArch64::LDTRWi: 1303 case AArch64::STTRHi: 1304 case AArch64::LDTRHi: 1305 case AArch64::LDTRBi: 1306 case AArch64::STTRBi: 1307 case AArch64::LDRSBWpre: 1308 case AArch64::LDRSHWpre: 1309 case AArch64::STRBBpre: 1310 case AArch64::LDRBBpre: 1311 case AArch64::STRHHpre: 1312 case AArch64::LDRHHpre: 1313 case AArch64::STRWpre: 1314 case AArch64::LDRWpre: 1315 case AArch64::LDRSBWpost: 1316 case AArch64::LDRSHWpost: 1317 case AArch64::STRBBpost: 1318 case AArch64::LDRBBpost: 1319 case AArch64::STRHHpost: 1320 case AArch64::LDRHHpost: 1321 case AArch64::STRWpost: 1322 case AArch64::LDRWpost: 1323 case AArch64::STLURBi: 1324 case AArch64::STLURHi: 1325 case AArch64::STLURWi: 1326 case AArch64::LDAPURBi: 1327 case AArch64::LDAPURSBWi: 1328 case AArch64::LDAPURHi: 1329 case AArch64::LDAPURSHWi: 1330 case AArch64::LDAPURi: 1331 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1332 break; 1333 case AArch64::LDURSBXi: 1334 case AArch64::LDURSHXi: 1335 case AArch64::LDURSWi: 1336 case AArch64::STURXi: 1337 case AArch64::LDURXi: 1338 case AArch64::LDTRSBXi: 1339 case AArch64::LDTRSHXi: 1340 case AArch64::LDTRSWi: 1341 case AArch64::STTRXi: 1342 case AArch64::LDTRXi: 1343 case AArch64::LDRSBXpre: 1344 case AArch64::LDRSHXpre: 1345 case AArch64::STRXpre: 1346 case AArch64::LDRSWpre: 1347 case AArch64::LDRXpre: 1348 case AArch64::LDRSBXpost: 1349 case AArch64::LDRSHXpost: 1350 case AArch64::STRXpost: 1351 case AArch64::LDRSWpost: 1352 case AArch64::LDRXpost: 1353 case AArch64::LDAPURSWi: 1354 case AArch64::LDAPURSHXi: 1355 case AArch64::LDAPURSBXi: 1356 case AArch64::STLURXi: 1357 case AArch64::LDAPURXi: 1358 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1359 break; 1360 case AArch64::LDURQi: 1361 case AArch64::STURQi: 1362 case AArch64::LDRQpre: 1363 case AArch64::STRQpre: 1364 case AArch64::LDRQpost: 1365 case AArch64::STRQpost: 1366 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1367 break; 1368 case AArch64::LDURDi: 1369 case AArch64::STURDi: 1370 case AArch64::LDRDpre: 1371 case AArch64::STRDpre: 1372 case AArch64::LDRDpost: 1373 case AArch64::STRDpost: 1374 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1375 break; 1376 case AArch64::LDURSi: 1377 case AArch64::STURSi: 1378 case AArch64::LDRSpre: 1379 case AArch64::STRSpre: 1380 case AArch64::LDRSpost: 1381 case AArch64::STRSpost: 1382 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1383 break; 1384 case AArch64::LDURHi: 1385 case AArch64::STURHi: 1386 case AArch64::LDRHpre: 1387 case AArch64::STRHpre: 1388 case AArch64::LDRHpost: 1389 case AArch64::STRHpost: 1390 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1391 break; 1392 case AArch64::LDURBi: 1393 case AArch64::STURBi: 1394 case AArch64::LDRBpre: 1395 case AArch64::STRBpre: 1396 case AArch64::LDRBpost: 1397 case AArch64::STRBpost: 1398 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1399 break; 1400 } 1401 1402 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1403 Inst.addOperand(MCOperand::createImm(offset)); 1404 1405 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1406 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1407 bool IsFP = fieldFromInstruction(insn, 26, 1); 1408 1409 // Cannot write back to a transfer register (but xzr != sp). 1410 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1411 return SoftFail; 1412 1413 return Success; 1414 } 1415 1416 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1417 uint64_t Addr, 1418 const void *Decoder) { 1419 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1420 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1421 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1422 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1423 1424 unsigned Opcode = Inst.getOpcode(); 1425 switch (Opcode) { 1426 default: 1427 return Fail; 1428 case AArch64::STLXRW: 1429 case AArch64::STLXRB: 1430 case AArch64::STLXRH: 1431 case AArch64::STXRW: 1432 case AArch64::STXRB: 1433 case AArch64::STXRH: 1434 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1435 LLVM_FALLTHROUGH; 1436 case AArch64::LDARW: 1437 case AArch64::LDARB: 1438 case AArch64::LDARH: 1439 case AArch64::LDAXRW: 1440 case AArch64::LDAXRB: 1441 case AArch64::LDAXRH: 1442 case AArch64::LDXRW: 1443 case AArch64::LDXRB: 1444 case AArch64::LDXRH: 1445 case AArch64::STLRW: 1446 case AArch64::STLRB: 1447 case AArch64::STLRH: 1448 case AArch64::STLLRW: 1449 case AArch64::STLLRB: 1450 case AArch64::STLLRH: 1451 case AArch64::LDLARW: 1452 case AArch64::LDLARB: 1453 case AArch64::LDLARH: 1454 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1455 break; 1456 case AArch64::STLXRX: 1457 case AArch64::STXRX: 1458 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1459 LLVM_FALLTHROUGH; 1460 case AArch64::LDARX: 1461 case AArch64::LDAXRX: 1462 case AArch64::LDXRX: 1463 case AArch64::STLRX: 1464 case AArch64::LDLARX: 1465 case AArch64::STLLRX: 1466 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1467 break; 1468 case AArch64::STLXPW: 1469 case AArch64::STXPW: 1470 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1471 LLVM_FALLTHROUGH; 1472 case AArch64::LDAXPW: 1473 case AArch64::LDXPW: 1474 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1475 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1476 break; 1477 case AArch64::STLXPX: 1478 case AArch64::STXPX: 1479 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1480 LLVM_FALLTHROUGH; 1481 case AArch64::LDAXPX: 1482 case AArch64::LDXPX: 1483 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1484 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1485 break; 1486 } 1487 1488 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1489 1490 // You shouldn't load to the same register twice in an instruction... 1491 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1492 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1493 Rt == Rt2) 1494 return SoftFail; 1495 1496 return Success; 1497 } 1498 1499 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1500 uint64_t Addr, 1501 const void *Decoder) { 1502 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1503 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1504 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1505 int64_t offset = fieldFromInstruction(insn, 15, 7); 1506 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1507 1508 // offset is a 7-bit signed immediate, so sign extend it to 1509 // fill the unsigned. 1510 if (offset & (1 << (7 - 1))) 1511 offset |= ~((1LL << 7) - 1); 1512 1513 unsigned Opcode = Inst.getOpcode(); 1514 bool NeedsDisjointWritebackTransfer = false; 1515 1516 // First operand is always writeback of base register. 1517 switch (Opcode) { 1518 default: 1519 break; 1520 case AArch64::LDPXpost: 1521 case AArch64::STPXpost: 1522 case AArch64::LDPSWpost: 1523 case AArch64::LDPXpre: 1524 case AArch64::STPXpre: 1525 case AArch64::LDPSWpre: 1526 case AArch64::LDPWpost: 1527 case AArch64::STPWpost: 1528 case AArch64::LDPWpre: 1529 case AArch64::STPWpre: 1530 case AArch64::LDPQpost: 1531 case AArch64::STPQpost: 1532 case AArch64::LDPQpre: 1533 case AArch64::STPQpre: 1534 case AArch64::LDPDpost: 1535 case AArch64::STPDpost: 1536 case AArch64::LDPDpre: 1537 case AArch64::STPDpre: 1538 case AArch64::LDPSpost: 1539 case AArch64::STPSpost: 1540 case AArch64::LDPSpre: 1541 case AArch64::STPSpre: 1542 case AArch64::STGPpre: 1543 case AArch64::STGPpost: 1544 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1545 break; 1546 } 1547 1548 switch (Opcode) { 1549 default: 1550 return Fail; 1551 case AArch64::LDPXpost: 1552 case AArch64::STPXpost: 1553 case AArch64::LDPSWpost: 1554 case AArch64::LDPXpre: 1555 case AArch64::STPXpre: 1556 case AArch64::LDPSWpre: 1557 case AArch64::STGPpre: 1558 case AArch64::STGPpost: 1559 NeedsDisjointWritebackTransfer = true; 1560 LLVM_FALLTHROUGH; 1561 case AArch64::LDNPXi: 1562 case AArch64::STNPXi: 1563 case AArch64::LDPXi: 1564 case AArch64::STPXi: 1565 case AArch64::LDPSWi: 1566 case AArch64::STGPi: 1567 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1568 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1569 break; 1570 case AArch64::LDPWpost: 1571 case AArch64::STPWpost: 1572 case AArch64::LDPWpre: 1573 case AArch64::STPWpre: 1574 NeedsDisjointWritebackTransfer = true; 1575 LLVM_FALLTHROUGH; 1576 case AArch64::LDNPWi: 1577 case AArch64::STNPWi: 1578 case AArch64::LDPWi: 1579 case AArch64::STPWi: 1580 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1581 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1582 break; 1583 case AArch64::LDNPQi: 1584 case AArch64::STNPQi: 1585 case AArch64::LDPQpost: 1586 case AArch64::STPQpost: 1587 case AArch64::LDPQi: 1588 case AArch64::STPQi: 1589 case AArch64::LDPQpre: 1590 case AArch64::STPQpre: 1591 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1592 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1593 break; 1594 case AArch64::LDNPDi: 1595 case AArch64::STNPDi: 1596 case AArch64::LDPDpost: 1597 case AArch64::STPDpost: 1598 case AArch64::LDPDi: 1599 case AArch64::STPDi: 1600 case AArch64::LDPDpre: 1601 case AArch64::STPDpre: 1602 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1603 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1604 break; 1605 case AArch64::LDNPSi: 1606 case AArch64::STNPSi: 1607 case AArch64::LDPSpost: 1608 case AArch64::STPSpost: 1609 case AArch64::LDPSi: 1610 case AArch64::STPSi: 1611 case AArch64::LDPSpre: 1612 case AArch64::STPSpre: 1613 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1614 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1615 break; 1616 } 1617 1618 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1619 Inst.addOperand(MCOperand::createImm(offset)); 1620 1621 // You shouldn't load to the same register twice in an instruction... 1622 if (IsLoad && Rt == Rt2) 1623 return SoftFail; 1624 1625 // ... or do any operation that writes-back to a transfer register. But note 1626 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1627 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1628 return SoftFail; 1629 1630 return Success; 1631 } 1632 1633 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1634 uint64_t Addr, 1635 const void *Decoder) { 1636 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1637 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1638 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1639 fieldFromInstruction(insn, 12, 9); 1640 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1641 1642 switch (Inst.getOpcode()) { 1643 default: 1644 return Fail; 1645 case AArch64::LDRAAwriteback: 1646 case AArch64::LDRABwriteback: 1647 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1648 Decoder); 1649 break; 1650 case AArch64::LDRAAindexed: 1651 case AArch64::LDRABindexed: 1652 break; 1653 } 1654 1655 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1656 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1657 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1658 1659 if (writeback && Rt == Rn && Rn != 31) { 1660 return SoftFail; 1661 } 1662 1663 return Success; 1664 } 1665 1666 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1667 uint64_t Addr, 1668 const void *Decoder) { 1669 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1670 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1671 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1672 unsigned extend = fieldFromInstruction(insn, 10, 6); 1673 1674 unsigned shift = extend & 0x7; 1675 if (shift > 4) 1676 return Fail; 1677 1678 switch (Inst.getOpcode()) { 1679 default: 1680 return Fail; 1681 case AArch64::ADDWrx: 1682 case AArch64::SUBWrx: 1683 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1684 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1685 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1686 break; 1687 case AArch64::ADDSWrx: 1688 case AArch64::SUBSWrx: 1689 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1690 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1691 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1692 break; 1693 case AArch64::ADDXrx: 1694 case AArch64::SUBXrx: 1695 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1696 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1697 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1698 break; 1699 case AArch64::ADDSXrx: 1700 case AArch64::SUBSXrx: 1701 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1702 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1703 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1704 break; 1705 case AArch64::ADDXrx64: 1706 case AArch64::SUBXrx64: 1707 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1708 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1709 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1710 break; 1711 case AArch64::SUBSXrx64: 1712 case AArch64::ADDSXrx64: 1713 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1714 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1715 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1716 break; 1717 } 1718 1719 Inst.addOperand(MCOperand::createImm(extend)); 1720 return Success; 1721 } 1722 1723 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1724 uint64_t Addr, 1725 const void *Decoder) { 1726 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1727 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1728 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1729 unsigned imm; 1730 1731 if (Datasize) { 1732 if (Inst.getOpcode() == AArch64::ANDSXri) 1733 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1734 else 1735 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1736 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1737 imm = fieldFromInstruction(insn, 10, 13); 1738 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1739 return Fail; 1740 } else { 1741 if (Inst.getOpcode() == AArch64::ANDSWri) 1742 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1743 else 1744 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1745 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1746 imm = fieldFromInstruction(insn, 10, 12); 1747 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1748 return Fail; 1749 } 1750 Inst.addOperand(MCOperand::createImm(imm)); 1751 return Success; 1752 } 1753 1754 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1755 uint64_t Addr, 1756 const void *Decoder) { 1757 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1758 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1759 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1760 imm |= fieldFromInstruction(insn, 5, 5); 1761 1762 if (Inst.getOpcode() == AArch64::MOVID) 1763 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1764 else 1765 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1766 1767 Inst.addOperand(MCOperand::createImm(imm)); 1768 1769 switch (Inst.getOpcode()) { 1770 default: 1771 break; 1772 case AArch64::MOVIv4i16: 1773 case AArch64::MOVIv8i16: 1774 case AArch64::MVNIv4i16: 1775 case AArch64::MVNIv8i16: 1776 case AArch64::MOVIv2i32: 1777 case AArch64::MOVIv4i32: 1778 case AArch64::MVNIv2i32: 1779 case AArch64::MVNIv4i32: 1780 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1781 break; 1782 case AArch64::MOVIv2s_msl: 1783 case AArch64::MOVIv4s_msl: 1784 case AArch64::MVNIv2s_msl: 1785 case AArch64::MVNIv4s_msl: 1786 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1787 break; 1788 } 1789 1790 return Success; 1791 } 1792 1793 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1794 uint64_t Addr, 1795 const void *Decoder) { 1796 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1797 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1798 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1799 imm |= fieldFromInstruction(insn, 5, 5); 1800 1801 // Tied operands added twice. 1802 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1803 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1804 1805 Inst.addOperand(MCOperand::createImm(imm)); 1806 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1807 1808 return Success; 1809 } 1810 1811 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1812 uint64_t Addr, const void *Decoder) { 1813 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1814 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1815 imm |= fieldFromInstruction(insn, 29, 2); 1816 const AArch64Disassembler *Dis = 1817 static_cast<const AArch64Disassembler *>(Decoder); 1818 1819 // Sign-extend the 21-bit immediate. 1820 if (imm & (1 << (21 - 1))) 1821 imm |= ~((1LL << 21) - 1); 1822 1823 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1824 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1825 Inst.addOperand(MCOperand::createImm(imm)); 1826 1827 return Success; 1828 } 1829 1830 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1831 uint64_t Addr, const void *Decoder) { 1832 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1833 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1834 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1835 unsigned S = fieldFromInstruction(insn, 29, 1); 1836 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1837 1838 unsigned ShifterVal = (Imm >> 12) & 3; 1839 unsigned ImmVal = Imm & 0xFFF; 1840 const AArch64Disassembler *Dis = 1841 static_cast<const AArch64Disassembler *>(Decoder); 1842 1843 if (ShifterVal != 0 && ShifterVal != 1) 1844 return Fail; 1845 1846 if (Datasize) { 1847 if (Rd == 31 && !S) 1848 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1849 else 1850 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1851 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1852 } else { 1853 if (Rd == 31 && !S) 1854 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1855 else 1856 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1857 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1858 } 1859 1860 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1861 Inst.addOperand(MCOperand::createImm(ImmVal)); 1862 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1863 return Success; 1864 } 1865 1866 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1867 uint64_t Addr, 1868 const void *Decoder) { 1869 int64_t imm = fieldFromInstruction(insn, 0, 26); 1870 const AArch64Disassembler *Dis = 1871 static_cast<const AArch64Disassembler *>(Decoder); 1872 1873 // Sign-extend the 26-bit immediate. 1874 if (imm & (1 << (26 - 1))) 1875 imm |= ~((1LL << 26) - 1); 1876 1877 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1878 Inst.addOperand(MCOperand::createImm(imm)); 1879 1880 return Success; 1881 } 1882 1883 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1884 uint64_t Addr, 1885 const void *Decoder) { 1886 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1887 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1888 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1889 uint64_t pstate_field = (op1 << 3) | op2; 1890 1891 switch (pstate_field) { 1892 case 0x01: // XAFlag 1893 case 0x02: // AXFlag 1894 return Fail; 1895 } 1896 1897 if ((pstate_field == AArch64PState::PAN || 1898 pstate_field == AArch64PState::UAO || 1899 pstate_field == AArch64PState::SSBS) && crm > 1) 1900 return Fail; 1901 1902 Inst.addOperand(MCOperand::createImm(pstate_field)); 1903 Inst.addOperand(MCOperand::createImm(crm)); 1904 1905 const AArch64Disassembler *Dis = 1906 static_cast<const AArch64Disassembler *>(Decoder); 1907 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1908 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1909 return Success; 1910 return Fail; 1911 } 1912 1913 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1914 uint64_t Addr, const void *Decoder) { 1915 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1916 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1917 bit |= fieldFromInstruction(insn, 19, 5); 1918 int64_t dst = fieldFromInstruction(insn, 5, 14); 1919 const AArch64Disassembler *Dis = 1920 static_cast<const AArch64Disassembler *>(Decoder); 1921 1922 // Sign-extend 14-bit immediate. 1923 if (dst & (1 << (14 - 1))) 1924 dst |= ~((1LL << 14) - 1); 1925 1926 if (fieldFromInstruction(insn, 31, 1) == 0) 1927 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1928 else 1929 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1930 Inst.addOperand(MCOperand::createImm(bit)); 1931 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1932 Inst.addOperand(MCOperand::createImm(dst)); 1933 1934 return Success; 1935 } 1936 1937 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1938 unsigned RegClassID, 1939 unsigned RegNo, 1940 uint64_t Addr, 1941 const void *Decoder) { 1942 // Register number must be even (see CASP instruction) 1943 if (RegNo & 0x1) 1944 return Fail; 1945 1946 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1947 Inst.addOperand(MCOperand::createReg(Reg)); 1948 return Success; 1949 } 1950 1951 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1952 unsigned RegNo, 1953 uint64_t Addr, 1954 const void *Decoder) { 1955 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1956 AArch64::WSeqPairsClassRegClassID, 1957 RegNo, Addr, Decoder); 1958 } 1959 1960 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1961 unsigned RegNo, 1962 uint64_t Addr, 1963 const void *Decoder) { 1964 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1965 AArch64::XSeqPairsClassRegClassID, 1966 RegNo, Addr, Decoder); 1967 } 1968 1969 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1970 uint32_t insn, 1971 uint64_t Addr, 1972 const void *Decoder) { 1973 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1974 unsigned imm = fieldFromInstruction(insn, 5, 13); 1975 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1976 return Fail; 1977 1978 // The same (tied) operand is added twice to the instruction. 1979 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1980 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1981 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1982 Inst.addOperand(MCOperand::createImm(imm)); 1983 return Success; 1984 } 1985 1986 template<int Bits> 1987 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1988 uint64_t Address, const void *Decoder) { 1989 if (Imm & ~((1LL << Bits) - 1)) 1990 return Fail; 1991 1992 // Imm is a signed immediate, so sign extend it. 1993 if (Imm & (1 << (Bits - 1))) 1994 Imm |= ~((1LL << Bits) - 1); 1995 1996 Inst.addOperand(MCOperand::createImm(Imm)); 1997 return Success; 1998 } 1999 2000 // Decode 8-bit signed/unsigned immediate for a given element width. 2001 template <int ElementWidth> 2002 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 2003 uint64_t Addr, const void *Decoder) { 2004 unsigned Val = (uint8_t)Imm; 2005 unsigned Shift = (Imm & 0x100) ? 8 : 0; 2006 if (ElementWidth == 8 && Shift) 2007 return Fail; 2008 Inst.addOperand(MCOperand::createImm(Val)); 2009 Inst.addOperand(MCOperand::createImm(Shift)); 2010 return Success; 2011 } 2012 2013 // Decode uimm4 ranged from 1-16. 2014 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 2015 uint64_t Addr, const void *Decoder) { 2016 Inst.addOperand(MCOperand::createImm(Imm + 1)); 2017 return Success; 2018 } 2019 2020 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 2021 const void *Decoder) { 2022 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 2023 Inst.addOperand(MCOperand::createImm(Imm)); 2024 return Success; 2025 } 2026 return Fail; 2027 } 2028