1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 80 unsigned RegNo, uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 template <unsigned NumBitsForTile> 119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 122 unsigned RegMask, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 133 uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 162 uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 168 uint64_t Address, 169 const void *Decoder); 170 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 171 uint64_t Address, 172 const void *Decoder); 173 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 174 uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 177 uint64_t Address, 178 const void *Decoder); 179 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 184 uint64_t Address, 185 const void *Decoder); 186 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 187 uint64_t Address, 188 const void *Decoder); 189 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 190 uint64_t Address, const void *Decoder); 191 192 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 193 uint64_t Address, 194 const void *Decoder); 195 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, const void *Decoder); 197 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 198 uint64_t Addr, 199 const void *Decoder); 200 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 201 uint64_t Addr, const void *Decoder); 202 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const void *Decoder); 205 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, const void *Decoder); 207 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 208 uint64_t Addr, 209 const void *Decoder); 210 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, const void *Decoder); 214 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, const void *Decoder); 216 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, const void *Decoder); 218 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 219 uint64_t Addr, const void *Decoder); 220 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Addr, 223 const void *Decoder); 224 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 225 unsigned RegNo, 226 uint64_t Addr, 227 const void *Decoder); 228 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, 229 uint64_t Address, 230 const void *Decoder); 231 template <int Bits> 232 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 233 const void *Decoder); 234 template <int ElementWidth> 235 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 236 uint64_t Addr, const void *Decoder); 237 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 238 uint64_t Addr, const void *Decoder); 239 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 240 const void *Decoder); 241 242 static bool Check(DecodeStatus &Out, DecodeStatus In) { 243 switch (In) { 244 case MCDisassembler::Success: 245 // Out stays the same. 246 return true; 247 case MCDisassembler::SoftFail: 248 Out = In; 249 return true; 250 case MCDisassembler::Fail: 251 Out = In; 252 return false; 253 } 254 llvm_unreachable("Invalid DecodeStatus!"); 255 } 256 257 #include "AArch64GenDisassemblerTables.inc" 258 #include "AArch64GenInstrInfo.inc" 259 260 #define Success MCDisassembler::Success 261 #define Fail MCDisassembler::Fail 262 #define SoftFail MCDisassembler::SoftFail 263 264 static MCDisassembler *createAArch64Disassembler(const Target &T, 265 const MCSubtargetInfo &STI, 266 MCContext &Ctx) { 267 return new AArch64Disassembler(STI, Ctx); 268 } 269 270 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 271 ArrayRef<uint8_t> Bytes, 272 uint64_t Address, 273 raw_ostream &CS) const { 274 CommentStream = &CS; 275 276 Size = 0; 277 // We want to read exactly 4 bytes of data. 278 if (Bytes.size() < 4) 279 return Fail; 280 Size = 4; 281 282 // Encoded as a small-endian 32-bit word in the stream. 283 uint32_t Insn = 284 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 285 286 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 287 288 for (auto Table : Tables) { 289 DecodeStatus Result = 290 decodeInstruction(Table, MI, Insn, Address, this, STI); 291 292 switch (MI.getOpcode()) { 293 default: 294 break; 295 // For Scalable Matrix Extension (SME) instructions that have an implicit 296 // operand for the accumulator (ZA) which isn't encoded, manually insert 297 // operand. 298 case AArch64::LDR_ZA: 299 case AArch64::STR_ZA: { 300 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA)); 301 // Spill and fill instructions have a single immediate used for both the 302 // vector select offset and optional memory offset. Replicate the decoded 303 // immediate. 304 const MCOperand &Imm4Op = MI.getOperand(2); 305 assert(Imm4Op.isImm() && "Unexpected operand type!"); 306 MI.addOperand(Imm4Op); 307 break; 308 } 309 case AArch64::LD1_MXIPXX_H_B: 310 case AArch64::LD1_MXIPXX_V_B: 311 case AArch64::ST1_MXIPXX_H_B: 312 case AArch64::ST1_MXIPXX_V_B: 313 case AArch64::INSERT_MXIPZ_H_B: 314 case AArch64::INSERT_MXIPZ_V_B: 315 // e.g. 316 // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B 317 // ^ insert implicit 8-bit element tile 318 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 319 break; 320 case AArch64::EXTRACT_ZPMXI_H_B: 321 case AArch64::EXTRACT_ZPMXI_V_B: 322 // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>] 323 // ^ insert implicit 8-bit element tile 324 MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0)); 325 break; 326 } 327 328 if (Result != MCDisassembler::Fail) 329 return Result; 330 } 331 332 return MCDisassembler::Fail; 333 } 334 335 static MCSymbolizer * 336 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 337 LLVMSymbolLookupCallback SymbolLookUp, 338 void *DisInfo, MCContext *Ctx, 339 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 340 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 341 SymbolLookUp, DisInfo); 342 } 343 344 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 345 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 346 createAArch64Disassembler); 347 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 348 createAArch64Disassembler); 349 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 350 createAArch64ExternalSymbolizer); 351 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 352 createAArch64ExternalSymbolizer); 353 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 354 createAArch64Disassembler); 355 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 356 createAArch64ExternalSymbolizer); 357 358 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 359 createAArch64Disassembler); 360 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 361 createAArch64ExternalSymbolizer); 362 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 363 createAArch64Disassembler); 364 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 365 createAArch64ExternalSymbolizer); 366 } 367 368 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 369 uint64_t Addr, 370 const void *Decoder) { 371 if (RegNo > 31) 372 return Fail; 373 374 unsigned Register = 375 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo); 376 Inst.addOperand(MCOperand::createReg(Register)); 377 return Success; 378 } 379 380 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 381 uint64_t Addr, 382 const void *Decoder) { 383 if (RegNo > 15) 384 return Fail; 385 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 386 } 387 388 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 389 uint64_t Addr, 390 const void *Decoder) { 391 if (RegNo > 31) 392 return Fail; 393 394 unsigned Register = 395 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo); 396 Inst.addOperand(MCOperand::createReg(Register)); 397 return Success; 398 } 399 400 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 401 uint64_t Addr, 402 const void *Decoder) { 403 if (RegNo > 31) 404 return Fail; 405 406 unsigned Register = 407 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo); 408 Inst.addOperand(MCOperand::createReg(Register)); 409 return Success; 410 } 411 412 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 413 uint64_t Addr, 414 const void *Decoder) { 415 if (RegNo > 31) 416 return Fail; 417 418 unsigned Register = 419 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo); 420 Inst.addOperand(MCOperand::createReg(Register)); 421 return Success; 422 } 423 424 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 425 uint64_t Addr, 426 const void *Decoder) { 427 if (RegNo > 31) 428 return Fail; 429 430 unsigned Register = 431 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo); 432 Inst.addOperand(MCOperand::createReg(Register)); 433 return Success; 434 } 435 436 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 437 uint64_t Addr, 438 const void *Decoder) { 439 if (RegNo > 30) 440 return Fail; 441 442 unsigned Register = 443 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister( 444 RegNo); 445 Inst.addOperand(MCOperand::createReg(Register)); 446 return Success; 447 } 448 449 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 450 uint64_t Addr, 451 const void *Decoder) { 452 if (RegNo > 31) 453 return Fail; 454 455 unsigned Register = 456 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo); 457 Inst.addOperand(MCOperand::createReg(Register)); 458 return Success; 459 } 460 461 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 462 unsigned RegNo, 463 uint64_t Address, 464 const void *Decoder) { 465 if (RegNo > 22) 466 return Fail; 467 if (RegNo & 1) 468 return Fail; 469 470 unsigned Register = 471 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister( 472 RegNo >> 1); 473 Inst.addOperand(MCOperand::createReg(Register)); 474 return Success; 475 } 476 477 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 478 uint64_t Addr, 479 const void *Decoder) { 480 if (RegNo > 31) 481 return Fail; 482 unsigned Register = 483 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo); 484 Inst.addOperand(MCOperand::createReg(Register)); 485 return Success; 486 } 487 488 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 489 unsigned RegNo, 490 uint64_t Addr, 491 const void *Decoder) { 492 if (RegNo > 3) 493 return Fail; 494 495 unsigned Register = 496 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID] 497 .getRegister(RegNo); 498 Inst.addOperand(MCOperand::createReg(Register)); 499 return Success; 500 } 501 502 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 503 uint64_t Addr, 504 const void *Decoder) { 505 if (RegNo > 31) 506 return Fail; 507 508 unsigned Register = 509 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo); 510 Inst.addOperand(MCOperand::createReg(Register)); 511 return Success; 512 } 513 514 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 515 uint64_t Addr, 516 const void *Decoder) { 517 if (RegNo > 31) 518 return Fail; 519 520 unsigned Register = 521 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo); 522 Inst.addOperand(MCOperand::createReg(Register)); 523 return Success; 524 } 525 526 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 527 uint64_t Address, 528 const void* Decoder) { 529 if (RegNo > 31) 530 return Fail; 531 532 unsigned Register = 533 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo); 534 Inst.addOperand(MCOperand::createReg(Register)); 535 return Success; 536 } 537 538 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 539 uint64_t Address, 540 const void *Decoder) { 541 if (RegNo > 15) 542 return Fail; 543 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 544 } 545 546 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 547 uint64_t Address, 548 const void *Decoder) { 549 if (RegNo > 7) 550 return Fail; 551 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 552 } 553 554 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 555 uint64_t Address, 556 const void* Decoder) { 557 if (RegNo > 31) 558 return Fail; 559 unsigned Register = 560 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo); 561 Inst.addOperand(MCOperand::createReg(Register)); 562 return Success; 563 } 564 565 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 566 uint64_t Address, 567 const void* Decoder) { 568 if (RegNo > 31) 569 return Fail; 570 unsigned Register = 571 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo); 572 Inst.addOperand(MCOperand::createReg(Register)); 573 return Success; 574 } 575 576 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 577 uint64_t Address, 578 const void* Decoder) { 579 if (RegNo > 31) 580 return Fail; 581 unsigned Register = 582 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo); 583 Inst.addOperand(MCOperand::createReg(Register)); 584 return Success; 585 } 586 587 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 588 unsigned RegMask, 589 uint64_t Address, 590 const void *Decoder) { 591 if (RegMask > 0xFF) 592 return Fail; 593 Inst.addOperand(MCOperand::createImm(RegMask)); 594 return Success; 595 } 596 597 static const SmallVector<SmallVector<unsigned, 16>, 5> 598 MatrixZATileDecoderTable = { 599 {AArch64::ZAB0}, 600 {AArch64::ZAH0, AArch64::ZAH1}, 601 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 602 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 603 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 604 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 605 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 606 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 607 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 608 609 template <unsigned NumBitsForTile> 610 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 611 uint64_t Address, const void *Decoder) { 612 unsigned LastReg = (1 << NumBitsForTile) - 1; 613 if (RegNo > LastReg) 614 return Fail; 615 Inst.addOperand( 616 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 617 return Success; 618 } 619 620 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 621 uint64_t Addr, const void *Decoder) { 622 if (RegNo > 15) 623 return Fail; 624 625 unsigned Register = 626 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo); 627 Inst.addOperand(MCOperand::createReg(Register)); 628 return Success; 629 } 630 631 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 632 uint64_t Addr, 633 const void* Decoder) { 634 if (RegNo > 7) 635 return Fail; 636 637 // Just reuse the PPR decode table 638 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 639 } 640 641 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 642 uint64_t Addr, const void *Decoder) { 643 if (RegNo > 31) 644 return Fail; 645 unsigned Register = 646 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo); 647 Inst.addOperand(MCOperand::createReg(Register)); 648 return Success; 649 } 650 651 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 652 uint64_t Addr, const void *Decoder) { 653 if (RegNo > 31) 654 return Fail; 655 unsigned Register = 656 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo); 657 Inst.addOperand(MCOperand::createReg(Register)); 658 return Success; 659 } 660 661 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 662 uint64_t Addr, 663 const void *Decoder) { 664 if (RegNo > 31) 665 return Fail; 666 unsigned Register = 667 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo); 668 Inst.addOperand(MCOperand::createReg(Register)); 669 return Success; 670 } 671 672 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 673 uint64_t Addr, const void *Decoder) { 674 if (RegNo > 31) 675 return Fail; 676 unsigned Register = 677 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo); 678 Inst.addOperand(MCOperand::createReg(Register)); 679 return Success; 680 } 681 682 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 683 uint64_t Addr, const void *Decoder) { 684 if (RegNo > 31) 685 return Fail; 686 unsigned Register = 687 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo); 688 Inst.addOperand(MCOperand::createReg(Register)); 689 return Success; 690 } 691 692 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 693 uint64_t Addr, 694 const void *Decoder) { 695 if (RegNo > 31) 696 return Fail; 697 unsigned Register = 698 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo); 699 Inst.addOperand(MCOperand::createReg(Register)); 700 return Success; 701 } 702 703 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 704 uint64_t Addr, 705 const void *Decoder) { 706 // scale{5} is asserted as 1 in tblgen. 707 Imm |= 0x20; 708 Inst.addOperand(MCOperand::createImm(64 - Imm)); 709 return Success; 710 } 711 712 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 713 uint64_t Addr, 714 const void *Decoder) { 715 Inst.addOperand(MCOperand::createImm(64 - Imm)); 716 return Success; 717 } 718 719 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 720 uint64_t Addr, const void *Decoder) { 721 int64_t ImmVal = Imm; 722 const AArch64Disassembler *Dis = 723 static_cast<const AArch64Disassembler *>(Decoder); 724 725 // Sign-extend 19-bit immediate. 726 if (ImmVal & (1 << (19 - 1))) 727 ImmVal |= ~((1LL << 19) - 1); 728 729 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 730 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 731 Inst.addOperand(MCOperand::createImm(ImmVal)); 732 return Success; 733 } 734 735 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 736 uint64_t Address, const void *Decoder) { 737 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 738 Inst.addOperand(MCOperand::createImm(Imm & 1)); 739 return Success; 740 } 741 742 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 743 uint64_t Address, 744 const void *Decoder) { 745 Inst.addOperand(MCOperand::createImm(Imm)); 746 747 // Every system register in the encoding space is valid with the syntax 748 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 749 return Success; 750 } 751 752 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 753 uint64_t Address, 754 const void *Decoder) { 755 Inst.addOperand(MCOperand::createImm(Imm)); 756 757 return Success; 758 } 759 760 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 761 uint64_t Address, 762 const void *Decoder) { 763 // This decoder exists to add the dummy Lane operand to the MCInst, which must 764 // be 1 in assembly but has no other real manifestation. 765 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 766 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 767 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 768 769 if (IsToVec) { 770 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 771 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 772 } else { 773 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 774 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 775 } 776 777 // Add the lane 778 Inst.addOperand(MCOperand::createImm(1)); 779 780 return Success; 781 } 782 783 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 784 unsigned Add) { 785 Inst.addOperand(MCOperand::createImm(Add - Imm)); 786 return Success; 787 } 788 789 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 790 unsigned Add) { 791 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 792 return Success; 793 } 794 795 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 796 uint64_t Addr, const void *Decoder) { 797 return DecodeVecShiftRImm(Inst, Imm, 64); 798 } 799 800 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 801 uint64_t Addr, 802 const void *Decoder) { 803 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 804 } 805 806 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 807 uint64_t Addr, const void *Decoder) { 808 return DecodeVecShiftRImm(Inst, Imm, 32); 809 } 810 811 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 812 uint64_t Addr, 813 const void *Decoder) { 814 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 815 } 816 817 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 818 uint64_t Addr, const void *Decoder) { 819 return DecodeVecShiftRImm(Inst, Imm, 16); 820 } 821 822 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 823 uint64_t Addr, 824 const void *Decoder) { 825 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 826 } 827 828 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 829 uint64_t Addr, const void *Decoder) { 830 return DecodeVecShiftRImm(Inst, Imm, 8); 831 } 832 833 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 834 uint64_t Addr, const void *Decoder) { 835 return DecodeVecShiftLImm(Inst, Imm, 64); 836 } 837 838 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 839 uint64_t Addr, const void *Decoder) { 840 return DecodeVecShiftLImm(Inst, Imm, 32); 841 } 842 843 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 844 uint64_t Addr, const void *Decoder) { 845 return DecodeVecShiftLImm(Inst, Imm, 16); 846 } 847 848 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 849 uint64_t Addr, const void *Decoder) { 850 return DecodeVecShiftLImm(Inst, Imm, 8); 851 } 852 853 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 854 uint64_t Addr, 855 const void *Decoder) { 856 unsigned Rd = fieldFromInstruction(insn, 0, 5); 857 unsigned Rn = fieldFromInstruction(insn, 5, 5); 858 unsigned Rm = fieldFromInstruction(insn, 16, 5); 859 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 860 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 861 unsigned shift = (shiftHi << 6) | shiftLo; 862 switch (Inst.getOpcode()) { 863 default: 864 return Fail; 865 case AArch64::ADDWrs: 866 case AArch64::ADDSWrs: 867 case AArch64::SUBWrs: 868 case AArch64::SUBSWrs: 869 // if shift == '11' then ReservedValue() 870 if (shiftHi == 0x3) 871 return Fail; 872 LLVM_FALLTHROUGH; 873 case AArch64::ANDWrs: 874 case AArch64::ANDSWrs: 875 case AArch64::BICWrs: 876 case AArch64::BICSWrs: 877 case AArch64::ORRWrs: 878 case AArch64::ORNWrs: 879 case AArch64::EORWrs: 880 case AArch64::EONWrs: { 881 // if sf == '0' and imm6<5> == '1' then ReservedValue() 882 if (shiftLo >> 5 == 1) 883 return Fail; 884 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 885 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 886 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 887 break; 888 } 889 case AArch64::ADDXrs: 890 case AArch64::ADDSXrs: 891 case AArch64::SUBXrs: 892 case AArch64::SUBSXrs: 893 // if shift == '11' then ReservedValue() 894 if (shiftHi == 0x3) 895 return Fail; 896 LLVM_FALLTHROUGH; 897 case AArch64::ANDXrs: 898 case AArch64::ANDSXrs: 899 case AArch64::BICXrs: 900 case AArch64::BICSXrs: 901 case AArch64::ORRXrs: 902 case AArch64::ORNXrs: 903 case AArch64::EORXrs: 904 case AArch64::EONXrs: 905 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 906 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 907 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 908 break; 909 } 910 911 Inst.addOperand(MCOperand::createImm(shift)); 912 return Success; 913 } 914 915 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 916 uint64_t Addr, 917 const void *Decoder) { 918 unsigned Rd = fieldFromInstruction(insn, 0, 5); 919 unsigned imm = fieldFromInstruction(insn, 5, 16); 920 unsigned shift = fieldFromInstruction(insn, 21, 2); 921 shift <<= 4; 922 switch (Inst.getOpcode()) { 923 default: 924 return Fail; 925 case AArch64::MOVZWi: 926 case AArch64::MOVNWi: 927 case AArch64::MOVKWi: 928 if (shift & (1U << 5)) 929 return Fail; 930 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 931 break; 932 case AArch64::MOVZXi: 933 case AArch64::MOVNXi: 934 case AArch64::MOVKXi: 935 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 936 break; 937 } 938 939 if (Inst.getOpcode() == AArch64::MOVKWi || 940 Inst.getOpcode() == AArch64::MOVKXi) 941 Inst.addOperand(Inst.getOperand(0)); 942 943 Inst.addOperand(MCOperand::createImm(imm)); 944 Inst.addOperand(MCOperand::createImm(shift)); 945 return Success; 946 } 947 948 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 949 uint64_t Addr, 950 const void *Decoder) { 951 unsigned Rt = fieldFromInstruction(insn, 0, 5); 952 unsigned Rn = fieldFromInstruction(insn, 5, 5); 953 unsigned offset = fieldFromInstruction(insn, 10, 12); 954 const AArch64Disassembler *Dis = 955 static_cast<const AArch64Disassembler *>(Decoder); 956 957 switch (Inst.getOpcode()) { 958 default: 959 return Fail; 960 case AArch64::PRFMui: 961 // Rt is an immediate in prefetch. 962 Inst.addOperand(MCOperand::createImm(Rt)); 963 break; 964 case AArch64::STRBBui: 965 case AArch64::LDRBBui: 966 case AArch64::LDRSBWui: 967 case AArch64::STRHHui: 968 case AArch64::LDRHHui: 969 case AArch64::LDRSHWui: 970 case AArch64::STRWui: 971 case AArch64::LDRWui: 972 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 973 break; 974 case AArch64::LDRSBXui: 975 case AArch64::LDRSHXui: 976 case AArch64::LDRSWui: 977 case AArch64::STRXui: 978 case AArch64::LDRXui: 979 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 980 break; 981 case AArch64::LDRQui: 982 case AArch64::STRQui: 983 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 984 break; 985 case AArch64::LDRDui: 986 case AArch64::STRDui: 987 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 988 break; 989 case AArch64::LDRSui: 990 case AArch64::STRSui: 991 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 992 break; 993 case AArch64::LDRHui: 994 case AArch64::STRHui: 995 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 996 break; 997 case AArch64::LDRBui: 998 case AArch64::STRBui: 999 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1000 break; 1001 } 1002 1003 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1004 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1005 Inst.addOperand(MCOperand::createImm(offset)); 1006 return Success; 1007 } 1008 1009 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1010 uint64_t Addr, 1011 const void *Decoder) { 1012 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1013 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1014 int64_t offset = fieldFromInstruction(insn, 12, 9); 1015 1016 // offset is a 9-bit signed immediate, so sign extend it to 1017 // fill the unsigned. 1018 if (offset & (1 << (9 - 1))) 1019 offset |= ~((1LL << 9) - 1); 1020 1021 // First operand is always the writeback to the address register, if needed. 1022 switch (Inst.getOpcode()) { 1023 default: 1024 break; 1025 case AArch64::LDRSBWpre: 1026 case AArch64::LDRSHWpre: 1027 case AArch64::STRBBpre: 1028 case AArch64::LDRBBpre: 1029 case AArch64::STRHHpre: 1030 case AArch64::LDRHHpre: 1031 case AArch64::STRWpre: 1032 case AArch64::LDRWpre: 1033 case AArch64::LDRSBWpost: 1034 case AArch64::LDRSHWpost: 1035 case AArch64::STRBBpost: 1036 case AArch64::LDRBBpost: 1037 case AArch64::STRHHpost: 1038 case AArch64::LDRHHpost: 1039 case AArch64::STRWpost: 1040 case AArch64::LDRWpost: 1041 case AArch64::LDRSBXpre: 1042 case AArch64::LDRSHXpre: 1043 case AArch64::STRXpre: 1044 case AArch64::LDRSWpre: 1045 case AArch64::LDRXpre: 1046 case AArch64::LDRSBXpost: 1047 case AArch64::LDRSHXpost: 1048 case AArch64::STRXpost: 1049 case AArch64::LDRSWpost: 1050 case AArch64::LDRXpost: 1051 case AArch64::LDRQpre: 1052 case AArch64::STRQpre: 1053 case AArch64::LDRQpost: 1054 case AArch64::STRQpost: 1055 case AArch64::LDRDpre: 1056 case AArch64::STRDpre: 1057 case AArch64::LDRDpost: 1058 case AArch64::STRDpost: 1059 case AArch64::LDRSpre: 1060 case AArch64::STRSpre: 1061 case AArch64::LDRSpost: 1062 case AArch64::STRSpost: 1063 case AArch64::LDRHpre: 1064 case AArch64::STRHpre: 1065 case AArch64::LDRHpost: 1066 case AArch64::STRHpost: 1067 case AArch64::LDRBpre: 1068 case AArch64::STRBpre: 1069 case AArch64::LDRBpost: 1070 case AArch64::STRBpost: 1071 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1072 break; 1073 } 1074 1075 switch (Inst.getOpcode()) { 1076 default: 1077 return Fail; 1078 case AArch64::PRFUMi: 1079 // Rt is an immediate in prefetch. 1080 Inst.addOperand(MCOperand::createImm(Rt)); 1081 break; 1082 case AArch64::STURBBi: 1083 case AArch64::LDURBBi: 1084 case AArch64::LDURSBWi: 1085 case AArch64::STURHHi: 1086 case AArch64::LDURHHi: 1087 case AArch64::LDURSHWi: 1088 case AArch64::STURWi: 1089 case AArch64::LDURWi: 1090 case AArch64::LDTRSBWi: 1091 case AArch64::LDTRSHWi: 1092 case AArch64::STTRWi: 1093 case AArch64::LDTRWi: 1094 case AArch64::STTRHi: 1095 case AArch64::LDTRHi: 1096 case AArch64::LDTRBi: 1097 case AArch64::STTRBi: 1098 case AArch64::LDRSBWpre: 1099 case AArch64::LDRSHWpre: 1100 case AArch64::STRBBpre: 1101 case AArch64::LDRBBpre: 1102 case AArch64::STRHHpre: 1103 case AArch64::LDRHHpre: 1104 case AArch64::STRWpre: 1105 case AArch64::LDRWpre: 1106 case AArch64::LDRSBWpost: 1107 case AArch64::LDRSHWpost: 1108 case AArch64::STRBBpost: 1109 case AArch64::LDRBBpost: 1110 case AArch64::STRHHpost: 1111 case AArch64::LDRHHpost: 1112 case AArch64::STRWpost: 1113 case AArch64::LDRWpost: 1114 case AArch64::STLURBi: 1115 case AArch64::STLURHi: 1116 case AArch64::STLURWi: 1117 case AArch64::LDAPURBi: 1118 case AArch64::LDAPURSBWi: 1119 case AArch64::LDAPURHi: 1120 case AArch64::LDAPURSHWi: 1121 case AArch64::LDAPURi: 1122 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1123 break; 1124 case AArch64::LDURSBXi: 1125 case AArch64::LDURSHXi: 1126 case AArch64::LDURSWi: 1127 case AArch64::STURXi: 1128 case AArch64::LDURXi: 1129 case AArch64::LDTRSBXi: 1130 case AArch64::LDTRSHXi: 1131 case AArch64::LDTRSWi: 1132 case AArch64::STTRXi: 1133 case AArch64::LDTRXi: 1134 case AArch64::LDRSBXpre: 1135 case AArch64::LDRSHXpre: 1136 case AArch64::STRXpre: 1137 case AArch64::LDRSWpre: 1138 case AArch64::LDRXpre: 1139 case AArch64::LDRSBXpost: 1140 case AArch64::LDRSHXpost: 1141 case AArch64::STRXpost: 1142 case AArch64::LDRSWpost: 1143 case AArch64::LDRXpost: 1144 case AArch64::LDAPURSWi: 1145 case AArch64::LDAPURSHXi: 1146 case AArch64::LDAPURSBXi: 1147 case AArch64::STLURXi: 1148 case AArch64::LDAPURXi: 1149 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1150 break; 1151 case AArch64::LDURQi: 1152 case AArch64::STURQi: 1153 case AArch64::LDRQpre: 1154 case AArch64::STRQpre: 1155 case AArch64::LDRQpost: 1156 case AArch64::STRQpost: 1157 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1158 break; 1159 case AArch64::LDURDi: 1160 case AArch64::STURDi: 1161 case AArch64::LDRDpre: 1162 case AArch64::STRDpre: 1163 case AArch64::LDRDpost: 1164 case AArch64::STRDpost: 1165 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1166 break; 1167 case AArch64::LDURSi: 1168 case AArch64::STURSi: 1169 case AArch64::LDRSpre: 1170 case AArch64::STRSpre: 1171 case AArch64::LDRSpost: 1172 case AArch64::STRSpost: 1173 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1174 break; 1175 case AArch64::LDURHi: 1176 case AArch64::STURHi: 1177 case AArch64::LDRHpre: 1178 case AArch64::STRHpre: 1179 case AArch64::LDRHpost: 1180 case AArch64::STRHpost: 1181 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1182 break; 1183 case AArch64::LDURBi: 1184 case AArch64::STURBi: 1185 case AArch64::LDRBpre: 1186 case AArch64::STRBpre: 1187 case AArch64::LDRBpost: 1188 case AArch64::STRBpost: 1189 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1190 break; 1191 } 1192 1193 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1194 Inst.addOperand(MCOperand::createImm(offset)); 1195 1196 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1197 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1198 bool IsFP = fieldFromInstruction(insn, 26, 1); 1199 1200 // Cannot write back to a transfer register (but xzr != sp). 1201 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1202 return SoftFail; 1203 1204 return Success; 1205 } 1206 1207 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1208 uint64_t Addr, 1209 const void *Decoder) { 1210 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1211 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1212 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1213 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1214 1215 unsigned Opcode = Inst.getOpcode(); 1216 switch (Opcode) { 1217 default: 1218 return Fail; 1219 case AArch64::STLXRW: 1220 case AArch64::STLXRB: 1221 case AArch64::STLXRH: 1222 case AArch64::STXRW: 1223 case AArch64::STXRB: 1224 case AArch64::STXRH: 1225 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1226 LLVM_FALLTHROUGH; 1227 case AArch64::LDARW: 1228 case AArch64::LDARB: 1229 case AArch64::LDARH: 1230 case AArch64::LDAXRW: 1231 case AArch64::LDAXRB: 1232 case AArch64::LDAXRH: 1233 case AArch64::LDXRW: 1234 case AArch64::LDXRB: 1235 case AArch64::LDXRH: 1236 case AArch64::STLRW: 1237 case AArch64::STLRB: 1238 case AArch64::STLRH: 1239 case AArch64::STLLRW: 1240 case AArch64::STLLRB: 1241 case AArch64::STLLRH: 1242 case AArch64::LDLARW: 1243 case AArch64::LDLARB: 1244 case AArch64::LDLARH: 1245 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1246 break; 1247 case AArch64::STLXRX: 1248 case AArch64::STXRX: 1249 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1250 LLVM_FALLTHROUGH; 1251 case AArch64::LDARX: 1252 case AArch64::LDAXRX: 1253 case AArch64::LDXRX: 1254 case AArch64::STLRX: 1255 case AArch64::LDLARX: 1256 case AArch64::STLLRX: 1257 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1258 break; 1259 case AArch64::STLXPW: 1260 case AArch64::STXPW: 1261 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1262 LLVM_FALLTHROUGH; 1263 case AArch64::LDAXPW: 1264 case AArch64::LDXPW: 1265 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1266 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1267 break; 1268 case AArch64::STLXPX: 1269 case AArch64::STXPX: 1270 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1271 LLVM_FALLTHROUGH; 1272 case AArch64::LDAXPX: 1273 case AArch64::LDXPX: 1274 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1275 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1276 break; 1277 } 1278 1279 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1280 1281 // You shouldn't load to the same register twice in an instruction... 1282 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1283 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1284 Rt == Rt2) 1285 return SoftFail; 1286 1287 return Success; 1288 } 1289 1290 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1291 uint64_t Addr, 1292 const void *Decoder) { 1293 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1294 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1295 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1296 int64_t offset = fieldFromInstruction(insn, 15, 7); 1297 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1298 1299 // offset is a 7-bit signed immediate, so sign extend it to 1300 // fill the unsigned. 1301 if (offset & (1 << (7 - 1))) 1302 offset |= ~((1LL << 7) - 1); 1303 1304 unsigned Opcode = Inst.getOpcode(); 1305 bool NeedsDisjointWritebackTransfer = false; 1306 1307 // First operand is always writeback of base register. 1308 switch (Opcode) { 1309 default: 1310 break; 1311 case AArch64::LDPXpost: 1312 case AArch64::STPXpost: 1313 case AArch64::LDPSWpost: 1314 case AArch64::LDPXpre: 1315 case AArch64::STPXpre: 1316 case AArch64::LDPSWpre: 1317 case AArch64::LDPWpost: 1318 case AArch64::STPWpost: 1319 case AArch64::LDPWpre: 1320 case AArch64::STPWpre: 1321 case AArch64::LDPQpost: 1322 case AArch64::STPQpost: 1323 case AArch64::LDPQpre: 1324 case AArch64::STPQpre: 1325 case AArch64::LDPDpost: 1326 case AArch64::STPDpost: 1327 case AArch64::LDPDpre: 1328 case AArch64::STPDpre: 1329 case AArch64::LDPSpost: 1330 case AArch64::STPSpost: 1331 case AArch64::LDPSpre: 1332 case AArch64::STPSpre: 1333 case AArch64::STGPpre: 1334 case AArch64::STGPpost: 1335 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1336 break; 1337 } 1338 1339 switch (Opcode) { 1340 default: 1341 return Fail; 1342 case AArch64::LDPXpost: 1343 case AArch64::STPXpost: 1344 case AArch64::LDPSWpost: 1345 case AArch64::LDPXpre: 1346 case AArch64::STPXpre: 1347 case AArch64::LDPSWpre: 1348 case AArch64::STGPpre: 1349 case AArch64::STGPpost: 1350 NeedsDisjointWritebackTransfer = true; 1351 LLVM_FALLTHROUGH; 1352 case AArch64::LDNPXi: 1353 case AArch64::STNPXi: 1354 case AArch64::LDPXi: 1355 case AArch64::STPXi: 1356 case AArch64::LDPSWi: 1357 case AArch64::STGPi: 1358 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1359 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1360 break; 1361 case AArch64::LDPWpost: 1362 case AArch64::STPWpost: 1363 case AArch64::LDPWpre: 1364 case AArch64::STPWpre: 1365 NeedsDisjointWritebackTransfer = true; 1366 LLVM_FALLTHROUGH; 1367 case AArch64::LDNPWi: 1368 case AArch64::STNPWi: 1369 case AArch64::LDPWi: 1370 case AArch64::STPWi: 1371 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1372 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1373 break; 1374 case AArch64::LDNPQi: 1375 case AArch64::STNPQi: 1376 case AArch64::LDPQpost: 1377 case AArch64::STPQpost: 1378 case AArch64::LDPQi: 1379 case AArch64::STPQi: 1380 case AArch64::LDPQpre: 1381 case AArch64::STPQpre: 1382 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1383 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1384 break; 1385 case AArch64::LDNPDi: 1386 case AArch64::STNPDi: 1387 case AArch64::LDPDpost: 1388 case AArch64::STPDpost: 1389 case AArch64::LDPDi: 1390 case AArch64::STPDi: 1391 case AArch64::LDPDpre: 1392 case AArch64::STPDpre: 1393 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1394 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1395 break; 1396 case AArch64::LDNPSi: 1397 case AArch64::STNPSi: 1398 case AArch64::LDPSpost: 1399 case AArch64::STPSpost: 1400 case AArch64::LDPSi: 1401 case AArch64::STPSi: 1402 case AArch64::LDPSpre: 1403 case AArch64::STPSpre: 1404 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1405 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1406 break; 1407 } 1408 1409 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1410 Inst.addOperand(MCOperand::createImm(offset)); 1411 1412 // You shouldn't load to the same register twice in an instruction... 1413 if (IsLoad && Rt == Rt2) 1414 return SoftFail; 1415 1416 // ... or do any operation that writes-back to a transfer register. But note 1417 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1418 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1419 return SoftFail; 1420 1421 return Success; 1422 } 1423 1424 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1425 uint64_t Addr, 1426 const void *Decoder) { 1427 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1428 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1429 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1430 fieldFromInstruction(insn, 12, 9); 1431 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1432 1433 switch (Inst.getOpcode()) { 1434 default: 1435 return Fail; 1436 case AArch64::LDRAAwriteback: 1437 case AArch64::LDRABwriteback: 1438 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1439 Decoder); 1440 break; 1441 case AArch64::LDRAAindexed: 1442 case AArch64::LDRABindexed: 1443 break; 1444 } 1445 1446 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1447 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1448 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1449 1450 if (writeback && Rt == Rn && Rn != 31) { 1451 return SoftFail; 1452 } 1453 1454 return Success; 1455 } 1456 1457 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1458 uint64_t Addr, 1459 const void *Decoder) { 1460 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1461 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1462 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1463 unsigned extend = fieldFromInstruction(insn, 10, 6); 1464 1465 unsigned shift = extend & 0x7; 1466 if (shift > 4) 1467 return Fail; 1468 1469 switch (Inst.getOpcode()) { 1470 default: 1471 return Fail; 1472 case AArch64::ADDWrx: 1473 case AArch64::SUBWrx: 1474 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1475 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1476 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1477 break; 1478 case AArch64::ADDSWrx: 1479 case AArch64::SUBSWrx: 1480 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1481 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1482 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1483 break; 1484 case AArch64::ADDXrx: 1485 case AArch64::SUBXrx: 1486 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1487 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1488 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1489 break; 1490 case AArch64::ADDSXrx: 1491 case AArch64::SUBSXrx: 1492 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1493 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1494 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1495 break; 1496 case AArch64::ADDXrx64: 1497 case AArch64::SUBXrx64: 1498 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1499 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1500 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1501 break; 1502 case AArch64::SUBSXrx64: 1503 case AArch64::ADDSXrx64: 1504 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1505 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1506 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1507 break; 1508 } 1509 1510 Inst.addOperand(MCOperand::createImm(extend)); 1511 return Success; 1512 } 1513 1514 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1515 uint64_t Addr, 1516 const void *Decoder) { 1517 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1518 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1519 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1520 unsigned imm; 1521 1522 if (Datasize) { 1523 if (Inst.getOpcode() == AArch64::ANDSXri) 1524 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1525 else 1526 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1527 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1528 imm = fieldFromInstruction(insn, 10, 13); 1529 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1530 return Fail; 1531 } else { 1532 if (Inst.getOpcode() == AArch64::ANDSWri) 1533 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1534 else 1535 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1536 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1537 imm = fieldFromInstruction(insn, 10, 12); 1538 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1539 return Fail; 1540 } 1541 Inst.addOperand(MCOperand::createImm(imm)); 1542 return Success; 1543 } 1544 1545 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1546 uint64_t Addr, 1547 const void *Decoder) { 1548 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1549 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1550 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1551 imm |= fieldFromInstruction(insn, 5, 5); 1552 1553 if (Inst.getOpcode() == AArch64::MOVID) 1554 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1555 else 1556 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1557 1558 Inst.addOperand(MCOperand::createImm(imm)); 1559 1560 switch (Inst.getOpcode()) { 1561 default: 1562 break; 1563 case AArch64::MOVIv4i16: 1564 case AArch64::MOVIv8i16: 1565 case AArch64::MVNIv4i16: 1566 case AArch64::MVNIv8i16: 1567 case AArch64::MOVIv2i32: 1568 case AArch64::MOVIv4i32: 1569 case AArch64::MVNIv2i32: 1570 case AArch64::MVNIv4i32: 1571 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1572 break; 1573 case AArch64::MOVIv2s_msl: 1574 case AArch64::MOVIv4s_msl: 1575 case AArch64::MVNIv2s_msl: 1576 case AArch64::MVNIv4s_msl: 1577 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1578 break; 1579 } 1580 1581 return Success; 1582 } 1583 1584 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1585 uint64_t Addr, 1586 const void *Decoder) { 1587 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1588 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1589 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1590 imm |= fieldFromInstruction(insn, 5, 5); 1591 1592 // Tied operands added twice. 1593 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1594 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1595 1596 Inst.addOperand(MCOperand::createImm(imm)); 1597 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1598 1599 return Success; 1600 } 1601 1602 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1603 uint64_t Addr, const void *Decoder) { 1604 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1605 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1606 imm |= fieldFromInstruction(insn, 29, 2); 1607 const AArch64Disassembler *Dis = 1608 static_cast<const AArch64Disassembler *>(Decoder); 1609 1610 // Sign-extend the 21-bit immediate. 1611 if (imm & (1 << (21 - 1))) 1612 imm |= ~((1LL << 21) - 1); 1613 1614 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1615 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1616 Inst.addOperand(MCOperand::createImm(imm)); 1617 1618 return Success; 1619 } 1620 1621 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1622 uint64_t Addr, const void *Decoder) { 1623 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1624 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1625 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1626 unsigned S = fieldFromInstruction(insn, 29, 1); 1627 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1628 1629 unsigned ShifterVal = (Imm >> 12) & 3; 1630 unsigned ImmVal = Imm & 0xFFF; 1631 const AArch64Disassembler *Dis = 1632 static_cast<const AArch64Disassembler *>(Decoder); 1633 1634 if (ShifterVal != 0 && ShifterVal != 1) 1635 return Fail; 1636 1637 if (Datasize) { 1638 if (Rd == 31 && !S) 1639 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1640 else 1641 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1642 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1643 } else { 1644 if (Rd == 31 && !S) 1645 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1646 else 1647 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1648 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1649 } 1650 1651 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1652 Inst.addOperand(MCOperand::createImm(ImmVal)); 1653 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1654 return Success; 1655 } 1656 1657 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1658 uint64_t Addr, 1659 const void *Decoder) { 1660 int64_t imm = fieldFromInstruction(insn, 0, 26); 1661 const AArch64Disassembler *Dis = 1662 static_cast<const AArch64Disassembler *>(Decoder); 1663 1664 // Sign-extend the 26-bit immediate. 1665 if (imm & (1 << (26 - 1))) 1666 imm |= ~((1LL << 26) - 1); 1667 1668 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1669 Inst.addOperand(MCOperand::createImm(imm)); 1670 1671 return Success; 1672 } 1673 1674 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1675 uint64_t Addr, 1676 const void *Decoder) { 1677 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1678 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1679 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1680 uint64_t pstate_field = (op1 << 3) | op2; 1681 1682 switch (pstate_field) { 1683 case 0x01: // XAFlag 1684 case 0x02: // AXFlag 1685 return Fail; 1686 } 1687 1688 if ((pstate_field == AArch64PState::PAN || 1689 pstate_field == AArch64PState::UAO || 1690 pstate_field == AArch64PState::SSBS) && crm > 1) 1691 return Fail; 1692 1693 Inst.addOperand(MCOperand::createImm(pstate_field)); 1694 Inst.addOperand(MCOperand::createImm(crm)); 1695 1696 const AArch64Disassembler *Dis = 1697 static_cast<const AArch64Disassembler *>(Decoder); 1698 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1699 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1700 return Success; 1701 return Fail; 1702 } 1703 1704 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1705 uint64_t Addr, const void *Decoder) { 1706 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1707 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1708 bit |= fieldFromInstruction(insn, 19, 5); 1709 int64_t dst = fieldFromInstruction(insn, 5, 14); 1710 const AArch64Disassembler *Dis = 1711 static_cast<const AArch64Disassembler *>(Decoder); 1712 1713 // Sign-extend 14-bit immediate. 1714 if (dst & (1 << (14 - 1))) 1715 dst |= ~((1LL << 14) - 1); 1716 1717 if (fieldFromInstruction(insn, 31, 1) == 0) 1718 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1719 else 1720 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1721 Inst.addOperand(MCOperand::createImm(bit)); 1722 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1723 Inst.addOperand(MCOperand::createImm(dst)); 1724 1725 return Success; 1726 } 1727 1728 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1729 unsigned RegClassID, 1730 unsigned RegNo, 1731 uint64_t Addr, 1732 const void *Decoder) { 1733 // Register number must be even (see CASP instruction) 1734 if (RegNo & 0x1) 1735 return Fail; 1736 1737 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1738 Inst.addOperand(MCOperand::createReg(Reg)); 1739 return Success; 1740 } 1741 1742 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1743 unsigned RegNo, 1744 uint64_t Addr, 1745 const void *Decoder) { 1746 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1747 AArch64::WSeqPairsClassRegClassID, 1748 RegNo, Addr, Decoder); 1749 } 1750 1751 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1752 unsigned RegNo, 1753 uint64_t Addr, 1754 const void *Decoder) { 1755 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1756 AArch64::XSeqPairsClassRegClassID, 1757 RegNo, Addr, Decoder); 1758 } 1759 1760 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, 1761 uint64_t Addr, 1762 const void *Decoder) { 1763 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1764 unsigned imm = fieldFromInstruction(insn, 5, 13); 1765 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1766 return Fail; 1767 1768 // The same (tied) operand is added twice to the instruction. 1769 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1770 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1771 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1772 Inst.addOperand(MCOperand::createImm(imm)); 1773 return Success; 1774 } 1775 1776 template <int Bits> 1777 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 1778 const void *Decoder) { 1779 if (Imm & ~((1LL << Bits) - 1)) 1780 return Fail; 1781 1782 // Imm is a signed immediate, so sign extend it. 1783 if (Imm & (1 << (Bits - 1))) 1784 Imm |= ~((1LL << Bits) - 1); 1785 1786 Inst.addOperand(MCOperand::createImm(Imm)); 1787 return Success; 1788 } 1789 1790 // Decode 8-bit signed/unsigned immediate for a given element width. 1791 template <int ElementWidth> 1792 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1793 uint64_t Addr, const void *Decoder) { 1794 unsigned Val = (uint8_t)Imm; 1795 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1796 if (ElementWidth == 8 && Shift) 1797 return Fail; 1798 Inst.addOperand(MCOperand::createImm(Val)); 1799 Inst.addOperand(MCOperand::createImm(Shift)); 1800 return Success; 1801 } 1802 1803 // Decode uimm4 ranged from 1-16. 1804 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1805 uint64_t Addr, const void *Decoder) { 1806 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1807 return Success; 1808 } 1809 1810 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 1811 const void *Decoder) { 1812 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 1813 Inst.addOperand(MCOperand::createImm(Imm)); 1814 return Success; 1815 } 1816 return Fail; 1817 } 1818