1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm-c/Disassembler.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include <algorithm> 28 #include <memory> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "aarch64-disassembler" 33 34 // Pull DecodeStatus and its enum values into the global namespace. 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 // Forward declare these because the autogenerated code will reference them. 38 // Definitions are further down. 39 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 40 unsigned RegNo, uint64_t Address, 41 const void *Decoder); 42 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 43 unsigned RegNo, 44 uint64_t Address, 45 const void *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const void *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const void *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const void *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const void *Decoder); 58 LLVM_ATTRIBUTE_UNUSED 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 66 unsigned RegNo, uint64_t Address, 67 const void *Decoder); 68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 72 unsigned RegNo, uint64_t Address, 73 const void *Decoder); 74 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 81 uint64_t Address, 82 const void *Decoder); 83 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 93 uint64_t Address, 94 const void *Decode); 95 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 96 uint64_t Address, 97 const void *Decode); 98 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 99 uint64_t Address, 100 const void *Decode); 101 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 102 uint64_t Address, 103 const void *Decode); 104 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 105 uint64_t Address, 106 const void *Decode); 107 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 108 uint64_t Address, 109 const void *Decode); 110 111 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 112 uint64_t Address, 113 const void *Decoder); 114 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 115 uint64_t Address, 116 const void *Decoder); 117 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 124 uint64_t Address, const void *Decoder); 125 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 129 uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 132 uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 135 uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 138 uint64_t Address, 139 const void *Decoder); 140 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 141 uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 144 uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 160 uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 163 uint64_t Address, 164 const void *Decoder); 165 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 166 uint64_t Address, const void *Decoder); 167 168 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 169 uint64_t Address, 170 const void *Decoder); 171 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 172 uint64_t Addr, const void *Decoder); 173 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 174 uint64_t Addr, 175 const void *Decoder); 176 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 177 uint64_t Addr, const void *Decoder); 178 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 179 uint64_t Addr, 180 const void *Decoder); 181 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 182 uint64_t Addr, const void *Decoder); 183 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 184 uint64_t Addr, 185 const void *Decoder); 186 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 187 uint64_t Addr, const void *Decoder); 188 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 189 uint64_t Addr, const void *Decoder); 190 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 191 uint64_t Addr, const void *Decoder); 192 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 193 uint64_t Addr, const void *Decoder); 194 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 195 uint64_t Addr, const void *Decoder); 196 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 197 unsigned RegNo, 198 uint64_t Addr, 199 const void *Decoder); 200 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Addr, 203 const void *Decoder); 204 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 205 uint32_t insn, 206 uint64_t Address, 207 const void *Decoder); 208 template<int Bits> 209 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 210 uint64_t Address, const void *Decoder); 211 212 static bool Check(DecodeStatus &Out, DecodeStatus In) { 213 switch (In) { 214 case MCDisassembler::Success: 215 // Out stays the same. 216 return true; 217 case MCDisassembler::SoftFail: 218 Out = In; 219 return true; 220 case MCDisassembler::Fail: 221 Out = In; 222 return false; 223 } 224 llvm_unreachable("Invalid DecodeStatus!"); 225 } 226 227 #include "AArch64GenDisassemblerTables.inc" 228 #include "AArch64GenInstrInfo.inc" 229 230 #define Success MCDisassembler::Success 231 #define Fail MCDisassembler::Fail 232 #define SoftFail MCDisassembler::SoftFail 233 234 static MCDisassembler *createAArch64Disassembler(const Target &T, 235 const MCSubtargetInfo &STI, 236 MCContext &Ctx) { 237 return new AArch64Disassembler(STI, Ctx); 238 } 239 240 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 241 ArrayRef<uint8_t> Bytes, 242 uint64_t Address, 243 raw_ostream &OS, 244 raw_ostream &CS) const { 245 CommentStream = &CS; 246 247 Size = 0; 248 // We want to read exactly 4 bytes of data. 249 if (Bytes.size() < 4) 250 return Fail; 251 Size = 4; 252 253 // Encoded as a small-endian 32-bit word in the stream. 254 uint32_t Insn = 255 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 256 257 // Calling the auto-generated decoder function. 258 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 259 } 260 261 static MCSymbolizer * 262 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 263 LLVMSymbolLookupCallback SymbolLookUp, 264 void *DisInfo, MCContext *Ctx, 265 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 266 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 267 SymbolLookUp, DisInfo); 268 } 269 270 extern "C" void LLVMInitializeAArch64Disassembler() { 271 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 272 createAArch64Disassembler); 273 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 274 createAArch64Disassembler); 275 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 276 createAArch64ExternalSymbolizer); 277 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 278 createAArch64ExternalSymbolizer); 279 280 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 281 createAArch64Disassembler); 282 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 283 createAArch64ExternalSymbolizer); 284 } 285 286 static const unsigned FPR128DecoderTable[] = { 287 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 288 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 289 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 290 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 291 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 292 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 293 AArch64::Q30, AArch64::Q31 294 }; 295 296 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 297 uint64_t Addr, 298 const void *Decoder) { 299 if (RegNo > 31) 300 return Fail; 301 302 unsigned Register = FPR128DecoderTable[RegNo]; 303 Inst.addOperand(MCOperand::createReg(Register)); 304 return Success; 305 } 306 307 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 308 uint64_t Addr, 309 const void *Decoder) { 310 if (RegNo > 15) 311 return Fail; 312 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 313 } 314 315 static const unsigned FPR64DecoderTable[] = { 316 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 317 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 318 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 319 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 320 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 321 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 322 AArch64::D30, AArch64::D31 323 }; 324 325 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 326 uint64_t Addr, 327 const void *Decoder) { 328 if (RegNo > 31) 329 return Fail; 330 331 unsigned Register = FPR64DecoderTable[RegNo]; 332 Inst.addOperand(MCOperand::createReg(Register)); 333 return Success; 334 } 335 336 static const unsigned FPR32DecoderTable[] = { 337 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 338 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 339 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 340 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 341 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 342 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 343 AArch64::S30, AArch64::S31 344 }; 345 346 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 347 uint64_t Addr, 348 const void *Decoder) { 349 if (RegNo > 31) 350 return Fail; 351 352 unsigned Register = FPR32DecoderTable[RegNo]; 353 Inst.addOperand(MCOperand::createReg(Register)); 354 return Success; 355 } 356 357 static const unsigned FPR16DecoderTable[] = { 358 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 359 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 360 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 361 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 362 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 363 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 364 AArch64::H30, AArch64::H31 365 }; 366 367 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 368 uint64_t Addr, 369 const void *Decoder) { 370 if (RegNo > 31) 371 return Fail; 372 373 unsigned Register = FPR16DecoderTable[RegNo]; 374 Inst.addOperand(MCOperand::createReg(Register)); 375 return Success; 376 } 377 378 static const unsigned FPR8DecoderTable[] = { 379 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 380 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 381 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 382 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 383 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 384 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 385 AArch64::B30, AArch64::B31 386 }; 387 388 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 389 uint64_t Addr, 390 const void *Decoder) { 391 if (RegNo > 31) 392 return Fail; 393 394 unsigned Register = FPR8DecoderTable[RegNo]; 395 Inst.addOperand(MCOperand::createReg(Register)); 396 return Success; 397 } 398 399 static const unsigned GPR64DecoderTable[] = { 400 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 401 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 402 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 403 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 404 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 405 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 406 AArch64::LR, AArch64::XZR 407 }; 408 409 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 410 uint64_t Addr, 411 const void *Decoder) { 412 if (RegNo > 30) 413 return Fail; 414 415 unsigned Register = GPR64DecoderTable[RegNo]; 416 Inst.addOperand(MCOperand::createReg(Register)); 417 return Success; 418 } 419 420 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 421 uint64_t Addr, 422 const void *Decoder) { 423 if (RegNo > 31) 424 return Fail; 425 426 unsigned Register = GPR64DecoderTable[RegNo]; 427 Inst.addOperand(MCOperand::createReg(Register)); 428 return Success; 429 } 430 431 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 432 uint64_t Addr, 433 const void *Decoder) { 434 if (RegNo > 31) 435 return Fail; 436 unsigned Register = GPR64DecoderTable[RegNo]; 437 if (Register == AArch64::XZR) 438 Register = AArch64::SP; 439 Inst.addOperand(MCOperand::createReg(Register)); 440 return Success; 441 } 442 443 static const unsigned GPR32DecoderTable[] = { 444 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 445 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 446 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 447 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 448 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 449 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 450 AArch64::W30, AArch64::WZR 451 }; 452 453 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 454 uint64_t Addr, 455 const void *Decoder) { 456 if (RegNo > 31) 457 return Fail; 458 459 unsigned Register = GPR32DecoderTable[RegNo]; 460 Inst.addOperand(MCOperand::createReg(Register)); 461 return Success; 462 } 463 464 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 465 uint64_t Addr, 466 const void *Decoder) { 467 if (RegNo > 31) 468 return Fail; 469 470 unsigned Register = GPR32DecoderTable[RegNo]; 471 if (Register == AArch64::WZR) 472 Register = AArch64::WSP; 473 Inst.addOperand(MCOperand::createReg(Register)); 474 return Success; 475 } 476 static const unsigned ZPRDecoderTable[] = { 477 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 478 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 479 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 480 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 481 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 482 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 483 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 484 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 485 }; 486 487 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 488 uint64_t Address, 489 const void* Decoder) { 490 if (RegNo > 31) 491 return Fail; 492 493 unsigned Register = ZPRDecoderTable[RegNo]; 494 Inst.addOperand(MCOperand::createReg(Register)); 495 return Success; 496 } 497 498 static const unsigned ZZDecoderTable[] = { 499 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 500 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 501 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 502 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 503 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 504 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 505 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 506 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 507 }; 508 509 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 510 uint64_t Address, 511 const void* Decoder) { 512 if (RegNo > 31) 513 return Fail; 514 unsigned Register = ZZDecoderTable[RegNo]; 515 Inst.addOperand(MCOperand::createReg(Register)); 516 return Success; 517 } 518 519 static const unsigned ZZZDecoderTable[] = { 520 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 521 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 522 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 523 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 524 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 525 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 526 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 527 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 528 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 529 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 530 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 531 }; 532 533 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 534 uint64_t Address, 535 const void* Decoder) { 536 if (RegNo > 31) 537 return Fail; 538 unsigned Register = ZZZDecoderTable[RegNo]; 539 Inst.addOperand(MCOperand::createReg(Register)); 540 return Success; 541 } 542 543 static const unsigned ZZZZDecoderTable[] = { 544 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 545 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 546 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 547 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 548 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 549 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 550 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 551 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 552 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 553 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 554 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 555 }; 556 557 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 558 uint64_t Address, 559 const void* Decoder) { 560 if (RegNo > 31) 561 return Fail; 562 unsigned Register = ZZZZDecoderTable[RegNo]; 563 Inst.addOperand(MCOperand::createReg(Register)); 564 return Success; 565 } 566 567 static const unsigned PPRDecoderTable[] = { 568 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 569 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 570 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 571 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 572 }; 573 574 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 575 uint64_t Addr, const void *Decoder) { 576 if (RegNo > 15) 577 return Fail; 578 579 unsigned Register = PPRDecoderTable[RegNo]; 580 Inst.addOperand(MCOperand::createReg(Register)); 581 return Success; 582 } 583 584 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 585 uint64_t Addr, 586 const void* Decoder) { 587 if (RegNo > 7) 588 return Fail; 589 590 // Just reuse the PPR decode table 591 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 592 } 593 594 static const unsigned VectorDecoderTable[] = { 595 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 596 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 597 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 598 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 599 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 600 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 601 AArch64::Q30, AArch64::Q31 602 }; 603 604 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 605 uint64_t Addr, 606 const void *Decoder) { 607 if (RegNo > 31) 608 return Fail; 609 610 unsigned Register = VectorDecoderTable[RegNo]; 611 Inst.addOperand(MCOperand::createReg(Register)); 612 return Success; 613 } 614 615 static const unsigned QQDecoderTable[] = { 616 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 617 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 618 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 619 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 620 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 621 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 622 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 623 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 624 }; 625 626 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 627 uint64_t Addr, const void *Decoder) { 628 if (RegNo > 31) 629 return Fail; 630 unsigned Register = QQDecoderTable[RegNo]; 631 Inst.addOperand(MCOperand::createReg(Register)); 632 return Success; 633 } 634 635 static const unsigned QQQDecoderTable[] = { 636 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 637 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 638 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 639 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 640 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 641 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 642 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 643 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 644 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 645 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 646 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 647 }; 648 649 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 650 uint64_t Addr, const void *Decoder) { 651 if (RegNo > 31) 652 return Fail; 653 unsigned Register = QQQDecoderTable[RegNo]; 654 Inst.addOperand(MCOperand::createReg(Register)); 655 return Success; 656 } 657 658 static const unsigned QQQQDecoderTable[] = { 659 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 660 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 661 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 662 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 663 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 664 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 665 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 666 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 667 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 668 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 669 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 670 }; 671 672 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 673 uint64_t Addr, 674 const void *Decoder) { 675 if (RegNo > 31) 676 return Fail; 677 unsigned Register = QQQQDecoderTable[RegNo]; 678 Inst.addOperand(MCOperand::createReg(Register)); 679 return Success; 680 } 681 682 static const unsigned DDDecoderTable[] = { 683 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 684 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 685 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 686 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 687 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 688 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 689 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 690 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 691 }; 692 693 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 694 uint64_t Addr, const void *Decoder) { 695 if (RegNo > 31) 696 return Fail; 697 unsigned Register = DDDecoderTable[RegNo]; 698 Inst.addOperand(MCOperand::createReg(Register)); 699 return Success; 700 } 701 702 static const unsigned DDDDecoderTable[] = { 703 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 704 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 705 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 706 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 707 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 708 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 709 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 710 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 711 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 712 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 713 AArch64::D30_D31_D0, AArch64::D31_D0_D1 714 }; 715 716 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 717 uint64_t Addr, const void *Decoder) { 718 if (RegNo > 31) 719 return Fail; 720 unsigned Register = DDDDecoderTable[RegNo]; 721 Inst.addOperand(MCOperand::createReg(Register)); 722 return Success; 723 } 724 725 static const unsigned DDDDDecoderTable[] = { 726 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 727 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 728 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 729 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 730 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 731 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 732 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 733 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 734 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 735 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 736 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 737 }; 738 739 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 740 uint64_t Addr, 741 const void *Decoder) { 742 if (RegNo > 31) 743 return Fail; 744 unsigned Register = DDDDDecoderTable[RegNo]; 745 Inst.addOperand(MCOperand::createReg(Register)); 746 return Success; 747 } 748 749 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 750 uint64_t Addr, 751 const void *Decoder) { 752 // scale{5} is asserted as 1 in tblgen. 753 Imm |= 0x20; 754 Inst.addOperand(MCOperand::createImm(64 - Imm)); 755 return Success; 756 } 757 758 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 759 uint64_t Addr, 760 const void *Decoder) { 761 Inst.addOperand(MCOperand::createImm(64 - Imm)); 762 return Success; 763 } 764 765 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 766 uint64_t Addr, const void *Decoder) { 767 int64_t ImmVal = Imm; 768 const AArch64Disassembler *Dis = 769 static_cast<const AArch64Disassembler *>(Decoder); 770 771 // Sign-extend 19-bit immediate. 772 if (ImmVal & (1 << (19 - 1))) 773 ImmVal |= ~((1LL << 19) - 1); 774 775 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 776 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 777 Inst.addOperand(MCOperand::createImm(ImmVal)); 778 return Success; 779 } 780 781 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 782 uint64_t Address, const void *Decoder) { 783 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 784 Inst.addOperand(MCOperand::createImm(Imm & 1)); 785 return Success; 786 } 787 788 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 789 uint64_t Address, 790 const void *Decoder) { 791 Inst.addOperand(MCOperand::createImm(Imm)); 792 793 // Every system register in the encoding space is valid with the syntax 794 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 795 return Success; 796 } 797 798 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 799 uint64_t Address, 800 const void *Decoder) { 801 Inst.addOperand(MCOperand::createImm(Imm)); 802 803 return Success; 804 } 805 806 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 807 uint64_t Address, 808 const void *Decoder) { 809 // This decoder exists to add the dummy Lane operand to the MCInst, which must 810 // be 1 in assembly but has no other real manifestation. 811 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 812 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 813 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 814 815 if (IsToVec) { 816 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 817 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 818 } else { 819 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 820 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 821 } 822 823 // Add the lane 824 Inst.addOperand(MCOperand::createImm(1)); 825 826 return Success; 827 } 828 829 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 830 unsigned Add) { 831 Inst.addOperand(MCOperand::createImm(Add - Imm)); 832 return Success; 833 } 834 835 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 836 unsigned Add) { 837 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 838 return Success; 839 } 840 841 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 842 uint64_t Addr, const void *Decoder) { 843 return DecodeVecShiftRImm(Inst, Imm, 64); 844 } 845 846 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 847 uint64_t Addr, 848 const void *Decoder) { 849 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 850 } 851 852 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 853 uint64_t Addr, const void *Decoder) { 854 return DecodeVecShiftRImm(Inst, Imm, 32); 855 } 856 857 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 858 uint64_t Addr, 859 const void *Decoder) { 860 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 861 } 862 863 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 864 uint64_t Addr, const void *Decoder) { 865 return DecodeVecShiftRImm(Inst, Imm, 16); 866 } 867 868 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 869 uint64_t Addr, 870 const void *Decoder) { 871 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 872 } 873 874 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 875 uint64_t Addr, const void *Decoder) { 876 return DecodeVecShiftRImm(Inst, Imm, 8); 877 } 878 879 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 880 uint64_t Addr, const void *Decoder) { 881 return DecodeVecShiftLImm(Inst, Imm, 64); 882 } 883 884 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 885 uint64_t Addr, const void *Decoder) { 886 return DecodeVecShiftLImm(Inst, Imm, 32); 887 } 888 889 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 890 uint64_t Addr, const void *Decoder) { 891 return DecodeVecShiftLImm(Inst, Imm, 16); 892 } 893 894 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 895 uint64_t Addr, const void *Decoder) { 896 return DecodeVecShiftLImm(Inst, Imm, 8); 897 } 898 899 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 900 uint64_t Addr, 901 const void *Decoder) { 902 unsigned Rd = fieldFromInstruction(insn, 0, 5); 903 unsigned Rn = fieldFromInstruction(insn, 5, 5); 904 unsigned Rm = fieldFromInstruction(insn, 16, 5); 905 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 906 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 907 unsigned shift = (shiftHi << 6) | shiftLo; 908 switch (Inst.getOpcode()) { 909 default: 910 return Fail; 911 case AArch64::ADDWrs: 912 case AArch64::ADDSWrs: 913 case AArch64::SUBWrs: 914 case AArch64::SUBSWrs: 915 // if shift == '11' then ReservedValue() 916 if (shiftHi == 0x3) 917 return Fail; 918 LLVM_FALLTHROUGH; 919 case AArch64::ANDWrs: 920 case AArch64::ANDSWrs: 921 case AArch64::BICWrs: 922 case AArch64::BICSWrs: 923 case AArch64::ORRWrs: 924 case AArch64::ORNWrs: 925 case AArch64::EORWrs: 926 case AArch64::EONWrs: { 927 // if sf == '0' and imm6<5> == '1' then ReservedValue() 928 if (shiftLo >> 5 == 1) 929 return Fail; 930 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 931 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 932 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 933 break; 934 } 935 case AArch64::ADDXrs: 936 case AArch64::ADDSXrs: 937 case AArch64::SUBXrs: 938 case AArch64::SUBSXrs: 939 // if shift == '11' then ReservedValue() 940 if (shiftHi == 0x3) 941 return Fail; 942 LLVM_FALLTHROUGH; 943 case AArch64::ANDXrs: 944 case AArch64::ANDSXrs: 945 case AArch64::BICXrs: 946 case AArch64::BICSXrs: 947 case AArch64::ORRXrs: 948 case AArch64::ORNXrs: 949 case AArch64::EORXrs: 950 case AArch64::EONXrs: 951 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 952 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 953 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 954 break; 955 } 956 957 Inst.addOperand(MCOperand::createImm(shift)); 958 return Success; 959 } 960 961 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 962 uint64_t Addr, 963 const void *Decoder) { 964 unsigned Rd = fieldFromInstruction(insn, 0, 5); 965 unsigned imm = fieldFromInstruction(insn, 5, 16); 966 unsigned shift = fieldFromInstruction(insn, 21, 2); 967 shift <<= 4; 968 switch (Inst.getOpcode()) { 969 default: 970 return Fail; 971 case AArch64::MOVZWi: 972 case AArch64::MOVNWi: 973 case AArch64::MOVKWi: 974 if (shift & (1U << 5)) 975 return Fail; 976 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 977 break; 978 case AArch64::MOVZXi: 979 case AArch64::MOVNXi: 980 case AArch64::MOVKXi: 981 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 982 break; 983 } 984 985 if (Inst.getOpcode() == AArch64::MOVKWi || 986 Inst.getOpcode() == AArch64::MOVKXi) 987 Inst.addOperand(Inst.getOperand(0)); 988 989 Inst.addOperand(MCOperand::createImm(imm)); 990 Inst.addOperand(MCOperand::createImm(shift)); 991 return Success; 992 } 993 994 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 995 uint64_t Addr, 996 const void *Decoder) { 997 unsigned Rt = fieldFromInstruction(insn, 0, 5); 998 unsigned Rn = fieldFromInstruction(insn, 5, 5); 999 unsigned offset = fieldFromInstruction(insn, 10, 12); 1000 const AArch64Disassembler *Dis = 1001 static_cast<const AArch64Disassembler *>(Decoder); 1002 1003 switch (Inst.getOpcode()) { 1004 default: 1005 return Fail; 1006 case AArch64::PRFMui: 1007 // Rt is an immediate in prefetch. 1008 Inst.addOperand(MCOperand::createImm(Rt)); 1009 break; 1010 case AArch64::STRBBui: 1011 case AArch64::LDRBBui: 1012 case AArch64::LDRSBWui: 1013 case AArch64::STRHHui: 1014 case AArch64::LDRHHui: 1015 case AArch64::LDRSHWui: 1016 case AArch64::STRWui: 1017 case AArch64::LDRWui: 1018 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1019 break; 1020 case AArch64::LDRSBXui: 1021 case AArch64::LDRSHXui: 1022 case AArch64::LDRSWui: 1023 case AArch64::STRXui: 1024 case AArch64::LDRXui: 1025 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1026 break; 1027 case AArch64::LDRQui: 1028 case AArch64::STRQui: 1029 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1030 break; 1031 case AArch64::LDRDui: 1032 case AArch64::STRDui: 1033 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1034 break; 1035 case AArch64::LDRSui: 1036 case AArch64::STRSui: 1037 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1038 break; 1039 case AArch64::LDRHui: 1040 case AArch64::STRHui: 1041 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1042 break; 1043 case AArch64::LDRBui: 1044 case AArch64::STRBui: 1045 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1046 break; 1047 } 1048 1049 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1050 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1051 Inst.addOperand(MCOperand::createImm(offset)); 1052 return Success; 1053 } 1054 1055 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1056 uint64_t Addr, 1057 const void *Decoder) { 1058 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1059 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1060 int64_t offset = fieldFromInstruction(insn, 12, 9); 1061 1062 // offset is a 9-bit signed immediate, so sign extend it to 1063 // fill the unsigned. 1064 if (offset & (1 << (9 - 1))) 1065 offset |= ~((1LL << 9) - 1); 1066 1067 // First operand is always the writeback to the address register, if needed. 1068 switch (Inst.getOpcode()) { 1069 default: 1070 break; 1071 case AArch64::LDRSBWpre: 1072 case AArch64::LDRSHWpre: 1073 case AArch64::STRBBpre: 1074 case AArch64::LDRBBpre: 1075 case AArch64::STRHHpre: 1076 case AArch64::LDRHHpre: 1077 case AArch64::STRWpre: 1078 case AArch64::LDRWpre: 1079 case AArch64::LDRSBWpost: 1080 case AArch64::LDRSHWpost: 1081 case AArch64::STRBBpost: 1082 case AArch64::LDRBBpost: 1083 case AArch64::STRHHpost: 1084 case AArch64::LDRHHpost: 1085 case AArch64::STRWpost: 1086 case AArch64::LDRWpost: 1087 case AArch64::LDRSBXpre: 1088 case AArch64::LDRSHXpre: 1089 case AArch64::STRXpre: 1090 case AArch64::LDRSWpre: 1091 case AArch64::LDRXpre: 1092 case AArch64::LDRSBXpost: 1093 case AArch64::LDRSHXpost: 1094 case AArch64::STRXpost: 1095 case AArch64::LDRSWpost: 1096 case AArch64::LDRXpost: 1097 case AArch64::LDRQpre: 1098 case AArch64::STRQpre: 1099 case AArch64::LDRQpost: 1100 case AArch64::STRQpost: 1101 case AArch64::LDRDpre: 1102 case AArch64::STRDpre: 1103 case AArch64::LDRDpost: 1104 case AArch64::STRDpost: 1105 case AArch64::LDRSpre: 1106 case AArch64::STRSpre: 1107 case AArch64::LDRSpost: 1108 case AArch64::STRSpost: 1109 case AArch64::LDRHpre: 1110 case AArch64::STRHpre: 1111 case AArch64::LDRHpost: 1112 case AArch64::STRHpost: 1113 case AArch64::LDRBpre: 1114 case AArch64::STRBpre: 1115 case AArch64::LDRBpost: 1116 case AArch64::STRBpost: 1117 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1118 break; 1119 } 1120 1121 switch (Inst.getOpcode()) { 1122 default: 1123 return Fail; 1124 case AArch64::PRFUMi: 1125 // Rt is an immediate in prefetch. 1126 Inst.addOperand(MCOperand::createImm(Rt)); 1127 break; 1128 case AArch64::STURBBi: 1129 case AArch64::LDURBBi: 1130 case AArch64::LDURSBWi: 1131 case AArch64::STURHHi: 1132 case AArch64::LDURHHi: 1133 case AArch64::LDURSHWi: 1134 case AArch64::STURWi: 1135 case AArch64::LDURWi: 1136 case AArch64::LDTRSBWi: 1137 case AArch64::LDTRSHWi: 1138 case AArch64::STTRWi: 1139 case AArch64::LDTRWi: 1140 case AArch64::STTRHi: 1141 case AArch64::LDTRHi: 1142 case AArch64::LDTRBi: 1143 case AArch64::STTRBi: 1144 case AArch64::LDRSBWpre: 1145 case AArch64::LDRSHWpre: 1146 case AArch64::STRBBpre: 1147 case AArch64::LDRBBpre: 1148 case AArch64::STRHHpre: 1149 case AArch64::LDRHHpre: 1150 case AArch64::STRWpre: 1151 case AArch64::LDRWpre: 1152 case AArch64::LDRSBWpost: 1153 case AArch64::LDRSHWpost: 1154 case AArch64::STRBBpost: 1155 case AArch64::LDRBBpost: 1156 case AArch64::STRHHpost: 1157 case AArch64::LDRHHpost: 1158 case AArch64::STRWpost: 1159 case AArch64::LDRWpost: 1160 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1161 break; 1162 case AArch64::LDURSBXi: 1163 case AArch64::LDURSHXi: 1164 case AArch64::LDURSWi: 1165 case AArch64::STURXi: 1166 case AArch64::LDURXi: 1167 case AArch64::LDTRSBXi: 1168 case AArch64::LDTRSHXi: 1169 case AArch64::LDTRSWi: 1170 case AArch64::STTRXi: 1171 case AArch64::LDTRXi: 1172 case AArch64::LDRSBXpre: 1173 case AArch64::LDRSHXpre: 1174 case AArch64::STRXpre: 1175 case AArch64::LDRSWpre: 1176 case AArch64::LDRXpre: 1177 case AArch64::LDRSBXpost: 1178 case AArch64::LDRSHXpost: 1179 case AArch64::STRXpost: 1180 case AArch64::LDRSWpost: 1181 case AArch64::LDRXpost: 1182 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1183 break; 1184 case AArch64::LDURQi: 1185 case AArch64::STURQi: 1186 case AArch64::LDRQpre: 1187 case AArch64::STRQpre: 1188 case AArch64::LDRQpost: 1189 case AArch64::STRQpost: 1190 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1191 break; 1192 case AArch64::LDURDi: 1193 case AArch64::STURDi: 1194 case AArch64::LDRDpre: 1195 case AArch64::STRDpre: 1196 case AArch64::LDRDpost: 1197 case AArch64::STRDpost: 1198 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1199 break; 1200 case AArch64::LDURSi: 1201 case AArch64::STURSi: 1202 case AArch64::LDRSpre: 1203 case AArch64::STRSpre: 1204 case AArch64::LDRSpost: 1205 case AArch64::STRSpost: 1206 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1207 break; 1208 case AArch64::LDURHi: 1209 case AArch64::STURHi: 1210 case AArch64::LDRHpre: 1211 case AArch64::STRHpre: 1212 case AArch64::LDRHpost: 1213 case AArch64::STRHpost: 1214 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1215 break; 1216 case AArch64::LDURBi: 1217 case AArch64::STURBi: 1218 case AArch64::LDRBpre: 1219 case AArch64::STRBpre: 1220 case AArch64::LDRBpost: 1221 case AArch64::STRBpost: 1222 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1223 break; 1224 } 1225 1226 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1227 Inst.addOperand(MCOperand::createImm(offset)); 1228 1229 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1230 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1231 bool IsFP = fieldFromInstruction(insn, 26, 1); 1232 1233 // Cannot write back to a transfer register (but xzr != sp). 1234 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1235 return SoftFail; 1236 1237 return Success; 1238 } 1239 1240 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1241 uint64_t Addr, 1242 const void *Decoder) { 1243 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1244 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1245 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1246 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1247 1248 unsigned Opcode = Inst.getOpcode(); 1249 switch (Opcode) { 1250 default: 1251 return Fail; 1252 case AArch64::STLXRW: 1253 case AArch64::STLXRB: 1254 case AArch64::STLXRH: 1255 case AArch64::STXRW: 1256 case AArch64::STXRB: 1257 case AArch64::STXRH: 1258 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1259 LLVM_FALLTHROUGH; 1260 case AArch64::LDARW: 1261 case AArch64::LDARB: 1262 case AArch64::LDARH: 1263 case AArch64::LDAXRW: 1264 case AArch64::LDAXRB: 1265 case AArch64::LDAXRH: 1266 case AArch64::LDXRW: 1267 case AArch64::LDXRB: 1268 case AArch64::LDXRH: 1269 case AArch64::STLRW: 1270 case AArch64::STLRB: 1271 case AArch64::STLRH: 1272 case AArch64::STLLRW: 1273 case AArch64::STLLRB: 1274 case AArch64::STLLRH: 1275 case AArch64::LDLARW: 1276 case AArch64::LDLARB: 1277 case AArch64::LDLARH: 1278 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1279 break; 1280 case AArch64::STLXRX: 1281 case AArch64::STXRX: 1282 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1283 LLVM_FALLTHROUGH; 1284 case AArch64::LDARX: 1285 case AArch64::LDAXRX: 1286 case AArch64::LDXRX: 1287 case AArch64::STLRX: 1288 case AArch64::LDLARX: 1289 case AArch64::STLLRX: 1290 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1291 break; 1292 case AArch64::STLXPW: 1293 case AArch64::STXPW: 1294 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1295 LLVM_FALLTHROUGH; 1296 case AArch64::LDAXPW: 1297 case AArch64::LDXPW: 1298 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1299 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1300 break; 1301 case AArch64::STLXPX: 1302 case AArch64::STXPX: 1303 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1304 LLVM_FALLTHROUGH; 1305 case AArch64::LDAXPX: 1306 case AArch64::LDXPX: 1307 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1308 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1309 break; 1310 } 1311 1312 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1313 1314 // You shouldn't load to the same register twice in an instruction... 1315 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1316 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1317 Rt == Rt2) 1318 return SoftFail; 1319 1320 return Success; 1321 } 1322 1323 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1324 uint64_t Addr, 1325 const void *Decoder) { 1326 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1327 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1328 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1329 int64_t offset = fieldFromInstruction(insn, 15, 7); 1330 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1331 1332 // offset is a 7-bit signed immediate, so sign extend it to 1333 // fill the unsigned. 1334 if (offset & (1 << (7 - 1))) 1335 offset |= ~((1LL << 7) - 1); 1336 1337 unsigned Opcode = Inst.getOpcode(); 1338 bool NeedsDisjointWritebackTransfer = false; 1339 1340 // First operand is always writeback of base register. 1341 switch (Opcode) { 1342 default: 1343 break; 1344 case AArch64::LDPXpost: 1345 case AArch64::STPXpost: 1346 case AArch64::LDPSWpost: 1347 case AArch64::LDPXpre: 1348 case AArch64::STPXpre: 1349 case AArch64::LDPSWpre: 1350 case AArch64::LDPWpost: 1351 case AArch64::STPWpost: 1352 case AArch64::LDPWpre: 1353 case AArch64::STPWpre: 1354 case AArch64::LDPQpost: 1355 case AArch64::STPQpost: 1356 case AArch64::LDPQpre: 1357 case AArch64::STPQpre: 1358 case AArch64::LDPDpost: 1359 case AArch64::STPDpost: 1360 case AArch64::LDPDpre: 1361 case AArch64::STPDpre: 1362 case AArch64::LDPSpost: 1363 case AArch64::STPSpost: 1364 case AArch64::LDPSpre: 1365 case AArch64::STPSpre: 1366 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1367 break; 1368 } 1369 1370 switch (Opcode) { 1371 default: 1372 return Fail; 1373 case AArch64::LDPXpost: 1374 case AArch64::STPXpost: 1375 case AArch64::LDPSWpost: 1376 case AArch64::LDPXpre: 1377 case AArch64::STPXpre: 1378 case AArch64::LDPSWpre: 1379 NeedsDisjointWritebackTransfer = true; 1380 LLVM_FALLTHROUGH; 1381 case AArch64::LDNPXi: 1382 case AArch64::STNPXi: 1383 case AArch64::LDPXi: 1384 case AArch64::STPXi: 1385 case AArch64::LDPSWi: 1386 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1387 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1388 break; 1389 case AArch64::LDPWpost: 1390 case AArch64::STPWpost: 1391 case AArch64::LDPWpre: 1392 case AArch64::STPWpre: 1393 NeedsDisjointWritebackTransfer = true; 1394 LLVM_FALLTHROUGH; 1395 case AArch64::LDNPWi: 1396 case AArch64::STNPWi: 1397 case AArch64::LDPWi: 1398 case AArch64::STPWi: 1399 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1400 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1401 break; 1402 case AArch64::LDNPQi: 1403 case AArch64::STNPQi: 1404 case AArch64::LDPQpost: 1405 case AArch64::STPQpost: 1406 case AArch64::LDPQi: 1407 case AArch64::STPQi: 1408 case AArch64::LDPQpre: 1409 case AArch64::STPQpre: 1410 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1411 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1412 break; 1413 case AArch64::LDNPDi: 1414 case AArch64::STNPDi: 1415 case AArch64::LDPDpost: 1416 case AArch64::STPDpost: 1417 case AArch64::LDPDi: 1418 case AArch64::STPDi: 1419 case AArch64::LDPDpre: 1420 case AArch64::STPDpre: 1421 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1422 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1423 break; 1424 case AArch64::LDNPSi: 1425 case AArch64::STNPSi: 1426 case AArch64::LDPSpost: 1427 case AArch64::STPSpost: 1428 case AArch64::LDPSi: 1429 case AArch64::STPSi: 1430 case AArch64::LDPSpre: 1431 case AArch64::STPSpre: 1432 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1433 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1434 break; 1435 } 1436 1437 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1438 Inst.addOperand(MCOperand::createImm(offset)); 1439 1440 // You shouldn't load to the same register twice in an instruction... 1441 if (IsLoad && Rt == Rt2) 1442 return SoftFail; 1443 1444 // ... or do any operation that writes-back to a transfer register. But note 1445 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1446 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1447 return SoftFail; 1448 1449 return Success; 1450 } 1451 1452 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1453 uint64_t Addr, 1454 const void *Decoder) { 1455 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1456 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1457 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1458 unsigned extend = fieldFromInstruction(insn, 10, 6); 1459 1460 unsigned shift = extend & 0x7; 1461 if (shift > 4) 1462 return Fail; 1463 1464 switch (Inst.getOpcode()) { 1465 default: 1466 return Fail; 1467 case AArch64::ADDWrx: 1468 case AArch64::SUBWrx: 1469 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1470 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1471 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1472 break; 1473 case AArch64::ADDSWrx: 1474 case AArch64::SUBSWrx: 1475 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1476 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1477 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1478 break; 1479 case AArch64::ADDXrx: 1480 case AArch64::SUBXrx: 1481 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1482 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1483 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1484 break; 1485 case AArch64::ADDSXrx: 1486 case AArch64::SUBSXrx: 1487 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1488 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1489 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1490 break; 1491 case AArch64::ADDXrx64: 1492 case AArch64::SUBXrx64: 1493 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1494 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1495 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1496 break; 1497 case AArch64::SUBSXrx64: 1498 case AArch64::ADDSXrx64: 1499 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1500 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1501 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1502 break; 1503 } 1504 1505 Inst.addOperand(MCOperand::createImm(extend)); 1506 return Success; 1507 } 1508 1509 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1510 uint64_t Addr, 1511 const void *Decoder) { 1512 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1513 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1514 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1515 unsigned imm; 1516 1517 if (Datasize) { 1518 if (Inst.getOpcode() == AArch64::ANDSXri) 1519 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1520 else 1521 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1522 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1523 imm = fieldFromInstruction(insn, 10, 13); 1524 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1525 return Fail; 1526 } else { 1527 if (Inst.getOpcode() == AArch64::ANDSWri) 1528 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1529 else 1530 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1531 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1532 imm = fieldFromInstruction(insn, 10, 12); 1533 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1534 return Fail; 1535 } 1536 Inst.addOperand(MCOperand::createImm(imm)); 1537 return Success; 1538 } 1539 1540 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1541 uint64_t Addr, 1542 const void *Decoder) { 1543 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1544 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1545 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1546 imm |= fieldFromInstruction(insn, 5, 5); 1547 1548 if (Inst.getOpcode() == AArch64::MOVID) 1549 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1550 else 1551 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1552 1553 Inst.addOperand(MCOperand::createImm(imm)); 1554 1555 switch (Inst.getOpcode()) { 1556 default: 1557 break; 1558 case AArch64::MOVIv4i16: 1559 case AArch64::MOVIv8i16: 1560 case AArch64::MVNIv4i16: 1561 case AArch64::MVNIv8i16: 1562 case AArch64::MOVIv2i32: 1563 case AArch64::MOVIv4i32: 1564 case AArch64::MVNIv2i32: 1565 case AArch64::MVNIv4i32: 1566 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1567 break; 1568 case AArch64::MOVIv2s_msl: 1569 case AArch64::MOVIv4s_msl: 1570 case AArch64::MVNIv2s_msl: 1571 case AArch64::MVNIv4s_msl: 1572 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1573 break; 1574 } 1575 1576 return Success; 1577 } 1578 1579 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1580 uint64_t Addr, 1581 const void *Decoder) { 1582 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1583 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1584 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1585 imm |= fieldFromInstruction(insn, 5, 5); 1586 1587 // Tied operands added twice. 1588 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1589 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1590 1591 Inst.addOperand(MCOperand::createImm(imm)); 1592 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1593 1594 return Success; 1595 } 1596 1597 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1598 uint64_t Addr, const void *Decoder) { 1599 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1600 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1601 imm |= fieldFromInstruction(insn, 29, 2); 1602 const AArch64Disassembler *Dis = 1603 static_cast<const AArch64Disassembler *>(Decoder); 1604 1605 // Sign-extend the 21-bit immediate. 1606 if (imm & (1 << (21 - 1))) 1607 imm |= ~((1LL << 21) - 1); 1608 1609 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1610 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1611 Inst.addOperand(MCOperand::createImm(imm)); 1612 1613 return Success; 1614 } 1615 1616 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1617 uint64_t Addr, const void *Decoder) { 1618 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1619 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1620 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1621 unsigned S = fieldFromInstruction(insn, 29, 1); 1622 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1623 1624 unsigned ShifterVal = (Imm >> 12) & 3; 1625 unsigned ImmVal = Imm & 0xFFF; 1626 const AArch64Disassembler *Dis = 1627 static_cast<const AArch64Disassembler *>(Decoder); 1628 1629 if (ShifterVal != 0 && ShifterVal != 1) 1630 return Fail; 1631 1632 if (Datasize) { 1633 if (Rd == 31 && !S) 1634 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1635 else 1636 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1637 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1638 } else { 1639 if (Rd == 31 && !S) 1640 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1641 else 1642 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1643 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1644 } 1645 1646 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1647 Inst.addOperand(MCOperand::createImm(ImmVal)); 1648 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1649 return Success; 1650 } 1651 1652 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1653 uint64_t Addr, 1654 const void *Decoder) { 1655 int64_t imm = fieldFromInstruction(insn, 0, 26); 1656 const AArch64Disassembler *Dis = 1657 static_cast<const AArch64Disassembler *>(Decoder); 1658 1659 // Sign-extend the 26-bit immediate. 1660 if (imm & (1 << (26 - 1))) 1661 imm |= ~((1LL << 26) - 1); 1662 1663 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1664 Inst.addOperand(MCOperand::createImm(imm)); 1665 1666 return Success; 1667 } 1668 1669 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1670 uint64_t Addr, 1671 const void *Decoder) { 1672 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1673 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1674 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1675 1676 uint64_t pstate_field = (op1 << 3) | op2; 1677 1678 if ((pstate_field == AArch64PState::PAN || 1679 pstate_field == AArch64PState::UAO) && crm > 1) 1680 return Fail; 1681 1682 Inst.addOperand(MCOperand::createImm(pstate_field)); 1683 Inst.addOperand(MCOperand::createImm(crm)); 1684 1685 const AArch64Disassembler *Dis = 1686 static_cast<const AArch64Disassembler *>(Decoder); 1687 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1688 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1689 return Success; 1690 return Fail; 1691 } 1692 1693 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1694 uint64_t Addr, const void *Decoder) { 1695 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1696 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1697 bit |= fieldFromInstruction(insn, 19, 5); 1698 int64_t dst = fieldFromInstruction(insn, 5, 14); 1699 const AArch64Disassembler *Dis = 1700 static_cast<const AArch64Disassembler *>(Decoder); 1701 1702 // Sign-extend 14-bit immediate. 1703 if (dst & (1 << (14 - 1))) 1704 dst |= ~((1LL << 14) - 1); 1705 1706 if (fieldFromInstruction(insn, 31, 1) == 0) 1707 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1708 else 1709 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1710 Inst.addOperand(MCOperand::createImm(bit)); 1711 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1712 Inst.addOperand(MCOperand::createImm(dst)); 1713 1714 return Success; 1715 } 1716 1717 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1718 unsigned RegClassID, 1719 unsigned RegNo, 1720 uint64_t Addr, 1721 const void *Decoder) { 1722 // Register number must be even (see CASP instruction) 1723 if (RegNo & 0x1) 1724 return Fail; 1725 1726 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1727 Inst.addOperand(MCOperand::createReg(Register)); 1728 return Success; 1729 } 1730 1731 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1732 unsigned RegNo, 1733 uint64_t Addr, 1734 const void *Decoder) { 1735 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1736 AArch64::WSeqPairsClassRegClassID, 1737 RegNo, Addr, Decoder); 1738 } 1739 1740 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1741 unsigned RegNo, 1742 uint64_t Addr, 1743 const void *Decoder) { 1744 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1745 AArch64::XSeqPairsClassRegClassID, 1746 RegNo, Addr, Decoder); 1747 } 1748 1749 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1750 uint32_t insn, 1751 uint64_t Addr, 1752 const void *Decoder) { 1753 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1754 unsigned imm = fieldFromInstruction(insn, 5, 13); 1755 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1756 return Fail; 1757 1758 // The same (tied) operand is added twice to the instruction. 1759 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1760 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1761 Inst.addOperand(MCOperand::createImm(imm)); 1762 return Success; 1763 } 1764 1765 template<int Bits> 1766 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1767 uint64_t Address, const void *Decoder) { 1768 if (Imm & ~((1LL << Bits) - 1)) 1769 return Fail; 1770 1771 // Imm is a signed immediate, so sign extend it. 1772 if (Imm & (1 << (Bits - 1))) 1773 Imm |= ~((1LL << Bits) - 1); 1774 1775 Inst.addOperand(MCOperand::createImm(Imm)); 1776 return Success; 1777 } 1778 1779