1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 80 unsigned RegNo, uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 template <unsigned NumBitsForTile> 119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 129 uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 132 uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 143 uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 152 uint64_t Address, 153 const void *Decoder); 154 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 155 uint64_t Address, 156 const void *Decoder); 157 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 158 uint64_t Address, 159 const void *Decoder); 160 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 161 uint64_t Address, 162 const void *Decoder); 163 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 164 uint64_t Address, 165 const void *Decoder); 166 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 167 uint64_t Address, 168 const void *Decoder); 169 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 170 uint64_t Address, 171 const void *Decoder); 172 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 173 uint64_t Address, 174 const void *Decoder); 175 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 180 uint64_t Address, 181 const void *Decoder); 182 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 183 uint64_t Address, 184 const void *Decoder); 185 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 186 uint64_t Address, const void *Decoder); 187 188 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 189 uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, const void *Decoder); 193 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 194 uint64_t Addr, 195 const void *Decoder); 196 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, const void *Decoder); 198 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const void *Decoder); 201 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 202 uint64_t Addr, const void *Decoder); 203 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, 205 const void *Decoder); 206 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 207 uint64_t Addr, const void *Decoder); 208 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 209 uint64_t Addr, const void *Decoder); 210 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, const void *Decoder); 214 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, const void *Decoder); 216 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 217 unsigned RegNo, 218 uint64_t Addr, 219 const void *Decoder); 220 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Addr, 223 const void *Decoder); 224 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 225 uint32_t insn, 226 uint64_t Address, 227 const void *Decoder); 228 template<int Bits> 229 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 230 uint64_t Address, const void *Decoder); 231 template <int ElementWidth> 232 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 233 uint64_t Addr, const void *Decoder); 234 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 235 uint64_t Addr, const void *Decoder); 236 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 237 const void *Decoder); 238 239 static bool Check(DecodeStatus &Out, DecodeStatus In) { 240 switch (In) { 241 case MCDisassembler::Success: 242 // Out stays the same. 243 return true; 244 case MCDisassembler::SoftFail: 245 Out = In; 246 return true; 247 case MCDisassembler::Fail: 248 Out = In; 249 return false; 250 } 251 llvm_unreachable("Invalid DecodeStatus!"); 252 } 253 254 #include "AArch64GenDisassemblerTables.inc" 255 #include "AArch64GenInstrInfo.inc" 256 257 #define Success MCDisassembler::Success 258 #define Fail MCDisassembler::Fail 259 #define SoftFail MCDisassembler::SoftFail 260 261 static MCDisassembler *createAArch64Disassembler(const Target &T, 262 const MCSubtargetInfo &STI, 263 MCContext &Ctx) { 264 return new AArch64Disassembler(STI, Ctx); 265 } 266 267 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 268 ArrayRef<uint8_t> Bytes, 269 uint64_t Address, 270 raw_ostream &CS) const { 271 CommentStream = &CS; 272 273 Size = 0; 274 // We want to read exactly 4 bytes of data. 275 if (Bytes.size() < 4) 276 return Fail; 277 Size = 4; 278 279 // Encoded as a small-endian 32-bit word in the stream. 280 uint32_t Insn = 281 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 282 283 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 284 285 for (auto Table : Tables) { 286 DecodeStatus Result = 287 decodeInstruction(Table, MI, Insn, Address, this, STI); 288 289 switch (MI.getOpcode()) { 290 default: 291 break; 292 // For Scalable Matrix Extension (SME) instructions that have an implicit 293 // operand for the accumulator (ZA) which isn't encoded, manually insert 294 // operand. 295 case AArch64::LD1_MXIPXX_H_B: 296 case AArch64::LD1_MXIPXX_V_B: 297 case AArch64::ST1_MXIPXX_H_B: 298 case AArch64::ST1_MXIPXX_V_B: 299 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 300 break; 301 } 302 303 if (Result != MCDisassembler::Fail) 304 return Result; 305 } 306 307 return MCDisassembler::Fail; 308 } 309 310 static MCSymbolizer * 311 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 312 LLVMSymbolLookupCallback SymbolLookUp, 313 void *DisInfo, MCContext *Ctx, 314 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 315 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 316 SymbolLookUp, DisInfo); 317 } 318 319 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 320 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 321 createAArch64Disassembler); 322 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 323 createAArch64Disassembler); 324 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 325 createAArch64ExternalSymbolizer); 326 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 327 createAArch64ExternalSymbolizer); 328 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 329 createAArch64Disassembler); 330 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 331 createAArch64ExternalSymbolizer); 332 333 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 334 createAArch64Disassembler); 335 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 336 createAArch64ExternalSymbolizer); 337 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 338 createAArch64Disassembler); 339 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 340 createAArch64ExternalSymbolizer); 341 } 342 343 static const unsigned FPR128DecoderTable[] = { 344 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 345 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 346 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 347 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 348 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 349 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 350 AArch64::Q30, AArch64::Q31 351 }; 352 353 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 354 uint64_t Addr, 355 const void *Decoder) { 356 if (RegNo > 31) 357 return Fail; 358 359 unsigned Register = FPR128DecoderTable[RegNo]; 360 Inst.addOperand(MCOperand::createReg(Register)); 361 return Success; 362 } 363 364 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 365 uint64_t Addr, 366 const void *Decoder) { 367 if (RegNo > 15) 368 return Fail; 369 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 370 } 371 372 static const unsigned FPR64DecoderTable[] = { 373 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 374 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 375 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 376 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 377 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 378 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 379 AArch64::D30, AArch64::D31 380 }; 381 382 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 383 uint64_t Addr, 384 const void *Decoder) { 385 if (RegNo > 31) 386 return Fail; 387 388 unsigned Register = FPR64DecoderTable[RegNo]; 389 Inst.addOperand(MCOperand::createReg(Register)); 390 return Success; 391 } 392 393 static const unsigned FPR32DecoderTable[] = { 394 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 395 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 396 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 397 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 398 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 399 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 400 AArch64::S30, AArch64::S31 401 }; 402 403 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 404 uint64_t Addr, 405 const void *Decoder) { 406 if (RegNo > 31) 407 return Fail; 408 409 unsigned Register = FPR32DecoderTable[RegNo]; 410 Inst.addOperand(MCOperand::createReg(Register)); 411 return Success; 412 } 413 414 static const unsigned FPR16DecoderTable[] = { 415 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 416 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 417 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 418 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 419 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 420 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 421 AArch64::H30, AArch64::H31 422 }; 423 424 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 425 uint64_t Addr, 426 const void *Decoder) { 427 if (RegNo > 31) 428 return Fail; 429 430 unsigned Register = FPR16DecoderTable[RegNo]; 431 Inst.addOperand(MCOperand::createReg(Register)); 432 return Success; 433 } 434 435 static const unsigned FPR8DecoderTable[] = { 436 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 437 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 438 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 439 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 440 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 441 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 442 AArch64::B30, AArch64::B31 443 }; 444 445 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 446 uint64_t Addr, 447 const void *Decoder) { 448 if (RegNo > 31) 449 return Fail; 450 451 unsigned Register = FPR8DecoderTable[RegNo]; 452 Inst.addOperand(MCOperand::createReg(Register)); 453 return Success; 454 } 455 456 static const unsigned GPR64DecoderTable[] = { 457 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 458 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 459 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 460 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 461 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 462 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 463 AArch64::LR, AArch64::XZR 464 }; 465 466 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 467 uint64_t Addr, 468 const void *Decoder) { 469 if (RegNo > 30) 470 return Fail; 471 472 unsigned Register = GPR64DecoderTable[RegNo]; 473 Inst.addOperand(MCOperand::createReg(Register)); 474 return Success; 475 } 476 477 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 478 uint64_t Addr, 479 const void *Decoder) { 480 if (RegNo > 31) 481 return Fail; 482 483 unsigned Register = GPR64DecoderTable[RegNo]; 484 Inst.addOperand(MCOperand::createReg(Register)); 485 return Success; 486 } 487 488 static const unsigned GPR64x8DecoderTable[] = { 489 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 490 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 491 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 492 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 493 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 494 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 495 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 496 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 497 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 498 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 499 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 500 AArch64::X22_X23_X24_X25_X26_X27_X28_FP, 501 }; 502 503 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 504 unsigned RegNo, 505 uint64_t Address, 506 const void *Decoder) { 507 if (RegNo > 22) 508 return Fail; 509 if (RegNo & 1) 510 return Fail; 511 512 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 513 Inst.addOperand(MCOperand::createReg(Register)); 514 return Success; 515 } 516 517 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 518 uint64_t Addr, 519 const void *Decoder) { 520 if (RegNo > 31) 521 return Fail; 522 unsigned Register = GPR64DecoderTable[RegNo]; 523 if (Register == AArch64::XZR) 524 Register = AArch64::SP; 525 Inst.addOperand(MCOperand::createReg(Register)); 526 return Success; 527 } 528 529 static const unsigned MatrixIndexGPR32_12_15DecoderTable[] = { 530 AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15 531 }; 532 533 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 534 unsigned RegNo, 535 uint64_t Addr, 536 const void *Decoder) { 537 if (RegNo > 3) 538 return Fail; 539 540 unsigned Register = MatrixIndexGPR32_12_15DecoderTable[RegNo]; 541 Inst.addOperand(MCOperand::createReg(Register)); 542 return Success; 543 } 544 545 static const unsigned GPR32DecoderTable[] = { 546 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 547 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 548 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 549 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 550 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 551 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 552 AArch64::W30, AArch64::WZR 553 }; 554 555 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 556 uint64_t Addr, 557 const void *Decoder) { 558 if (RegNo > 31) 559 return Fail; 560 561 unsigned Register = GPR32DecoderTable[RegNo]; 562 Inst.addOperand(MCOperand::createReg(Register)); 563 return Success; 564 } 565 566 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 567 uint64_t Addr, 568 const void *Decoder) { 569 if (RegNo > 31) 570 return Fail; 571 572 unsigned Register = GPR32DecoderTable[RegNo]; 573 if (Register == AArch64::WZR) 574 Register = AArch64::WSP; 575 Inst.addOperand(MCOperand::createReg(Register)); 576 return Success; 577 } 578 static const unsigned ZPRDecoderTable[] = { 579 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 580 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 581 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 582 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 583 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 584 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 585 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 586 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 587 }; 588 589 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 590 uint64_t Address, 591 const void* Decoder) { 592 if (RegNo > 31) 593 return Fail; 594 595 unsigned Register = ZPRDecoderTable[RegNo]; 596 Inst.addOperand(MCOperand::createReg(Register)); 597 return Success; 598 } 599 600 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 601 uint64_t Address, 602 const void *Decoder) { 603 if (RegNo > 15) 604 return Fail; 605 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 606 } 607 608 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 609 uint64_t Address, 610 const void *Decoder) { 611 if (RegNo > 7) 612 return Fail; 613 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 614 } 615 616 static const unsigned ZZDecoderTable[] = { 617 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 618 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 619 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 620 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 621 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 622 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 623 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 624 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 625 }; 626 627 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 628 uint64_t Address, 629 const void* Decoder) { 630 if (RegNo > 31) 631 return Fail; 632 unsigned Register = ZZDecoderTable[RegNo]; 633 Inst.addOperand(MCOperand::createReg(Register)); 634 return Success; 635 } 636 637 static const unsigned ZZZDecoderTable[] = { 638 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 639 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 640 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 641 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 642 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 643 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 644 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 645 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 646 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 647 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 648 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 649 }; 650 651 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 652 uint64_t Address, 653 const void* Decoder) { 654 if (RegNo > 31) 655 return Fail; 656 unsigned Register = ZZZDecoderTable[RegNo]; 657 Inst.addOperand(MCOperand::createReg(Register)); 658 return Success; 659 } 660 661 static const unsigned ZZZZDecoderTable[] = { 662 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 663 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 664 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 665 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 666 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 667 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 668 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 669 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 670 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 671 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 672 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 673 }; 674 675 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 676 uint64_t Address, 677 const void* Decoder) { 678 if (RegNo > 31) 679 return Fail; 680 unsigned Register = ZZZZDecoderTable[RegNo]; 681 Inst.addOperand(MCOperand::createReg(Register)); 682 return Success; 683 } 684 685 static const SmallVector<SmallVector<unsigned, 16>, 5> 686 MatrixZATileDecoderTable = { 687 {AArch64::ZAB0}, 688 {AArch64::ZAH0, AArch64::ZAH1}, 689 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 690 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 691 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 692 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 693 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 694 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 695 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 696 697 template <unsigned NumBitsForTile> 698 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 699 uint64_t Address, const void *Decoder) { 700 unsigned LastReg = (1 << NumBitsForTile) - 1; 701 if (RegNo > LastReg) 702 return Fail; 703 Inst.addOperand( 704 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 705 return Success; 706 } 707 708 static const unsigned PPRDecoderTable[] = { 709 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 710 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 711 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 712 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 713 }; 714 715 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 716 uint64_t Addr, const void *Decoder) { 717 if (RegNo > 15) 718 return Fail; 719 720 unsigned Register = PPRDecoderTable[RegNo]; 721 Inst.addOperand(MCOperand::createReg(Register)); 722 return Success; 723 } 724 725 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 726 uint64_t Addr, 727 const void* Decoder) { 728 if (RegNo > 7) 729 return Fail; 730 731 // Just reuse the PPR decode table 732 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 733 } 734 735 static const unsigned VectorDecoderTable[] = { 736 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 737 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 738 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 739 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 740 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 741 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 742 AArch64::Q30, AArch64::Q31 743 }; 744 745 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 746 uint64_t Addr, 747 const void *Decoder) { 748 if (RegNo > 31) 749 return Fail; 750 751 unsigned Register = VectorDecoderTable[RegNo]; 752 Inst.addOperand(MCOperand::createReg(Register)); 753 return Success; 754 } 755 756 static const unsigned QQDecoderTable[] = { 757 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 758 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 759 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 760 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 761 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 762 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 763 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 764 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 765 }; 766 767 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 768 uint64_t Addr, const void *Decoder) { 769 if (RegNo > 31) 770 return Fail; 771 unsigned Register = QQDecoderTable[RegNo]; 772 Inst.addOperand(MCOperand::createReg(Register)); 773 return Success; 774 } 775 776 static const unsigned QQQDecoderTable[] = { 777 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 778 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 779 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 780 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 781 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 782 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 783 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 784 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 785 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 786 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 787 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 788 }; 789 790 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 791 uint64_t Addr, const void *Decoder) { 792 if (RegNo > 31) 793 return Fail; 794 unsigned Register = QQQDecoderTable[RegNo]; 795 Inst.addOperand(MCOperand::createReg(Register)); 796 return Success; 797 } 798 799 static const unsigned QQQQDecoderTable[] = { 800 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 801 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 802 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 803 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 804 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 805 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 806 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 807 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 808 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 809 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 810 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 811 }; 812 813 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 814 uint64_t Addr, 815 const void *Decoder) { 816 if (RegNo > 31) 817 return Fail; 818 unsigned Register = QQQQDecoderTable[RegNo]; 819 Inst.addOperand(MCOperand::createReg(Register)); 820 return Success; 821 } 822 823 static const unsigned DDDecoderTable[] = { 824 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 825 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 826 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 827 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 828 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 829 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 830 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 831 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 832 }; 833 834 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 835 uint64_t Addr, const void *Decoder) { 836 if (RegNo > 31) 837 return Fail; 838 unsigned Register = DDDecoderTable[RegNo]; 839 Inst.addOperand(MCOperand::createReg(Register)); 840 return Success; 841 } 842 843 static const unsigned DDDDecoderTable[] = { 844 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 845 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 846 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 847 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 848 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 849 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 850 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 851 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 852 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 853 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 854 AArch64::D30_D31_D0, AArch64::D31_D0_D1 855 }; 856 857 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 858 uint64_t Addr, const void *Decoder) { 859 if (RegNo > 31) 860 return Fail; 861 unsigned Register = DDDDecoderTable[RegNo]; 862 Inst.addOperand(MCOperand::createReg(Register)); 863 return Success; 864 } 865 866 static const unsigned DDDDDecoderTable[] = { 867 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 868 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 869 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 870 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 871 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 872 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 873 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 874 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 875 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 876 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 877 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 878 }; 879 880 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 881 uint64_t Addr, 882 const void *Decoder) { 883 if (RegNo > 31) 884 return Fail; 885 unsigned Register = DDDDDecoderTable[RegNo]; 886 Inst.addOperand(MCOperand::createReg(Register)); 887 return Success; 888 } 889 890 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 891 uint64_t Addr, 892 const void *Decoder) { 893 // scale{5} is asserted as 1 in tblgen. 894 Imm |= 0x20; 895 Inst.addOperand(MCOperand::createImm(64 - Imm)); 896 return Success; 897 } 898 899 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 900 uint64_t Addr, 901 const void *Decoder) { 902 Inst.addOperand(MCOperand::createImm(64 - Imm)); 903 return Success; 904 } 905 906 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 907 uint64_t Addr, const void *Decoder) { 908 int64_t ImmVal = Imm; 909 const AArch64Disassembler *Dis = 910 static_cast<const AArch64Disassembler *>(Decoder); 911 912 // Sign-extend 19-bit immediate. 913 if (ImmVal & (1 << (19 - 1))) 914 ImmVal |= ~((1LL << 19) - 1); 915 916 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 917 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 918 Inst.addOperand(MCOperand::createImm(ImmVal)); 919 return Success; 920 } 921 922 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 923 uint64_t Address, const void *Decoder) { 924 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 925 Inst.addOperand(MCOperand::createImm(Imm & 1)); 926 return Success; 927 } 928 929 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 930 uint64_t Address, 931 const void *Decoder) { 932 Inst.addOperand(MCOperand::createImm(Imm)); 933 934 // Every system register in the encoding space is valid with the syntax 935 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 936 return Success; 937 } 938 939 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 940 uint64_t Address, 941 const void *Decoder) { 942 Inst.addOperand(MCOperand::createImm(Imm)); 943 944 return Success; 945 } 946 947 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 948 uint64_t Address, 949 const void *Decoder) { 950 // This decoder exists to add the dummy Lane operand to the MCInst, which must 951 // be 1 in assembly but has no other real manifestation. 952 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 953 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 954 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 955 956 if (IsToVec) { 957 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 958 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 959 } else { 960 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 961 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 962 } 963 964 // Add the lane 965 Inst.addOperand(MCOperand::createImm(1)); 966 967 return Success; 968 } 969 970 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 971 unsigned Add) { 972 Inst.addOperand(MCOperand::createImm(Add - Imm)); 973 return Success; 974 } 975 976 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 977 unsigned Add) { 978 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 979 return Success; 980 } 981 982 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 983 uint64_t Addr, const void *Decoder) { 984 return DecodeVecShiftRImm(Inst, Imm, 64); 985 } 986 987 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 988 uint64_t Addr, 989 const void *Decoder) { 990 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 991 } 992 993 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 994 uint64_t Addr, const void *Decoder) { 995 return DecodeVecShiftRImm(Inst, Imm, 32); 996 } 997 998 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 999 uint64_t Addr, 1000 const void *Decoder) { 1001 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 1002 } 1003 1004 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 1005 uint64_t Addr, const void *Decoder) { 1006 return DecodeVecShiftRImm(Inst, Imm, 16); 1007 } 1008 1009 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 1010 uint64_t Addr, 1011 const void *Decoder) { 1012 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 1013 } 1014 1015 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 1016 uint64_t Addr, const void *Decoder) { 1017 return DecodeVecShiftRImm(Inst, Imm, 8); 1018 } 1019 1020 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 1021 uint64_t Addr, const void *Decoder) { 1022 return DecodeVecShiftLImm(Inst, Imm, 64); 1023 } 1024 1025 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 1026 uint64_t Addr, const void *Decoder) { 1027 return DecodeVecShiftLImm(Inst, Imm, 32); 1028 } 1029 1030 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 1031 uint64_t Addr, const void *Decoder) { 1032 return DecodeVecShiftLImm(Inst, Imm, 16); 1033 } 1034 1035 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 1036 uint64_t Addr, const void *Decoder) { 1037 return DecodeVecShiftLImm(Inst, Imm, 8); 1038 } 1039 1040 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 1041 uint64_t Addr, 1042 const void *Decoder) { 1043 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1044 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1045 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1046 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 1047 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 1048 unsigned shift = (shiftHi << 6) | shiftLo; 1049 switch (Inst.getOpcode()) { 1050 default: 1051 return Fail; 1052 case AArch64::ADDWrs: 1053 case AArch64::ADDSWrs: 1054 case AArch64::SUBWrs: 1055 case AArch64::SUBSWrs: 1056 // if shift == '11' then ReservedValue() 1057 if (shiftHi == 0x3) 1058 return Fail; 1059 LLVM_FALLTHROUGH; 1060 case AArch64::ANDWrs: 1061 case AArch64::ANDSWrs: 1062 case AArch64::BICWrs: 1063 case AArch64::BICSWrs: 1064 case AArch64::ORRWrs: 1065 case AArch64::ORNWrs: 1066 case AArch64::EORWrs: 1067 case AArch64::EONWrs: { 1068 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1069 if (shiftLo >> 5 == 1) 1070 return Fail; 1071 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1072 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1073 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1074 break; 1075 } 1076 case AArch64::ADDXrs: 1077 case AArch64::ADDSXrs: 1078 case AArch64::SUBXrs: 1079 case AArch64::SUBSXrs: 1080 // if shift == '11' then ReservedValue() 1081 if (shiftHi == 0x3) 1082 return Fail; 1083 LLVM_FALLTHROUGH; 1084 case AArch64::ANDXrs: 1085 case AArch64::ANDSXrs: 1086 case AArch64::BICXrs: 1087 case AArch64::BICSXrs: 1088 case AArch64::ORRXrs: 1089 case AArch64::ORNXrs: 1090 case AArch64::EORXrs: 1091 case AArch64::EONXrs: 1092 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1093 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1094 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1095 break; 1096 } 1097 1098 Inst.addOperand(MCOperand::createImm(shift)); 1099 return Success; 1100 } 1101 1102 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1103 uint64_t Addr, 1104 const void *Decoder) { 1105 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1106 unsigned imm = fieldFromInstruction(insn, 5, 16); 1107 unsigned shift = fieldFromInstruction(insn, 21, 2); 1108 shift <<= 4; 1109 switch (Inst.getOpcode()) { 1110 default: 1111 return Fail; 1112 case AArch64::MOVZWi: 1113 case AArch64::MOVNWi: 1114 case AArch64::MOVKWi: 1115 if (shift & (1U << 5)) 1116 return Fail; 1117 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1118 break; 1119 case AArch64::MOVZXi: 1120 case AArch64::MOVNXi: 1121 case AArch64::MOVKXi: 1122 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1123 break; 1124 } 1125 1126 if (Inst.getOpcode() == AArch64::MOVKWi || 1127 Inst.getOpcode() == AArch64::MOVKXi) 1128 Inst.addOperand(Inst.getOperand(0)); 1129 1130 Inst.addOperand(MCOperand::createImm(imm)); 1131 Inst.addOperand(MCOperand::createImm(shift)); 1132 return Success; 1133 } 1134 1135 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1136 uint64_t Addr, 1137 const void *Decoder) { 1138 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1139 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1140 unsigned offset = fieldFromInstruction(insn, 10, 12); 1141 const AArch64Disassembler *Dis = 1142 static_cast<const AArch64Disassembler *>(Decoder); 1143 1144 switch (Inst.getOpcode()) { 1145 default: 1146 return Fail; 1147 case AArch64::PRFMui: 1148 // Rt is an immediate in prefetch. 1149 Inst.addOperand(MCOperand::createImm(Rt)); 1150 break; 1151 case AArch64::STRBBui: 1152 case AArch64::LDRBBui: 1153 case AArch64::LDRSBWui: 1154 case AArch64::STRHHui: 1155 case AArch64::LDRHHui: 1156 case AArch64::LDRSHWui: 1157 case AArch64::STRWui: 1158 case AArch64::LDRWui: 1159 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1160 break; 1161 case AArch64::LDRSBXui: 1162 case AArch64::LDRSHXui: 1163 case AArch64::LDRSWui: 1164 case AArch64::STRXui: 1165 case AArch64::LDRXui: 1166 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1167 break; 1168 case AArch64::LDRQui: 1169 case AArch64::STRQui: 1170 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1171 break; 1172 case AArch64::LDRDui: 1173 case AArch64::STRDui: 1174 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1175 break; 1176 case AArch64::LDRSui: 1177 case AArch64::STRSui: 1178 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1179 break; 1180 case AArch64::LDRHui: 1181 case AArch64::STRHui: 1182 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1183 break; 1184 case AArch64::LDRBui: 1185 case AArch64::STRBui: 1186 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1187 break; 1188 } 1189 1190 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1191 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1192 Inst.addOperand(MCOperand::createImm(offset)); 1193 return Success; 1194 } 1195 1196 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1197 uint64_t Addr, 1198 const void *Decoder) { 1199 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1200 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1201 int64_t offset = fieldFromInstruction(insn, 12, 9); 1202 1203 // offset is a 9-bit signed immediate, so sign extend it to 1204 // fill the unsigned. 1205 if (offset & (1 << (9 - 1))) 1206 offset |= ~((1LL << 9) - 1); 1207 1208 // First operand is always the writeback to the address register, if needed. 1209 switch (Inst.getOpcode()) { 1210 default: 1211 break; 1212 case AArch64::LDRSBWpre: 1213 case AArch64::LDRSHWpre: 1214 case AArch64::STRBBpre: 1215 case AArch64::LDRBBpre: 1216 case AArch64::STRHHpre: 1217 case AArch64::LDRHHpre: 1218 case AArch64::STRWpre: 1219 case AArch64::LDRWpre: 1220 case AArch64::LDRSBWpost: 1221 case AArch64::LDRSHWpost: 1222 case AArch64::STRBBpost: 1223 case AArch64::LDRBBpost: 1224 case AArch64::STRHHpost: 1225 case AArch64::LDRHHpost: 1226 case AArch64::STRWpost: 1227 case AArch64::LDRWpost: 1228 case AArch64::LDRSBXpre: 1229 case AArch64::LDRSHXpre: 1230 case AArch64::STRXpre: 1231 case AArch64::LDRSWpre: 1232 case AArch64::LDRXpre: 1233 case AArch64::LDRSBXpost: 1234 case AArch64::LDRSHXpost: 1235 case AArch64::STRXpost: 1236 case AArch64::LDRSWpost: 1237 case AArch64::LDRXpost: 1238 case AArch64::LDRQpre: 1239 case AArch64::STRQpre: 1240 case AArch64::LDRQpost: 1241 case AArch64::STRQpost: 1242 case AArch64::LDRDpre: 1243 case AArch64::STRDpre: 1244 case AArch64::LDRDpost: 1245 case AArch64::STRDpost: 1246 case AArch64::LDRSpre: 1247 case AArch64::STRSpre: 1248 case AArch64::LDRSpost: 1249 case AArch64::STRSpost: 1250 case AArch64::LDRHpre: 1251 case AArch64::STRHpre: 1252 case AArch64::LDRHpost: 1253 case AArch64::STRHpost: 1254 case AArch64::LDRBpre: 1255 case AArch64::STRBpre: 1256 case AArch64::LDRBpost: 1257 case AArch64::STRBpost: 1258 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1259 break; 1260 } 1261 1262 switch (Inst.getOpcode()) { 1263 default: 1264 return Fail; 1265 case AArch64::PRFUMi: 1266 // Rt is an immediate in prefetch. 1267 Inst.addOperand(MCOperand::createImm(Rt)); 1268 break; 1269 case AArch64::STURBBi: 1270 case AArch64::LDURBBi: 1271 case AArch64::LDURSBWi: 1272 case AArch64::STURHHi: 1273 case AArch64::LDURHHi: 1274 case AArch64::LDURSHWi: 1275 case AArch64::STURWi: 1276 case AArch64::LDURWi: 1277 case AArch64::LDTRSBWi: 1278 case AArch64::LDTRSHWi: 1279 case AArch64::STTRWi: 1280 case AArch64::LDTRWi: 1281 case AArch64::STTRHi: 1282 case AArch64::LDTRHi: 1283 case AArch64::LDTRBi: 1284 case AArch64::STTRBi: 1285 case AArch64::LDRSBWpre: 1286 case AArch64::LDRSHWpre: 1287 case AArch64::STRBBpre: 1288 case AArch64::LDRBBpre: 1289 case AArch64::STRHHpre: 1290 case AArch64::LDRHHpre: 1291 case AArch64::STRWpre: 1292 case AArch64::LDRWpre: 1293 case AArch64::LDRSBWpost: 1294 case AArch64::LDRSHWpost: 1295 case AArch64::STRBBpost: 1296 case AArch64::LDRBBpost: 1297 case AArch64::STRHHpost: 1298 case AArch64::LDRHHpost: 1299 case AArch64::STRWpost: 1300 case AArch64::LDRWpost: 1301 case AArch64::STLURBi: 1302 case AArch64::STLURHi: 1303 case AArch64::STLURWi: 1304 case AArch64::LDAPURBi: 1305 case AArch64::LDAPURSBWi: 1306 case AArch64::LDAPURHi: 1307 case AArch64::LDAPURSHWi: 1308 case AArch64::LDAPURi: 1309 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1310 break; 1311 case AArch64::LDURSBXi: 1312 case AArch64::LDURSHXi: 1313 case AArch64::LDURSWi: 1314 case AArch64::STURXi: 1315 case AArch64::LDURXi: 1316 case AArch64::LDTRSBXi: 1317 case AArch64::LDTRSHXi: 1318 case AArch64::LDTRSWi: 1319 case AArch64::STTRXi: 1320 case AArch64::LDTRXi: 1321 case AArch64::LDRSBXpre: 1322 case AArch64::LDRSHXpre: 1323 case AArch64::STRXpre: 1324 case AArch64::LDRSWpre: 1325 case AArch64::LDRXpre: 1326 case AArch64::LDRSBXpost: 1327 case AArch64::LDRSHXpost: 1328 case AArch64::STRXpost: 1329 case AArch64::LDRSWpost: 1330 case AArch64::LDRXpost: 1331 case AArch64::LDAPURSWi: 1332 case AArch64::LDAPURSHXi: 1333 case AArch64::LDAPURSBXi: 1334 case AArch64::STLURXi: 1335 case AArch64::LDAPURXi: 1336 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1337 break; 1338 case AArch64::LDURQi: 1339 case AArch64::STURQi: 1340 case AArch64::LDRQpre: 1341 case AArch64::STRQpre: 1342 case AArch64::LDRQpost: 1343 case AArch64::STRQpost: 1344 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1345 break; 1346 case AArch64::LDURDi: 1347 case AArch64::STURDi: 1348 case AArch64::LDRDpre: 1349 case AArch64::STRDpre: 1350 case AArch64::LDRDpost: 1351 case AArch64::STRDpost: 1352 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1353 break; 1354 case AArch64::LDURSi: 1355 case AArch64::STURSi: 1356 case AArch64::LDRSpre: 1357 case AArch64::STRSpre: 1358 case AArch64::LDRSpost: 1359 case AArch64::STRSpost: 1360 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1361 break; 1362 case AArch64::LDURHi: 1363 case AArch64::STURHi: 1364 case AArch64::LDRHpre: 1365 case AArch64::STRHpre: 1366 case AArch64::LDRHpost: 1367 case AArch64::STRHpost: 1368 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1369 break; 1370 case AArch64::LDURBi: 1371 case AArch64::STURBi: 1372 case AArch64::LDRBpre: 1373 case AArch64::STRBpre: 1374 case AArch64::LDRBpost: 1375 case AArch64::STRBpost: 1376 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1377 break; 1378 } 1379 1380 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1381 Inst.addOperand(MCOperand::createImm(offset)); 1382 1383 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1384 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1385 bool IsFP = fieldFromInstruction(insn, 26, 1); 1386 1387 // Cannot write back to a transfer register (but xzr != sp). 1388 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1389 return SoftFail; 1390 1391 return Success; 1392 } 1393 1394 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1395 uint64_t Addr, 1396 const void *Decoder) { 1397 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1398 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1399 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1400 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1401 1402 unsigned Opcode = Inst.getOpcode(); 1403 switch (Opcode) { 1404 default: 1405 return Fail; 1406 case AArch64::STLXRW: 1407 case AArch64::STLXRB: 1408 case AArch64::STLXRH: 1409 case AArch64::STXRW: 1410 case AArch64::STXRB: 1411 case AArch64::STXRH: 1412 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1413 LLVM_FALLTHROUGH; 1414 case AArch64::LDARW: 1415 case AArch64::LDARB: 1416 case AArch64::LDARH: 1417 case AArch64::LDAXRW: 1418 case AArch64::LDAXRB: 1419 case AArch64::LDAXRH: 1420 case AArch64::LDXRW: 1421 case AArch64::LDXRB: 1422 case AArch64::LDXRH: 1423 case AArch64::STLRW: 1424 case AArch64::STLRB: 1425 case AArch64::STLRH: 1426 case AArch64::STLLRW: 1427 case AArch64::STLLRB: 1428 case AArch64::STLLRH: 1429 case AArch64::LDLARW: 1430 case AArch64::LDLARB: 1431 case AArch64::LDLARH: 1432 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1433 break; 1434 case AArch64::STLXRX: 1435 case AArch64::STXRX: 1436 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1437 LLVM_FALLTHROUGH; 1438 case AArch64::LDARX: 1439 case AArch64::LDAXRX: 1440 case AArch64::LDXRX: 1441 case AArch64::STLRX: 1442 case AArch64::LDLARX: 1443 case AArch64::STLLRX: 1444 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1445 break; 1446 case AArch64::STLXPW: 1447 case AArch64::STXPW: 1448 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1449 LLVM_FALLTHROUGH; 1450 case AArch64::LDAXPW: 1451 case AArch64::LDXPW: 1452 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1453 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1454 break; 1455 case AArch64::STLXPX: 1456 case AArch64::STXPX: 1457 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1458 LLVM_FALLTHROUGH; 1459 case AArch64::LDAXPX: 1460 case AArch64::LDXPX: 1461 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1462 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1463 break; 1464 } 1465 1466 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1467 1468 // You shouldn't load to the same register twice in an instruction... 1469 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1470 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1471 Rt == Rt2) 1472 return SoftFail; 1473 1474 return Success; 1475 } 1476 1477 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1478 uint64_t Addr, 1479 const void *Decoder) { 1480 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1481 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1482 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1483 int64_t offset = fieldFromInstruction(insn, 15, 7); 1484 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1485 1486 // offset is a 7-bit signed immediate, so sign extend it to 1487 // fill the unsigned. 1488 if (offset & (1 << (7 - 1))) 1489 offset |= ~((1LL << 7) - 1); 1490 1491 unsigned Opcode = Inst.getOpcode(); 1492 bool NeedsDisjointWritebackTransfer = false; 1493 1494 // First operand is always writeback of base register. 1495 switch (Opcode) { 1496 default: 1497 break; 1498 case AArch64::LDPXpost: 1499 case AArch64::STPXpost: 1500 case AArch64::LDPSWpost: 1501 case AArch64::LDPXpre: 1502 case AArch64::STPXpre: 1503 case AArch64::LDPSWpre: 1504 case AArch64::LDPWpost: 1505 case AArch64::STPWpost: 1506 case AArch64::LDPWpre: 1507 case AArch64::STPWpre: 1508 case AArch64::LDPQpost: 1509 case AArch64::STPQpost: 1510 case AArch64::LDPQpre: 1511 case AArch64::STPQpre: 1512 case AArch64::LDPDpost: 1513 case AArch64::STPDpost: 1514 case AArch64::LDPDpre: 1515 case AArch64::STPDpre: 1516 case AArch64::LDPSpost: 1517 case AArch64::STPSpost: 1518 case AArch64::LDPSpre: 1519 case AArch64::STPSpre: 1520 case AArch64::STGPpre: 1521 case AArch64::STGPpost: 1522 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1523 break; 1524 } 1525 1526 switch (Opcode) { 1527 default: 1528 return Fail; 1529 case AArch64::LDPXpost: 1530 case AArch64::STPXpost: 1531 case AArch64::LDPSWpost: 1532 case AArch64::LDPXpre: 1533 case AArch64::STPXpre: 1534 case AArch64::LDPSWpre: 1535 case AArch64::STGPpre: 1536 case AArch64::STGPpost: 1537 NeedsDisjointWritebackTransfer = true; 1538 LLVM_FALLTHROUGH; 1539 case AArch64::LDNPXi: 1540 case AArch64::STNPXi: 1541 case AArch64::LDPXi: 1542 case AArch64::STPXi: 1543 case AArch64::LDPSWi: 1544 case AArch64::STGPi: 1545 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1546 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1547 break; 1548 case AArch64::LDPWpost: 1549 case AArch64::STPWpost: 1550 case AArch64::LDPWpre: 1551 case AArch64::STPWpre: 1552 NeedsDisjointWritebackTransfer = true; 1553 LLVM_FALLTHROUGH; 1554 case AArch64::LDNPWi: 1555 case AArch64::STNPWi: 1556 case AArch64::LDPWi: 1557 case AArch64::STPWi: 1558 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1559 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1560 break; 1561 case AArch64::LDNPQi: 1562 case AArch64::STNPQi: 1563 case AArch64::LDPQpost: 1564 case AArch64::STPQpost: 1565 case AArch64::LDPQi: 1566 case AArch64::STPQi: 1567 case AArch64::LDPQpre: 1568 case AArch64::STPQpre: 1569 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1570 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1571 break; 1572 case AArch64::LDNPDi: 1573 case AArch64::STNPDi: 1574 case AArch64::LDPDpost: 1575 case AArch64::STPDpost: 1576 case AArch64::LDPDi: 1577 case AArch64::STPDi: 1578 case AArch64::LDPDpre: 1579 case AArch64::STPDpre: 1580 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1581 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1582 break; 1583 case AArch64::LDNPSi: 1584 case AArch64::STNPSi: 1585 case AArch64::LDPSpost: 1586 case AArch64::STPSpost: 1587 case AArch64::LDPSi: 1588 case AArch64::STPSi: 1589 case AArch64::LDPSpre: 1590 case AArch64::STPSpre: 1591 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1592 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1593 break; 1594 } 1595 1596 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1597 Inst.addOperand(MCOperand::createImm(offset)); 1598 1599 // You shouldn't load to the same register twice in an instruction... 1600 if (IsLoad && Rt == Rt2) 1601 return SoftFail; 1602 1603 // ... or do any operation that writes-back to a transfer register. But note 1604 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1605 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1606 return SoftFail; 1607 1608 return Success; 1609 } 1610 1611 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1612 uint64_t Addr, 1613 const void *Decoder) { 1614 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1615 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1616 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1617 fieldFromInstruction(insn, 12, 9); 1618 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1619 1620 switch (Inst.getOpcode()) { 1621 default: 1622 return Fail; 1623 case AArch64::LDRAAwriteback: 1624 case AArch64::LDRABwriteback: 1625 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1626 Decoder); 1627 break; 1628 case AArch64::LDRAAindexed: 1629 case AArch64::LDRABindexed: 1630 break; 1631 } 1632 1633 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1634 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1635 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1636 1637 if (writeback && Rt == Rn && Rn != 31) { 1638 return SoftFail; 1639 } 1640 1641 return Success; 1642 } 1643 1644 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1645 uint64_t Addr, 1646 const void *Decoder) { 1647 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1648 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1649 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1650 unsigned extend = fieldFromInstruction(insn, 10, 6); 1651 1652 unsigned shift = extend & 0x7; 1653 if (shift > 4) 1654 return Fail; 1655 1656 switch (Inst.getOpcode()) { 1657 default: 1658 return Fail; 1659 case AArch64::ADDWrx: 1660 case AArch64::SUBWrx: 1661 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1662 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1663 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1664 break; 1665 case AArch64::ADDSWrx: 1666 case AArch64::SUBSWrx: 1667 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1668 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1669 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1670 break; 1671 case AArch64::ADDXrx: 1672 case AArch64::SUBXrx: 1673 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1674 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1675 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1676 break; 1677 case AArch64::ADDSXrx: 1678 case AArch64::SUBSXrx: 1679 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1680 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1681 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1682 break; 1683 case AArch64::ADDXrx64: 1684 case AArch64::SUBXrx64: 1685 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1686 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1687 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1688 break; 1689 case AArch64::SUBSXrx64: 1690 case AArch64::ADDSXrx64: 1691 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1692 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1693 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1694 break; 1695 } 1696 1697 Inst.addOperand(MCOperand::createImm(extend)); 1698 return Success; 1699 } 1700 1701 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1702 uint64_t Addr, 1703 const void *Decoder) { 1704 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1705 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1706 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1707 unsigned imm; 1708 1709 if (Datasize) { 1710 if (Inst.getOpcode() == AArch64::ANDSXri) 1711 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1712 else 1713 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1714 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1715 imm = fieldFromInstruction(insn, 10, 13); 1716 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1717 return Fail; 1718 } else { 1719 if (Inst.getOpcode() == AArch64::ANDSWri) 1720 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1721 else 1722 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1723 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1724 imm = fieldFromInstruction(insn, 10, 12); 1725 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1726 return Fail; 1727 } 1728 Inst.addOperand(MCOperand::createImm(imm)); 1729 return Success; 1730 } 1731 1732 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1733 uint64_t Addr, 1734 const void *Decoder) { 1735 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1736 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1737 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1738 imm |= fieldFromInstruction(insn, 5, 5); 1739 1740 if (Inst.getOpcode() == AArch64::MOVID) 1741 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1742 else 1743 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1744 1745 Inst.addOperand(MCOperand::createImm(imm)); 1746 1747 switch (Inst.getOpcode()) { 1748 default: 1749 break; 1750 case AArch64::MOVIv4i16: 1751 case AArch64::MOVIv8i16: 1752 case AArch64::MVNIv4i16: 1753 case AArch64::MVNIv8i16: 1754 case AArch64::MOVIv2i32: 1755 case AArch64::MOVIv4i32: 1756 case AArch64::MVNIv2i32: 1757 case AArch64::MVNIv4i32: 1758 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1759 break; 1760 case AArch64::MOVIv2s_msl: 1761 case AArch64::MOVIv4s_msl: 1762 case AArch64::MVNIv2s_msl: 1763 case AArch64::MVNIv4s_msl: 1764 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1765 break; 1766 } 1767 1768 return Success; 1769 } 1770 1771 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1772 uint64_t Addr, 1773 const void *Decoder) { 1774 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1775 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1776 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1777 imm |= fieldFromInstruction(insn, 5, 5); 1778 1779 // Tied operands added twice. 1780 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1781 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1782 1783 Inst.addOperand(MCOperand::createImm(imm)); 1784 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1785 1786 return Success; 1787 } 1788 1789 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1790 uint64_t Addr, const void *Decoder) { 1791 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1792 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1793 imm |= fieldFromInstruction(insn, 29, 2); 1794 const AArch64Disassembler *Dis = 1795 static_cast<const AArch64Disassembler *>(Decoder); 1796 1797 // Sign-extend the 21-bit immediate. 1798 if (imm & (1 << (21 - 1))) 1799 imm |= ~((1LL << 21) - 1); 1800 1801 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1802 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1803 Inst.addOperand(MCOperand::createImm(imm)); 1804 1805 return Success; 1806 } 1807 1808 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1809 uint64_t Addr, const void *Decoder) { 1810 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1811 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1812 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1813 unsigned S = fieldFromInstruction(insn, 29, 1); 1814 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1815 1816 unsigned ShifterVal = (Imm >> 12) & 3; 1817 unsigned ImmVal = Imm & 0xFFF; 1818 const AArch64Disassembler *Dis = 1819 static_cast<const AArch64Disassembler *>(Decoder); 1820 1821 if (ShifterVal != 0 && ShifterVal != 1) 1822 return Fail; 1823 1824 if (Datasize) { 1825 if (Rd == 31 && !S) 1826 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1827 else 1828 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1829 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1830 } else { 1831 if (Rd == 31 && !S) 1832 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1833 else 1834 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1835 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1836 } 1837 1838 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1839 Inst.addOperand(MCOperand::createImm(ImmVal)); 1840 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1841 return Success; 1842 } 1843 1844 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1845 uint64_t Addr, 1846 const void *Decoder) { 1847 int64_t imm = fieldFromInstruction(insn, 0, 26); 1848 const AArch64Disassembler *Dis = 1849 static_cast<const AArch64Disassembler *>(Decoder); 1850 1851 // Sign-extend the 26-bit immediate. 1852 if (imm & (1 << (26 - 1))) 1853 imm |= ~((1LL << 26) - 1); 1854 1855 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1856 Inst.addOperand(MCOperand::createImm(imm)); 1857 1858 return Success; 1859 } 1860 1861 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1862 uint64_t Addr, 1863 const void *Decoder) { 1864 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1865 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1866 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1867 uint64_t pstate_field = (op1 << 3) | op2; 1868 1869 switch (pstate_field) { 1870 case 0x01: // XAFlag 1871 case 0x02: // AXFlag 1872 return Fail; 1873 } 1874 1875 if ((pstate_field == AArch64PState::PAN || 1876 pstate_field == AArch64PState::UAO || 1877 pstate_field == AArch64PState::SSBS) && crm > 1) 1878 return Fail; 1879 1880 Inst.addOperand(MCOperand::createImm(pstate_field)); 1881 Inst.addOperand(MCOperand::createImm(crm)); 1882 1883 const AArch64Disassembler *Dis = 1884 static_cast<const AArch64Disassembler *>(Decoder); 1885 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1886 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1887 return Success; 1888 return Fail; 1889 } 1890 1891 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1892 uint64_t Addr, const void *Decoder) { 1893 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1894 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1895 bit |= fieldFromInstruction(insn, 19, 5); 1896 int64_t dst = fieldFromInstruction(insn, 5, 14); 1897 const AArch64Disassembler *Dis = 1898 static_cast<const AArch64Disassembler *>(Decoder); 1899 1900 // Sign-extend 14-bit immediate. 1901 if (dst & (1 << (14 - 1))) 1902 dst |= ~((1LL << 14) - 1); 1903 1904 if (fieldFromInstruction(insn, 31, 1) == 0) 1905 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1906 else 1907 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1908 Inst.addOperand(MCOperand::createImm(bit)); 1909 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1910 Inst.addOperand(MCOperand::createImm(dst)); 1911 1912 return Success; 1913 } 1914 1915 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1916 unsigned RegClassID, 1917 unsigned RegNo, 1918 uint64_t Addr, 1919 const void *Decoder) { 1920 // Register number must be even (see CASP instruction) 1921 if (RegNo & 0x1) 1922 return Fail; 1923 1924 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1925 Inst.addOperand(MCOperand::createReg(Reg)); 1926 return Success; 1927 } 1928 1929 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1930 unsigned RegNo, 1931 uint64_t Addr, 1932 const void *Decoder) { 1933 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1934 AArch64::WSeqPairsClassRegClassID, 1935 RegNo, Addr, Decoder); 1936 } 1937 1938 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1939 unsigned RegNo, 1940 uint64_t Addr, 1941 const void *Decoder) { 1942 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1943 AArch64::XSeqPairsClassRegClassID, 1944 RegNo, Addr, Decoder); 1945 } 1946 1947 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1948 uint32_t insn, 1949 uint64_t Addr, 1950 const void *Decoder) { 1951 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1952 unsigned imm = fieldFromInstruction(insn, 5, 13); 1953 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1954 return Fail; 1955 1956 // The same (tied) operand is added twice to the instruction. 1957 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1958 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1959 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1960 Inst.addOperand(MCOperand::createImm(imm)); 1961 return Success; 1962 } 1963 1964 template<int Bits> 1965 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1966 uint64_t Address, const void *Decoder) { 1967 if (Imm & ~((1LL << Bits) - 1)) 1968 return Fail; 1969 1970 // Imm is a signed immediate, so sign extend it. 1971 if (Imm & (1 << (Bits - 1))) 1972 Imm |= ~((1LL << Bits) - 1); 1973 1974 Inst.addOperand(MCOperand::createImm(Imm)); 1975 return Success; 1976 } 1977 1978 // Decode 8-bit signed/unsigned immediate for a given element width. 1979 template <int ElementWidth> 1980 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1981 uint64_t Addr, const void *Decoder) { 1982 unsigned Val = (uint8_t)Imm; 1983 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1984 if (ElementWidth == 8 && Shift) 1985 return Fail; 1986 Inst.addOperand(MCOperand::createImm(Val)); 1987 Inst.addOperand(MCOperand::createImm(Shift)); 1988 return Success; 1989 } 1990 1991 // Decode uimm4 ranged from 1-16. 1992 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1993 uint64_t Addr, const void *Decoder) { 1994 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1995 return Success; 1996 } 1997 1998 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 1999 const void *Decoder) { 2000 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 2001 Inst.addOperand(MCOperand::createImm(Imm)); 2002 return Success; 2003 } 2004 return Fail; 2005 } 2006