1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 80 unsigned RegNo, uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 template <unsigned NumBitsForTile> 119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 122 unsigned RegMask, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 133 uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 162 uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 168 uint64_t Address, 169 const void *Decoder); 170 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 171 uint64_t Address, 172 const void *Decoder); 173 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 174 uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 177 uint64_t Address, 178 const void *Decoder); 179 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 184 uint64_t Address, 185 const void *Decoder); 186 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 187 uint64_t Address, 188 const void *Decoder); 189 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 190 uint64_t Address, const void *Decoder); 191 192 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 193 uint64_t Address, 194 const void *Decoder); 195 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, const void *Decoder); 197 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 198 uint64_t Addr, 199 const void *Decoder); 200 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 201 uint64_t Addr, const void *Decoder); 202 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const void *Decoder); 205 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, const void *Decoder); 207 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 208 uint64_t Addr, 209 const void *Decoder); 210 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, const void *Decoder); 214 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, const void *Decoder); 216 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, const void *Decoder); 218 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 219 uint64_t Addr, const void *Decoder); 220 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Addr, 223 const void *Decoder); 224 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 225 unsigned RegNo, 226 uint64_t Addr, 227 const void *Decoder); 228 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, 229 uint64_t Address, 230 const void *Decoder); 231 template <int Bits> 232 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 233 const void *Decoder); 234 template <int ElementWidth> 235 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 236 uint64_t Addr, const void *Decoder); 237 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 238 uint64_t Addr, const void *Decoder); 239 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 240 const void *Decoder); 241 242 static bool Check(DecodeStatus &Out, DecodeStatus In) { 243 switch (In) { 244 case MCDisassembler::Success: 245 // Out stays the same. 246 return true; 247 case MCDisassembler::SoftFail: 248 Out = In; 249 return true; 250 case MCDisassembler::Fail: 251 Out = In; 252 return false; 253 } 254 llvm_unreachable("Invalid DecodeStatus!"); 255 } 256 257 #include "AArch64GenDisassemblerTables.inc" 258 #include "AArch64GenInstrInfo.inc" 259 260 #define Success MCDisassembler::Success 261 #define Fail MCDisassembler::Fail 262 #define SoftFail MCDisassembler::SoftFail 263 264 static MCDisassembler *createAArch64Disassembler(const Target &T, 265 const MCSubtargetInfo &STI, 266 MCContext &Ctx) { 267 return new AArch64Disassembler(STI, Ctx); 268 } 269 270 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 271 ArrayRef<uint8_t> Bytes, 272 uint64_t Address, 273 raw_ostream &CS) const { 274 CommentStream = &CS; 275 276 Size = 0; 277 // We want to read exactly 4 bytes of data. 278 if (Bytes.size() < 4) 279 return Fail; 280 Size = 4; 281 282 // Encoded as a small-endian 32-bit word in the stream. 283 uint32_t Insn = 284 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 285 286 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 287 288 for (auto Table : Tables) { 289 DecodeStatus Result = 290 decodeInstruction(Table, MI, Insn, Address, this, STI); 291 292 switch (MI.getOpcode()) { 293 default: 294 break; 295 // For Scalable Matrix Extension (SME) instructions that have an implicit 296 // operand for the accumulator (ZA) which isn't encoded, manually insert 297 // operand. 298 case AArch64::LDR_ZA: 299 case AArch64::STR_ZA: { 300 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA)); 301 // Spill and fill instructions have a single immediate used for both the 302 // vector select offset and optional memory offset. Replicate the decoded 303 // immediate. 304 const MCOperand &Imm4Op = MI.getOperand(2); 305 assert(Imm4Op.isImm() && "Unexpected operand type!"); 306 MI.addOperand(Imm4Op); 307 break; 308 } 309 case AArch64::LD1_MXIPXX_H_B: 310 case AArch64::LD1_MXIPXX_V_B: 311 case AArch64::ST1_MXIPXX_H_B: 312 case AArch64::ST1_MXIPXX_V_B: 313 case AArch64::INSERT_MXIPZ_H_B: 314 case AArch64::INSERT_MXIPZ_V_B: 315 // e.g. 316 // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B 317 // ^ insert implicit 8-bit element tile 318 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 319 break; 320 case AArch64::EXTRACT_ZPMXI_H_B: 321 case AArch64::EXTRACT_ZPMXI_V_B: 322 // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>] 323 // ^ insert implicit 8-bit element tile 324 MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0)); 325 break; 326 } 327 328 if (Result != MCDisassembler::Fail) 329 return Result; 330 } 331 332 return MCDisassembler::Fail; 333 } 334 335 static MCSymbolizer * 336 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 337 LLVMSymbolLookupCallback SymbolLookUp, 338 void *DisInfo, MCContext *Ctx, 339 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 340 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 341 SymbolLookUp, DisInfo); 342 } 343 344 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 345 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 346 createAArch64Disassembler); 347 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 348 createAArch64Disassembler); 349 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 350 createAArch64ExternalSymbolizer); 351 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 352 createAArch64ExternalSymbolizer); 353 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 354 createAArch64Disassembler); 355 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 356 createAArch64ExternalSymbolizer); 357 358 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 359 createAArch64Disassembler); 360 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 361 createAArch64ExternalSymbolizer); 362 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 363 createAArch64Disassembler); 364 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 365 createAArch64ExternalSymbolizer); 366 } 367 368 static const unsigned FPR128DecoderTable[] = { 369 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 370 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 371 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 372 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 373 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 374 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 375 AArch64::Q30, AArch64::Q31 376 }; 377 378 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 379 uint64_t Addr, 380 const void *Decoder) { 381 if (RegNo > 31) 382 return Fail; 383 384 unsigned Register = FPR128DecoderTable[RegNo]; 385 Inst.addOperand(MCOperand::createReg(Register)); 386 return Success; 387 } 388 389 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 390 uint64_t Addr, 391 const void *Decoder) { 392 if (RegNo > 15) 393 return Fail; 394 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 395 } 396 397 static const unsigned FPR64DecoderTable[] = { 398 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 399 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 400 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 401 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 402 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 403 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 404 AArch64::D30, AArch64::D31 405 }; 406 407 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 408 uint64_t Addr, 409 const void *Decoder) { 410 if (RegNo > 31) 411 return Fail; 412 413 unsigned Register = FPR64DecoderTable[RegNo]; 414 Inst.addOperand(MCOperand::createReg(Register)); 415 return Success; 416 } 417 418 static const unsigned FPR32DecoderTable[] = { 419 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 420 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 421 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 422 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 423 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 424 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 425 AArch64::S30, AArch64::S31 426 }; 427 428 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 429 uint64_t Addr, 430 const void *Decoder) { 431 if (RegNo > 31) 432 return Fail; 433 434 unsigned Register = FPR32DecoderTable[RegNo]; 435 Inst.addOperand(MCOperand::createReg(Register)); 436 return Success; 437 } 438 439 static const unsigned FPR16DecoderTable[] = { 440 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 441 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 442 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 443 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 444 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 445 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 446 AArch64::H30, AArch64::H31 447 }; 448 449 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 450 uint64_t Addr, 451 const void *Decoder) { 452 if (RegNo > 31) 453 return Fail; 454 455 unsigned Register = FPR16DecoderTable[RegNo]; 456 Inst.addOperand(MCOperand::createReg(Register)); 457 return Success; 458 } 459 460 static const unsigned FPR8DecoderTable[] = { 461 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 462 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 463 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 464 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 465 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 466 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 467 AArch64::B30, AArch64::B31 468 }; 469 470 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 471 uint64_t Addr, 472 const void *Decoder) { 473 if (RegNo > 31) 474 return Fail; 475 476 unsigned Register = FPR8DecoderTable[RegNo]; 477 Inst.addOperand(MCOperand::createReg(Register)); 478 return Success; 479 } 480 481 static const unsigned GPR64DecoderTable[] = { 482 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 483 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 484 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 485 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 486 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 487 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 488 AArch64::LR, AArch64::XZR 489 }; 490 491 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 492 uint64_t Addr, 493 const void *Decoder) { 494 if (RegNo > 30) 495 return Fail; 496 497 unsigned Register = GPR64DecoderTable[RegNo]; 498 Inst.addOperand(MCOperand::createReg(Register)); 499 return Success; 500 } 501 502 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 503 uint64_t Addr, 504 const void *Decoder) { 505 if (RegNo > 31) 506 return Fail; 507 508 unsigned Register = GPR64DecoderTable[RegNo]; 509 Inst.addOperand(MCOperand::createReg(Register)); 510 return Success; 511 } 512 513 static const unsigned GPR64x8DecoderTable[] = { 514 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 515 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 516 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 517 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 518 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 519 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 520 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 521 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 522 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 523 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 524 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 525 AArch64::X22_X23_X24_X25_X26_X27_X28_FP, 526 }; 527 528 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 529 unsigned RegNo, 530 uint64_t Address, 531 const void *Decoder) { 532 if (RegNo > 22) 533 return Fail; 534 if (RegNo & 1) 535 return Fail; 536 537 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 538 Inst.addOperand(MCOperand::createReg(Register)); 539 return Success; 540 } 541 542 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 543 uint64_t Addr, 544 const void *Decoder) { 545 if (RegNo > 31) 546 return Fail; 547 unsigned Register = GPR64DecoderTable[RegNo]; 548 if (Register == AArch64::XZR) 549 Register = AArch64::SP; 550 Inst.addOperand(MCOperand::createReg(Register)); 551 return Success; 552 } 553 554 static const unsigned MatrixIndexGPR32_12_15DecoderTable[] = { 555 AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15 556 }; 557 558 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 559 unsigned RegNo, 560 uint64_t Addr, 561 const void *Decoder) { 562 if (RegNo > 3) 563 return Fail; 564 565 unsigned Register = MatrixIndexGPR32_12_15DecoderTable[RegNo]; 566 Inst.addOperand(MCOperand::createReg(Register)); 567 return Success; 568 } 569 570 static const unsigned GPR32DecoderTable[] = { 571 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 572 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 573 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 574 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 575 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 576 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 577 AArch64::W30, AArch64::WZR 578 }; 579 580 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 581 uint64_t Addr, 582 const void *Decoder) { 583 if (RegNo > 31) 584 return Fail; 585 586 unsigned Register = GPR32DecoderTable[RegNo]; 587 Inst.addOperand(MCOperand::createReg(Register)); 588 return Success; 589 } 590 591 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 592 uint64_t Addr, 593 const void *Decoder) { 594 if (RegNo > 31) 595 return Fail; 596 597 unsigned Register = GPR32DecoderTable[RegNo]; 598 if (Register == AArch64::WZR) 599 Register = AArch64::WSP; 600 Inst.addOperand(MCOperand::createReg(Register)); 601 return Success; 602 } 603 static const unsigned ZPRDecoderTable[] = { 604 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 605 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 606 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 607 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 608 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 609 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 610 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 611 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 612 }; 613 614 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 615 uint64_t Address, 616 const void* Decoder) { 617 if (RegNo > 31) 618 return Fail; 619 620 unsigned Register = ZPRDecoderTable[RegNo]; 621 Inst.addOperand(MCOperand::createReg(Register)); 622 return Success; 623 } 624 625 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 626 uint64_t Address, 627 const void *Decoder) { 628 if (RegNo > 15) 629 return Fail; 630 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 631 } 632 633 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 634 uint64_t Address, 635 const void *Decoder) { 636 if (RegNo > 7) 637 return Fail; 638 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 639 } 640 641 static const unsigned ZZDecoderTable[] = { 642 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 643 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 644 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 645 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 646 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 647 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 648 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 649 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 650 }; 651 652 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 653 uint64_t Address, 654 const void* Decoder) { 655 if (RegNo > 31) 656 return Fail; 657 unsigned Register = ZZDecoderTable[RegNo]; 658 Inst.addOperand(MCOperand::createReg(Register)); 659 return Success; 660 } 661 662 static const unsigned ZZZDecoderTable[] = { 663 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 664 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 665 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 666 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 667 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 668 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 669 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 670 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 671 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 672 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 673 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 674 }; 675 676 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 677 uint64_t Address, 678 const void* Decoder) { 679 if (RegNo > 31) 680 return Fail; 681 unsigned Register = ZZZDecoderTable[RegNo]; 682 Inst.addOperand(MCOperand::createReg(Register)); 683 return Success; 684 } 685 686 static const unsigned ZZZZDecoderTable[] = { 687 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 688 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 689 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 690 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 691 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 692 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 693 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 694 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 695 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 696 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 697 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 698 }; 699 700 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 701 uint64_t Address, 702 const void* Decoder) { 703 if (RegNo > 31) 704 return Fail; 705 unsigned Register = ZZZZDecoderTable[RegNo]; 706 Inst.addOperand(MCOperand::createReg(Register)); 707 return Success; 708 } 709 710 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 711 unsigned RegMask, 712 uint64_t Address, 713 const void *Decoder) { 714 if (RegMask > 0xFF) 715 return Fail; 716 Inst.addOperand(MCOperand::createImm(RegMask)); 717 return Success; 718 } 719 720 static const SmallVector<SmallVector<unsigned, 16>, 5> 721 MatrixZATileDecoderTable = { 722 {AArch64::ZAB0}, 723 {AArch64::ZAH0, AArch64::ZAH1}, 724 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 725 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 726 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 727 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 728 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 729 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 730 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 731 732 template <unsigned NumBitsForTile> 733 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 734 uint64_t Address, const void *Decoder) { 735 unsigned LastReg = (1 << NumBitsForTile) - 1; 736 if (RegNo > LastReg) 737 return Fail; 738 Inst.addOperand( 739 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 740 return Success; 741 } 742 743 static const unsigned PPRDecoderTable[] = { 744 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 745 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 746 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 747 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 748 }; 749 750 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 751 uint64_t Addr, const void *Decoder) { 752 if (RegNo > 15) 753 return Fail; 754 755 unsigned Register = PPRDecoderTable[RegNo]; 756 Inst.addOperand(MCOperand::createReg(Register)); 757 return Success; 758 } 759 760 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 761 uint64_t Addr, 762 const void* Decoder) { 763 if (RegNo > 7) 764 return Fail; 765 766 // Just reuse the PPR decode table 767 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 768 } 769 770 static const unsigned VectorDecoderTable[] = { 771 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 772 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 773 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 774 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 775 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 776 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 777 AArch64::Q30, AArch64::Q31 778 }; 779 780 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 781 uint64_t Addr, 782 const void *Decoder) { 783 if (RegNo > 31) 784 return Fail; 785 786 unsigned Register = VectorDecoderTable[RegNo]; 787 Inst.addOperand(MCOperand::createReg(Register)); 788 return Success; 789 } 790 791 static const unsigned QQDecoderTable[] = { 792 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 793 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 794 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 795 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 796 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 797 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 798 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 799 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 800 }; 801 802 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 803 uint64_t Addr, const void *Decoder) { 804 if (RegNo > 31) 805 return Fail; 806 unsigned Register = QQDecoderTable[RegNo]; 807 Inst.addOperand(MCOperand::createReg(Register)); 808 return Success; 809 } 810 811 static const unsigned QQQDecoderTable[] = { 812 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 813 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 814 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 815 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 816 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 817 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 818 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 819 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 820 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 821 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 822 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 823 }; 824 825 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 826 uint64_t Addr, const void *Decoder) { 827 if (RegNo > 31) 828 return Fail; 829 unsigned Register = QQQDecoderTable[RegNo]; 830 Inst.addOperand(MCOperand::createReg(Register)); 831 return Success; 832 } 833 834 static const unsigned QQQQDecoderTable[] = { 835 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 836 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 837 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 838 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 839 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 840 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 841 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 842 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 843 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 844 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 845 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 846 }; 847 848 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 849 uint64_t Addr, 850 const void *Decoder) { 851 if (RegNo > 31) 852 return Fail; 853 unsigned Register = QQQQDecoderTable[RegNo]; 854 Inst.addOperand(MCOperand::createReg(Register)); 855 return Success; 856 } 857 858 static const unsigned DDDecoderTable[] = { 859 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 860 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 861 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 862 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 863 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 864 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 865 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 866 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 867 }; 868 869 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 870 uint64_t Addr, const void *Decoder) { 871 if (RegNo > 31) 872 return Fail; 873 unsigned Register = DDDecoderTable[RegNo]; 874 Inst.addOperand(MCOperand::createReg(Register)); 875 return Success; 876 } 877 878 static const unsigned DDDDecoderTable[] = { 879 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 880 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 881 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 882 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 883 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 884 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 885 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 886 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 887 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 888 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 889 AArch64::D30_D31_D0, AArch64::D31_D0_D1 890 }; 891 892 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 893 uint64_t Addr, const void *Decoder) { 894 if (RegNo > 31) 895 return Fail; 896 unsigned Register = DDDDecoderTable[RegNo]; 897 Inst.addOperand(MCOperand::createReg(Register)); 898 return Success; 899 } 900 901 static const unsigned DDDDDecoderTable[] = { 902 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 903 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 904 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 905 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 906 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 907 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 908 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 909 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 910 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 911 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 912 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 913 }; 914 915 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 916 uint64_t Addr, 917 const void *Decoder) { 918 if (RegNo > 31) 919 return Fail; 920 unsigned Register = DDDDDecoderTable[RegNo]; 921 Inst.addOperand(MCOperand::createReg(Register)); 922 return Success; 923 } 924 925 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 926 uint64_t Addr, 927 const void *Decoder) { 928 // scale{5} is asserted as 1 in tblgen. 929 Imm |= 0x20; 930 Inst.addOperand(MCOperand::createImm(64 - Imm)); 931 return Success; 932 } 933 934 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 935 uint64_t Addr, 936 const void *Decoder) { 937 Inst.addOperand(MCOperand::createImm(64 - Imm)); 938 return Success; 939 } 940 941 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 942 uint64_t Addr, const void *Decoder) { 943 int64_t ImmVal = Imm; 944 const AArch64Disassembler *Dis = 945 static_cast<const AArch64Disassembler *>(Decoder); 946 947 // Sign-extend 19-bit immediate. 948 if (ImmVal & (1 << (19 - 1))) 949 ImmVal |= ~((1LL << 19) - 1); 950 951 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 952 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 953 Inst.addOperand(MCOperand::createImm(ImmVal)); 954 return Success; 955 } 956 957 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 958 uint64_t Address, const void *Decoder) { 959 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 960 Inst.addOperand(MCOperand::createImm(Imm & 1)); 961 return Success; 962 } 963 964 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 965 uint64_t Address, 966 const void *Decoder) { 967 Inst.addOperand(MCOperand::createImm(Imm)); 968 969 // Every system register in the encoding space is valid with the syntax 970 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 971 return Success; 972 } 973 974 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 975 uint64_t Address, 976 const void *Decoder) { 977 Inst.addOperand(MCOperand::createImm(Imm)); 978 979 return Success; 980 } 981 982 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 983 uint64_t Address, 984 const void *Decoder) { 985 // This decoder exists to add the dummy Lane operand to the MCInst, which must 986 // be 1 in assembly but has no other real manifestation. 987 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 988 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 989 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 990 991 if (IsToVec) { 992 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 993 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 994 } else { 995 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 996 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 997 } 998 999 // Add the lane 1000 Inst.addOperand(MCOperand::createImm(1)); 1001 1002 return Success; 1003 } 1004 1005 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 1006 unsigned Add) { 1007 Inst.addOperand(MCOperand::createImm(Add - Imm)); 1008 return Success; 1009 } 1010 1011 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 1012 unsigned Add) { 1013 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 1014 return Success; 1015 } 1016 1017 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 1018 uint64_t Addr, const void *Decoder) { 1019 return DecodeVecShiftRImm(Inst, Imm, 64); 1020 } 1021 1022 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 1023 uint64_t Addr, 1024 const void *Decoder) { 1025 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 1026 } 1027 1028 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 1029 uint64_t Addr, const void *Decoder) { 1030 return DecodeVecShiftRImm(Inst, Imm, 32); 1031 } 1032 1033 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 1034 uint64_t Addr, 1035 const void *Decoder) { 1036 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 1037 } 1038 1039 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 1040 uint64_t Addr, const void *Decoder) { 1041 return DecodeVecShiftRImm(Inst, Imm, 16); 1042 } 1043 1044 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 1045 uint64_t Addr, 1046 const void *Decoder) { 1047 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 1048 } 1049 1050 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 1051 uint64_t Addr, const void *Decoder) { 1052 return DecodeVecShiftRImm(Inst, Imm, 8); 1053 } 1054 1055 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 1056 uint64_t Addr, const void *Decoder) { 1057 return DecodeVecShiftLImm(Inst, Imm, 64); 1058 } 1059 1060 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 1061 uint64_t Addr, const void *Decoder) { 1062 return DecodeVecShiftLImm(Inst, Imm, 32); 1063 } 1064 1065 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 1066 uint64_t Addr, const void *Decoder) { 1067 return DecodeVecShiftLImm(Inst, Imm, 16); 1068 } 1069 1070 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 1071 uint64_t Addr, const void *Decoder) { 1072 return DecodeVecShiftLImm(Inst, Imm, 8); 1073 } 1074 1075 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 1076 uint64_t Addr, 1077 const void *Decoder) { 1078 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1079 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1080 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1081 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 1082 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 1083 unsigned shift = (shiftHi << 6) | shiftLo; 1084 switch (Inst.getOpcode()) { 1085 default: 1086 return Fail; 1087 case AArch64::ADDWrs: 1088 case AArch64::ADDSWrs: 1089 case AArch64::SUBWrs: 1090 case AArch64::SUBSWrs: 1091 // if shift == '11' then ReservedValue() 1092 if (shiftHi == 0x3) 1093 return Fail; 1094 LLVM_FALLTHROUGH; 1095 case AArch64::ANDWrs: 1096 case AArch64::ANDSWrs: 1097 case AArch64::BICWrs: 1098 case AArch64::BICSWrs: 1099 case AArch64::ORRWrs: 1100 case AArch64::ORNWrs: 1101 case AArch64::EORWrs: 1102 case AArch64::EONWrs: { 1103 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1104 if (shiftLo >> 5 == 1) 1105 return Fail; 1106 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1107 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1108 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1109 break; 1110 } 1111 case AArch64::ADDXrs: 1112 case AArch64::ADDSXrs: 1113 case AArch64::SUBXrs: 1114 case AArch64::SUBSXrs: 1115 // if shift == '11' then ReservedValue() 1116 if (shiftHi == 0x3) 1117 return Fail; 1118 LLVM_FALLTHROUGH; 1119 case AArch64::ANDXrs: 1120 case AArch64::ANDSXrs: 1121 case AArch64::BICXrs: 1122 case AArch64::BICSXrs: 1123 case AArch64::ORRXrs: 1124 case AArch64::ORNXrs: 1125 case AArch64::EORXrs: 1126 case AArch64::EONXrs: 1127 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1128 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1129 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1130 break; 1131 } 1132 1133 Inst.addOperand(MCOperand::createImm(shift)); 1134 return Success; 1135 } 1136 1137 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1138 uint64_t Addr, 1139 const void *Decoder) { 1140 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1141 unsigned imm = fieldFromInstruction(insn, 5, 16); 1142 unsigned shift = fieldFromInstruction(insn, 21, 2); 1143 shift <<= 4; 1144 switch (Inst.getOpcode()) { 1145 default: 1146 return Fail; 1147 case AArch64::MOVZWi: 1148 case AArch64::MOVNWi: 1149 case AArch64::MOVKWi: 1150 if (shift & (1U << 5)) 1151 return Fail; 1152 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1153 break; 1154 case AArch64::MOVZXi: 1155 case AArch64::MOVNXi: 1156 case AArch64::MOVKXi: 1157 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1158 break; 1159 } 1160 1161 if (Inst.getOpcode() == AArch64::MOVKWi || 1162 Inst.getOpcode() == AArch64::MOVKXi) 1163 Inst.addOperand(Inst.getOperand(0)); 1164 1165 Inst.addOperand(MCOperand::createImm(imm)); 1166 Inst.addOperand(MCOperand::createImm(shift)); 1167 return Success; 1168 } 1169 1170 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1171 uint64_t Addr, 1172 const void *Decoder) { 1173 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1174 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1175 unsigned offset = fieldFromInstruction(insn, 10, 12); 1176 const AArch64Disassembler *Dis = 1177 static_cast<const AArch64Disassembler *>(Decoder); 1178 1179 switch (Inst.getOpcode()) { 1180 default: 1181 return Fail; 1182 case AArch64::PRFMui: 1183 // Rt is an immediate in prefetch. 1184 Inst.addOperand(MCOperand::createImm(Rt)); 1185 break; 1186 case AArch64::STRBBui: 1187 case AArch64::LDRBBui: 1188 case AArch64::LDRSBWui: 1189 case AArch64::STRHHui: 1190 case AArch64::LDRHHui: 1191 case AArch64::LDRSHWui: 1192 case AArch64::STRWui: 1193 case AArch64::LDRWui: 1194 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1195 break; 1196 case AArch64::LDRSBXui: 1197 case AArch64::LDRSHXui: 1198 case AArch64::LDRSWui: 1199 case AArch64::STRXui: 1200 case AArch64::LDRXui: 1201 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1202 break; 1203 case AArch64::LDRQui: 1204 case AArch64::STRQui: 1205 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1206 break; 1207 case AArch64::LDRDui: 1208 case AArch64::STRDui: 1209 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1210 break; 1211 case AArch64::LDRSui: 1212 case AArch64::STRSui: 1213 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1214 break; 1215 case AArch64::LDRHui: 1216 case AArch64::STRHui: 1217 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1218 break; 1219 case AArch64::LDRBui: 1220 case AArch64::STRBui: 1221 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1222 break; 1223 } 1224 1225 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1226 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1227 Inst.addOperand(MCOperand::createImm(offset)); 1228 return Success; 1229 } 1230 1231 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1232 uint64_t Addr, 1233 const void *Decoder) { 1234 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1235 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1236 int64_t offset = fieldFromInstruction(insn, 12, 9); 1237 1238 // offset is a 9-bit signed immediate, so sign extend it to 1239 // fill the unsigned. 1240 if (offset & (1 << (9 - 1))) 1241 offset |= ~((1LL << 9) - 1); 1242 1243 // First operand is always the writeback to the address register, if needed. 1244 switch (Inst.getOpcode()) { 1245 default: 1246 break; 1247 case AArch64::LDRSBWpre: 1248 case AArch64::LDRSHWpre: 1249 case AArch64::STRBBpre: 1250 case AArch64::LDRBBpre: 1251 case AArch64::STRHHpre: 1252 case AArch64::LDRHHpre: 1253 case AArch64::STRWpre: 1254 case AArch64::LDRWpre: 1255 case AArch64::LDRSBWpost: 1256 case AArch64::LDRSHWpost: 1257 case AArch64::STRBBpost: 1258 case AArch64::LDRBBpost: 1259 case AArch64::STRHHpost: 1260 case AArch64::LDRHHpost: 1261 case AArch64::STRWpost: 1262 case AArch64::LDRWpost: 1263 case AArch64::LDRSBXpre: 1264 case AArch64::LDRSHXpre: 1265 case AArch64::STRXpre: 1266 case AArch64::LDRSWpre: 1267 case AArch64::LDRXpre: 1268 case AArch64::LDRSBXpost: 1269 case AArch64::LDRSHXpost: 1270 case AArch64::STRXpost: 1271 case AArch64::LDRSWpost: 1272 case AArch64::LDRXpost: 1273 case AArch64::LDRQpre: 1274 case AArch64::STRQpre: 1275 case AArch64::LDRQpost: 1276 case AArch64::STRQpost: 1277 case AArch64::LDRDpre: 1278 case AArch64::STRDpre: 1279 case AArch64::LDRDpost: 1280 case AArch64::STRDpost: 1281 case AArch64::LDRSpre: 1282 case AArch64::STRSpre: 1283 case AArch64::LDRSpost: 1284 case AArch64::STRSpost: 1285 case AArch64::LDRHpre: 1286 case AArch64::STRHpre: 1287 case AArch64::LDRHpost: 1288 case AArch64::STRHpost: 1289 case AArch64::LDRBpre: 1290 case AArch64::STRBpre: 1291 case AArch64::LDRBpost: 1292 case AArch64::STRBpost: 1293 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1294 break; 1295 } 1296 1297 switch (Inst.getOpcode()) { 1298 default: 1299 return Fail; 1300 case AArch64::PRFUMi: 1301 // Rt is an immediate in prefetch. 1302 Inst.addOperand(MCOperand::createImm(Rt)); 1303 break; 1304 case AArch64::STURBBi: 1305 case AArch64::LDURBBi: 1306 case AArch64::LDURSBWi: 1307 case AArch64::STURHHi: 1308 case AArch64::LDURHHi: 1309 case AArch64::LDURSHWi: 1310 case AArch64::STURWi: 1311 case AArch64::LDURWi: 1312 case AArch64::LDTRSBWi: 1313 case AArch64::LDTRSHWi: 1314 case AArch64::STTRWi: 1315 case AArch64::LDTRWi: 1316 case AArch64::STTRHi: 1317 case AArch64::LDTRHi: 1318 case AArch64::LDTRBi: 1319 case AArch64::STTRBi: 1320 case AArch64::LDRSBWpre: 1321 case AArch64::LDRSHWpre: 1322 case AArch64::STRBBpre: 1323 case AArch64::LDRBBpre: 1324 case AArch64::STRHHpre: 1325 case AArch64::LDRHHpre: 1326 case AArch64::STRWpre: 1327 case AArch64::LDRWpre: 1328 case AArch64::LDRSBWpost: 1329 case AArch64::LDRSHWpost: 1330 case AArch64::STRBBpost: 1331 case AArch64::LDRBBpost: 1332 case AArch64::STRHHpost: 1333 case AArch64::LDRHHpost: 1334 case AArch64::STRWpost: 1335 case AArch64::LDRWpost: 1336 case AArch64::STLURBi: 1337 case AArch64::STLURHi: 1338 case AArch64::STLURWi: 1339 case AArch64::LDAPURBi: 1340 case AArch64::LDAPURSBWi: 1341 case AArch64::LDAPURHi: 1342 case AArch64::LDAPURSHWi: 1343 case AArch64::LDAPURi: 1344 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1345 break; 1346 case AArch64::LDURSBXi: 1347 case AArch64::LDURSHXi: 1348 case AArch64::LDURSWi: 1349 case AArch64::STURXi: 1350 case AArch64::LDURXi: 1351 case AArch64::LDTRSBXi: 1352 case AArch64::LDTRSHXi: 1353 case AArch64::LDTRSWi: 1354 case AArch64::STTRXi: 1355 case AArch64::LDTRXi: 1356 case AArch64::LDRSBXpre: 1357 case AArch64::LDRSHXpre: 1358 case AArch64::STRXpre: 1359 case AArch64::LDRSWpre: 1360 case AArch64::LDRXpre: 1361 case AArch64::LDRSBXpost: 1362 case AArch64::LDRSHXpost: 1363 case AArch64::STRXpost: 1364 case AArch64::LDRSWpost: 1365 case AArch64::LDRXpost: 1366 case AArch64::LDAPURSWi: 1367 case AArch64::LDAPURSHXi: 1368 case AArch64::LDAPURSBXi: 1369 case AArch64::STLURXi: 1370 case AArch64::LDAPURXi: 1371 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1372 break; 1373 case AArch64::LDURQi: 1374 case AArch64::STURQi: 1375 case AArch64::LDRQpre: 1376 case AArch64::STRQpre: 1377 case AArch64::LDRQpost: 1378 case AArch64::STRQpost: 1379 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1380 break; 1381 case AArch64::LDURDi: 1382 case AArch64::STURDi: 1383 case AArch64::LDRDpre: 1384 case AArch64::STRDpre: 1385 case AArch64::LDRDpost: 1386 case AArch64::STRDpost: 1387 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1388 break; 1389 case AArch64::LDURSi: 1390 case AArch64::STURSi: 1391 case AArch64::LDRSpre: 1392 case AArch64::STRSpre: 1393 case AArch64::LDRSpost: 1394 case AArch64::STRSpost: 1395 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1396 break; 1397 case AArch64::LDURHi: 1398 case AArch64::STURHi: 1399 case AArch64::LDRHpre: 1400 case AArch64::STRHpre: 1401 case AArch64::LDRHpost: 1402 case AArch64::STRHpost: 1403 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1404 break; 1405 case AArch64::LDURBi: 1406 case AArch64::STURBi: 1407 case AArch64::LDRBpre: 1408 case AArch64::STRBpre: 1409 case AArch64::LDRBpost: 1410 case AArch64::STRBpost: 1411 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1412 break; 1413 } 1414 1415 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1416 Inst.addOperand(MCOperand::createImm(offset)); 1417 1418 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1419 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1420 bool IsFP = fieldFromInstruction(insn, 26, 1); 1421 1422 // Cannot write back to a transfer register (but xzr != sp). 1423 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1424 return SoftFail; 1425 1426 return Success; 1427 } 1428 1429 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1430 uint64_t Addr, 1431 const void *Decoder) { 1432 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1433 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1434 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1435 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1436 1437 unsigned Opcode = Inst.getOpcode(); 1438 switch (Opcode) { 1439 default: 1440 return Fail; 1441 case AArch64::STLXRW: 1442 case AArch64::STLXRB: 1443 case AArch64::STLXRH: 1444 case AArch64::STXRW: 1445 case AArch64::STXRB: 1446 case AArch64::STXRH: 1447 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1448 LLVM_FALLTHROUGH; 1449 case AArch64::LDARW: 1450 case AArch64::LDARB: 1451 case AArch64::LDARH: 1452 case AArch64::LDAXRW: 1453 case AArch64::LDAXRB: 1454 case AArch64::LDAXRH: 1455 case AArch64::LDXRW: 1456 case AArch64::LDXRB: 1457 case AArch64::LDXRH: 1458 case AArch64::STLRW: 1459 case AArch64::STLRB: 1460 case AArch64::STLRH: 1461 case AArch64::STLLRW: 1462 case AArch64::STLLRB: 1463 case AArch64::STLLRH: 1464 case AArch64::LDLARW: 1465 case AArch64::LDLARB: 1466 case AArch64::LDLARH: 1467 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1468 break; 1469 case AArch64::STLXRX: 1470 case AArch64::STXRX: 1471 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1472 LLVM_FALLTHROUGH; 1473 case AArch64::LDARX: 1474 case AArch64::LDAXRX: 1475 case AArch64::LDXRX: 1476 case AArch64::STLRX: 1477 case AArch64::LDLARX: 1478 case AArch64::STLLRX: 1479 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1480 break; 1481 case AArch64::STLXPW: 1482 case AArch64::STXPW: 1483 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1484 LLVM_FALLTHROUGH; 1485 case AArch64::LDAXPW: 1486 case AArch64::LDXPW: 1487 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1488 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1489 break; 1490 case AArch64::STLXPX: 1491 case AArch64::STXPX: 1492 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1493 LLVM_FALLTHROUGH; 1494 case AArch64::LDAXPX: 1495 case AArch64::LDXPX: 1496 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1497 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1498 break; 1499 } 1500 1501 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1502 1503 // You shouldn't load to the same register twice in an instruction... 1504 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1505 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1506 Rt == Rt2) 1507 return SoftFail; 1508 1509 return Success; 1510 } 1511 1512 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1513 uint64_t Addr, 1514 const void *Decoder) { 1515 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1516 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1517 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1518 int64_t offset = fieldFromInstruction(insn, 15, 7); 1519 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1520 1521 // offset is a 7-bit signed immediate, so sign extend it to 1522 // fill the unsigned. 1523 if (offset & (1 << (7 - 1))) 1524 offset |= ~((1LL << 7) - 1); 1525 1526 unsigned Opcode = Inst.getOpcode(); 1527 bool NeedsDisjointWritebackTransfer = false; 1528 1529 // First operand is always writeback of base register. 1530 switch (Opcode) { 1531 default: 1532 break; 1533 case AArch64::LDPXpost: 1534 case AArch64::STPXpost: 1535 case AArch64::LDPSWpost: 1536 case AArch64::LDPXpre: 1537 case AArch64::STPXpre: 1538 case AArch64::LDPSWpre: 1539 case AArch64::LDPWpost: 1540 case AArch64::STPWpost: 1541 case AArch64::LDPWpre: 1542 case AArch64::STPWpre: 1543 case AArch64::LDPQpost: 1544 case AArch64::STPQpost: 1545 case AArch64::LDPQpre: 1546 case AArch64::STPQpre: 1547 case AArch64::LDPDpost: 1548 case AArch64::STPDpost: 1549 case AArch64::LDPDpre: 1550 case AArch64::STPDpre: 1551 case AArch64::LDPSpost: 1552 case AArch64::STPSpost: 1553 case AArch64::LDPSpre: 1554 case AArch64::STPSpre: 1555 case AArch64::STGPpre: 1556 case AArch64::STGPpost: 1557 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1558 break; 1559 } 1560 1561 switch (Opcode) { 1562 default: 1563 return Fail; 1564 case AArch64::LDPXpost: 1565 case AArch64::STPXpost: 1566 case AArch64::LDPSWpost: 1567 case AArch64::LDPXpre: 1568 case AArch64::STPXpre: 1569 case AArch64::LDPSWpre: 1570 case AArch64::STGPpre: 1571 case AArch64::STGPpost: 1572 NeedsDisjointWritebackTransfer = true; 1573 LLVM_FALLTHROUGH; 1574 case AArch64::LDNPXi: 1575 case AArch64::STNPXi: 1576 case AArch64::LDPXi: 1577 case AArch64::STPXi: 1578 case AArch64::LDPSWi: 1579 case AArch64::STGPi: 1580 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1581 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1582 break; 1583 case AArch64::LDPWpost: 1584 case AArch64::STPWpost: 1585 case AArch64::LDPWpre: 1586 case AArch64::STPWpre: 1587 NeedsDisjointWritebackTransfer = true; 1588 LLVM_FALLTHROUGH; 1589 case AArch64::LDNPWi: 1590 case AArch64::STNPWi: 1591 case AArch64::LDPWi: 1592 case AArch64::STPWi: 1593 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1594 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1595 break; 1596 case AArch64::LDNPQi: 1597 case AArch64::STNPQi: 1598 case AArch64::LDPQpost: 1599 case AArch64::STPQpost: 1600 case AArch64::LDPQi: 1601 case AArch64::STPQi: 1602 case AArch64::LDPQpre: 1603 case AArch64::STPQpre: 1604 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1605 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1606 break; 1607 case AArch64::LDNPDi: 1608 case AArch64::STNPDi: 1609 case AArch64::LDPDpost: 1610 case AArch64::STPDpost: 1611 case AArch64::LDPDi: 1612 case AArch64::STPDi: 1613 case AArch64::LDPDpre: 1614 case AArch64::STPDpre: 1615 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1616 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1617 break; 1618 case AArch64::LDNPSi: 1619 case AArch64::STNPSi: 1620 case AArch64::LDPSpost: 1621 case AArch64::STPSpost: 1622 case AArch64::LDPSi: 1623 case AArch64::STPSi: 1624 case AArch64::LDPSpre: 1625 case AArch64::STPSpre: 1626 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1627 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1628 break; 1629 } 1630 1631 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1632 Inst.addOperand(MCOperand::createImm(offset)); 1633 1634 // You shouldn't load to the same register twice in an instruction... 1635 if (IsLoad && Rt == Rt2) 1636 return SoftFail; 1637 1638 // ... or do any operation that writes-back to a transfer register. But note 1639 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1640 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1641 return SoftFail; 1642 1643 return Success; 1644 } 1645 1646 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1647 uint64_t Addr, 1648 const void *Decoder) { 1649 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1650 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1651 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1652 fieldFromInstruction(insn, 12, 9); 1653 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1654 1655 switch (Inst.getOpcode()) { 1656 default: 1657 return Fail; 1658 case AArch64::LDRAAwriteback: 1659 case AArch64::LDRABwriteback: 1660 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1661 Decoder); 1662 break; 1663 case AArch64::LDRAAindexed: 1664 case AArch64::LDRABindexed: 1665 break; 1666 } 1667 1668 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1669 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1670 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1671 1672 if (writeback && Rt == Rn && Rn != 31) { 1673 return SoftFail; 1674 } 1675 1676 return Success; 1677 } 1678 1679 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1680 uint64_t Addr, 1681 const void *Decoder) { 1682 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1683 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1684 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1685 unsigned extend = fieldFromInstruction(insn, 10, 6); 1686 1687 unsigned shift = extend & 0x7; 1688 if (shift > 4) 1689 return Fail; 1690 1691 switch (Inst.getOpcode()) { 1692 default: 1693 return Fail; 1694 case AArch64::ADDWrx: 1695 case AArch64::SUBWrx: 1696 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1697 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1698 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1699 break; 1700 case AArch64::ADDSWrx: 1701 case AArch64::SUBSWrx: 1702 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1703 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1704 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1705 break; 1706 case AArch64::ADDXrx: 1707 case AArch64::SUBXrx: 1708 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1709 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1710 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1711 break; 1712 case AArch64::ADDSXrx: 1713 case AArch64::SUBSXrx: 1714 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1715 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1716 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1717 break; 1718 case AArch64::ADDXrx64: 1719 case AArch64::SUBXrx64: 1720 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1721 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1722 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1723 break; 1724 case AArch64::SUBSXrx64: 1725 case AArch64::ADDSXrx64: 1726 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1727 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1728 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1729 break; 1730 } 1731 1732 Inst.addOperand(MCOperand::createImm(extend)); 1733 return Success; 1734 } 1735 1736 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1737 uint64_t Addr, 1738 const void *Decoder) { 1739 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1740 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1741 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1742 unsigned imm; 1743 1744 if (Datasize) { 1745 if (Inst.getOpcode() == AArch64::ANDSXri) 1746 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1747 else 1748 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1749 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1750 imm = fieldFromInstruction(insn, 10, 13); 1751 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1752 return Fail; 1753 } else { 1754 if (Inst.getOpcode() == AArch64::ANDSWri) 1755 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1756 else 1757 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1758 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1759 imm = fieldFromInstruction(insn, 10, 12); 1760 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1761 return Fail; 1762 } 1763 Inst.addOperand(MCOperand::createImm(imm)); 1764 return Success; 1765 } 1766 1767 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1768 uint64_t Addr, 1769 const void *Decoder) { 1770 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1771 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1772 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1773 imm |= fieldFromInstruction(insn, 5, 5); 1774 1775 if (Inst.getOpcode() == AArch64::MOVID) 1776 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1777 else 1778 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1779 1780 Inst.addOperand(MCOperand::createImm(imm)); 1781 1782 switch (Inst.getOpcode()) { 1783 default: 1784 break; 1785 case AArch64::MOVIv4i16: 1786 case AArch64::MOVIv8i16: 1787 case AArch64::MVNIv4i16: 1788 case AArch64::MVNIv8i16: 1789 case AArch64::MOVIv2i32: 1790 case AArch64::MOVIv4i32: 1791 case AArch64::MVNIv2i32: 1792 case AArch64::MVNIv4i32: 1793 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1794 break; 1795 case AArch64::MOVIv2s_msl: 1796 case AArch64::MOVIv4s_msl: 1797 case AArch64::MVNIv2s_msl: 1798 case AArch64::MVNIv4s_msl: 1799 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1800 break; 1801 } 1802 1803 return Success; 1804 } 1805 1806 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1807 uint64_t Addr, 1808 const void *Decoder) { 1809 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1810 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1811 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1812 imm |= fieldFromInstruction(insn, 5, 5); 1813 1814 // Tied operands added twice. 1815 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1816 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1817 1818 Inst.addOperand(MCOperand::createImm(imm)); 1819 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1820 1821 return Success; 1822 } 1823 1824 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1825 uint64_t Addr, const void *Decoder) { 1826 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1827 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1828 imm |= fieldFromInstruction(insn, 29, 2); 1829 const AArch64Disassembler *Dis = 1830 static_cast<const AArch64Disassembler *>(Decoder); 1831 1832 // Sign-extend the 21-bit immediate. 1833 if (imm & (1 << (21 - 1))) 1834 imm |= ~((1LL << 21) - 1); 1835 1836 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1837 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1838 Inst.addOperand(MCOperand::createImm(imm)); 1839 1840 return Success; 1841 } 1842 1843 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1844 uint64_t Addr, const void *Decoder) { 1845 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1846 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1847 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1848 unsigned S = fieldFromInstruction(insn, 29, 1); 1849 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1850 1851 unsigned ShifterVal = (Imm >> 12) & 3; 1852 unsigned ImmVal = Imm & 0xFFF; 1853 const AArch64Disassembler *Dis = 1854 static_cast<const AArch64Disassembler *>(Decoder); 1855 1856 if (ShifterVal != 0 && ShifterVal != 1) 1857 return Fail; 1858 1859 if (Datasize) { 1860 if (Rd == 31 && !S) 1861 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1862 else 1863 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1864 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1865 } else { 1866 if (Rd == 31 && !S) 1867 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1868 else 1869 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1870 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1871 } 1872 1873 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1874 Inst.addOperand(MCOperand::createImm(ImmVal)); 1875 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1876 return Success; 1877 } 1878 1879 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1880 uint64_t Addr, 1881 const void *Decoder) { 1882 int64_t imm = fieldFromInstruction(insn, 0, 26); 1883 const AArch64Disassembler *Dis = 1884 static_cast<const AArch64Disassembler *>(Decoder); 1885 1886 // Sign-extend the 26-bit immediate. 1887 if (imm & (1 << (26 - 1))) 1888 imm |= ~((1LL << 26) - 1); 1889 1890 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1891 Inst.addOperand(MCOperand::createImm(imm)); 1892 1893 return Success; 1894 } 1895 1896 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1897 uint64_t Addr, 1898 const void *Decoder) { 1899 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1900 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1901 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1902 uint64_t pstate_field = (op1 << 3) | op2; 1903 1904 switch (pstate_field) { 1905 case 0x01: // XAFlag 1906 case 0x02: // AXFlag 1907 return Fail; 1908 } 1909 1910 if ((pstate_field == AArch64PState::PAN || 1911 pstate_field == AArch64PState::UAO || 1912 pstate_field == AArch64PState::SSBS) && crm > 1) 1913 return Fail; 1914 1915 Inst.addOperand(MCOperand::createImm(pstate_field)); 1916 Inst.addOperand(MCOperand::createImm(crm)); 1917 1918 const AArch64Disassembler *Dis = 1919 static_cast<const AArch64Disassembler *>(Decoder); 1920 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1921 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1922 return Success; 1923 return Fail; 1924 } 1925 1926 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1927 uint64_t Addr, const void *Decoder) { 1928 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1929 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1930 bit |= fieldFromInstruction(insn, 19, 5); 1931 int64_t dst = fieldFromInstruction(insn, 5, 14); 1932 const AArch64Disassembler *Dis = 1933 static_cast<const AArch64Disassembler *>(Decoder); 1934 1935 // Sign-extend 14-bit immediate. 1936 if (dst & (1 << (14 - 1))) 1937 dst |= ~((1LL << 14) - 1); 1938 1939 if (fieldFromInstruction(insn, 31, 1) == 0) 1940 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1941 else 1942 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1943 Inst.addOperand(MCOperand::createImm(bit)); 1944 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1945 Inst.addOperand(MCOperand::createImm(dst)); 1946 1947 return Success; 1948 } 1949 1950 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1951 unsigned RegClassID, 1952 unsigned RegNo, 1953 uint64_t Addr, 1954 const void *Decoder) { 1955 // Register number must be even (see CASP instruction) 1956 if (RegNo & 0x1) 1957 return Fail; 1958 1959 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1960 Inst.addOperand(MCOperand::createReg(Reg)); 1961 return Success; 1962 } 1963 1964 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1965 unsigned RegNo, 1966 uint64_t Addr, 1967 const void *Decoder) { 1968 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1969 AArch64::WSeqPairsClassRegClassID, 1970 RegNo, Addr, Decoder); 1971 } 1972 1973 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1974 unsigned RegNo, 1975 uint64_t Addr, 1976 const void *Decoder) { 1977 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1978 AArch64::XSeqPairsClassRegClassID, 1979 RegNo, Addr, Decoder); 1980 } 1981 1982 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, 1983 uint64_t Addr, 1984 const void *Decoder) { 1985 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1986 unsigned imm = fieldFromInstruction(insn, 5, 13); 1987 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1988 return Fail; 1989 1990 // The same (tied) operand is added twice to the instruction. 1991 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1992 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1993 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1994 Inst.addOperand(MCOperand::createImm(imm)); 1995 return Success; 1996 } 1997 1998 template <int Bits> 1999 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 2000 const void *Decoder) { 2001 if (Imm & ~((1LL << Bits) - 1)) 2002 return Fail; 2003 2004 // Imm is a signed immediate, so sign extend it. 2005 if (Imm & (1 << (Bits - 1))) 2006 Imm |= ~((1LL << Bits) - 1); 2007 2008 Inst.addOperand(MCOperand::createImm(Imm)); 2009 return Success; 2010 } 2011 2012 // Decode 8-bit signed/unsigned immediate for a given element width. 2013 template <int ElementWidth> 2014 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 2015 uint64_t Addr, const void *Decoder) { 2016 unsigned Val = (uint8_t)Imm; 2017 unsigned Shift = (Imm & 0x100) ? 8 : 0; 2018 if (ElementWidth == 8 && Shift) 2019 return Fail; 2020 Inst.addOperand(MCOperand::createImm(Val)); 2021 Inst.addOperand(MCOperand::createImm(Shift)); 2022 return Success; 2023 } 2024 2025 // Decode uimm4 ranged from 1-16. 2026 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 2027 uint64_t Addr, const void *Decoder) { 2028 Inst.addOperand(MCOperand::createImm(Imm + 1)); 2029 return Success; 2030 } 2031 2032 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 2033 const void *Decoder) { 2034 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 2035 Inst.addOperand(MCOperand::createImm(Imm)); 2036 return Success; 2037 } 2038 return Fail; 2039 } 2040