1 //=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that performs load / store related peephole
11 // optimizations. This pass should be run after register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64InstrInfo.h"
16 #include "AArch64Subtarget.h"
17 #include "MCTargetDesc/AArch64AddressingModes.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "aarch64-ldst-opt"
35 
36 /// AArch64AllocLoadStoreOpt - Post-register allocation pass to combine
37 /// load / store instructions to form ldp / stp instructions.
38 
39 STATISTIC(NumPairCreated, "Number of load/store pair instructions generated");
40 STATISTIC(NumPostFolded, "Number of post-index updates folded");
41 STATISTIC(NumPreFolded, "Number of pre-index updates folded");
42 STATISTIC(NumUnscaledPairCreated,
43           "Number of load/store from unscaled generated");
44 
45 static cl::opt<unsigned> ScanLimit("aarch64-load-store-scan-limit",
46                                    cl::init(20), cl::Hidden);
47 
48 // Place holder while testing unscaled load/store combining
49 static cl::opt<bool> EnableAArch64UnscaledMemOp(
50     "aarch64-unscaled-mem-op", cl::Hidden,
51     cl::desc("Allow AArch64 unscaled load/store combining"), cl::init(true));
52 
53 namespace llvm {
54 void initializeAArch64LoadStoreOptPass(PassRegistry &);
55 }
56 
57 #define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
58 
59 namespace {
60 
61 typedef struct LdStPairFlags {
62   // If a matching instruction is found, MergeForward is set to true if the
63   // merge is to remove the first instruction and replace the second with
64   // a pair-wise insn, and false if the reverse is true.
65   bool MergeForward;
66 
67   // SExtIdx gives the index of the result of the load pair that must be
68   // extended. The value of SExtIdx assumes that the paired load produces the
69   // value in this order: (I, returned iterator), i.e., -1 means no value has
70   // to be extended, 0 means I, and 1 means the returned iterator.
71   int SExtIdx;
72 
73   LdStPairFlags() : MergeForward(false), SExtIdx(-1) {}
74 
75   void setMergeForward(bool V = true) { MergeForward = V; }
76   bool getMergeForward() const { return MergeForward; }
77 
78   void setSExtIdx(int V) { SExtIdx = V; }
79   int getSExtIdx() const { return SExtIdx; }
80 
81 } LdStPairFlags;
82 
83 struct AArch64LoadStoreOpt : public MachineFunctionPass {
84   static char ID;
85   AArch64LoadStoreOpt() : MachineFunctionPass(ID) {
86     initializeAArch64LoadStoreOptPass(*PassRegistry::getPassRegistry());
87   }
88 
89   const AArch64InstrInfo *TII;
90   const TargetRegisterInfo *TRI;
91 
92   // Scan the instructions looking for a load/store that can be combined
93   // with the current instruction into a load/store pair.
94   // Return the matching instruction if one is found, else MBB->end().
95   MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
96                                                LdStPairFlags &Flags,
97                                                unsigned Limit);
98   // Merge the two instructions indicated into a single pair-wise instruction.
99   // If MergeForward is true, erase the first instruction and fold its
100   // operation into the second. If false, the reverse. Return the instruction
101   // following the first instruction (which may change during processing).
102   MachineBasicBlock::iterator
103   mergePairedInsns(MachineBasicBlock::iterator I,
104                    MachineBasicBlock::iterator Paired,
105                    const LdStPairFlags &Flags);
106 
107   // Scan the instruction list to find a base register update that can
108   // be combined with the current instruction (a load or store) using
109   // pre or post indexed addressing with writeback. Scan forwards.
110   MachineBasicBlock::iterator
111   findMatchingUpdateInsnForward(MachineBasicBlock::iterator I, unsigned Limit,
112                                 int Value);
113 
114   // Scan the instruction list to find a base register update that can
115   // be combined with the current instruction (a load or store) using
116   // pre or post indexed addressing with writeback. Scan backwards.
117   MachineBasicBlock::iterator
118   findMatchingUpdateInsnBackward(MachineBasicBlock::iterator I, unsigned Limit);
119 
120   // Merge a pre-index base register update into a ld/st instruction.
121   MachineBasicBlock::iterator
122   mergePreIdxUpdateInsn(MachineBasicBlock::iterator I,
123                         MachineBasicBlock::iterator Update);
124 
125   // Merge a post-index base register update into a ld/st instruction.
126   MachineBasicBlock::iterator
127   mergePostIdxUpdateInsn(MachineBasicBlock::iterator I,
128                          MachineBasicBlock::iterator Update);
129 
130   bool optimizeBlock(MachineBasicBlock &MBB);
131 
132   bool runOnMachineFunction(MachineFunction &Fn) override;
133 
134   const char *getPassName() const override {
135     return AARCH64_LOAD_STORE_OPT_NAME;
136   }
137 };
138 char AArch64LoadStoreOpt::ID = 0;
139 } // namespace
140 
141 INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
142                 AARCH64_LOAD_STORE_OPT_NAME, false, false)
143 
144 static bool isUnscaledLdSt(unsigned Opc) {
145   switch (Opc) {
146   default:
147     return false;
148   case AArch64::STURSi:
149   case AArch64::STURDi:
150   case AArch64::STURQi:
151   case AArch64::STURWi:
152   case AArch64::STURXi:
153   case AArch64::LDURSi:
154   case AArch64::LDURDi:
155   case AArch64::LDURQi:
156   case AArch64::LDURWi:
157   case AArch64::LDURXi:
158   case AArch64::LDURSWi:
159     return true;
160   }
161 }
162 
163 static bool isUnscaledLdSt(MachineInstr *MI) {
164   return isUnscaledLdSt(MI->getOpcode());
165 }
166 
167 // Size in bytes of the data moved by an unscaled load or store
168 static int getMemSize(MachineInstr *MI) {
169   switch (MI->getOpcode()) {
170   default:
171     llvm_unreachable("Opcode has unknown size!");
172   case AArch64::STRSui:
173   case AArch64::STURSi:
174     return 4;
175   case AArch64::STRDui:
176   case AArch64::STURDi:
177     return 8;
178   case AArch64::STRQui:
179   case AArch64::STURQi:
180     return 16;
181   case AArch64::STRWui:
182   case AArch64::STURWi:
183     return 4;
184   case AArch64::STRXui:
185   case AArch64::STURXi:
186     return 8;
187   case AArch64::LDRSui:
188   case AArch64::LDURSi:
189     return 4;
190   case AArch64::LDRDui:
191   case AArch64::LDURDi:
192     return 8;
193   case AArch64::LDRQui:
194   case AArch64::LDURQi:
195     return 16;
196   case AArch64::LDRWui:
197   case AArch64::LDURWi:
198     return 4;
199   case AArch64::LDRXui:
200   case AArch64::LDURXi:
201     return 8;
202   case AArch64::LDRSWui:
203   case AArch64::LDURSWi:
204     return 4;
205   }
206 }
207 
208 static unsigned getMatchingNonSExtOpcode(unsigned Opc,
209                                          bool *IsValidLdStrOpc = nullptr) {
210   if (IsValidLdStrOpc)
211     *IsValidLdStrOpc = true;
212   switch (Opc) {
213   default:
214     if (IsValidLdStrOpc)
215       *IsValidLdStrOpc = false;
216     return UINT_MAX;
217   case AArch64::STRDui:
218   case AArch64::STURDi:
219   case AArch64::STRQui:
220   case AArch64::STURQi:
221   case AArch64::STRWui:
222   case AArch64::STURWi:
223   case AArch64::STRXui:
224   case AArch64::STURXi:
225   case AArch64::LDRDui:
226   case AArch64::LDURDi:
227   case AArch64::LDRQui:
228   case AArch64::LDURQi:
229   case AArch64::LDRWui:
230   case AArch64::LDURWi:
231   case AArch64::LDRXui:
232   case AArch64::LDURXi:
233   case AArch64::STRSui:
234   case AArch64::STURSi:
235   case AArch64::LDRSui:
236   case AArch64::LDURSi:
237     return Opc;
238   case AArch64::LDRSWui:
239     return AArch64::LDRWui;
240   case AArch64::LDURSWi:
241     return AArch64::LDURWi;
242   }
243 }
244 
245 static unsigned getMatchingPairOpcode(unsigned Opc) {
246   switch (Opc) {
247   default:
248     llvm_unreachable("Opcode has no pairwise equivalent!");
249   case AArch64::STRSui:
250   case AArch64::STURSi:
251     return AArch64::STPSi;
252   case AArch64::STRDui:
253   case AArch64::STURDi:
254     return AArch64::STPDi;
255   case AArch64::STRQui:
256   case AArch64::STURQi:
257     return AArch64::STPQi;
258   case AArch64::STRWui:
259   case AArch64::STURWi:
260     return AArch64::STPWi;
261   case AArch64::STRXui:
262   case AArch64::STURXi:
263     return AArch64::STPXi;
264   case AArch64::LDRSui:
265   case AArch64::LDURSi:
266     return AArch64::LDPSi;
267   case AArch64::LDRDui:
268   case AArch64::LDURDi:
269     return AArch64::LDPDi;
270   case AArch64::LDRQui:
271   case AArch64::LDURQi:
272     return AArch64::LDPQi;
273   case AArch64::LDRWui:
274   case AArch64::LDURWi:
275     return AArch64::LDPWi;
276   case AArch64::LDRXui:
277   case AArch64::LDURXi:
278     return AArch64::LDPXi;
279   case AArch64::LDRSWui:
280   case AArch64::LDURSWi:
281     return AArch64::LDPSWi;
282   }
283 }
284 
285 static unsigned getPreIndexedOpcode(unsigned Opc) {
286   switch (Opc) {
287   default:
288     llvm_unreachable("Opcode has no pre-indexed equivalent!");
289   case AArch64::STRSui:
290     return AArch64::STRSpre;
291   case AArch64::STRDui:
292     return AArch64::STRDpre;
293   case AArch64::STRQui:
294     return AArch64::STRQpre;
295   case AArch64::STRWui:
296     return AArch64::STRWpre;
297   case AArch64::STRXui:
298     return AArch64::STRXpre;
299   case AArch64::LDRSui:
300     return AArch64::LDRSpre;
301   case AArch64::LDRDui:
302     return AArch64::LDRDpre;
303   case AArch64::LDRQui:
304     return AArch64::LDRQpre;
305   case AArch64::LDRWui:
306     return AArch64::LDRWpre;
307   case AArch64::LDRXui:
308     return AArch64::LDRXpre;
309   case AArch64::LDRSWui:
310     return AArch64::LDRSWpre;
311   }
312 }
313 
314 static unsigned getPostIndexedOpcode(unsigned Opc) {
315   switch (Opc) {
316   default:
317     llvm_unreachable("Opcode has no post-indexed wise equivalent!");
318   case AArch64::STRSui:
319     return AArch64::STRSpost;
320   case AArch64::STRDui:
321     return AArch64::STRDpost;
322   case AArch64::STRQui:
323     return AArch64::STRQpost;
324   case AArch64::STRWui:
325     return AArch64::STRWpost;
326   case AArch64::STRXui:
327     return AArch64::STRXpost;
328   case AArch64::LDRSui:
329     return AArch64::LDRSpost;
330   case AArch64::LDRDui:
331     return AArch64::LDRDpost;
332   case AArch64::LDRQui:
333     return AArch64::LDRQpost;
334   case AArch64::LDRWui:
335     return AArch64::LDRWpost;
336   case AArch64::LDRXui:
337     return AArch64::LDRXpost;
338   case AArch64::LDRSWui:
339     return AArch64::LDRSWpost;
340   }
341 }
342 
343 static const MachineOperand &getLdStRegOp(const MachineInstr *MI) {
344   return MI->getOperand(0);
345 }
346 
347 static const MachineOperand &getLdStBaseOp(const MachineInstr *MI) {
348   return MI->getOperand(1);
349 }
350 
351 static const MachineOperand &getLdStOffsetOp(const MachineInstr *MI) {
352   return MI->getOperand(2);
353 }
354 
355 MachineBasicBlock::iterator
356 AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
357                                       MachineBasicBlock::iterator Paired,
358                                       const LdStPairFlags &Flags) {
359   MachineBasicBlock::iterator NextI = I;
360   ++NextI;
361   // If NextI is the second of the two instructions to be merged, we need
362   // to skip one further. Either way we merge will invalidate the iterator,
363   // and we don't need to scan the new instruction, as it's a pairwise
364   // instruction, which we're not considering for further action anyway.
365   if (NextI == Paired)
366     ++NextI;
367 
368   int SExtIdx = Flags.getSExtIdx();
369   unsigned Opc =
370       SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
371   bool IsUnscaled = isUnscaledLdSt(Opc);
372   int OffsetStride =
373       IsUnscaled && EnableAArch64UnscaledMemOp ? getMemSize(I) : 1;
374 
375   bool MergeForward = Flags.getMergeForward();
376   unsigned NewOpc = getMatchingPairOpcode(Opc);
377   // Insert our new paired instruction after whichever of the paired
378   // instructions MergeForward indicates.
379   MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
380   // Also based on MergeForward is from where we copy the base register operand
381   // so we get the flags compatible with the input code.
382   const MachineOperand &BaseRegOp =
383       MergeForward ? getLdStBaseOp(Paired) : getLdStBaseOp(I);
384 
385   // Which register is Rt and which is Rt2 depends on the offset order.
386   MachineInstr *RtMI, *Rt2MI;
387   if (getLdStOffsetOp(I).getImm() ==
388       getLdStOffsetOp(Paired).getImm() + OffsetStride) {
389     RtMI = Paired;
390     Rt2MI = I;
391     // Here we swapped the assumption made for SExtIdx.
392     // I.e., we turn ldp I, Paired into ldp Paired, I.
393     // Update the index accordingly.
394     if (SExtIdx != -1)
395       SExtIdx = (SExtIdx + 1) % 2;
396   } else {
397     RtMI = I;
398     Rt2MI = Paired;
399   }
400   // Handle Unscaled
401   int OffsetImm = getLdStOffsetOp(RtMI).getImm();
402   if (IsUnscaled && EnableAArch64UnscaledMemOp)
403     OffsetImm /= OffsetStride;
404 
405   // Construct the new instruction.
406   MachineInstrBuilder MIB = BuildMI(*I->getParent(), InsertionPoint,
407                                     I->getDebugLoc(), TII->get(NewOpc))
408                                 .addOperand(getLdStRegOp(RtMI))
409                                 .addOperand(getLdStRegOp(Rt2MI))
410                                 .addOperand(BaseRegOp)
411                                 .addImm(OffsetImm);
412   (void)MIB;
413 
414   // FIXME: Do we need/want to copy the mem operands from the source
415   //        instructions? Probably. What uses them after this?
416 
417   DEBUG(dbgs() << "Creating pair load/store. Replacing instructions:\n    ");
418   DEBUG(I->print(dbgs()));
419   DEBUG(dbgs() << "    ");
420   DEBUG(Paired->print(dbgs()));
421   DEBUG(dbgs() << "  with instruction:\n    ");
422 
423   if (SExtIdx != -1) {
424     // Generate the sign extension for the proper result of the ldp.
425     // I.e., with X1, that would be:
426     // %W1<def> = KILL %W1, %X1<imp-def>
427     // %X1<def> = SBFMXri %X1<kill>, 0, 31
428     MachineOperand &DstMO = MIB->getOperand(SExtIdx);
429     // Right now, DstMO has the extended register, since it comes from an
430     // extended opcode.
431     unsigned DstRegX = DstMO.getReg();
432     // Get the W variant of that register.
433     unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
434     // Update the result of LDP to use the W instead of the X variant.
435     DstMO.setReg(DstRegW);
436     DEBUG(((MachineInstr *)MIB)->print(dbgs()));
437     DEBUG(dbgs() << "\n");
438     // Make the machine verifier happy by providing a definition for
439     // the X register.
440     // Insert this definition right after the generated LDP, i.e., before
441     // InsertionPoint.
442     MachineInstrBuilder MIBKill =
443         BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
444                 TII->get(TargetOpcode::KILL), DstRegW)
445             .addReg(DstRegW)
446             .addReg(DstRegX, RegState::Define);
447     MIBKill->getOperand(2).setImplicit();
448     // Create the sign extension.
449     MachineInstrBuilder MIBSXTW =
450         BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
451                 TII->get(AArch64::SBFMXri), DstRegX)
452             .addReg(DstRegX)
453             .addImm(0)
454             .addImm(31);
455     (void)MIBSXTW;
456     DEBUG(dbgs() << "  Extend operand:\n    ");
457     DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
458     DEBUG(dbgs() << "\n");
459   } else {
460     DEBUG(((MachineInstr *)MIB)->print(dbgs()));
461     DEBUG(dbgs() << "\n");
462   }
463 
464   // Erase the old instructions.
465   I->eraseFromParent();
466   Paired->eraseFromParent();
467 
468   return NextI;
469 }
470 
471 /// trackRegDefsUses - Remember what registers the specified instruction uses
472 /// and modifies.
473 static void trackRegDefsUses(const MachineInstr *MI, BitVector &ModifiedRegs,
474                              BitVector &UsedRegs,
475                              const TargetRegisterInfo *TRI) {
476   for (const MachineOperand &MO : MI->operands()) {
477     if (MO.isRegMask())
478       ModifiedRegs.setBitsNotInMask(MO.getRegMask());
479 
480     if (!MO.isReg())
481       continue;
482     unsigned Reg = MO.getReg();
483     if (MO.isDef()) {
484       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
485         ModifiedRegs.set(*AI);
486     } else {
487       assert(MO.isUse() && "Reg operand not a def and not a use?!?");
488       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
489         UsedRegs.set(*AI);
490     }
491   }
492 }
493 
494 static bool inBoundsForPair(bool IsUnscaled, int Offset, int OffsetStride) {
495   // Convert the byte-offset used by unscaled into an "element" offset used
496   // by the scaled pair load/store instructions.
497   if (IsUnscaled)
498     Offset /= OffsetStride;
499 
500   return Offset <= 63 && Offset >= -64;
501 }
502 
503 // Do alignment, specialized to power of 2 and for signed ints,
504 // avoiding having to do a C-style cast from uint_64t to int when
505 // using RoundUpToAlignment from include/llvm/Support/MathExtras.h.
506 // FIXME: Move this function to include/MathExtras.h?
507 static int alignTo(int Num, int PowOf2) {
508   return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
509 }
510 
511 static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb,
512                      const AArch64InstrInfo *TII) {
513   // One of the instructions must modify memory.
514   if (!MIa->mayStore() && !MIb->mayStore())
515     return false;
516 
517   // Both instructions must be memory operations.
518   if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore())
519     return false;
520 
521   return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
522 }
523 
524 static bool mayAlias(MachineInstr *MIa,
525                      SmallVectorImpl<MachineInstr *> &MemInsns,
526                      const AArch64InstrInfo *TII) {
527   for (auto &MIb : MemInsns)
528     if (mayAlias(MIa, MIb, TII))
529       return true;
530 
531   return false;
532 }
533 
534 /// findMatchingInsn - Scan the instructions looking for a load/store that can
535 /// be combined with the current instruction into a load/store pair.
536 MachineBasicBlock::iterator
537 AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
538                                       LdStPairFlags &Flags,
539                                       unsigned Limit) {
540   MachineBasicBlock::iterator E = I->getParent()->end();
541   MachineBasicBlock::iterator MBBI = I;
542   MachineInstr *FirstMI = I;
543   ++MBBI;
544 
545   unsigned Opc = FirstMI->getOpcode();
546   bool MayLoad = FirstMI->mayLoad();
547   bool IsUnscaled = isUnscaledLdSt(FirstMI);
548   unsigned Reg = getLdStRegOp(FirstMI).getReg();
549   unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
550   int Offset = getLdStOffsetOp(FirstMI).getImm();
551 
552   // Early exit if the first instruction modifies the base register.
553   // e.g., ldr x0, [x0]
554   if (FirstMI->modifiesRegister(BaseReg, TRI))
555     return E;
556 
557   // Early exit if the offset if not possible to match. (6 bits of positive
558   // range, plus allow an extra one in case we find a later insn that matches
559   // with Offset-1)
560   int OffsetStride =
561       IsUnscaled && EnableAArch64UnscaledMemOp ? getMemSize(FirstMI) : 1;
562   if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride))
563     return E;
564 
565   // Track which registers have been modified and used between the first insn
566   // (inclusive) and the second insn.
567   BitVector ModifiedRegs, UsedRegs;
568   ModifiedRegs.resize(TRI->getNumRegs());
569   UsedRegs.resize(TRI->getNumRegs());
570 
571   // Remember any instructions that read/write memory between FirstMI and MI.
572   SmallVector<MachineInstr *, 4> MemInsns;
573 
574   for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
575     MachineInstr *MI = MBBI;
576     // Skip DBG_VALUE instructions. Otherwise debug info can affect the
577     // optimization by changing how far we scan.
578     if (MI->isDebugValue())
579       continue;
580 
581     // Now that we know this is a real instruction, count it.
582     ++Count;
583 
584     bool CanMergeOpc = Opc == MI->getOpcode();
585     Flags.setSExtIdx(-1);
586     if (!CanMergeOpc) {
587       bool IsValidLdStrOpc;
588       unsigned NonSExtOpc = getMatchingNonSExtOpcode(Opc, &IsValidLdStrOpc);
589       assert(IsValidLdStrOpc &&
590              "Given Opc should be a Load or Store with an immediate");
591       // Opc will be the first instruction in the pair.
592       Flags.setSExtIdx(NonSExtOpc == (unsigned)Opc ? 1 : 0);
593       CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode(MI->getOpcode());
594     }
595 
596     if (CanMergeOpc && getLdStOffsetOp(MI).isImm()) {
597       assert(MI->mayLoadOrStore() && "Expected memory operation.");
598       // If we've found another instruction with the same opcode, check to see
599       // if the base and offset are compatible with our starting instruction.
600       // These instructions all have scaled immediate operands, so we just
601       // check for +1/-1. Make sure to check the new instruction offset is
602       // actually an immediate and not a symbolic reference destined for
603       // a relocation.
604       //
605       // Pairwise instructions have a 7-bit signed offset field. Single insns
606       // have a 12-bit unsigned offset field. To be a valid combine, the
607       // final offset must be in range.
608       unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
609       int MIOffset = getLdStOffsetOp(MI).getImm();
610       if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
611                                    (Offset + OffsetStride == MIOffset))) {
612         int MinOffset = Offset < MIOffset ? Offset : MIOffset;
613         // If this is a volatile load/store that otherwise matched, stop looking
614         // as something is going on that we don't have enough information to
615         // safely transform. Similarly, stop if we see a hint to avoid pairs.
616         if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
617           return E;
618         // If the resultant immediate offset of merging these instructions
619         // is out of range for a pairwise instruction, bail and keep looking.
620         bool MIIsUnscaled = isUnscaledLdSt(MI);
621         if (!inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
622           trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
623           MemInsns.push_back(MI);
624           continue;
625         }
626         // If the alignment requirements of the paired (scaled) instruction
627         // can't express the offset of the unscaled input, bail and keep
628         // looking.
629         if (IsUnscaled && EnableAArch64UnscaledMemOp &&
630             (alignTo(MinOffset, OffsetStride) != MinOffset)) {
631           trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
632           MemInsns.push_back(MI);
633           continue;
634         }
635         // If the destination register of the loads is the same register, bail
636         // and keep looking. A load-pair instruction with both destination
637         // registers the same is UNPREDICTABLE and will result in an exception.
638         if (MayLoad && Reg == getLdStRegOp(MI).getReg()) {
639           trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
640           MemInsns.push_back(MI);
641           continue;
642         }
643 
644         // If the Rt of the second instruction was not modified or used between
645         // the two instructions and none of the instructions between the second
646         // and first alias with the second, we can combine the second into the
647         // first.
648         if (!ModifiedRegs[getLdStRegOp(MI).getReg()] &&
649             !(MI->mayLoad() && UsedRegs[getLdStRegOp(MI).getReg()]) &&
650             !mayAlias(MI, MemInsns, TII)) {
651           Flags.setMergeForward(false);
652           return MBBI;
653         }
654 
655         // Likewise, if the Rt of the first instruction is not modified or used
656         // between the two instructions and none of the instructions between the
657         // first and the second alias with the first, we can combine the first
658         // into the second.
659         if (!ModifiedRegs[getLdStRegOp(FirstMI).getReg()] &&
660             !(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) &&
661             !mayAlias(FirstMI, MemInsns, TII)) {
662           Flags.setMergeForward(true);
663           return MBBI;
664         }
665         // Unable to combine these instructions due to interference in between.
666         // Keep looking.
667       }
668     }
669 
670     // If the instruction wasn't a matching load or store.  Stop searching if we
671     // encounter a call instruction that might modify memory.
672     if (MI->isCall())
673       return E;
674 
675     // Update modified / uses register lists.
676     trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
677 
678     // Otherwise, if the base register is modified, we have no match, so
679     // return early.
680     if (ModifiedRegs[BaseReg])
681       return E;
682 
683     // Update list of instructions that read/write memory.
684     if (MI->mayLoadOrStore())
685       MemInsns.push_back(MI);
686   }
687   return E;
688 }
689 
690 MachineBasicBlock::iterator
691 AArch64LoadStoreOpt::mergePreIdxUpdateInsn(MachineBasicBlock::iterator I,
692                                            MachineBasicBlock::iterator Update) {
693   assert((Update->getOpcode() == AArch64::ADDXri ||
694           Update->getOpcode() == AArch64::SUBXri) &&
695          "Unexpected base register update instruction to merge!");
696   MachineBasicBlock::iterator NextI = I;
697   // Return the instruction following the merged instruction, which is
698   // the instruction following our unmerged load. Unless that's the add/sub
699   // instruction we're merging, in which case it's the one after that.
700   if (++NextI == Update)
701     ++NextI;
702 
703   int Value = Update->getOperand(2).getImm();
704   assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
705          "Can't merge 1 << 12 offset into pre-indexed load / store");
706   if (Update->getOpcode() == AArch64::SUBXri)
707     Value = -Value;
708 
709   unsigned NewOpc = getPreIndexedOpcode(I->getOpcode());
710   MachineInstrBuilder MIB =
711       BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
712           .addOperand(getLdStRegOp(Update))
713           .addOperand(getLdStRegOp(I))
714           .addOperand(getLdStBaseOp(I))
715           .addImm(Value);
716   (void)MIB;
717 
718   DEBUG(dbgs() << "Creating pre-indexed load/store.");
719   DEBUG(dbgs() << "    Replacing instructions:\n    ");
720   DEBUG(I->print(dbgs()));
721   DEBUG(dbgs() << "    ");
722   DEBUG(Update->print(dbgs()));
723   DEBUG(dbgs() << "  with instruction:\n    ");
724   DEBUG(((MachineInstr *)MIB)->print(dbgs()));
725   DEBUG(dbgs() << "\n");
726 
727   // Erase the old instructions for the block.
728   I->eraseFromParent();
729   Update->eraseFromParent();
730 
731   return NextI;
732 }
733 
734 MachineBasicBlock::iterator AArch64LoadStoreOpt::mergePostIdxUpdateInsn(
735     MachineBasicBlock::iterator I, MachineBasicBlock::iterator Update) {
736   assert((Update->getOpcode() == AArch64::ADDXri ||
737           Update->getOpcode() == AArch64::SUBXri) &&
738          "Unexpected base register update instruction to merge!");
739   MachineBasicBlock::iterator NextI = I;
740   // Return the instruction following the merged instruction, which is
741   // the instruction following our unmerged load. Unless that's the add/sub
742   // instruction we're merging, in which case it's the one after that.
743   if (++NextI == Update)
744     ++NextI;
745 
746   int Value = Update->getOperand(2).getImm();
747   assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
748          "Can't merge 1 << 12 offset into post-indexed load / store");
749   if (Update->getOpcode() == AArch64::SUBXri)
750     Value = -Value;
751 
752   unsigned NewOpc = getPostIndexedOpcode(I->getOpcode());
753   MachineInstrBuilder MIB =
754       BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
755           .addOperand(getLdStRegOp(Update))
756           .addOperand(getLdStRegOp(I))
757           .addOperand(getLdStBaseOp(I))
758           .addImm(Value);
759   (void)MIB;
760 
761   DEBUG(dbgs() << "Creating post-indexed load/store.");
762   DEBUG(dbgs() << "    Replacing instructions:\n    ");
763   DEBUG(I->print(dbgs()));
764   DEBUG(dbgs() << "    ");
765   DEBUG(Update->print(dbgs()));
766   DEBUG(dbgs() << "  with instruction:\n    ");
767   DEBUG(((MachineInstr *)MIB)->print(dbgs()));
768   DEBUG(dbgs() << "\n");
769 
770   // Erase the old instructions for the block.
771   I->eraseFromParent();
772   Update->eraseFromParent();
773 
774   return NextI;
775 }
776 
777 static bool isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg,
778                                  int Offset) {
779   switch (MI->getOpcode()) {
780   default:
781     break;
782   case AArch64::SUBXri:
783     // Negate the offset for a SUB instruction.
784     Offset *= -1;
785   // FALLTHROUGH
786   case AArch64::ADDXri:
787     // Make sure it's a vanilla immediate operand, not a relocation or
788     // anything else we can't handle.
789     if (!MI->getOperand(2).isImm())
790       break;
791     // Watch out for 1 << 12 shifted value.
792     if (AArch64_AM::getShiftValue(MI->getOperand(3).getImm()))
793       break;
794     // If the instruction has the base register as source and dest and the
795     // immediate will fit in a signed 9-bit integer, then we have a match.
796     if (getLdStRegOp(MI).getReg() == BaseReg &&
797         getLdStBaseOp(MI).getReg() == BaseReg &&
798         getLdStOffsetOp(MI).getImm() <= 255 &&
799         getLdStOffsetOp(MI).getImm() >= -256) {
800       // If we have a non-zero Offset, we check that it matches the amount
801       // we're adding to the register.
802       if (!Offset || Offset == MI->getOperand(2).getImm())
803         return true;
804     }
805     break;
806   }
807   return false;
808 }
809 
810 MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
811     MachineBasicBlock::iterator I, unsigned Limit, int Value) {
812   MachineBasicBlock::iterator E = I->getParent()->end();
813   MachineInstr *MemMI = I;
814   MachineBasicBlock::iterator MBBI = I;
815   const MachineFunction &MF = *MemMI->getParent()->getParent();
816 
817   unsigned DestReg = getLdStRegOp(MemMI).getReg();
818   unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
819   int Offset = getLdStOffsetOp(MemMI).getImm() *
820                TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
821 
822   // If the base register overlaps the destination register, we can't
823   // merge the update.
824   if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
825     return E;
826 
827   // Scan forward looking for post-index opportunities.
828   // Updating instructions can't be formed if the memory insn already
829   // has an offset other than the value we're looking for.
830   if (Offset != Value)
831     return E;
832 
833   // Track which registers have been modified and used between the first insn
834   // (inclusive) and the second insn.
835   BitVector ModifiedRegs, UsedRegs;
836   ModifiedRegs.resize(TRI->getNumRegs());
837   UsedRegs.resize(TRI->getNumRegs());
838   ++MBBI;
839   for (unsigned Count = 0; MBBI != E; ++MBBI) {
840     MachineInstr *MI = MBBI;
841     // Skip DBG_VALUE instructions. Otherwise debug info can affect the
842     // optimization by changing how far we scan.
843     if (MI->isDebugValue())
844       continue;
845 
846     // Now that we know this is a real instruction, count it.
847     ++Count;
848 
849     // If we found a match, return it.
850     if (isMatchingUpdateInsn(MI, BaseReg, Value))
851       return MBBI;
852 
853     // Update the status of what the instruction clobbered and used.
854     trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
855 
856     // Otherwise, if the base register is used or modified, we have no match, so
857     // return early.
858     if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
859       return E;
860   }
861   return E;
862 }
863 
864 MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
865     MachineBasicBlock::iterator I, unsigned Limit) {
866   MachineBasicBlock::iterator B = I->getParent()->begin();
867   MachineBasicBlock::iterator E = I->getParent()->end();
868   MachineInstr *MemMI = I;
869   MachineBasicBlock::iterator MBBI = I;
870   const MachineFunction &MF = *MemMI->getParent()->getParent();
871 
872   unsigned DestReg = getLdStRegOp(MemMI).getReg();
873   unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
874   int Offset = getLdStOffsetOp(MemMI).getImm();
875   unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
876 
877   // If the load/store is the first instruction in the block, there's obviously
878   // not any matching update. Ditto if the memory offset isn't zero.
879   if (MBBI == B || Offset != 0)
880     return E;
881   // If the base register overlaps the destination register, we can't
882   // merge the update.
883   if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
884     return E;
885 
886   // Track which registers have been modified and used between the first insn
887   // (inclusive) and the second insn.
888   BitVector ModifiedRegs, UsedRegs;
889   ModifiedRegs.resize(TRI->getNumRegs());
890   UsedRegs.resize(TRI->getNumRegs());
891   --MBBI;
892   for (unsigned Count = 0; MBBI != B; --MBBI) {
893     MachineInstr *MI = MBBI;
894     // Skip DBG_VALUE instructions. Otherwise debug info can affect the
895     // optimization by changing how far we scan.
896     if (MI->isDebugValue())
897       continue;
898 
899     // Now that we know this is a real instruction, count it.
900     ++Count;
901 
902     // If we found a match, return it.
903     if (isMatchingUpdateInsn(MI, BaseReg, RegSize))
904       return MBBI;
905 
906     // Update the status of what the instruction clobbered and used.
907     trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
908 
909     // Otherwise, if the base register is used or modified, we have no match, so
910     // return early.
911     if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
912       return E;
913   }
914   return E;
915 }
916 
917 bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB) {
918   bool Modified = false;
919   // Two tranformations to do here:
920   // 1) Find loads and stores that can be merged into a single load or store
921   //    pair instruction.
922   //      e.g.,
923   //        ldr x0, [x2]
924   //        ldr x1, [x2, #8]
925   //        ; becomes
926   //        ldp x0, x1, [x2]
927   // 2) Find base register updates that can be merged into the load or store
928   //    as a base-reg writeback.
929   //      e.g.,
930   //        ldr x0, [x2]
931   //        add x2, x2, #4
932   //        ; becomes
933   //        ldr x0, [x2], #4
934 
935   for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
936        MBBI != E;) {
937     MachineInstr *MI = MBBI;
938     switch (MI->getOpcode()) {
939     default:
940       // Just move on to the next instruction.
941       ++MBBI;
942       break;
943     case AArch64::STRSui:
944     case AArch64::STRDui:
945     case AArch64::STRQui:
946     case AArch64::STRXui:
947     case AArch64::STRWui:
948     case AArch64::LDRSui:
949     case AArch64::LDRDui:
950     case AArch64::LDRQui:
951     case AArch64::LDRXui:
952     case AArch64::LDRWui:
953     case AArch64::LDRSWui:
954     // do the unscaled versions as well
955     case AArch64::STURSi:
956     case AArch64::STURDi:
957     case AArch64::STURQi:
958     case AArch64::STURWi:
959     case AArch64::STURXi:
960     case AArch64::LDURSi:
961     case AArch64::LDURDi:
962     case AArch64::LDURQi:
963     case AArch64::LDURWi:
964     case AArch64::LDURXi:
965     case AArch64::LDURSWi: {
966       // If this is a volatile load/store, don't mess with it.
967       if (MI->hasOrderedMemoryRef()) {
968         ++MBBI;
969         break;
970       }
971       // Make sure this is a reg+imm (as opposed to an address reloc).
972       if (!getLdStOffsetOp(MI).isImm()) {
973         ++MBBI;
974         break;
975       }
976       // Check if this load/store has a hint to avoid pair formation.
977       // MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
978       if (TII->isLdStPairSuppressed(MI)) {
979         ++MBBI;
980         break;
981       }
982       // Look ahead up to ScanLimit instructions for a pairable instruction.
983       LdStPairFlags Flags;
984       MachineBasicBlock::iterator Paired =
985           findMatchingInsn(MBBI, Flags, ScanLimit);
986       if (Paired != E) {
987         ++NumPairCreated;
988         if (isUnscaledLdSt(MI))
989           ++NumUnscaledPairCreated;
990 
991         // Merge the loads into a pair. Keeping the iterator straight is a
992         // pain, so we let the merge routine tell us what the next instruction
993         // is after it's done mucking about.
994         MBBI = mergePairedInsns(MBBI, Paired, Flags);
995         Modified = true;
996         break;
997       }
998       ++MBBI;
999       break;
1000     }
1001       // FIXME: Do the other instructions.
1002     }
1003   }
1004 
1005   for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1006        MBBI != E;) {
1007     MachineInstr *MI = MBBI;
1008     // Do update merging. It's simpler to keep this separate from the above
1009     // switch, though not strictly necessary.
1010     unsigned Opc = MI->getOpcode();
1011     switch (Opc) {
1012     default:
1013       // Just move on to the next instruction.
1014       ++MBBI;
1015       break;
1016     case AArch64::STRSui:
1017     case AArch64::STRDui:
1018     case AArch64::STRQui:
1019     case AArch64::STRXui:
1020     case AArch64::STRWui:
1021     case AArch64::LDRSui:
1022     case AArch64::LDRDui:
1023     case AArch64::LDRQui:
1024     case AArch64::LDRXui:
1025     case AArch64::LDRWui:
1026     // do the unscaled versions as well
1027     case AArch64::STURSi:
1028     case AArch64::STURDi:
1029     case AArch64::STURQi:
1030     case AArch64::STURWi:
1031     case AArch64::STURXi:
1032     case AArch64::LDURSi:
1033     case AArch64::LDURDi:
1034     case AArch64::LDURQi:
1035     case AArch64::LDURWi:
1036     case AArch64::LDURXi: {
1037       // Make sure this is a reg+imm (as opposed to an address reloc).
1038       if (!getLdStOffsetOp(MI).isImm()) {
1039         ++MBBI;
1040         break;
1041       }
1042       // Look ahead up to ScanLimit instructions for a mergable instruction.
1043       MachineBasicBlock::iterator Update =
1044           findMatchingUpdateInsnForward(MBBI, ScanLimit, 0);
1045       if (Update != E) {
1046         // Merge the update into the ld/st.
1047         MBBI = mergePostIdxUpdateInsn(MBBI, Update);
1048         Modified = true;
1049         ++NumPostFolded;
1050         break;
1051       }
1052       // Don't know how to handle pre/post-index versions, so move to the next
1053       // instruction.
1054       if (isUnscaledLdSt(Opc)) {
1055         ++MBBI;
1056         break;
1057       }
1058 
1059       // Look back to try to find a pre-index instruction. For example,
1060       // add x0, x0, #8
1061       // ldr x1, [x0]
1062       //   merged into:
1063       // ldr x1, [x0, #8]!
1064       Update = findMatchingUpdateInsnBackward(MBBI, ScanLimit);
1065       if (Update != E) {
1066         // Merge the update into the ld/st.
1067         MBBI = mergePreIdxUpdateInsn(MBBI, Update);
1068         Modified = true;
1069         ++NumPreFolded;
1070         break;
1071       }
1072 
1073       // Look forward to try to find a post-index instruction. For example,
1074       // ldr x1, [x0, #64]
1075       // add x0, x0, #64
1076       //   merged into:
1077       // ldr x1, [x0, #64]!
1078 
1079       // The immediate in the load/store is scaled by the size of the register
1080       // being loaded. The immediate in the add we're looking for,
1081       // however, is not, so adjust here.
1082       int Value = MI->getOperand(2).getImm() *
1083                   TII->getRegClass(MI->getDesc(), 0, TRI, *(MBB.getParent()))
1084                       ->getSize();
1085       Update = findMatchingUpdateInsnForward(MBBI, ScanLimit, Value);
1086       if (Update != E) {
1087         // Merge the update into the ld/st.
1088         MBBI = mergePreIdxUpdateInsn(MBBI, Update);
1089         Modified = true;
1090         ++NumPreFolded;
1091         break;
1092       }
1093 
1094       // Nothing found. Just move to the next instruction.
1095       ++MBBI;
1096       break;
1097     }
1098       // FIXME: Do the other instructions.
1099     }
1100   }
1101 
1102   return Modified;
1103 }
1104 
1105 bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
1106   TII = static_cast<const AArch64InstrInfo *>(Fn.getSubtarget().getInstrInfo());
1107   TRI = Fn.getSubtarget().getRegisterInfo();
1108 
1109   bool Modified = false;
1110   for (auto &MBB : Fn)
1111     Modified |= optimizeBlock(MBB);
1112 
1113   return Modified;
1114 }
1115 
1116 // FIXME: Do we need/want a pre-alloc pass like ARM has to try to keep
1117 // loads and stores near one another?
1118 
1119 /// createAArch64LoadStoreOptimizationPass - returns an instance of the
1120 /// load / store optimization pass.
1121 FunctionPass *llvm::createAArch64LoadStoreOptimizationPass() {
1122   return new AArch64LoadStoreOpt();
1123 }
1124