1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64InstrInfo.h"
14 #include "AArch64MachineFunctionInfo.h"
15 #include "AArch64Subtarget.h"
16 #include "MCTargetDesc/AArch64AddressingModes.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/CodeGen/TargetRegisterInfo.h"
32 #include "llvm/CodeGen/TargetSubtargetInfo.h"
33 #include "llvm/IR/DebugInfoMetadata.h"
34 #include "llvm/IR/DebugLoc.h"
35 #include "llvm/IR/GlobalValue.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCInstrDesc.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include <cassert>
48 #include <cstdint>
49 #include <iterator>
50 #include <utility>
51 
52 using namespace llvm;
53 
54 #define GET_INSTRINFO_CTOR_DTOR
55 #include "AArch64GenInstrInfo.inc"
56 
57 static cl::opt<unsigned> TBZDisplacementBits(
58     "aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
59     cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"));
60 
61 static cl::opt<unsigned> CBZDisplacementBits(
62     "aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
63     cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"));
64 
65 static cl::opt<unsigned>
66     BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
67                         cl::desc("Restrict range of Bcc instructions (DEBUG)"));
68 
69 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
70     : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP,
71                           AArch64::CATCHRET),
72       RI(STI.getTargetTriple()), Subtarget(STI) {}
73 
74 /// GetInstSize - Return the number of bytes of code the specified
75 /// instruction may be.  This returns the maximum number of bytes.
76 unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
77   const MachineBasicBlock &MBB = *MI.getParent();
78   const MachineFunction *MF = MBB.getParent();
79   const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
80 
81   {
82     auto Op = MI.getOpcode();
83     if (Op == AArch64::INLINEASM || Op == AArch64::INLINEASM_BR)
84       return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
85   }
86 
87   // Meta-instructions emit no code.
88   if (MI.isMetaInstruction())
89     return 0;
90 
91   // FIXME: We currently only handle pseudoinstructions that don't get expanded
92   //        before the assembly printer.
93   unsigned NumBytes = 0;
94   const MCInstrDesc &Desc = MI.getDesc();
95   switch (Desc.getOpcode()) {
96   default:
97     // Anything not explicitly designated otherwise is a normal 4-byte insn.
98     NumBytes = 4;
99     break;
100   case TargetOpcode::STACKMAP:
101     // The upper bound for a stackmap intrinsic is the full length of its shadow
102     NumBytes = StackMapOpers(&MI).getNumPatchBytes();
103     assert(NumBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
104     break;
105   case TargetOpcode::PATCHPOINT:
106     // The size of the patchpoint intrinsic is the number of bytes requested
107     NumBytes = PatchPointOpers(&MI).getNumPatchBytes();
108     assert(NumBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
109     break;
110   case AArch64::TLSDESC_CALLSEQ:
111     // This gets lowered to an instruction sequence which takes 16 bytes
112     NumBytes = 16;
113     break;
114   case AArch64::JumpTableDest32:
115   case AArch64::JumpTableDest16:
116   case AArch64::JumpTableDest8:
117     NumBytes = 12;
118     break;
119   case AArch64::SPACE:
120     NumBytes = MI.getOperand(1).getImm();
121     break;
122   case TargetOpcode::BUNDLE:
123     NumBytes = getInstBundleLength(MI);
124     break;
125   }
126 
127   return NumBytes;
128 }
129 
130 unsigned AArch64InstrInfo::getInstBundleLength(const MachineInstr &MI) const {
131   unsigned Size = 0;
132   MachineBasicBlock::const_instr_iterator I = MI.getIterator();
133   MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
134   while (++I != E && I->isInsideBundle()) {
135     assert(!I->isBundle() && "No nested bundle!");
136     Size += getInstSizeInBytes(*I);
137   }
138   return Size;
139 }
140 
141 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
142                             SmallVectorImpl<MachineOperand> &Cond) {
143   // Block ends with fall-through condbranch.
144   switch (LastInst->getOpcode()) {
145   default:
146     llvm_unreachable("Unknown branch instruction?");
147   case AArch64::Bcc:
148     Target = LastInst->getOperand(1).getMBB();
149     Cond.push_back(LastInst->getOperand(0));
150     break;
151   case AArch64::CBZW:
152   case AArch64::CBZX:
153   case AArch64::CBNZW:
154   case AArch64::CBNZX:
155     Target = LastInst->getOperand(1).getMBB();
156     Cond.push_back(MachineOperand::CreateImm(-1));
157     Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
158     Cond.push_back(LastInst->getOperand(0));
159     break;
160   case AArch64::TBZW:
161   case AArch64::TBZX:
162   case AArch64::TBNZW:
163   case AArch64::TBNZX:
164     Target = LastInst->getOperand(2).getMBB();
165     Cond.push_back(MachineOperand::CreateImm(-1));
166     Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
167     Cond.push_back(LastInst->getOperand(0));
168     Cond.push_back(LastInst->getOperand(1));
169   }
170 }
171 
172 static unsigned getBranchDisplacementBits(unsigned Opc) {
173   switch (Opc) {
174   default:
175     llvm_unreachable("unexpected opcode!");
176   case AArch64::B:
177     return 64;
178   case AArch64::TBNZW:
179   case AArch64::TBZW:
180   case AArch64::TBNZX:
181   case AArch64::TBZX:
182     return TBZDisplacementBits;
183   case AArch64::CBNZW:
184   case AArch64::CBZW:
185   case AArch64::CBNZX:
186   case AArch64::CBZX:
187     return CBZDisplacementBits;
188   case AArch64::Bcc:
189     return BCCDisplacementBits;
190   }
191 }
192 
193 bool AArch64InstrInfo::isBranchOffsetInRange(unsigned BranchOp,
194                                              int64_t BrOffset) const {
195   unsigned Bits = getBranchDisplacementBits(BranchOp);
196   assert(Bits >= 3 && "max branch displacement must be enough to jump"
197                       "over conditional branch expansion");
198   return isIntN(Bits, BrOffset / 4);
199 }
200 
201 MachineBasicBlock *
202 AArch64InstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
203   switch (MI.getOpcode()) {
204   default:
205     llvm_unreachable("unexpected opcode!");
206   case AArch64::B:
207     return MI.getOperand(0).getMBB();
208   case AArch64::TBZW:
209   case AArch64::TBNZW:
210   case AArch64::TBZX:
211   case AArch64::TBNZX:
212     return MI.getOperand(2).getMBB();
213   case AArch64::CBZW:
214   case AArch64::CBNZW:
215   case AArch64::CBZX:
216   case AArch64::CBNZX:
217   case AArch64::Bcc:
218     return MI.getOperand(1).getMBB();
219   }
220 }
221 
222 // Branch analysis.
223 bool AArch64InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
224                                      MachineBasicBlock *&TBB,
225                                      MachineBasicBlock *&FBB,
226                                      SmallVectorImpl<MachineOperand> &Cond,
227                                      bool AllowModify) const {
228   // If the block has no terminators, it just falls into the block after it.
229   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
230   if (I == MBB.end())
231     return false;
232 
233   if (!isUnpredicatedTerminator(*I))
234     return false;
235 
236   // Get the last instruction in the block.
237   MachineInstr *LastInst = &*I;
238 
239   // If there is only one terminator instruction, process it.
240   unsigned LastOpc = LastInst->getOpcode();
241   if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
242     if (isUncondBranchOpcode(LastOpc)) {
243       TBB = LastInst->getOperand(0).getMBB();
244       return false;
245     }
246     if (isCondBranchOpcode(LastOpc)) {
247       // Block ends with fall-through condbranch.
248       parseCondBranch(LastInst, TBB, Cond);
249       return false;
250     }
251     return true; // Can't handle indirect branch.
252   }
253 
254   // Get the instruction before it if it is a terminator.
255   MachineInstr *SecondLastInst = &*I;
256   unsigned SecondLastOpc = SecondLastInst->getOpcode();
257 
258   // If AllowModify is true and the block ends with two or more unconditional
259   // branches, delete all but the first unconditional branch.
260   if (AllowModify && isUncondBranchOpcode(LastOpc)) {
261     while (isUncondBranchOpcode(SecondLastOpc)) {
262       LastInst->eraseFromParent();
263       LastInst = SecondLastInst;
264       LastOpc = LastInst->getOpcode();
265       if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
266         // Return now the only terminator is an unconditional branch.
267         TBB = LastInst->getOperand(0).getMBB();
268         return false;
269       } else {
270         SecondLastInst = &*I;
271         SecondLastOpc = SecondLastInst->getOpcode();
272       }
273     }
274   }
275 
276   // If there are three terminators, we don't know what sort of block this is.
277   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
278     return true;
279 
280   // If the block ends with a B and a Bcc, handle it.
281   if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
282     parseCondBranch(SecondLastInst, TBB, Cond);
283     FBB = LastInst->getOperand(0).getMBB();
284     return false;
285   }
286 
287   // If the block ends with two unconditional branches, handle it.  The second
288   // one is not executed, so remove it.
289   if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
290     TBB = SecondLastInst->getOperand(0).getMBB();
291     I = LastInst;
292     if (AllowModify)
293       I->eraseFromParent();
294     return false;
295   }
296 
297   // ...likewise if it ends with an indirect branch followed by an unconditional
298   // branch.
299   if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
300     I = LastInst;
301     if (AllowModify)
302       I->eraseFromParent();
303     return true;
304   }
305 
306   // Otherwise, can't handle this.
307   return true;
308 }
309 
310 bool AArch64InstrInfo::reverseBranchCondition(
311     SmallVectorImpl<MachineOperand> &Cond) const {
312   if (Cond[0].getImm() != -1) {
313     // Regular Bcc
314     AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
315     Cond[0].setImm(AArch64CC::getInvertedCondCode(CC));
316   } else {
317     // Folded compare-and-branch
318     switch (Cond[1].getImm()) {
319     default:
320       llvm_unreachable("Unknown conditional branch!");
321     case AArch64::CBZW:
322       Cond[1].setImm(AArch64::CBNZW);
323       break;
324     case AArch64::CBNZW:
325       Cond[1].setImm(AArch64::CBZW);
326       break;
327     case AArch64::CBZX:
328       Cond[1].setImm(AArch64::CBNZX);
329       break;
330     case AArch64::CBNZX:
331       Cond[1].setImm(AArch64::CBZX);
332       break;
333     case AArch64::TBZW:
334       Cond[1].setImm(AArch64::TBNZW);
335       break;
336     case AArch64::TBNZW:
337       Cond[1].setImm(AArch64::TBZW);
338       break;
339     case AArch64::TBZX:
340       Cond[1].setImm(AArch64::TBNZX);
341       break;
342     case AArch64::TBNZX:
343       Cond[1].setImm(AArch64::TBZX);
344       break;
345     }
346   }
347 
348   return false;
349 }
350 
351 unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB,
352                                         int *BytesRemoved) const {
353   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
354   if (I == MBB.end())
355     return 0;
356 
357   if (!isUncondBranchOpcode(I->getOpcode()) &&
358       !isCondBranchOpcode(I->getOpcode()))
359     return 0;
360 
361   // Remove the branch.
362   I->eraseFromParent();
363 
364   I = MBB.end();
365 
366   if (I == MBB.begin()) {
367     if (BytesRemoved)
368       *BytesRemoved = 4;
369     return 1;
370   }
371   --I;
372   if (!isCondBranchOpcode(I->getOpcode())) {
373     if (BytesRemoved)
374       *BytesRemoved = 4;
375     return 1;
376   }
377 
378   // Remove the branch.
379   I->eraseFromParent();
380   if (BytesRemoved)
381     *BytesRemoved = 8;
382 
383   return 2;
384 }
385 
386 void AArch64InstrInfo::instantiateCondBranch(
387     MachineBasicBlock &MBB, const DebugLoc &DL, MachineBasicBlock *TBB,
388     ArrayRef<MachineOperand> Cond) const {
389   if (Cond[0].getImm() != -1) {
390     // Regular Bcc
391     BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
392   } else {
393     // Folded compare-and-branch
394     // Note that we use addOperand instead of addReg to keep the flags.
395     const MachineInstrBuilder MIB =
396         BuildMI(&MBB, DL, get(Cond[1].getImm())).add(Cond[2]);
397     if (Cond.size() > 3)
398       MIB.addImm(Cond[3].getImm());
399     MIB.addMBB(TBB);
400   }
401 }
402 
403 unsigned AArch64InstrInfo::insertBranch(
404     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
405     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
406   // Shouldn't be a fall through.
407   assert(TBB && "insertBranch must not be told to insert a fallthrough");
408 
409   if (!FBB) {
410     if (Cond.empty()) // Unconditional branch?
411       BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
412     else
413       instantiateCondBranch(MBB, DL, TBB, Cond);
414 
415     if (BytesAdded)
416       *BytesAdded = 4;
417 
418     return 1;
419   }
420 
421   // Two-way conditional branch.
422   instantiateCondBranch(MBB, DL, TBB, Cond);
423   BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
424 
425   if (BytesAdded)
426     *BytesAdded = 8;
427 
428   return 2;
429 }
430 
431 // Find the original register that VReg is copied from.
432 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
433   while (Register::isVirtualRegister(VReg)) {
434     const MachineInstr *DefMI = MRI.getVRegDef(VReg);
435     if (!DefMI->isFullCopy())
436       return VReg;
437     VReg = DefMI->getOperand(1).getReg();
438   }
439   return VReg;
440 }
441 
442 // Determine if VReg is defined by an instruction that can be folded into a
443 // csel instruction. If so, return the folded opcode, and the replacement
444 // register.
445 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
446                                 unsigned *NewVReg = nullptr) {
447   VReg = removeCopies(MRI, VReg);
448   if (!Register::isVirtualRegister(VReg))
449     return 0;
450 
451   bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
452   const MachineInstr *DefMI = MRI.getVRegDef(VReg);
453   unsigned Opc = 0;
454   unsigned SrcOpNum = 0;
455   switch (DefMI->getOpcode()) {
456   case AArch64::ADDSXri:
457   case AArch64::ADDSWri:
458     // if NZCV is used, do not fold.
459     if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
460       return 0;
461     // fall-through to ADDXri and ADDWri.
462     LLVM_FALLTHROUGH;
463   case AArch64::ADDXri:
464   case AArch64::ADDWri:
465     // add x, 1 -> csinc.
466     if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
467         DefMI->getOperand(3).getImm() != 0)
468       return 0;
469     SrcOpNum = 1;
470     Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
471     break;
472 
473   case AArch64::ORNXrr:
474   case AArch64::ORNWrr: {
475     // not x -> csinv, represented as orn dst, xzr, src.
476     unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
477     if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
478       return 0;
479     SrcOpNum = 2;
480     Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr;
481     break;
482   }
483 
484   case AArch64::SUBSXrr:
485   case AArch64::SUBSWrr:
486     // if NZCV is used, do not fold.
487     if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
488       return 0;
489     // fall-through to SUBXrr and SUBWrr.
490     LLVM_FALLTHROUGH;
491   case AArch64::SUBXrr:
492   case AArch64::SUBWrr: {
493     // neg x -> csneg, represented as sub dst, xzr, src.
494     unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
495     if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
496       return 0;
497     SrcOpNum = 2;
498     Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr;
499     break;
500   }
501   default:
502     return 0;
503   }
504   assert(Opc && SrcOpNum && "Missing parameters");
505 
506   if (NewVReg)
507     *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
508   return Opc;
509 }
510 
511 bool AArch64InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
512                                        ArrayRef<MachineOperand> Cond,
513                                        Register DstReg, Register TrueReg,
514                                        Register FalseReg, int &CondCycles,
515                                        int &TrueCycles,
516                                        int &FalseCycles) const {
517   // Check register classes.
518   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
519   const TargetRegisterClass *RC =
520       RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
521   if (!RC)
522     return false;
523 
524   // Also need to check the dest regclass, in case we're trying to optimize
525   // something like:
526   // %1(gpr) = PHI %2(fpr), bb1, %(fpr), bb2
527   if (!RI.getCommonSubClass(RC, MRI.getRegClass(DstReg)))
528     return false;
529 
530   // Expanding cbz/tbz requires an extra cycle of latency on the condition.
531   unsigned ExtraCondLat = Cond.size() != 1;
532 
533   // GPRs are handled by csel.
534   // FIXME: Fold in x+1, -x, and ~x when applicable.
535   if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
536       AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
537     // Single-cycle csel, csinc, csinv, and csneg.
538     CondCycles = 1 + ExtraCondLat;
539     TrueCycles = FalseCycles = 1;
540     if (canFoldIntoCSel(MRI, TrueReg))
541       TrueCycles = 0;
542     else if (canFoldIntoCSel(MRI, FalseReg))
543       FalseCycles = 0;
544     return true;
545   }
546 
547   // Scalar floating point is handled by fcsel.
548   // FIXME: Form fabs, fmin, and fmax when applicable.
549   if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
550       AArch64::FPR32RegClass.hasSubClassEq(RC)) {
551     CondCycles = 5 + ExtraCondLat;
552     TrueCycles = FalseCycles = 2;
553     return true;
554   }
555 
556   // Can't do vectors.
557   return false;
558 }
559 
560 void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
561                                     MachineBasicBlock::iterator I,
562                                     const DebugLoc &DL, Register DstReg,
563                                     ArrayRef<MachineOperand> Cond,
564                                     Register TrueReg, Register FalseReg) const {
565   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
566 
567   // Parse the condition code, see parseCondBranch() above.
568   AArch64CC::CondCode CC;
569   switch (Cond.size()) {
570   default:
571     llvm_unreachable("Unknown condition opcode in Cond");
572   case 1: // b.cc
573     CC = AArch64CC::CondCode(Cond[0].getImm());
574     break;
575   case 3: { // cbz/cbnz
576     // We must insert a compare against 0.
577     bool Is64Bit;
578     switch (Cond[1].getImm()) {
579     default:
580       llvm_unreachable("Unknown branch opcode in Cond");
581     case AArch64::CBZW:
582       Is64Bit = false;
583       CC = AArch64CC::EQ;
584       break;
585     case AArch64::CBZX:
586       Is64Bit = true;
587       CC = AArch64CC::EQ;
588       break;
589     case AArch64::CBNZW:
590       Is64Bit = false;
591       CC = AArch64CC::NE;
592       break;
593     case AArch64::CBNZX:
594       Is64Bit = true;
595       CC = AArch64CC::NE;
596       break;
597     }
598     Register SrcReg = Cond[2].getReg();
599     if (Is64Bit) {
600       // cmp reg, #0 is actually subs xzr, reg, #0.
601       MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
602       BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
603           .addReg(SrcReg)
604           .addImm(0)
605           .addImm(0);
606     } else {
607       MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
608       BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
609           .addReg(SrcReg)
610           .addImm(0)
611           .addImm(0);
612     }
613     break;
614   }
615   case 4: { // tbz/tbnz
616     // We must insert a tst instruction.
617     switch (Cond[1].getImm()) {
618     default:
619       llvm_unreachable("Unknown branch opcode in Cond");
620     case AArch64::TBZW:
621     case AArch64::TBZX:
622       CC = AArch64CC::EQ;
623       break;
624     case AArch64::TBNZW:
625     case AArch64::TBNZX:
626       CC = AArch64CC::NE;
627       break;
628     }
629     // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
630     if (Cond[1].getImm() == AArch64::TBZW || Cond[1].getImm() == AArch64::TBNZW)
631       BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
632           .addReg(Cond[2].getReg())
633           .addImm(
634               AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 32));
635     else
636       BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
637           .addReg(Cond[2].getReg())
638           .addImm(
639               AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
640     break;
641   }
642   }
643 
644   unsigned Opc = 0;
645   const TargetRegisterClass *RC = nullptr;
646   bool TryFold = false;
647   if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
648     RC = &AArch64::GPR64RegClass;
649     Opc = AArch64::CSELXr;
650     TryFold = true;
651   } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
652     RC = &AArch64::GPR32RegClass;
653     Opc = AArch64::CSELWr;
654     TryFold = true;
655   } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
656     RC = &AArch64::FPR64RegClass;
657     Opc = AArch64::FCSELDrrr;
658   } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
659     RC = &AArch64::FPR32RegClass;
660     Opc = AArch64::FCSELSrrr;
661   }
662   assert(RC && "Unsupported regclass");
663 
664   // Try folding simple instructions into the csel.
665   if (TryFold) {
666     unsigned NewVReg = 0;
667     unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
668     if (FoldedOpc) {
669       // The folded opcodes csinc, csinc and csneg apply the operation to
670       // FalseReg, so we need to invert the condition.
671       CC = AArch64CC::getInvertedCondCode(CC);
672       TrueReg = FalseReg;
673     } else
674       FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
675 
676     // Fold the operation. Leave any dead instructions for DCE to clean up.
677     if (FoldedOpc) {
678       FalseReg = NewVReg;
679       Opc = FoldedOpc;
680       // The extends the live range of NewVReg.
681       MRI.clearKillFlags(NewVReg);
682     }
683   }
684 
685   // Pull all virtual register into the appropriate class.
686   MRI.constrainRegClass(TrueReg, RC);
687   MRI.constrainRegClass(FalseReg, RC);
688 
689   // Insert the csel.
690   BuildMI(MBB, I, DL, get(Opc), DstReg)
691       .addReg(TrueReg)
692       .addReg(FalseReg)
693       .addImm(CC);
694 }
695 
696 /// Returns true if a MOVi32imm or MOVi64imm can be expanded to an  ORRxx.
697 static bool canBeExpandedToORR(const MachineInstr &MI, unsigned BitSize) {
698   uint64_t Imm = MI.getOperand(1).getImm();
699   uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
700   uint64_t Encoding;
701   return AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding);
702 }
703 
704 // FIXME: this implementation should be micro-architecture dependent, so a
705 // micro-architecture target hook should be introduced here in future.
706 bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
707   if (!Subtarget.hasCustomCheapAsMoveHandling())
708     return MI.isAsCheapAsAMove();
709 
710   const unsigned Opcode = MI.getOpcode();
711 
712   // Firstly, check cases gated by features.
713 
714   if (Subtarget.hasZeroCycleZeroingFP()) {
715     if (Opcode == AArch64::FMOVH0 ||
716         Opcode == AArch64::FMOVS0 ||
717         Opcode == AArch64::FMOVD0)
718       return true;
719   }
720 
721   if (Subtarget.hasZeroCycleZeroingGP()) {
722     if (Opcode == TargetOpcode::COPY &&
723         (MI.getOperand(1).getReg() == AArch64::WZR ||
724          MI.getOperand(1).getReg() == AArch64::XZR))
725       return true;
726   }
727 
728   // Secondly, check cases specific to sub-targets.
729 
730   if (Subtarget.hasExynosCheapAsMoveHandling()) {
731     if (isExynosCheapAsMove(MI))
732       return true;
733 
734     return MI.isAsCheapAsAMove();
735   }
736 
737   // Finally, check generic cases.
738 
739   switch (Opcode) {
740   default:
741     return false;
742 
743   // add/sub on register without shift
744   case AArch64::ADDWri:
745   case AArch64::ADDXri:
746   case AArch64::SUBWri:
747   case AArch64::SUBXri:
748     return (MI.getOperand(3).getImm() == 0);
749 
750   // logical ops on immediate
751   case AArch64::ANDWri:
752   case AArch64::ANDXri:
753   case AArch64::EORWri:
754   case AArch64::EORXri:
755   case AArch64::ORRWri:
756   case AArch64::ORRXri:
757     return true;
758 
759   // logical ops on register without shift
760   case AArch64::ANDWrr:
761   case AArch64::ANDXrr:
762   case AArch64::BICWrr:
763   case AArch64::BICXrr:
764   case AArch64::EONWrr:
765   case AArch64::EONXrr:
766   case AArch64::EORWrr:
767   case AArch64::EORXrr:
768   case AArch64::ORNWrr:
769   case AArch64::ORNXrr:
770   case AArch64::ORRWrr:
771   case AArch64::ORRXrr:
772     return true;
773 
774   // If MOVi32imm or MOVi64imm can be expanded into ORRWri or
775   // ORRXri, it is as cheap as MOV
776   case AArch64::MOVi32imm:
777     return canBeExpandedToORR(MI, 32);
778   case AArch64::MOVi64imm:
779     return canBeExpandedToORR(MI, 64);
780   }
781 
782   llvm_unreachable("Unknown opcode to check as cheap as a move!");
783 }
784 
785 bool AArch64InstrInfo::isFalkorShiftExtFast(const MachineInstr &MI) {
786   switch (MI.getOpcode()) {
787   default:
788     return false;
789 
790   case AArch64::ADDWrs:
791   case AArch64::ADDXrs:
792   case AArch64::ADDSWrs:
793   case AArch64::ADDSXrs: {
794     unsigned Imm = MI.getOperand(3).getImm();
795     unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
796     if (ShiftVal == 0)
797       return true;
798     return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5;
799   }
800 
801   case AArch64::ADDWrx:
802   case AArch64::ADDXrx:
803   case AArch64::ADDXrx64:
804   case AArch64::ADDSWrx:
805   case AArch64::ADDSXrx:
806   case AArch64::ADDSXrx64: {
807     unsigned Imm = MI.getOperand(3).getImm();
808     switch (AArch64_AM::getArithExtendType(Imm)) {
809     default:
810       return false;
811     case AArch64_AM::UXTB:
812     case AArch64_AM::UXTH:
813     case AArch64_AM::UXTW:
814     case AArch64_AM::UXTX:
815       return AArch64_AM::getArithShiftValue(Imm) <= 4;
816     }
817   }
818 
819   case AArch64::SUBWrs:
820   case AArch64::SUBSWrs: {
821     unsigned Imm = MI.getOperand(3).getImm();
822     unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
823     return ShiftVal == 0 ||
824            (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31);
825   }
826 
827   case AArch64::SUBXrs:
828   case AArch64::SUBSXrs: {
829     unsigned Imm = MI.getOperand(3).getImm();
830     unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
831     return ShiftVal == 0 ||
832            (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63);
833   }
834 
835   case AArch64::SUBWrx:
836   case AArch64::SUBXrx:
837   case AArch64::SUBXrx64:
838   case AArch64::SUBSWrx:
839   case AArch64::SUBSXrx:
840   case AArch64::SUBSXrx64: {
841     unsigned Imm = MI.getOperand(3).getImm();
842     switch (AArch64_AM::getArithExtendType(Imm)) {
843     default:
844       return false;
845     case AArch64_AM::UXTB:
846     case AArch64_AM::UXTH:
847     case AArch64_AM::UXTW:
848     case AArch64_AM::UXTX:
849       return AArch64_AM::getArithShiftValue(Imm) == 0;
850     }
851   }
852 
853   case AArch64::LDRBBroW:
854   case AArch64::LDRBBroX:
855   case AArch64::LDRBroW:
856   case AArch64::LDRBroX:
857   case AArch64::LDRDroW:
858   case AArch64::LDRDroX:
859   case AArch64::LDRHHroW:
860   case AArch64::LDRHHroX:
861   case AArch64::LDRHroW:
862   case AArch64::LDRHroX:
863   case AArch64::LDRQroW:
864   case AArch64::LDRQroX:
865   case AArch64::LDRSBWroW:
866   case AArch64::LDRSBWroX:
867   case AArch64::LDRSBXroW:
868   case AArch64::LDRSBXroX:
869   case AArch64::LDRSHWroW:
870   case AArch64::LDRSHWroX:
871   case AArch64::LDRSHXroW:
872   case AArch64::LDRSHXroX:
873   case AArch64::LDRSWroW:
874   case AArch64::LDRSWroX:
875   case AArch64::LDRSroW:
876   case AArch64::LDRSroX:
877   case AArch64::LDRWroW:
878   case AArch64::LDRWroX:
879   case AArch64::LDRXroW:
880   case AArch64::LDRXroX:
881   case AArch64::PRFMroW:
882   case AArch64::PRFMroX:
883   case AArch64::STRBBroW:
884   case AArch64::STRBBroX:
885   case AArch64::STRBroW:
886   case AArch64::STRBroX:
887   case AArch64::STRDroW:
888   case AArch64::STRDroX:
889   case AArch64::STRHHroW:
890   case AArch64::STRHHroX:
891   case AArch64::STRHroW:
892   case AArch64::STRHroX:
893   case AArch64::STRQroW:
894   case AArch64::STRQroX:
895   case AArch64::STRSroW:
896   case AArch64::STRSroX:
897   case AArch64::STRWroW:
898   case AArch64::STRWroX:
899   case AArch64::STRXroW:
900   case AArch64::STRXroX: {
901     unsigned IsSigned = MI.getOperand(3).getImm();
902     return !IsSigned;
903   }
904   }
905 }
906 
907 bool AArch64InstrInfo::isSEHInstruction(const MachineInstr &MI) {
908   unsigned Opc = MI.getOpcode();
909   switch (Opc) {
910     default:
911       return false;
912     case AArch64::SEH_StackAlloc:
913     case AArch64::SEH_SaveFPLR:
914     case AArch64::SEH_SaveFPLR_X:
915     case AArch64::SEH_SaveReg:
916     case AArch64::SEH_SaveReg_X:
917     case AArch64::SEH_SaveRegP:
918     case AArch64::SEH_SaveRegP_X:
919     case AArch64::SEH_SaveFReg:
920     case AArch64::SEH_SaveFReg_X:
921     case AArch64::SEH_SaveFRegP:
922     case AArch64::SEH_SaveFRegP_X:
923     case AArch64::SEH_SetFP:
924     case AArch64::SEH_AddFP:
925     case AArch64::SEH_Nop:
926     case AArch64::SEH_PrologEnd:
927     case AArch64::SEH_EpilogStart:
928     case AArch64::SEH_EpilogEnd:
929       return true;
930   }
931 }
932 
933 bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
934                                              Register &SrcReg, Register &DstReg,
935                                              unsigned &SubIdx) const {
936   switch (MI.getOpcode()) {
937   default:
938     return false;
939   case AArch64::SBFMXri: // aka sxtw
940   case AArch64::UBFMXri: // aka uxtw
941     // Check for the 32 -> 64 bit extension case, these instructions can do
942     // much more.
943     if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31)
944       return false;
945     // This is a signed or unsigned 32 -> 64 bit extension.
946     SrcReg = MI.getOperand(1).getReg();
947     DstReg = MI.getOperand(0).getReg();
948     SubIdx = AArch64::sub_32;
949     return true;
950   }
951 }
952 
953 bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint(
954     const MachineInstr &MIa, const MachineInstr &MIb) const {
955   const TargetRegisterInfo *TRI = &getRegisterInfo();
956   const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
957   int64_t OffsetA = 0, OffsetB = 0;
958   unsigned WidthA = 0, WidthB = 0;
959   bool OffsetAIsScalable = false, OffsetBIsScalable = false;
960 
961   assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
962   assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
963 
964   if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
965       MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
966     return false;
967 
968   // Retrieve the base, offset from the base and width. Width
969   // is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8).  If
970   // base are identical, and the offset of a lower memory access +
971   // the width doesn't overlap the offset of a higher memory access,
972   // then the memory accesses are different.
973   // If OffsetAIsScalable and OffsetBIsScalable are both true, they
974   // are assumed to have the same scale (vscale).
975   if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, OffsetAIsScalable,
976                                    WidthA, TRI) &&
977       getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, OffsetBIsScalable,
978                                    WidthB, TRI)) {
979     if (BaseOpA->isIdenticalTo(*BaseOpB) &&
980         OffsetAIsScalable == OffsetBIsScalable) {
981       int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
982       int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
983       int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
984       if (LowOffset + LowWidth <= HighOffset)
985         return true;
986     }
987   }
988   return false;
989 }
990 
991 bool AArch64InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
992                                             const MachineBasicBlock *MBB,
993                                             const MachineFunction &MF) const {
994   if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF))
995     return true;
996   switch (MI.getOpcode()) {
997   case AArch64::HINT:
998     // CSDB hints are scheduling barriers.
999     if (MI.getOperand(0).getImm() == 0x14)
1000       return true;
1001     break;
1002   case AArch64::DSB:
1003   case AArch64::ISB:
1004     // DSB and ISB also are scheduling barriers.
1005     return true;
1006   default:;
1007   }
1008   return isSEHInstruction(MI);
1009 }
1010 
1011 /// analyzeCompare - For a comparison instruction, return the source registers
1012 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
1013 /// Return true if the comparison instruction can be analyzed.
1014 bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1015                                       Register &SrcReg2, int &CmpMask,
1016                                       int &CmpValue) const {
1017   // The first operand can be a frame index where we'd normally expect a
1018   // register.
1019   assert(MI.getNumOperands() >= 2 && "All AArch64 cmps should have 2 operands");
1020   if (!MI.getOperand(1).isReg())
1021     return false;
1022 
1023   switch (MI.getOpcode()) {
1024   default:
1025     break;
1026   case AArch64::SUBSWrr:
1027   case AArch64::SUBSWrs:
1028   case AArch64::SUBSWrx:
1029   case AArch64::SUBSXrr:
1030   case AArch64::SUBSXrs:
1031   case AArch64::SUBSXrx:
1032   case AArch64::ADDSWrr:
1033   case AArch64::ADDSWrs:
1034   case AArch64::ADDSWrx:
1035   case AArch64::ADDSXrr:
1036   case AArch64::ADDSXrs:
1037   case AArch64::ADDSXrx:
1038     // Replace SUBSWrr with SUBWrr if NZCV is not used.
1039     SrcReg = MI.getOperand(1).getReg();
1040     SrcReg2 = MI.getOperand(2).getReg();
1041     CmpMask = ~0;
1042     CmpValue = 0;
1043     return true;
1044   case AArch64::SUBSWri:
1045   case AArch64::ADDSWri:
1046   case AArch64::SUBSXri:
1047   case AArch64::ADDSXri:
1048     SrcReg = MI.getOperand(1).getReg();
1049     SrcReg2 = 0;
1050     CmpMask = ~0;
1051     // FIXME: In order to convert CmpValue to 0 or 1
1052     CmpValue = MI.getOperand(2).getImm() != 0;
1053     return true;
1054   case AArch64::ANDSWri:
1055   case AArch64::ANDSXri:
1056     // ANDS does not use the same encoding scheme as the others xxxS
1057     // instructions.
1058     SrcReg = MI.getOperand(1).getReg();
1059     SrcReg2 = 0;
1060     CmpMask = ~0;
1061     // FIXME:The return val type of decodeLogicalImmediate is uint64_t,
1062     // while the type of CmpValue is int. When converting uint64_t to int,
1063     // the high 32 bits of uint64_t will be lost.
1064     // In fact it causes a bug in spec2006-483.xalancbmk
1065     // CmpValue is only used to compare with zero in OptimizeCompareInstr
1066     CmpValue = AArch64_AM::decodeLogicalImmediate(
1067                    MI.getOperand(2).getImm(),
1068                    MI.getOpcode() == AArch64::ANDSWri ? 32 : 64) != 0;
1069     return true;
1070   }
1071 
1072   return false;
1073 }
1074 
1075 static bool UpdateOperandRegClass(MachineInstr &Instr) {
1076   MachineBasicBlock *MBB = Instr.getParent();
1077   assert(MBB && "Can't get MachineBasicBlock here");
1078   MachineFunction *MF = MBB->getParent();
1079   assert(MF && "Can't get MachineFunction here");
1080   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1081   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1082   MachineRegisterInfo *MRI = &MF->getRegInfo();
1083 
1084   for (unsigned OpIdx = 0, EndIdx = Instr.getNumOperands(); OpIdx < EndIdx;
1085        ++OpIdx) {
1086     MachineOperand &MO = Instr.getOperand(OpIdx);
1087     const TargetRegisterClass *OpRegCstraints =
1088         Instr.getRegClassConstraint(OpIdx, TII, TRI);
1089 
1090     // If there's no constraint, there's nothing to do.
1091     if (!OpRegCstraints)
1092       continue;
1093     // If the operand is a frame index, there's nothing to do here.
1094     // A frame index operand will resolve correctly during PEI.
1095     if (MO.isFI())
1096       continue;
1097 
1098     assert(MO.isReg() &&
1099            "Operand has register constraints without being a register!");
1100 
1101     Register Reg = MO.getReg();
1102     if (Register::isPhysicalRegister(Reg)) {
1103       if (!OpRegCstraints->contains(Reg))
1104         return false;
1105     } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
1106                !MRI->constrainRegClass(Reg, OpRegCstraints))
1107       return false;
1108   }
1109 
1110   return true;
1111 }
1112 
1113 /// Return the opcode that does not set flags when possible - otherwise
1114 /// return the original opcode. The caller is responsible to do the actual
1115 /// substitution and legality checking.
1116 static unsigned convertToNonFlagSettingOpc(const MachineInstr &MI) {
1117   // Don't convert all compare instructions, because for some the zero register
1118   // encoding becomes the sp register.
1119   bool MIDefinesZeroReg = false;
1120   if (MI.definesRegister(AArch64::WZR) || MI.definesRegister(AArch64::XZR))
1121     MIDefinesZeroReg = true;
1122 
1123   switch (MI.getOpcode()) {
1124   default:
1125     return MI.getOpcode();
1126   case AArch64::ADDSWrr:
1127     return AArch64::ADDWrr;
1128   case AArch64::ADDSWri:
1129     return MIDefinesZeroReg ? AArch64::ADDSWri : AArch64::ADDWri;
1130   case AArch64::ADDSWrs:
1131     return MIDefinesZeroReg ? AArch64::ADDSWrs : AArch64::ADDWrs;
1132   case AArch64::ADDSWrx:
1133     return AArch64::ADDWrx;
1134   case AArch64::ADDSXrr:
1135     return AArch64::ADDXrr;
1136   case AArch64::ADDSXri:
1137     return MIDefinesZeroReg ? AArch64::ADDSXri : AArch64::ADDXri;
1138   case AArch64::ADDSXrs:
1139     return MIDefinesZeroReg ? AArch64::ADDSXrs : AArch64::ADDXrs;
1140   case AArch64::ADDSXrx:
1141     return AArch64::ADDXrx;
1142   case AArch64::SUBSWrr:
1143     return AArch64::SUBWrr;
1144   case AArch64::SUBSWri:
1145     return MIDefinesZeroReg ? AArch64::SUBSWri : AArch64::SUBWri;
1146   case AArch64::SUBSWrs:
1147     return MIDefinesZeroReg ? AArch64::SUBSWrs : AArch64::SUBWrs;
1148   case AArch64::SUBSWrx:
1149     return AArch64::SUBWrx;
1150   case AArch64::SUBSXrr:
1151     return AArch64::SUBXrr;
1152   case AArch64::SUBSXri:
1153     return MIDefinesZeroReg ? AArch64::SUBSXri : AArch64::SUBXri;
1154   case AArch64::SUBSXrs:
1155     return MIDefinesZeroReg ? AArch64::SUBSXrs : AArch64::SUBXrs;
1156   case AArch64::SUBSXrx:
1157     return AArch64::SUBXrx;
1158   }
1159 }
1160 
1161 enum AccessKind { AK_Write = 0x01, AK_Read = 0x10, AK_All = 0x11 };
1162 
1163 /// True when condition flags are accessed (either by writing or reading)
1164 /// on the instruction trace starting at From and ending at To.
1165 ///
1166 /// Note: If From and To are from different blocks it's assumed CC are accessed
1167 ///       on the path.
1168 static bool areCFlagsAccessedBetweenInstrs(
1169     MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,
1170     const TargetRegisterInfo *TRI, const AccessKind AccessToCheck = AK_All) {
1171   // Early exit if To is at the beginning of the BB.
1172   if (To == To->getParent()->begin())
1173     return true;
1174 
1175   // Check whether the instructions are in the same basic block
1176   // If not, assume the condition flags might get modified somewhere.
1177   if (To->getParent() != From->getParent())
1178     return true;
1179 
1180   // From must be above To.
1181   assert(std::find_if(++To.getReverse(), To->getParent()->rend(),
1182                       [From](MachineInstr &MI) {
1183                         return MI.getIterator() == From;
1184                       }) != To->getParent()->rend());
1185 
1186   // We iterate backward starting at \p To until we hit \p From.
1187   for (const MachineInstr &Instr :
1188        instructionsWithoutDebug(++To.getReverse(), From.getReverse())) {
1189     if (((AccessToCheck & AK_Write) &&
1190          Instr.modifiesRegister(AArch64::NZCV, TRI)) ||
1191         ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI)))
1192       return true;
1193   }
1194   return false;
1195 }
1196 
1197 /// Try to optimize a compare instruction. A compare instruction is an
1198 /// instruction which produces AArch64::NZCV. It can be truly compare
1199 /// instruction
1200 /// when there are no uses of its destination register.
1201 ///
1202 /// The following steps are tried in order:
1203 /// 1. Convert CmpInstr into an unconditional version.
1204 /// 2. Remove CmpInstr if above there is an instruction producing a needed
1205 ///    condition code or an instruction which can be converted into such an
1206 ///    instruction.
1207 ///    Only comparison with zero is supported.
1208 bool AArch64InstrInfo::optimizeCompareInstr(
1209     MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask,
1210     int CmpValue, const MachineRegisterInfo *MRI) const {
1211   assert(CmpInstr.getParent());
1212   assert(MRI);
1213 
1214   // Replace SUBSWrr with SUBWrr if NZCV is not used.
1215   int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true);
1216   if (DeadNZCVIdx != -1) {
1217     if (CmpInstr.definesRegister(AArch64::WZR) ||
1218         CmpInstr.definesRegister(AArch64::XZR)) {
1219       CmpInstr.eraseFromParent();
1220       return true;
1221     }
1222     unsigned Opc = CmpInstr.getOpcode();
1223     unsigned NewOpc = convertToNonFlagSettingOpc(CmpInstr);
1224     if (NewOpc == Opc)
1225       return false;
1226     const MCInstrDesc &MCID = get(NewOpc);
1227     CmpInstr.setDesc(MCID);
1228     CmpInstr.RemoveOperand(DeadNZCVIdx);
1229     bool succeeded = UpdateOperandRegClass(CmpInstr);
1230     (void)succeeded;
1231     assert(succeeded && "Some operands reg class are incompatible!");
1232     return true;
1233   }
1234 
1235   // Continue only if we have a "ri" where immediate is zero.
1236   // FIXME:CmpValue has already been converted to 0 or 1 in analyzeCompare
1237   // function.
1238   assert((CmpValue == 0 || CmpValue == 1) && "CmpValue must be 0 or 1!");
1239   if (CmpValue != 0 || SrcReg2 != 0)
1240     return false;
1241 
1242   // CmpInstr is a Compare instruction if destination register is not used.
1243   if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
1244     return false;
1245 
1246   return substituteCmpToZero(CmpInstr, SrcReg, MRI);
1247 }
1248 
1249 /// Get opcode of S version of Instr.
1250 /// If Instr is S version its opcode is returned.
1251 /// AArch64::INSTRUCTION_LIST_END is returned if Instr does not have S version
1252 /// or we are not interested in it.
1253 static unsigned sForm(MachineInstr &Instr) {
1254   switch (Instr.getOpcode()) {
1255   default:
1256     return AArch64::INSTRUCTION_LIST_END;
1257 
1258   case AArch64::ADDSWrr:
1259   case AArch64::ADDSWri:
1260   case AArch64::ADDSXrr:
1261   case AArch64::ADDSXri:
1262   case AArch64::SUBSWrr:
1263   case AArch64::SUBSWri:
1264   case AArch64::SUBSXrr:
1265   case AArch64::SUBSXri:
1266     return Instr.getOpcode();
1267 
1268   case AArch64::ADDWrr:
1269     return AArch64::ADDSWrr;
1270   case AArch64::ADDWri:
1271     return AArch64::ADDSWri;
1272   case AArch64::ADDXrr:
1273     return AArch64::ADDSXrr;
1274   case AArch64::ADDXri:
1275     return AArch64::ADDSXri;
1276   case AArch64::ADCWr:
1277     return AArch64::ADCSWr;
1278   case AArch64::ADCXr:
1279     return AArch64::ADCSXr;
1280   case AArch64::SUBWrr:
1281     return AArch64::SUBSWrr;
1282   case AArch64::SUBWri:
1283     return AArch64::SUBSWri;
1284   case AArch64::SUBXrr:
1285     return AArch64::SUBSXrr;
1286   case AArch64::SUBXri:
1287     return AArch64::SUBSXri;
1288   case AArch64::SBCWr:
1289     return AArch64::SBCSWr;
1290   case AArch64::SBCXr:
1291     return AArch64::SBCSXr;
1292   case AArch64::ANDWri:
1293     return AArch64::ANDSWri;
1294   case AArch64::ANDXri:
1295     return AArch64::ANDSXri;
1296   }
1297 }
1298 
1299 /// Check if AArch64::NZCV should be alive in successors of MBB.
1300 static bool areCFlagsAliveInSuccessors(MachineBasicBlock *MBB) {
1301   for (auto *BB : MBB->successors())
1302     if (BB->isLiveIn(AArch64::NZCV))
1303       return true;
1304   return false;
1305 }
1306 
1307 namespace {
1308 
1309 struct UsedNZCV {
1310   bool N = false;
1311   bool Z = false;
1312   bool C = false;
1313   bool V = false;
1314 
1315   UsedNZCV() = default;
1316 
1317   UsedNZCV &operator|=(const UsedNZCV &UsedFlags) {
1318     this->N |= UsedFlags.N;
1319     this->Z |= UsedFlags.Z;
1320     this->C |= UsedFlags.C;
1321     this->V |= UsedFlags.V;
1322     return *this;
1323   }
1324 };
1325 
1326 } // end anonymous namespace
1327 
1328 /// Find a condition code used by the instruction.
1329 /// Returns AArch64CC::Invalid if either the instruction does not use condition
1330 /// codes or we don't optimize CmpInstr in the presence of such instructions.
1331 static AArch64CC::CondCode findCondCodeUsedByInstr(const MachineInstr &Instr) {
1332   switch (Instr.getOpcode()) {
1333   default:
1334     return AArch64CC::Invalid;
1335 
1336   case AArch64::Bcc: {
1337     int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
1338     assert(Idx >= 2);
1339     return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 2).getImm());
1340   }
1341 
1342   case AArch64::CSINVWr:
1343   case AArch64::CSINVXr:
1344   case AArch64::CSINCWr:
1345   case AArch64::CSINCXr:
1346   case AArch64::CSELWr:
1347   case AArch64::CSELXr:
1348   case AArch64::CSNEGWr:
1349   case AArch64::CSNEGXr:
1350   case AArch64::FCSELSrrr:
1351   case AArch64::FCSELDrrr: {
1352     int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
1353     assert(Idx >= 1);
1354     return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 1).getImm());
1355   }
1356   }
1357 }
1358 
1359 static UsedNZCV getUsedNZCV(AArch64CC::CondCode CC) {
1360   assert(CC != AArch64CC::Invalid);
1361   UsedNZCV UsedFlags;
1362   switch (CC) {
1363   default:
1364     break;
1365 
1366   case AArch64CC::EQ: // Z set
1367   case AArch64CC::NE: // Z clear
1368     UsedFlags.Z = true;
1369     break;
1370 
1371   case AArch64CC::HI: // Z clear and C set
1372   case AArch64CC::LS: // Z set   or  C clear
1373     UsedFlags.Z = true;
1374     LLVM_FALLTHROUGH;
1375   case AArch64CC::HS: // C set
1376   case AArch64CC::LO: // C clear
1377     UsedFlags.C = true;
1378     break;
1379 
1380   case AArch64CC::MI: // N set
1381   case AArch64CC::PL: // N clear
1382     UsedFlags.N = true;
1383     break;
1384 
1385   case AArch64CC::VS: // V set
1386   case AArch64CC::VC: // V clear
1387     UsedFlags.V = true;
1388     break;
1389 
1390   case AArch64CC::GT: // Z clear, N and V the same
1391   case AArch64CC::LE: // Z set,   N and V differ
1392     UsedFlags.Z = true;
1393     LLVM_FALLTHROUGH;
1394   case AArch64CC::GE: // N and V the same
1395   case AArch64CC::LT: // N and V differ
1396     UsedFlags.N = true;
1397     UsedFlags.V = true;
1398     break;
1399   }
1400   return UsedFlags;
1401 }
1402 
1403 static bool isADDSRegImm(unsigned Opcode) {
1404   return Opcode == AArch64::ADDSWri || Opcode == AArch64::ADDSXri;
1405 }
1406 
1407 static bool isSUBSRegImm(unsigned Opcode) {
1408   return Opcode == AArch64::SUBSWri || Opcode == AArch64::SUBSXri;
1409 }
1410 
1411 /// Check if CmpInstr can be substituted by MI.
1412 ///
1413 /// CmpInstr can be substituted:
1414 /// - CmpInstr is either 'ADDS %vreg, 0' or 'SUBS %vreg, 0'
1415 /// - and, MI and CmpInstr are from the same MachineBB
1416 /// - and, condition flags are not alive in successors of the CmpInstr parent
1417 /// - and, if MI opcode is the S form there must be no defs of flags between
1418 ///        MI and CmpInstr
1419 ///        or if MI opcode is not the S form there must be neither defs of flags
1420 ///        nor uses of flags between MI and CmpInstr.
1421 /// - and  C/V flags are not used after CmpInstr
1422 static bool canInstrSubstituteCmpInstr(MachineInstr *MI, MachineInstr *CmpInstr,
1423                                        const TargetRegisterInfo *TRI) {
1424   assert(MI);
1425   assert(sForm(*MI) != AArch64::INSTRUCTION_LIST_END);
1426   assert(CmpInstr);
1427 
1428   const unsigned CmpOpcode = CmpInstr->getOpcode();
1429   if (!isADDSRegImm(CmpOpcode) && !isSUBSRegImm(CmpOpcode))
1430     return false;
1431 
1432   if (MI->getParent() != CmpInstr->getParent())
1433     return false;
1434 
1435   if (areCFlagsAliveInSuccessors(CmpInstr->getParent()))
1436     return false;
1437 
1438   AccessKind AccessToCheck = AK_Write;
1439   if (sForm(*MI) != MI->getOpcode())
1440     AccessToCheck = AK_All;
1441   if (areCFlagsAccessedBetweenInstrs(MI, CmpInstr, TRI, AccessToCheck))
1442     return false;
1443 
1444   UsedNZCV NZCVUsedAfterCmp;
1445   for (const MachineInstr &Instr :
1446        instructionsWithoutDebug(std::next(CmpInstr->getIterator()),
1447                                 CmpInstr->getParent()->instr_end())) {
1448     if (Instr.readsRegister(AArch64::NZCV, TRI)) {
1449       AArch64CC::CondCode CC = findCondCodeUsedByInstr(Instr);
1450       if (CC == AArch64CC::Invalid) // Unsupported conditional instruction
1451         return false;
1452       NZCVUsedAfterCmp |= getUsedNZCV(CC);
1453     }
1454 
1455     if (Instr.modifiesRegister(AArch64::NZCV, TRI))
1456       break;
1457   }
1458 
1459   return !NZCVUsedAfterCmp.C && !NZCVUsedAfterCmp.V;
1460 }
1461 
1462 /// Substitute an instruction comparing to zero with another instruction
1463 /// which produces needed condition flags.
1464 ///
1465 /// Return true on success.
1466 bool AArch64InstrInfo::substituteCmpToZero(
1467     MachineInstr &CmpInstr, unsigned SrcReg,
1468     const MachineRegisterInfo *MRI) const {
1469   assert(MRI);
1470   // Get the unique definition of SrcReg.
1471   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1472   if (!MI)
1473     return false;
1474 
1475   const TargetRegisterInfo *TRI = &getRegisterInfo();
1476 
1477   unsigned NewOpc = sForm(*MI);
1478   if (NewOpc == AArch64::INSTRUCTION_LIST_END)
1479     return false;
1480 
1481   if (!canInstrSubstituteCmpInstr(MI, &CmpInstr, TRI))
1482     return false;
1483 
1484   // Update the instruction to set NZCV.
1485   MI->setDesc(get(NewOpc));
1486   CmpInstr.eraseFromParent();
1487   bool succeeded = UpdateOperandRegClass(*MI);
1488   (void)succeeded;
1489   assert(succeeded && "Some operands reg class are incompatible!");
1490   MI->addRegisterDefined(AArch64::NZCV, TRI);
1491   return true;
1492 }
1493 
1494 bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1495   if (MI.getOpcode() != TargetOpcode::LOAD_STACK_GUARD &&
1496       MI.getOpcode() != AArch64::CATCHRET)
1497     return false;
1498 
1499   MachineBasicBlock &MBB = *MI.getParent();
1500   auto &Subtarget = MBB.getParent()->getSubtarget<AArch64Subtarget>();
1501   auto TRI = Subtarget.getRegisterInfo();
1502   DebugLoc DL = MI.getDebugLoc();
1503 
1504   if (MI.getOpcode() == AArch64::CATCHRET) {
1505     // Skip to the first instruction before the epilog.
1506     const TargetInstrInfo *TII =
1507       MBB.getParent()->getSubtarget().getInstrInfo();
1508     MachineBasicBlock *TargetMBB = MI.getOperand(0).getMBB();
1509     auto MBBI = MachineBasicBlock::iterator(MI);
1510     MachineBasicBlock::iterator FirstEpilogSEH = std::prev(MBBI);
1511     while (FirstEpilogSEH->getFlag(MachineInstr::FrameDestroy) &&
1512            FirstEpilogSEH != MBB.begin())
1513       FirstEpilogSEH = std::prev(FirstEpilogSEH);
1514     if (FirstEpilogSEH != MBB.begin())
1515       FirstEpilogSEH = std::next(FirstEpilogSEH);
1516     BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADRP))
1517         .addReg(AArch64::X0, RegState::Define)
1518         .addMBB(TargetMBB);
1519     BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADDXri))
1520         .addReg(AArch64::X0, RegState::Define)
1521         .addReg(AArch64::X0)
1522         .addMBB(TargetMBB)
1523         .addImm(0);
1524     return true;
1525   }
1526 
1527   Register Reg = MI.getOperand(0).getReg();
1528   const GlobalValue *GV =
1529       cast<GlobalValue>((*MI.memoperands_begin())->getValue());
1530   const TargetMachine &TM = MBB.getParent()->getTarget();
1531   unsigned OpFlags = Subtarget.ClassifyGlobalReference(GV, TM);
1532   const unsigned char MO_NC = AArch64II::MO_NC;
1533 
1534   if ((OpFlags & AArch64II::MO_GOT) != 0) {
1535     BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
1536         .addGlobalAddress(GV, 0, OpFlags);
1537     if (Subtarget.isTargetILP32()) {
1538       unsigned Reg32 = TRI->getSubReg(Reg, AArch64::sub_32);
1539       BuildMI(MBB, MI, DL, get(AArch64::LDRWui))
1540           .addDef(Reg32, RegState::Dead)
1541           .addUse(Reg, RegState::Kill)
1542           .addImm(0)
1543           .addMemOperand(*MI.memoperands_begin())
1544           .addDef(Reg, RegState::Implicit);
1545     } else {
1546       BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1547           .addReg(Reg, RegState::Kill)
1548           .addImm(0)
1549           .addMemOperand(*MI.memoperands_begin());
1550     }
1551   } else if (TM.getCodeModel() == CodeModel::Large) {
1552     assert(!Subtarget.isTargetILP32() && "how can large exist in ILP32?");
1553     BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
1554         .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC)
1555         .addImm(0);
1556     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1557         .addReg(Reg, RegState::Kill)
1558         .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC)
1559         .addImm(16);
1560     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1561         .addReg(Reg, RegState::Kill)
1562         .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC)
1563         .addImm(32);
1564     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1565         .addReg(Reg, RegState::Kill)
1566         .addGlobalAddress(GV, 0, AArch64II::MO_G3)
1567         .addImm(48);
1568     BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1569         .addReg(Reg, RegState::Kill)
1570         .addImm(0)
1571         .addMemOperand(*MI.memoperands_begin());
1572   } else if (TM.getCodeModel() == CodeModel::Tiny) {
1573     BuildMI(MBB, MI, DL, get(AArch64::ADR), Reg)
1574         .addGlobalAddress(GV, 0, OpFlags);
1575   } else {
1576     BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
1577         .addGlobalAddress(GV, 0, OpFlags | AArch64II::MO_PAGE);
1578     unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | MO_NC;
1579     if (Subtarget.isTargetILP32()) {
1580       unsigned Reg32 = TRI->getSubReg(Reg, AArch64::sub_32);
1581       BuildMI(MBB, MI, DL, get(AArch64::LDRWui))
1582           .addDef(Reg32, RegState::Dead)
1583           .addUse(Reg, RegState::Kill)
1584           .addGlobalAddress(GV, 0, LoFlags)
1585           .addMemOperand(*MI.memoperands_begin())
1586           .addDef(Reg, RegState::Implicit);
1587     } else {
1588       BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1589           .addReg(Reg, RegState::Kill)
1590           .addGlobalAddress(GV, 0, LoFlags)
1591           .addMemOperand(*MI.memoperands_begin());
1592     }
1593   }
1594 
1595   MBB.erase(MI);
1596 
1597   return true;
1598 }
1599 
1600 // Return true if this instruction simply sets its single destination register
1601 // to zero. This is equivalent to a register rename of the zero-register.
1602 bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) {
1603   switch (MI.getOpcode()) {
1604   default:
1605     break;
1606   case AArch64::MOVZWi:
1607   case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)
1608     if (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) {
1609       assert(MI.getDesc().getNumOperands() == 3 &&
1610              MI.getOperand(2).getImm() == 0 && "invalid MOVZi operands");
1611       return true;
1612     }
1613     break;
1614   case AArch64::ANDWri: // and Rd, Rzr, #imm
1615     return MI.getOperand(1).getReg() == AArch64::WZR;
1616   case AArch64::ANDXri:
1617     return MI.getOperand(1).getReg() == AArch64::XZR;
1618   case TargetOpcode::COPY:
1619     return MI.getOperand(1).getReg() == AArch64::WZR;
1620   }
1621   return false;
1622 }
1623 
1624 // Return true if this instruction simply renames a general register without
1625 // modifying bits.
1626 bool AArch64InstrInfo::isGPRCopy(const MachineInstr &MI) {
1627   switch (MI.getOpcode()) {
1628   default:
1629     break;
1630   case TargetOpcode::COPY: {
1631     // GPR32 copies will by lowered to ORRXrs
1632     Register DstReg = MI.getOperand(0).getReg();
1633     return (AArch64::GPR32RegClass.contains(DstReg) ||
1634             AArch64::GPR64RegClass.contains(DstReg));
1635   }
1636   case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
1637     if (MI.getOperand(1).getReg() == AArch64::XZR) {
1638       assert(MI.getDesc().getNumOperands() == 4 &&
1639              MI.getOperand(3).getImm() == 0 && "invalid ORRrs operands");
1640       return true;
1641     }
1642     break;
1643   case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0)
1644     if (MI.getOperand(2).getImm() == 0) {
1645       assert(MI.getDesc().getNumOperands() == 4 &&
1646              MI.getOperand(3).getImm() == 0 && "invalid ADDXri operands");
1647       return true;
1648     }
1649     break;
1650   }
1651   return false;
1652 }
1653 
1654 // Return true if this instruction simply renames a general register without
1655 // modifying bits.
1656 bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
1657   switch (MI.getOpcode()) {
1658   default:
1659     break;
1660   case TargetOpcode::COPY: {
1661     // FPR64 copies will by lowered to ORR.16b
1662     Register DstReg = MI.getOperand(0).getReg();
1663     return (AArch64::FPR64RegClass.contains(DstReg) ||
1664             AArch64::FPR128RegClass.contains(DstReg));
1665   }
1666   case AArch64::ORRv16i8:
1667     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
1668       assert(MI.getDesc().getNumOperands() == 3 && MI.getOperand(0).isReg() &&
1669              "invalid ORRv16i8 operands");
1670       return true;
1671     }
1672     break;
1673   }
1674   return false;
1675 }
1676 
1677 unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1678                                                int &FrameIndex) const {
1679   switch (MI.getOpcode()) {
1680   default:
1681     break;
1682   case AArch64::LDRWui:
1683   case AArch64::LDRXui:
1684   case AArch64::LDRBui:
1685   case AArch64::LDRHui:
1686   case AArch64::LDRSui:
1687   case AArch64::LDRDui:
1688   case AArch64::LDRQui:
1689     if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1690         MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
1691       FrameIndex = MI.getOperand(1).getIndex();
1692       return MI.getOperand(0).getReg();
1693     }
1694     break;
1695   }
1696 
1697   return 0;
1698 }
1699 
1700 unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1701                                               int &FrameIndex) const {
1702   switch (MI.getOpcode()) {
1703   default:
1704     break;
1705   case AArch64::STRWui:
1706   case AArch64::STRXui:
1707   case AArch64::STRBui:
1708   case AArch64::STRHui:
1709   case AArch64::STRSui:
1710   case AArch64::STRDui:
1711   case AArch64::STRQui:
1712   case AArch64::LDR_PXI:
1713   case AArch64::STR_PXI:
1714     if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1715         MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
1716       FrameIndex = MI.getOperand(1).getIndex();
1717       return MI.getOperand(0).getReg();
1718     }
1719     break;
1720   }
1721   return 0;
1722 }
1723 
1724 /// Check all MachineMemOperands for a hint to suppress pairing.
1725 bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) {
1726   return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
1727     return MMO->getFlags() & MOSuppressPair;
1728   });
1729 }
1730 
1731 /// Set a flag on the first MachineMemOperand to suppress pairing.
1732 void AArch64InstrInfo::suppressLdStPair(MachineInstr &MI) {
1733   if (MI.memoperands_empty())
1734     return;
1735   (*MI.memoperands_begin())->setFlags(MOSuppressPair);
1736 }
1737 
1738 /// Check all MachineMemOperands for a hint that the load/store is strided.
1739 bool AArch64InstrInfo::isStridedAccess(const MachineInstr &MI) {
1740   return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
1741     return MMO->getFlags() & MOStridedAccess;
1742   });
1743 }
1744 
1745 bool AArch64InstrInfo::isUnscaledLdSt(unsigned Opc) {
1746   switch (Opc) {
1747   default:
1748     return false;
1749   case AArch64::STURSi:
1750   case AArch64::STURDi:
1751   case AArch64::STURQi:
1752   case AArch64::STURBBi:
1753   case AArch64::STURHHi:
1754   case AArch64::STURWi:
1755   case AArch64::STURXi:
1756   case AArch64::LDURSi:
1757   case AArch64::LDURDi:
1758   case AArch64::LDURQi:
1759   case AArch64::LDURWi:
1760   case AArch64::LDURXi:
1761   case AArch64::LDURSWi:
1762   case AArch64::LDURHHi:
1763   case AArch64::LDURBBi:
1764   case AArch64::LDURSBWi:
1765   case AArch64::LDURSHWi:
1766     return true;
1767   }
1768 }
1769 
1770 Optional<unsigned> AArch64InstrInfo::getUnscaledLdSt(unsigned Opc) {
1771   switch (Opc) {
1772   default: return {};
1773   case AArch64::PRFMui: return AArch64::PRFUMi;
1774   case AArch64::LDRXui: return AArch64::LDURXi;
1775   case AArch64::LDRWui: return AArch64::LDURWi;
1776   case AArch64::LDRBui: return AArch64::LDURBi;
1777   case AArch64::LDRHui: return AArch64::LDURHi;
1778   case AArch64::LDRSui: return AArch64::LDURSi;
1779   case AArch64::LDRDui: return AArch64::LDURDi;
1780   case AArch64::LDRQui: return AArch64::LDURQi;
1781   case AArch64::LDRBBui: return AArch64::LDURBBi;
1782   case AArch64::LDRHHui: return AArch64::LDURHHi;
1783   case AArch64::LDRSBXui: return AArch64::LDURSBXi;
1784   case AArch64::LDRSBWui: return AArch64::LDURSBWi;
1785   case AArch64::LDRSHXui: return AArch64::LDURSHXi;
1786   case AArch64::LDRSHWui: return AArch64::LDURSHWi;
1787   case AArch64::LDRSWui: return AArch64::LDURSWi;
1788   case AArch64::STRXui: return AArch64::STURXi;
1789   case AArch64::STRWui: return AArch64::STURWi;
1790   case AArch64::STRBui: return AArch64::STURBi;
1791   case AArch64::STRHui: return AArch64::STURHi;
1792   case AArch64::STRSui: return AArch64::STURSi;
1793   case AArch64::STRDui: return AArch64::STURDi;
1794   case AArch64::STRQui: return AArch64::STURQi;
1795   case AArch64::STRBBui: return AArch64::STURBBi;
1796   case AArch64::STRHHui: return AArch64::STURHHi;
1797   }
1798 }
1799 
1800 unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) {
1801   switch (Opc) {
1802   default:
1803     return 2;
1804   case AArch64::LDPXi:
1805   case AArch64::LDPDi:
1806   case AArch64::STPXi:
1807   case AArch64::STPDi:
1808   case AArch64::LDNPXi:
1809   case AArch64::LDNPDi:
1810   case AArch64::STNPXi:
1811   case AArch64::STNPDi:
1812   case AArch64::LDPQi:
1813   case AArch64::STPQi:
1814   case AArch64::LDNPQi:
1815   case AArch64::STNPQi:
1816   case AArch64::LDPWi:
1817   case AArch64::LDPSi:
1818   case AArch64::STPWi:
1819   case AArch64::STPSi:
1820   case AArch64::LDNPWi:
1821   case AArch64::LDNPSi:
1822   case AArch64::STNPWi:
1823   case AArch64::STNPSi:
1824   case AArch64::LDG:
1825   case AArch64::STGPi:
1826   case AArch64::LD1B_IMM:
1827   case AArch64::LD1H_IMM:
1828   case AArch64::LD1W_IMM:
1829   case AArch64::LD1D_IMM:
1830   case AArch64::ST1B_IMM:
1831   case AArch64::ST1H_IMM:
1832   case AArch64::ST1W_IMM:
1833   case AArch64::ST1D_IMM:
1834     return 3;
1835   case AArch64::ADDG:
1836   case AArch64::STGOffset:
1837   case AArch64::LDR_PXI:
1838   case AArch64::STR_PXI:
1839     return 2;
1840   }
1841 }
1842 
1843 bool AArch64InstrInfo::isPairableLdStInst(const MachineInstr &MI) {
1844   switch (MI.getOpcode()) {
1845   default:
1846     return false;
1847   // Scaled instructions.
1848   case AArch64::STRSui:
1849   case AArch64::STRDui:
1850   case AArch64::STRQui:
1851   case AArch64::STRXui:
1852   case AArch64::STRWui:
1853   case AArch64::LDRSui:
1854   case AArch64::LDRDui:
1855   case AArch64::LDRQui:
1856   case AArch64::LDRXui:
1857   case AArch64::LDRWui:
1858   case AArch64::LDRSWui:
1859   // Unscaled instructions.
1860   case AArch64::STURSi:
1861   case AArch64::STURDi:
1862   case AArch64::STURQi:
1863   case AArch64::STURWi:
1864   case AArch64::STURXi:
1865   case AArch64::LDURSi:
1866   case AArch64::LDURDi:
1867   case AArch64::LDURQi:
1868   case AArch64::LDURWi:
1869   case AArch64::LDURXi:
1870   case AArch64::LDURSWi:
1871     return true;
1872   }
1873 }
1874 
1875 unsigned AArch64InstrInfo::convertToFlagSettingOpc(unsigned Opc,
1876                                                    bool &Is64Bit) {
1877   switch (Opc) {
1878   default:
1879     llvm_unreachable("Opcode has no flag setting equivalent!");
1880   // 32-bit cases:
1881   case AArch64::ADDWri:
1882     Is64Bit = false;
1883     return AArch64::ADDSWri;
1884   case AArch64::ADDWrr:
1885     Is64Bit = false;
1886     return AArch64::ADDSWrr;
1887   case AArch64::ADDWrs:
1888     Is64Bit = false;
1889     return AArch64::ADDSWrs;
1890   case AArch64::ADDWrx:
1891     Is64Bit = false;
1892     return AArch64::ADDSWrx;
1893   case AArch64::ANDWri:
1894     Is64Bit = false;
1895     return AArch64::ANDSWri;
1896   case AArch64::ANDWrr:
1897     Is64Bit = false;
1898     return AArch64::ANDSWrr;
1899   case AArch64::ANDWrs:
1900     Is64Bit = false;
1901     return AArch64::ANDSWrs;
1902   case AArch64::BICWrr:
1903     Is64Bit = false;
1904     return AArch64::BICSWrr;
1905   case AArch64::BICWrs:
1906     Is64Bit = false;
1907     return AArch64::BICSWrs;
1908   case AArch64::SUBWri:
1909     Is64Bit = false;
1910     return AArch64::SUBSWri;
1911   case AArch64::SUBWrr:
1912     Is64Bit = false;
1913     return AArch64::SUBSWrr;
1914   case AArch64::SUBWrs:
1915     Is64Bit = false;
1916     return AArch64::SUBSWrs;
1917   case AArch64::SUBWrx:
1918     Is64Bit = false;
1919     return AArch64::SUBSWrx;
1920   // 64-bit cases:
1921   case AArch64::ADDXri:
1922     Is64Bit = true;
1923     return AArch64::ADDSXri;
1924   case AArch64::ADDXrr:
1925     Is64Bit = true;
1926     return AArch64::ADDSXrr;
1927   case AArch64::ADDXrs:
1928     Is64Bit = true;
1929     return AArch64::ADDSXrs;
1930   case AArch64::ADDXrx:
1931     Is64Bit = true;
1932     return AArch64::ADDSXrx;
1933   case AArch64::ANDXri:
1934     Is64Bit = true;
1935     return AArch64::ANDSXri;
1936   case AArch64::ANDXrr:
1937     Is64Bit = true;
1938     return AArch64::ANDSXrr;
1939   case AArch64::ANDXrs:
1940     Is64Bit = true;
1941     return AArch64::ANDSXrs;
1942   case AArch64::BICXrr:
1943     Is64Bit = true;
1944     return AArch64::BICSXrr;
1945   case AArch64::BICXrs:
1946     Is64Bit = true;
1947     return AArch64::BICSXrs;
1948   case AArch64::SUBXri:
1949     Is64Bit = true;
1950     return AArch64::SUBSXri;
1951   case AArch64::SUBXrr:
1952     Is64Bit = true;
1953     return AArch64::SUBSXrr;
1954   case AArch64::SUBXrs:
1955     Is64Bit = true;
1956     return AArch64::SUBSXrs;
1957   case AArch64::SUBXrx:
1958     Is64Bit = true;
1959     return AArch64::SUBSXrx;
1960   }
1961 }
1962 
1963 // Is this a candidate for ld/st merging or pairing?  For example, we don't
1964 // touch volatiles or load/stores that have a hint to avoid pair formation.
1965 bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
1966   // If this is a volatile load/store, don't mess with it.
1967   if (MI.hasOrderedMemoryRef())
1968     return false;
1969 
1970   // Make sure this is a reg/fi+imm (as opposed to an address reloc).
1971   assert((MI.getOperand(1).isReg() || MI.getOperand(1).isFI()) &&
1972          "Expected a reg or frame index operand.");
1973   if (!MI.getOperand(2).isImm())
1974     return false;
1975 
1976   // Can't merge/pair if the instruction modifies the base register.
1977   // e.g., ldr x0, [x0]
1978   // This case will never occur with an FI base.
1979   if (MI.getOperand(1).isReg()) {
1980     Register BaseReg = MI.getOperand(1).getReg();
1981     const TargetRegisterInfo *TRI = &getRegisterInfo();
1982     if (MI.modifiesRegister(BaseReg, TRI))
1983       return false;
1984   }
1985 
1986   // Check if this load/store has a hint to avoid pair formation.
1987   // MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
1988   if (isLdStPairSuppressed(MI))
1989     return false;
1990 
1991   // Do not pair any callee-save store/reload instructions in the
1992   // prologue/epilogue if the CFI information encoded the operations as separate
1993   // instructions, as that will cause the size of the actual prologue to mismatch
1994   // with the prologue size recorded in the Windows CFI.
1995   const MCAsmInfo *MAI = MI.getMF()->getTarget().getMCAsmInfo();
1996   bool NeedsWinCFI = MAI->usesWindowsCFI() &&
1997                      MI.getMF()->getFunction().needsUnwindTableEntry();
1998   if (NeedsWinCFI && (MI.getFlag(MachineInstr::FrameSetup) ||
1999                       MI.getFlag(MachineInstr::FrameDestroy)))
2000     return false;
2001 
2002   // On some CPUs quad load/store pairs are slower than two single load/stores.
2003   if (Subtarget.isPaired128Slow()) {
2004     switch (MI.getOpcode()) {
2005     default:
2006       break;
2007     case AArch64::LDURQi:
2008     case AArch64::STURQi:
2009     case AArch64::LDRQui:
2010     case AArch64::STRQui:
2011       return false;
2012     }
2013   }
2014 
2015   return true;
2016 }
2017 
2018 bool AArch64InstrInfo::getMemOperandsWithOffset(
2019     const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
2020     int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI)
2021     const {
2022   if (!LdSt.mayLoadOrStore())
2023     return false;
2024 
2025   const MachineOperand *BaseOp;
2026   unsigned Width;
2027   if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable,
2028                                     Width, TRI))
2029     return false;
2030   BaseOps.push_back(BaseOp);
2031   return true;
2032 }
2033 
2034 bool AArch64InstrInfo::getMemOperandWithOffsetWidth(
2035     const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2036     bool &OffsetIsScalable, unsigned &Width,
2037     const TargetRegisterInfo *TRI) const {
2038   assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
2039   // Handle only loads/stores with base register followed by immediate offset.
2040   if (LdSt.getNumExplicitOperands() == 3) {
2041     // Non-paired instruction (e.g., ldr x1, [x0, #8]).
2042     if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
2043         !LdSt.getOperand(2).isImm())
2044       return false;
2045   } else if (LdSt.getNumExplicitOperands() == 4) {
2046     // Paired instruction (e.g., ldp x1, x2, [x0, #8]).
2047     if (!LdSt.getOperand(1).isReg() ||
2048         (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) ||
2049         !LdSt.getOperand(3).isImm())
2050       return false;
2051   } else
2052     return false;
2053 
2054   // Get the scaling factor for the instruction and set the width for the
2055   // instruction.
2056   TypeSize Scale(0U, false);
2057   int64_t Dummy1, Dummy2;
2058 
2059   // If this returns false, then it's an instruction we don't want to handle.
2060   if (!getMemOpInfo(LdSt.getOpcode(), Scale, Width, Dummy1, Dummy2))
2061     return false;
2062 
2063   // Compute the offset. Offset is calculated as the immediate operand
2064   // multiplied by the scaling factor. Unscaled instructions have scaling factor
2065   // set to 1.
2066   if (LdSt.getNumExplicitOperands() == 3) {
2067     BaseOp = &LdSt.getOperand(1);
2068     Offset = LdSt.getOperand(2).getImm() * Scale.getKnownMinSize();
2069   } else {
2070     assert(LdSt.getNumExplicitOperands() == 4 && "invalid number of operands");
2071     BaseOp = &LdSt.getOperand(2);
2072     Offset = LdSt.getOperand(3).getImm() * Scale.getKnownMinSize();
2073   }
2074   OffsetIsScalable = Scale.isScalable();
2075 
2076   if (!BaseOp->isReg() && !BaseOp->isFI())
2077     return false;
2078 
2079   return true;
2080 }
2081 
2082 MachineOperand &
2083 AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const {
2084   assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
2085   MachineOperand &OfsOp = LdSt.getOperand(LdSt.getNumExplicitOperands() - 1);
2086   assert(OfsOp.isImm() && "Offset operand wasn't immediate.");
2087   return OfsOp;
2088 }
2089 
2090 bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
2091                                     unsigned &Width, int64_t &MinOffset,
2092                                     int64_t &MaxOffset) {
2093   const unsigned SVEMaxBytesPerVector = AArch64::SVEMaxBitsPerVector / 8;
2094   switch (Opcode) {
2095   // Not a memory operation or something we want to handle.
2096   default:
2097     Scale = TypeSize::Fixed(0);
2098     Width = 0;
2099     MinOffset = MaxOffset = 0;
2100     return false;
2101   case AArch64::STRWpost:
2102   case AArch64::LDRWpost:
2103     Width = 32;
2104     Scale = TypeSize::Fixed(4);
2105     MinOffset = -256;
2106     MaxOffset = 255;
2107     break;
2108   case AArch64::LDURQi:
2109   case AArch64::STURQi:
2110     Width = 16;
2111     Scale = TypeSize::Fixed(1);
2112     MinOffset = -256;
2113     MaxOffset = 255;
2114     break;
2115   case AArch64::PRFUMi:
2116   case AArch64::LDURXi:
2117   case AArch64::LDURDi:
2118   case AArch64::STURXi:
2119   case AArch64::STURDi:
2120     Width = 8;
2121     Scale = TypeSize::Fixed(1);
2122     MinOffset = -256;
2123     MaxOffset = 255;
2124     break;
2125   case AArch64::LDURWi:
2126   case AArch64::LDURSi:
2127   case AArch64::LDURSWi:
2128   case AArch64::STURWi:
2129   case AArch64::STURSi:
2130     Width = 4;
2131     Scale = TypeSize::Fixed(1);
2132     MinOffset = -256;
2133     MaxOffset = 255;
2134     break;
2135   case AArch64::LDURHi:
2136   case AArch64::LDURHHi:
2137   case AArch64::LDURSHXi:
2138   case AArch64::LDURSHWi:
2139   case AArch64::STURHi:
2140   case AArch64::STURHHi:
2141     Width = 2;
2142     Scale = TypeSize::Fixed(1);
2143     MinOffset = -256;
2144     MaxOffset = 255;
2145     break;
2146   case AArch64::LDURBi:
2147   case AArch64::LDURBBi:
2148   case AArch64::LDURSBXi:
2149   case AArch64::LDURSBWi:
2150   case AArch64::STURBi:
2151   case AArch64::STURBBi:
2152     Width = 1;
2153     Scale = TypeSize::Fixed(1);
2154     MinOffset = -256;
2155     MaxOffset = 255;
2156     break;
2157   case AArch64::LDPQi:
2158   case AArch64::LDNPQi:
2159   case AArch64::STPQi:
2160   case AArch64::STNPQi:
2161     Scale = TypeSize::Fixed(16);
2162     Width = 32;
2163     MinOffset = -64;
2164     MaxOffset = 63;
2165     break;
2166   case AArch64::LDRQui:
2167   case AArch64::STRQui:
2168     Scale = TypeSize::Fixed(16);
2169     Width = 16;
2170     MinOffset = 0;
2171     MaxOffset = 4095;
2172     break;
2173   case AArch64::LDPXi:
2174   case AArch64::LDPDi:
2175   case AArch64::LDNPXi:
2176   case AArch64::LDNPDi:
2177   case AArch64::STPXi:
2178   case AArch64::STPDi:
2179   case AArch64::STNPXi:
2180   case AArch64::STNPDi:
2181     Scale = TypeSize::Fixed(8);
2182     Width = 16;
2183     MinOffset = -64;
2184     MaxOffset = 63;
2185     break;
2186   case AArch64::PRFMui:
2187   case AArch64::LDRXui:
2188   case AArch64::LDRDui:
2189   case AArch64::STRXui:
2190   case AArch64::STRDui:
2191     Scale = TypeSize::Fixed(8);
2192     Width = 8;
2193     MinOffset = 0;
2194     MaxOffset = 4095;
2195     break;
2196   case AArch64::LDPWi:
2197   case AArch64::LDPSi:
2198   case AArch64::LDNPWi:
2199   case AArch64::LDNPSi:
2200   case AArch64::STPWi:
2201   case AArch64::STPSi:
2202   case AArch64::STNPWi:
2203   case AArch64::STNPSi:
2204     Scale = TypeSize::Fixed(4);
2205     Width = 8;
2206     MinOffset = -64;
2207     MaxOffset = 63;
2208     break;
2209   case AArch64::LDRWui:
2210   case AArch64::LDRSui:
2211   case AArch64::LDRSWui:
2212   case AArch64::STRWui:
2213   case AArch64::STRSui:
2214     Scale = TypeSize::Fixed(4);
2215     Width = 4;
2216     MinOffset = 0;
2217     MaxOffset = 4095;
2218     break;
2219   case AArch64::LDRHui:
2220   case AArch64::LDRHHui:
2221   case AArch64::LDRSHWui:
2222   case AArch64::LDRSHXui:
2223   case AArch64::STRHui:
2224   case AArch64::STRHHui:
2225     Scale = TypeSize::Fixed(2);
2226     Width = 2;
2227     MinOffset = 0;
2228     MaxOffset = 4095;
2229     break;
2230   case AArch64::LDRBui:
2231   case AArch64::LDRBBui:
2232   case AArch64::LDRSBWui:
2233   case AArch64::LDRSBXui:
2234   case AArch64::STRBui:
2235   case AArch64::STRBBui:
2236     Scale = TypeSize::Fixed(1);
2237     Width = 1;
2238     MinOffset = 0;
2239     MaxOffset = 4095;
2240     break;
2241   case AArch64::ADDG:
2242     Scale = TypeSize::Fixed(16);
2243     Width = 0;
2244     MinOffset = 0;
2245     MaxOffset = 63;
2246     break;
2247   case AArch64::TAGPstack:
2248     Scale = TypeSize::Fixed(16);
2249     Width = 0;
2250     // TAGP with a negative offset turns into SUBP, which has a maximum offset
2251     // of 63 (not 64!).
2252     MinOffset = -63;
2253     MaxOffset = 63;
2254     break;
2255   case AArch64::LDG:
2256   case AArch64::STGOffset:
2257   case AArch64::STZGOffset:
2258     Scale = TypeSize::Fixed(16);
2259     Width = 16;
2260     MinOffset = -256;
2261     MaxOffset = 255;
2262     break;
2263   case AArch64::LDR_PXI:
2264   case AArch64::STR_PXI:
2265     Scale = TypeSize::Scalable(2);
2266     Width = SVEMaxBytesPerVector / 8;
2267     MinOffset = -256;
2268     MaxOffset = 255;
2269     break;
2270   case AArch64::LDR_ZXI:
2271   case AArch64::STR_ZXI:
2272     Scale = TypeSize::Scalable(16);
2273     Width = SVEMaxBytesPerVector;
2274     MinOffset = -256;
2275     MaxOffset = 255;
2276     break;
2277   case AArch64::LD1B_IMM:
2278   case AArch64::LD1H_IMM:
2279   case AArch64::LD1W_IMM:
2280   case AArch64::LD1D_IMM:
2281   case AArch64::ST1B_IMM:
2282   case AArch64::ST1H_IMM:
2283   case AArch64::ST1W_IMM:
2284   case AArch64::ST1D_IMM:
2285     // A full vectors worth of data
2286     // Width = mbytes * elements
2287     Scale = TypeSize::Scalable(16);
2288     Width = SVEMaxBytesPerVector;
2289     MinOffset = -8;
2290     MaxOffset = 7;
2291     break;
2292   case AArch64::ST2GOffset:
2293   case AArch64::STZ2GOffset:
2294     Scale = TypeSize::Fixed(16);
2295     Width = 32;
2296     MinOffset = -256;
2297     MaxOffset = 255;
2298     break;
2299   case AArch64::STGPi:
2300     Scale = TypeSize::Fixed(16);
2301     Width = 16;
2302     MinOffset = -64;
2303     MaxOffset = 63;
2304     break;
2305   }
2306 
2307   return true;
2308 }
2309 
2310 // Scaling factor for unscaled load or store.
2311 int AArch64InstrInfo::getMemScale(unsigned Opc) {
2312   switch (Opc) {
2313   default:
2314     llvm_unreachable("Opcode has unknown scale!");
2315   case AArch64::LDRBBui:
2316   case AArch64::LDURBBi:
2317   case AArch64::LDRSBWui:
2318   case AArch64::LDURSBWi:
2319   case AArch64::STRBBui:
2320   case AArch64::STURBBi:
2321     return 1;
2322   case AArch64::LDRHHui:
2323   case AArch64::LDURHHi:
2324   case AArch64::LDRSHWui:
2325   case AArch64::LDURSHWi:
2326   case AArch64::STRHHui:
2327   case AArch64::STURHHi:
2328     return 2;
2329   case AArch64::LDRSui:
2330   case AArch64::LDURSi:
2331   case AArch64::LDRSWui:
2332   case AArch64::LDURSWi:
2333   case AArch64::LDRWui:
2334   case AArch64::LDURWi:
2335   case AArch64::STRSui:
2336   case AArch64::STURSi:
2337   case AArch64::STRWui:
2338   case AArch64::STURWi:
2339   case AArch64::LDPSi:
2340   case AArch64::LDPSWi:
2341   case AArch64::LDPWi:
2342   case AArch64::STPSi:
2343   case AArch64::STPWi:
2344     return 4;
2345   case AArch64::LDRDui:
2346   case AArch64::LDURDi:
2347   case AArch64::LDRXui:
2348   case AArch64::LDURXi:
2349   case AArch64::STRDui:
2350   case AArch64::STURDi:
2351   case AArch64::STRXui:
2352   case AArch64::STURXi:
2353   case AArch64::LDPDi:
2354   case AArch64::LDPXi:
2355   case AArch64::STPDi:
2356   case AArch64::STPXi:
2357     return 8;
2358   case AArch64::LDRQui:
2359   case AArch64::LDURQi:
2360   case AArch64::STRQui:
2361   case AArch64::STURQi:
2362   case AArch64::LDPQi:
2363   case AArch64::STPQi:
2364   case AArch64::STGOffset:
2365   case AArch64::STZGOffset:
2366   case AArch64::ST2GOffset:
2367   case AArch64::STZ2GOffset:
2368   case AArch64::STGPi:
2369     return 16;
2370   }
2371 }
2372 
2373 // Scale the unscaled offsets.  Returns false if the unscaled offset can't be
2374 // scaled.
2375 static bool scaleOffset(unsigned Opc, int64_t &Offset) {
2376   int Scale = AArch64InstrInfo::getMemScale(Opc);
2377 
2378   // If the byte-offset isn't a multiple of the stride, we can't scale this
2379   // offset.
2380   if (Offset % Scale != 0)
2381     return false;
2382 
2383   // Convert the byte-offset used by unscaled into an "element" offset used
2384   // by the scaled pair load/store instructions.
2385   Offset /= Scale;
2386   return true;
2387 }
2388 
2389 static bool canPairLdStOpc(unsigned FirstOpc, unsigned SecondOpc) {
2390   if (FirstOpc == SecondOpc)
2391     return true;
2392   // We can also pair sign-ext and zero-ext instructions.
2393   switch (FirstOpc) {
2394   default:
2395     return false;
2396   case AArch64::LDRWui:
2397   case AArch64::LDURWi:
2398     return SecondOpc == AArch64::LDRSWui || SecondOpc == AArch64::LDURSWi;
2399   case AArch64::LDRSWui:
2400   case AArch64::LDURSWi:
2401     return SecondOpc == AArch64::LDRWui || SecondOpc == AArch64::LDURWi;
2402   }
2403   // These instructions can't be paired based on their opcodes.
2404   return false;
2405 }
2406 
2407 static bool shouldClusterFI(const MachineFrameInfo &MFI, int FI1,
2408                             int64_t Offset1, unsigned Opcode1, int FI2,
2409                             int64_t Offset2, unsigned Opcode2) {
2410   // Accesses through fixed stack object frame indices may access a different
2411   // fixed stack slot. Check that the object offsets + offsets match.
2412   if (MFI.isFixedObjectIndex(FI1) && MFI.isFixedObjectIndex(FI2)) {
2413     int64_t ObjectOffset1 = MFI.getObjectOffset(FI1);
2414     int64_t ObjectOffset2 = MFI.getObjectOffset(FI2);
2415     assert(ObjectOffset1 <= ObjectOffset2 && "Object offsets are not ordered.");
2416     // Convert to scaled object offsets.
2417     int Scale1 = AArch64InstrInfo::getMemScale(Opcode1);
2418     if (ObjectOffset1 % Scale1 != 0)
2419       return false;
2420     ObjectOffset1 /= Scale1;
2421     int Scale2 = AArch64InstrInfo::getMemScale(Opcode2);
2422     if (ObjectOffset2 % Scale2 != 0)
2423       return false;
2424     ObjectOffset2 /= Scale2;
2425     ObjectOffset1 += Offset1;
2426     ObjectOffset2 += Offset2;
2427     return ObjectOffset1 + 1 == ObjectOffset2;
2428   }
2429 
2430   return FI1 == FI2;
2431 }
2432 
2433 /// Detect opportunities for ldp/stp formation.
2434 ///
2435 /// Only called for LdSt for which getMemOperandWithOffset returns true.
2436 bool AArch64InstrInfo::shouldClusterMemOps(
2437     ArrayRef<const MachineOperand *> BaseOps1,
2438     ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads) const {
2439   assert(BaseOps1.size() == 1 && BaseOps2.size() == 1);
2440   const MachineOperand &BaseOp1 = *BaseOps1.front();
2441   const MachineOperand &BaseOp2 = *BaseOps2.front();
2442   const MachineInstr &FirstLdSt = *BaseOp1.getParent();
2443   const MachineInstr &SecondLdSt = *BaseOp2.getParent();
2444   if (BaseOp1.getType() != BaseOp2.getType())
2445     return false;
2446 
2447   assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
2448          "Only base registers and frame indices are supported.");
2449 
2450   // Check for both base regs and base FI.
2451   if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg())
2452     return false;
2453 
2454   // Only cluster up to a single pair.
2455   if (NumLoads > 2)
2456     return false;
2457 
2458   if (!isPairableLdStInst(FirstLdSt) || !isPairableLdStInst(SecondLdSt))
2459     return false;
2460 
2461   // Can we pair these instructions based on their opcodes?
2462   unsigned FirstOpc = FirstLdSt.getOpcode();
2463   unsigned SecondOpc = SecondLdSt.getOpcode();
2464   if (!canPairLdStOpc(FirstOpc, SecondOpc))
2465     return false;
2466 
2467   // Can't merge volatiles or load/stores that have a hint to avoid pair
2468   // formation, for example.
2469   if (!isCandidateToMergeOrPair(FirstLdSt) ||
2470       !isCandidateToMergeOrPair(SecondLdSt))
2471     return false;
2472 
2473   // isCandidateToMergeOrPair guarantees that operand 2 is an immediate.
2474   int64_t Offset1 = FirstLdSt.getOperand(2).getImm();
2475   if (isUnscaledLdSt(FirstOpc) && !scaleOffset(FirstOpc, Offset1))
2476     return false;
2477 
2478   int64_t Offset2 = SecondLdSt.getOperand(2).getImm();
2479   if (isUnscaledLdSt(SecondOpc) && !scaleOffset(SecondOpc, Offset2))
2480     return false;
2481 
2482   // Pairwise instructions have a 7-bit signed offset field.
2483   if (Offset1 > 63 || Offset1 < -64)
2484     return false;
2485 
2486   // The caller should already have ordered First/SecondLdSt by offset.
2487   // Note: except for non-equal frame index bases
2488   if (BaseOp1.isFI()) {
2489     assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) &&
2490            "Caller should have ordered offsets.");
2491 
2492     const MachineFrameInfo &MFI =
2493         FirstLdSt.getParent()->getParent()->getFrameInfo();
2494     return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc,
2495                            BaseOp2.getIndex(), Offset2, SecondOpc);
2496   }
2497 
2498   assert(Offset1 <= Offset2 && "Caller should have ordered offsets.");
2499 
2500   return Offset1 + 1 == Offset2;
2501 }
2502 
2503 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
2504                                             unsigned Reg, unsigned SubIdx,
2505                                             unsigned State,
2506                                             const TargetRegisterInfo *TRI) {
2507   if (!SubIdx)
2508     return MIB.addReg(Reg, State);
2509 
2510   if (Register::isPhysicalRegister(Reg))
2511     return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
2512   return MIB.addReg(Reg, State, SubIdx);
2513 }
2514 
2515 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg,
2516                                         unsigned NumRegs) {
2517   // We really want the positive remainder mod 32 here, that happens to be
2518   // easily obtainable with a mask.
2519   return ((DestReg - SrcReg) & 0x1f) < NumRegs;
2520 }
2521 
2522 void AArch64InstrInfo::copyPhysRegTuple(MachineBasicBlock &MBB,
2523                                         MachineBasicBlock::iterator I,
2524                                         const DebugLoc &DL, MCRegister DestReg,
2525                                         MCRegister SrcReg, bool KillSrc,
2526                                         unsigned Opcode,
2527                                         ArrayRef<unsigned> Indices) const {
2528   assert(Subtarget.hasNEON() && "Unexpected register copy without NEON");
2529   const TargetRegisterInfo *TRI = &getRegisterInfo();
2530   uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
2531   uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
2532   unsigned NumRegs = Indices.size();
2533 
2534   int SubReg = 0, End = NumRegs, Incr = 1;
2535   if (forwardCopyWillClobberTuple(DestEncoding, SrcEncoding, NumRegs)) {
2536     SubReg = NumRegs - 1;
2537     End = -1;
2538     Incr = -1;
2539   }
2540 
2541   for (; SubReg != End; SubReg += Incr) {
2542     const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2543     AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
2544     AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
2545     AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
2546   }
2547 }
2548 
2549 void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
2550                                        MachineBasicBlock::iterator I,
2551                                        DebugLoc DL, unsigned DestReg,
2552                                        unsigned SrcReg, bool KillSrc,
2553                                        unsigned Opcode, unsigned ZeroReg,
2554                                        llvm::ArrayRef<unsigned> Indices) const {
2555   const TargetRegisterInfo *TRI = &getRegisterInfo();
2556   unsigned NumRegs = Indices.size();
2557 
2558 #ifndef NDEBUG
2559   uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
2560   uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
2561   assert(DestEncoding % NumRegs == 0 && SrcEncoding % NumRegs == 0 &&
2562          "GPR reg sequences should not be able to overlap");
2563 #endif
2564 
2565   for (unsigned SubReg = 0; SubReg != NumRegs; ++SubReg) {
2566     const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2567     AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
2568     MIB.addReg(ZeroReg);
2569     AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
2570     MIB.addImm(0);
2571   }
2572 }
2573 
2574 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2575                                    MachineBasicBlock::iterator I,
2576                                    const DebugLoc &DL, MCRegister DestReg,
2577                                    MCRegister SrcReg, bool KillSrc) const {
2578   if (AArch64::GPR32spRegClass.contains(DestReg) &&
2579       (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
2580     const TargetRegisterInfo *TRI = &getRegisterInfo();
2581 
2582     if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
2583       // If either operand is WSP, expand to ADD #0.
2584       if (Subtarget.hasZeroCycleRegMove()) {
2585         // Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
2586         MCRegister DestRegX = TRI->getMatchingSuperReg(
2587             DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
2588         MCRegister SrcRegX = TRI->getMatchingSuperReg(
2589             SrcReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
2590         // This instruction is reading and writing X registers.  This may upset
2591         // the register scavenger and machine verifier, so we need to indicate
2592         // that we are reading an undefined value from SrcRegX, but a proper
2593         // value from SrcReg.
2594         BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
2595             .addReg(SrcRegX, RegState::Undef)
2596             .addImm(0)
2597             .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
2598             .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
2599       } else {
2600         BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
2601             .addReg(SrcReg, getKillRegState(KillSrc))
2602             .addImm(0)
2603             .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2604       }
2605     } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGP()) {
2606       BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
2607           .addImm(0)
2608           .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2609     } else {
2610       if (Subtarget.hasZeroCycleRegMove()) {
2611         // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
2612         MCRegister DestRegX = TRI->getMatchingSuperReg(
2613             DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
2614         MCRegister SrcRegX = TRI->getMatchingSuperReg(
2615             SrcReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
2616         // This instruction is reading and writing X registers.  This may upset
2617         // the register scavenger and machine verifier, so we need to indicate
2618         // that we are reading an undefined value from SrcRegX, but a proper
2619         // value from SrcReg.
2620         BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX)
2621             .addReg(AArch64::XZR)
2622             .addReg(SrcRegX, RegState::Undef)
2623             .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
2624       } else {
2625         // Otherwise, expand to ORR WZR.
2626         BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
2627             .addReg(AArch64::WZR)
2628             .addReg(SrcReg, getKillRegState(KillSrc));
2629       }
2630     }
2631     return;
2632   }
2633 
2634   // Copy a Predicate register by ORRing with itself.
2635   if (AArch64::PPRRegClass.contains(DestReg) &&
2636       AArch64::PPRRegClass.contains(SrcReg)) {
2637     assert(Subtarget.hasSVE() && "Unexpected SVE register.");
2638     BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg)
2639       .addReg(SrcReg) // Pg
2640       .addReg(SrcReg)
2641       .addReg(SrcReg, getKillRegState(KillSrc));
2642     return;
2643   }
2644 
2645   // Copy a Z register by ORRing with itself.
2646   if (AArch64::ZPRRegClass.contains(DestReg) &&
2647       AArch64::ZPRRegClass.contains(SrcReg)) {
2648     assert(Subtarget.hasSVE() && "Unexpected SVE register.");
2649     BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ), DestReg)
2650       .addReg(SrcReg)
2651       .addReg(SrcReg, getKillRegState(KillSrc));
2652     return;
2653   }
2654 
2655   if (AArch64::GPR64spRegClass.contains(DestReg) &&
2656       (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) {
2657     if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
2658       // If either operand is SP, expand to ADD #0.
2659       BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
2660           .addReg(SrcReg, getKillRegState(KillSrc))
2661           .addImm(0)
2662           .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2663     } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGP()) {
2664       BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
2665           .addImm(0)
2666           .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2667     } else {
2668       // Otherwise, expand to ORR XZR.
2669       BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
2670           .addReg(AArch64::XZR)
2671           .addReg(SrcReg, getKillRegState(KillSrc));
2672     }
2673     return;
2674   }
2675 
2676   // Copy a DDDD register quad by copying the individual sub-registers.
2677   if (AArch64::DDDDRegClass.contains(DestReg) &&
2678       AArch64::DDDDRegClass.contains(SrcReg)) {
2679     static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1,
2680                                        AArch64::dsub2, AArch64::dsub3};
2681     copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
2682                      Indices);
2683     return;
2684   }
2685 
2686   // Copy a DDD register triple by copying the individual sub-registers.
2687   if (AArch64::DDDRegClass.contains(DestReg) &&
2688       AArch64::DDDRegClass.contains(SrcReg)) {
2689     static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1,
2690                                        AArch64::dsub2};
2691     copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
2692                      Indices);
2693     return;
2694   }
2695 
2696   // Copy a DD register pair by copying the individual sub-registers.
2697   if (AArch64::DDRegClass.contains(DestReg) &&
2698       AArch64::DDRegClass.contains(SrcReg)) {
2699     static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1};
2700     copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
2701                      Indices);
2702     return;
2703   }
2704 
2705   // Copy a QQQQ register quad by copying the individual sub-registers.
2706   if (AArch64::QQQQRegClass.contains(DestReg) &&
2707       AArch64::QQQQRegClass.contains(SrcReg)) {
2708     static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1,
2709                                        AArch64::qsub2, AArch64::qsub3};
2710     copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
2711                      Indices);
2712     return;
2713   }
2714 
2715   // Copy a QQQ register triple by copying the individual sub-registers.
2716   if (AArch64::QQQRegClass.contains(DestReg) &&
2717       AArch64::QQQRegClass.contains(SrcReg)) {
2718     static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1,
2719                                        AArch64::qsub2};
2720     copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
2721                      Indices);
2722     return;
2723   }
2724 
2725   // Copy a QQ register pair by copying the individual sub-registers.
2726   if (AArch64::QQRegClass.contains(DestReg) &&
2727       AArch64::QQRegClass.contains(SrcReg)) {
2728     static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1};
2729     copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
2730                      Indices);
2731     return;
2732   }
2733 
2734   if (AArch64::XSeqPairsClassRegClass.contains(DestReg) &&
2735       AArch64::XSeqPairsClassRegClass.contains(SrcReg)) {
2736     static const unsigned Indices[] = {AArch64::sube64, AArch64::subo64};
2737     copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRXrs,
2738                     AArch64::XZR, Indices);
2739     return;
2740   }
2741 
2742   if (AArch64::WSeqPairsClassRegClass.contains(DestReg) &&
2743       AArch64::WSeqPairsClassRegClass.contains(SrcReg)) {
2744     static const unsigned Indices[] = {AArch64::sube32, AArch64::subo32};
2745     copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRWrs,
2746                     AArch64::WZR, Indices);
2747     return;
2748   }
2749 
2750   if (AArch64::FPR128RegClass.contains(DestReg) &&
2751       AArch64::FPR128RegClass.contains(SrcReg)) {
2752     if (Subtarget.hasNEON()) {
2753       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2754           .addReg(SrcReg)
2755           .addReg(SrcReg, getKillRegState(KillSrc));
2756     } else {
2757       BuildMI(MBB, I, DL, get(AArch64::STRQpre))
2758           .addReg(AArch64::SP, RegState::Define)
2759           .addReg(SrcReg, getKillRegState(KillSrc))
2760           .addReg(AArch64::SP)
2761           .addImm(-16);
2762       BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
2763           .addReg(AArch64::SP, RegState::Define)
2764           .addReg(DestReg, RegState::Define)
2765           .addReg(AArch64::SP)
2766           .addImm(16);
2767     }
2768     return;
2769   }
2770 
2771   if (AArch64::FPR64RegClass.contains(DestReg) &&
2772       AArch64::FPR64RegClass.contains(SrcReg)) {
2773     if (Subtarget.hasNEON()) {
2774       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
2775                                        &AArch64::FPR128RegClass);
2776       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
2777                                       &AArch64::FPR128RegClass);
2778       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2779           .addReg(SrcReg)
2780           .addReg(SrcReg, getKillRegState(KillSrc));
2781     } else {
2782       BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
2783           .addReg(SrcReg, getKillRegState(KillSrc));
2784     }
2785     return;
2786   }
2787 
2788   if (AArch64::FPR32RegClass.contains(DestReg) &&
2789       AArch64::FPR32RegClass.contains(SrcReg)) {
2790     if (Subtarget.hasNEON()) {
2791       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
2792                                        &AArch64::FPR128RegClass);
2793       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
2794                                       &AArch64::FPR128RegClass);
2795       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2796           .addReg(SrcReg)
2797           .addReg(SrcReg, getKillRegState(KillSrc));
2798     } else {
2799       BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2800           .addReg(SrcReg, getKillRegState(KillSrc));
2801     }
2802     return;
2803   }
2804 
2805   if (AArch64::FPR16RegClass.contains(DestReg) &&
2806       AArch64::FPR16RegClass.contains(SrcReg)) {
2807     if (Subtarget.hasNEON()) {
2808       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
2809                                        &AArch64::FPR128RegClass);
2810       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
2811                                       &AArch64::FPR128RegClass);
2812       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2813           .addReg(SrcReg)
2814           .addReg(SrcReg, getKillRegState(KillSrc));
2815     } else {
2816       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
2817                                        &AArch64::FPR32RegClass);
2818       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
2819                                       &AArch64::FPR32RegClass);
2820       BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2821           .addReg(SrcReg, getKillRegState(KillSrc));
2822     }
2823     return;
2824   }
2825 
2826   if (AArch64::FPR8RegClass.contains(DestReg) &&
2827       AArch64::FPR8RegClass.contains(SrcReg)) {
2828     if (Subtarget.hasNEON()) {
2829       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
2830                                        &AArch64::FPR128RegClass);
2831       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
2832                                       &AArch64::FPR128RegClass);
2833       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2834           .addReg(SrcReg)
2835           .addReg(SrcReg, getKillRegState(KillSrc));
2836     } else {
2837       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
2838                                        &AArch64::FPR32RegClass);
2839       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
2840                                       &AArch64::FPR32RegClass);
2841       BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2842           .addReg(SrcReg, getKillRegState(KillSrc));
2843     }
2844     return;
2845   }
2846 
2847   // Copies between GPR64 and FPR64.
2848   if (AArch64::FPR64RegClass.contains(DestReg) &&
2849       AArch64::GPR64RegClass.contains(SrcReg)) {
2850     BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
2851         .addReg(SrcReg, getKillRegState(KillSrc));
2852     return;
2853   }
2854   if (AArch64::GPR64RegClass.contains(DestReg) &&
2855       AArch64::FPR64RegClass.contains(SrcReg)) {
2856     BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
2857         .addReg(SrcReg, getKillRegState(KillSrc));
2858     return;
2859   }
2860   // Copies between GPR32 and FPR32.
2861   if (AArch64::FPR32RegClass.contains(DestReg) &&
2862       AArch64::GPR32RegClass.contains(SrcReg)) {
2863     BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
2864         .addReg(SrcReg, getKillRegState(KillSrc));
2865     return;
2866   }
2867   if (AArch64::GPR32RegClass.contains(DestReg) &&
2868       AArch64::FPR32RegClass.contains(SrcReg)) {
2869     BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
2870         .addReg(SrcReg, getKillRegState(KillSrc));
2871     return;
2872   }
2873 
2874   if (DestReg == AArch64::NZCV) {
2875     assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy");
2876     BuildMI(MBB, I, DL, get(AArch64::MSR))
2877         .addImm(AArch64SysReg::NZCV)
2878         .addReg(SrcReg, getKillRegState(KillSrc))
2879         .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
2880     return;
2881   }
2882 
2883   if (SrcReg == AArch64::NZCV) {
2884     assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
2885     BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg)
2886         .addImm(AArch64SysReg::NZCV)
2887         .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
2888     return;
2889   }
2890 
2891   llvm_unreachable("unimplemented reg-to-reg copy");
2892 }
2893 
2894 static void storeRegPairToStackSlot(const TargetRegisterInfo &TRI,
2895                                     MachineBasicBlock &MBB,
2896                                     MachineBasicBlock::iterator InsertBefore,
2897                                     const MCInstrDesc &MCID,
2898                                     Register SrcReg, bool IsKill,
2899                                     unsigned SubIdx0, unsigned SubIdx1, int FI,
2900                                     MachineMemOperand *MMO) {
2901   Register SrcReg0 = SrcReg;
2902   Register SrcReg1 = SrcReg;
2903   if (Register::isPhysicalRegister(SrcReg)) {
2904     SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0);
2905     SubIdx0 = 0;
2906     SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1);
2907     SubIdx1 = 0;
2908   }
2909   BuildMI(MBB, InsertBefore, DebugLoc(), MCID)
2910       .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0)
2911       .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1)
2912       .addFrameIndex(FI)
2913       .addImm(0)
2914       .addMemOperand(MMO);
2915 }
2916 
2917 void AArch64InstrInfo::storeRegToStackSlot(
2918     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
2919     bool isKill, int FI, const TargetRegisterClass *RC,
2920     const TargetRegisterInfo *TRI) const {
2921   MachineFunction &MF = *MBB.getParent();
2922   MachineFrameInfo &MFI = MF.getFrameInfo();
2923 
2924   MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
2925   MachineMemOperand *MMO =
2926       MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
2927                               MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
2928   unsigned Opc = 0;
2929   bool Offset = true;
2930   switch (TRI->getSpillSize(*RC)) {
2931   case 1:
2932     if (AArch64::FPR8RegClass.hasSubClassEq(RC))
2933       Opc = AArch64::STRBui;
2934     break;
2935   case 2:
2936     if (AArch64::FPR16RegClass.hasSubClassEq(RC))
2937       Opc = AArch64::STRHui;
2938     break;
2939   case 4:
2940     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
2941       Opc = AArch64::STRWui;
2942       if (Register::isVirtualRegister(SrcReg))
2943         MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
2944       else
2945         assert(SrcReg != AArch64::WSP);
2946     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
2947       Opc = AArch64::STRSui;
2948     break;
2949   case 8:
2950     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
2951       Opc = AArch64::STRXui;
2952       if (Register::isVirtualRegister(SrcReg))
2953         MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
2954       else
2955         assert(SrcReg != AArch64::SP);
2956     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {
2957       Opc = AArch64::STRDui;
2958     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {
2959       storeRegPairToStackSlot(getRegisterInfo(), MBB, MBBI,
2960                               get(AArch64::STPWi), SrcReg, isKill,
2961                               AArch64::sube32, AArch64::subo32, FI, MMO);
2962       return;
2963     }
2964     break;
2965   case 16:
2966     if (AArch64::FPR128RegClass.hasSubClassEq(RC))
2967       Opc = AArch64::STRQui;
2968     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
2969       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
2970       Opc = AArch64::ST1Twov1d;
2971       Offset = false;
2972     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
2973       storeRegPairToStackSlot(getRegisterInfo(), MBB, MBBI,
2974                               get(AArch64::STPXi), SrcReg, isKill,
2975                               AArch64::sube64, AArch64::subo64, FI, MMO);
2976       return;
2977     }
2978     break;
2979   case 24:
2980     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
2981       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
2982       Opc = AArch64::ST1Threev1d;
2983       Offset = false;
2984     }
2985     break;
2986   case 32:
2987     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
2988       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
2989       Opc = AArch64::ST1Fourv1d;
2990       Offset = false;
2991     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
2992       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
2993       Opc = AArch64::ST1Twov2d;
2994       Offset = false;
2995     }
2996     break;
2997   case 48:
2998     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
2999       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
3000       Opc = AArch64::ST1Threev2d;
3001       Offset = false;
3002     }
3003     break;
3004   case 64:
3005     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
3006       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
3007       Opc = AArch64::ST1Fourv2d;
3008       Offset = false;
3009     }
3010     break;
3011   }
3012   unsigned StackID = TargetStackID::Default;
3013   if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
3014     assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
3015     Opc = AArch64::STR_PXI;
3016     StackID = TargetStackID::SVEVector;
3017   } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
3018     assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
3019     Opc = AArch64::STR_ZXI;
3020     StackID = TargetStackID::SVEVector;
3021   }
3022   assert(Opc && "Unknown register class");
3023   MFI.setStackID(FI, StackID);
3024 
3025   const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
3026                                      .addReg(SrcReg, getKillRegState(isKill))
3027                                      .addFrameIndex(FI);
3028 
3029   if (Offset)
3030     MI.addImm(0);
3031   MI.addMemOperand(MMO);
3032 }
3033 
3034 static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
3035                                      MachineBasicBlock &MBB,
3036                                      MachineBasicBlock::iterator InsertBefore,
3037                                      const MCInstrDesc &MCID,
3038                                      Register DestReg, unsigned SubIdx0,
3039                                      unsigned SubIdx1, int FI,
3040                                      MachineMemOperand *MMO) {
3041   Register DestReg0 = DestReg;
3042   Register DestReg1 = DestReg;
3043   bool IsUndef = true;
3044   if (Register::isPhysicalRegister(DestReg)) {
3045     DestReg0 = TRI.getSubReg(DestReg, SubIdx0);
3046     SubIdx0 = 0;
3047     DestReg1 = TRI.getSubReg(DestReg, SubIdx1);
3048     SubIdx1 = 0;
3049     IsUndef = false;
3050   }
3051   BuildMI(MBB, InsertBefore, DebugLoc(), MCID)
3052       .addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0)
3053       .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1)
3054       .addFrameIndex(FI)
3055       .addImm(0)
3056       .addMemOperand(MMO);
3057 }
3058 
3059 void AArch64InstrInfo::loadRegFromStackSlot(
3060     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
3061     int FI, const TargetRegisterClass *RC,
3062     const TargetRegisterInfo *TRI) const {
3063   MachineFunction &MF = *MBB.getParent();
3064   MachineFrameInfo &MFI = MF.getFrameInfo();
3065   MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
3066   MachineMemOperand *MMO =
3067       MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
3068                               MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
3069 
3070   unsigned Opc = 0;
3071   bool Offset = true;
3072   switch (TRI->getSpillSize(*RC)) {
3073   case 1:
3074     if (AArch64::FPR8RegClass.hasSubClassEq(RC))
3075       Opc = AArch64::LDRBui;
3076     break;
3077   case 2:
3078     if (AArch64::FPR16RegClass.hasSubClassEq(RC))
3079       Opc = AArch64::LDRHui;
3080     break;
3081   case 4:
3082     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
3083       Opc = AArch64::LDRWui;
3084       if (Register::isVirtualRegister(DestReg))
3085         MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
3086       else
3087         assert(DestReg != AArch64::WSP);
3088     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
3089       Opc = AArch64::LDRSui;
3090     break;
3091   case 8:
3092     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
3093       Opc = AArch64::LDRXui;
3094       if (Register::isVirtualRegister(DestReg))
3095         MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
3096       else
3097         assert(DestReg != AArch64::SP);
3098     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {
3099       Opc = AArch64::LDRDui;
3100     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {
3101       loadRegPairFromStackSlot(getRegisterInfo(), MBB, MBBI,
3102                                get(AArch64::LDPWi), DestReg, AArch64::sube32,
3103                                AArch64::subo32, FI, MMO);
3104       return;
3105     }
3106     break;
3107   case 16:
3108     if (AArch64::FPR128RegClass.hasSubClassEq(RC))
3109       Opc = AArch64::LDRQui;
3110     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
3111       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
3112       Opc = AArch64::LD1Twov1d;
3113       Offset = false;
3114     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
3115       loadRegPairFromStackSlot(getRegisterInfo(), MBB, MBBI,
3116                                get(AArch64::LDPXi), DestReg, AArch64::sube64,
3117                                AArch64::subo64, FI, MMO);
3118       return;
3119     }
3120     break;
3121   case 24:
3122     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
3123       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
3124       Opc = AArch64::LD1Threev1d;
3125       Offset = false;
3126     }
3127     break;
3128   case 32:
3129     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
3130       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
3131       Opc = AArch64::LD1Fourv1d;
3132       Offset = false;
3133     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
3134       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
3135       Opc = AArch64::LD1Twov2d;
3136       Offset = false;
3137     }
3138     break;
3139   case 48:
3140     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
3141       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
3142       Opc = AArch64::LD1Threev2d;
3143       Offset = false;
3144     }
3145     break;
3146   case 64:
3147     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
3148       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
3149       Opc = AArch64::LD1Fourv2d;
3150       Offset = false;
3151     }
3152     break;
3153   }
3154 
3155   unsigned StackID = TargetStackID::Default;
3156   if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
3157     assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
3158     Opc = AArch64::LDR_PXI;
3159     StackID = TargetStackID::SVEVector;
3160   } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
3161     assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
3162     Opc = AArch64::LDR_ZXI;
3163     StackID = TargetStackID::SVEVector;
3164   }
3165   assert(Opc && "Unknown register class");
3166   MFI.setStackID(FI, StackID);
3167 
3168   const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
3169                                      .addReg(DestReg, getDefRegState(true))
3170                                      .addFrameIndex(FI);
3171   if (Offset)
3172     MI.addImm(0);
3173   MI.addMemOperand(MMO);
3174 }
3175 
3176 bool llvm::isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
3177                                            const MachineInstr &UseMI,
3178                                            const TargetRegisterInfo *TRI) {
3179   return any_of(instructionsWithoutDebug(std::next(DefMI.getIterator()),
3180                                          UseMI.getIterator()),
3181                 [TRI](const MachineInstr &I) {
3182                   return I.modifiesRegister(AArch64::NZCV, TRI) ||
3183                          I.readsRegister(AArch64::NZCV, TRI);
3184                 });
3185 }
3186 
3187 // Helper function to emit a frame offset adjustment from a given
3188 // pointer (SrcReg), stored into DestReg. This function is explicit
3189 // in that it requires the opcode.
3190 static void emitFrameOffsetAdj(MachineBasicBlock &MBB,
3191                                MachineBasicBlock::iterator MBBI,
3192                                const DebugLoc &DL, unsigned DestReg,
3193                                unsigned SrcReg, int64_t Offset, unsigned Opc,
3194                                const TargetInstrInfo *TII,
3195                                MachineInstr::MIFlag Flag, bool NeedsWinCFI,
3196                                bool *HasWinCFI) {
3197   int Sign = 1;
3198   unsigned MaxEncoding, ShiftSize;
3199   switch (Opc) {
3200   case AArch64::ADDXri:
3201   case AArch64::ADDSXri:
3202   case AArch64::SUBXri:
3203   case AArch64::SUBSXri:
3204     MaxEncoding = 0xfff;
3205     ShiftSize = 12;
3206     break;
3207   case AArch64::ADDVL_XXI:
3208   case AArch64::ADDPL_XXI:
3209     MaxEncoding = 31;
3210     ShiftSize = 0;
3211     if (Offset < 0) {
3212       MaxEncoding = 32;
3213       Sign = -1;
3214       Offset = -Offset;
3215     }
3216     break;
3217   default:
3218     llvm_unreachable("Unsupported opcode");
3219   }
3220 
3221   // FIXME: If the offset won't fit in 24-bits, compute the offset into a
3222   // scratch register.  If DestReg is a virtual register, use it as the
3223   // scratch register; otherwise, create a new virtual register (to be
3224   // replaced by the scavenger at the end of PEI).  That case can be optimized
3225   // slightly if DestReg is SP which is always 16-byte aligned, so the scratch
3226   // register can be loaded with offset%8 and the add/sub can use an extending
3227   // instruction with LSL#3.
3228   // Currently the function handles any offsets but generates a poor sequence
3229   // of code.
3230   //  assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
3231 
3232   const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
3233   do {
3234     uint64_t ThisVal = std::min<uint64_t>(Offset, MaxEncodableValue);
3235     unsigned LocalShiftSize = 0;
3236     if (ThisVal > MaxEncoding) {
3237       ThisVal = ThisVal >> ShiftSize;
3238       LocalShiftSize = ShiftSize;
3239     }
3240     assert((ThisVal >> ShiftSize) <= MaxEncoding &&
3241            "Encoding cannot handle value that big");
3242     auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
3243                    .addReg(SrcReg)
3244                    .addImm(Sign * (int)ThisVal);
3245     if (ShiftSize)
3246       MBI = MBI.addImm(
3247           AArch64_AM::getShifterImm(AArch64_AM::LSL, LocalShiftSize));
3248     MBI = MBI.setMIFlag(Flag);
3249 
3250     if (NeedsWinCFI) {
3251       assert(Sign == 1 && "SEH directives should always have a positive sign");
3252       int Imm = (int)(ThisVal << LocalShiftSize);
3253       if ((DestReg == AArch64::FP && SrcReg == AArch64::SP) ||
3254           (SrcReg == AArch64::FP && DestReg == AArch64::SP)) {
3255         if (HasWinCFI)
3256           *HasWinCFI = true;
3257         if (Imm == 0)
3258           BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_SetFP)).setMIFlag(Flag);
3259         else
3260           BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_AddFP))
3261               .addImm(Imm)
3262               .setMIFlag(Flag);
3263         assert((Offset - Imm) == 0 && "Expected remaining offset to be zero to "
3264                                       "emit a single SEH directive");
3265       } else if (DestReg == AArch64::SP) {
3266         if (HasWinCFI)
3267           *HasWinCFI = true;
3268         assert(SrcReg == AArch64::SP && "Unexpected SrcReg for SEH_StackAlloc");
3269         BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
3270             .addImm(Imm)
3271             .setMIFlag(Flag);
3272       }
3273       if (HasWinCFI)
3274         *HasWinCFI = true;
3275     }
3276 
3277     SrcReg = DestReg;
3278     Offset -= ThisVal << LocalShiftSize;
3279   } while (Offset);
3280 }
3281 
3282 void llvm::emitFrameOffset(MachineBasicBlock &MBB,
3283                            MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
3284                            unsigned DestReg, unsigned SrcReg,
3285                            StackOffset Offset, const TargetInstrInfo *TII,
3286                            MachineInstr::MIFlag Flag, bool SetNZCV,
3287                            bool NeedsWinCFI, bool *HasWinCFI) {
3288   int64_t Bytes, NumPredicateVectors, NumDataVectors;
3289   Offset.getForFrameOffset(Bytes, NumPredicateVectors, NumDataVectors);
3290 
3291   // First emit non-scalable frame offsets, or a simple 'mov'.
3292   if (Bytes || (!Offset && SrcReg != DestReg)) {
3293     assert((DestReg != AArch64::SP || Bytes % 16 == 0) &&
3294            "SP increment/decrement not 16-byte aligned");
3295     unsigned Opc = SetNZCV ? AArch64::ADDSXri : AArch64::ADDXri;
3296     if (Bytes < 0) {
3297       Bytes = -Bytes;
3298       Opc = SetNZCV ? AArch64::SUBSXri : AArch64::SUBXri;
3299     }
3300     emitFrameOffsetAdj(MBB, MBBI, DL, DestReg, SrcReg, Bytes, Opc, TII, Flag,
3301                        NeedsWinCFI, HasWinCFI);
3302     SrcReg = DestReg;
3303   }
3304 
3305   assert(!(SetNZCV && (NumPredicateVectors || NumDataVectors)) &&
3306          "SetNZCV not supported with SVE vectors");
3307   assert(!(NeedsWinCFI && (NumPredicateVectors || NumDataVectors)) &&
3308          "WinCFI not supported with SVE vectors");
3309 
3310   if (NumDataVectors) {
3311     emitFrameOffsetAdj(MBB, MBBI, DL, DestReg, SrcReg, NumDataVectors,
3312                        AArch64::ADDVL_XXI, TII, Flag, NeedsWinCFI, nullptr);
3313     SrcReg = DestReg;
3314   }
3315 
3316   if (NumPredicateVectors) {
3317     assert(DestReg != AArch64::SP && "Unaligned access to SP");
3318     emitFrameOffsetAdj(MBB, MBBI, DL, DestReg, SrcReg, NumPredicateVectors,
3319                        AArch64::ADDPL_XXI, TII, Flag, NeedsWinCFI, nullptr);
3320   }
3321 }
3322 
3323 MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
3324     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
3325     MachineBasicBlock::iterator InsertPt, int FrameIndex,
3326     LiveIntervals *LIS, VirtRegMap *VRM) const {
3327   // This is a bit of a hack. Consider this instruction:
3328   //
3329   //   %0 = COPY %sp; GPR64all:%0
3330   //
3331   // We explicitly chose GPR64all for the virtual register so such a copy might
3332   // be eliminated by RegisterCoalescer. However, that may not be possible, and
3333   // %0 may even spill. We can't spill %sp, and since it is in the GPR64all
3334   // register class, TargetInstrInfo::foldMemoryOperand() is going to try.
3335   //
3336   // To prevent that, we are going to constrain the %0 register class here.
3337   //
3338   // <rdar://problem/11522048>
3339   //
3340   if (MI.isFullCopy()) {
3341     Register DstReg = MI.getOperand(0).getReg();
3342     Register SrcReg = MI.getOperand(1).getReg();
3343     if (SrcReg == AArch64::SP && Register::isVirtualRegister(DstReg)) {
3344       MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
3345       return nullptr;
3346     }
3347     if (DstReg == AArch64::SP && Register::isVirtualRegister(SrcReg)) {
3348       MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
3349       return nullptr;
3350     }
3351   }
3352 
3353   // Handle the case where a copy is being spilled or filled but the source
3354   // and destination register class don't match.  For example:
3355   //
3356   //   %0 = COPY %xzr; GPR64common:%0
3357   //
3358   // In this case we can still safely fold away the COPY and generate the
3359   // following spill code:
3360   //
3361   //   STRXui %xzr, %stack.0
3362   //
3363   // This also eliminates spilled cross register class COPYs (e.g. between x and
3364   // d regs) of the same size.  For example:
3365   //
3366   //   %0 = COPY %1; GPR64:%0, FPR64:%1
3367   //
3368   // will be filled as
3369   //
3370   //   LDRDui %0, fi<#0>
3371   //
3372   // instead of
3373   //
3374   //   LDRXui %Temp, fi<#0>
3375   //   %0 = FMOV %Temp
3376   //
3377   if (MI.isCopy() && Ops.size() == 1 &&
3378       // Make sure we're only folding the explicit COPY defs/uses.
3379       (Ops[0] == 0 || Ops[0] == 1)) {
3380     bool IsSpill = Ops[0] == 0;
3381     bool IsFill = !IsSpill;
3382     const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3383     const MachineRegisterInfo &MRI = MF.getRegInfo();
3384     MachineBasicBlock &MBB = *MI.getParent();
3385     const MachineOperand &DstMO = MI.getOperand(0);
3386     const MachineOperand &SrcMO = MI.getOperand(1);
3387     Register DstReg = DstMO.getReg();
3388     Register SrcReg = SrcMO.getReg();
3389     // This is slightly expensive to compute for physical regs since
3390     // getMinimalPhysRegClass is slow.
3391     auto getRegClass = [&](unsigned Reg) {
3392       return Register::isVirtualRegister(Reg) ? MRI.getRegClass(Reg)
3393                                               : TRI.getMinimalPhysRegClass(Reg);
3394     };
3395 
3396     if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) {
3397       assert(TRI.getRegSizeInBits(*getRegClass(DstReg)) ==
3398                  TRI.getRegSizeInBits(*getRegClass(SrcReg)) &&
3399              "Mismatched register size in non subreg COPY");
3400       if (IsSpill)
3401         storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
3402                             getRegClass(SrcReg), &TRI);
3403       else
3404         loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex,
3405                              getRegClass(DstReg), &TRI);
3406       return &*--InsertPt;
3407     }
3408 
3409     // Handle cases like spilling def of:
3410     //
3411     //   %0:sub_32<def,read-undef> = COPY %wzr; GPR64common:%0
3412     //
3413     // where the physical register source can be widened and stored to the full
3414     // virtual reg destination stack slot, in this case producing:
3415     //
3416     //   STRXui %xzr, %stack.0
3417     //
3418     if (IsSpill && DstMO.isUndef() && Register::isPhysicalRegister(SrcReg)) {
3419       assert(SrcMO.getSubReg() == 0 &&
3420              "Unexpected subreg on physical register");
3421       const TargetRegisterClass *SpillRC;
3422       unsigned SpillSubreg;
3423       switch (DstMO.getSubReg()) {
3424       default:
3425         SpillRC = nullptr;
3426         break;
3427       case AArch64::sub_32:
3428       case AArch64::ssub:
3429         if (AArch64::GPR32RegClass.contains(SrcReg)) {
3430           SpillRC = &AArch64::GPR64RegClass;
3431           SpillSubreg = AArch64::sub_32;
3432         } else if (AArch64::FPR32RegClass.contains(SrcReg)) {
3433           SpillRC = &AArch64::FPR64RegClass;
3434           SpillSubreg = AArch64::ssub;
3435         } else
3436           SpillRC = nullptr;
3437         break;
3438       case AArch64::dsub:
3439         if (AArch64::FPR64RegClass.contains(SrcReg)) {
3440           SpillRC = &AArch64::FPR128RegClass;
3441           SpillSubreg = AArch64::dsub;
3442         } else
3443           SpillRC = nullptr;
3444         break;
3445       }
3446 
3447       if (SpillRC)
3448         if (unsigned WidenedSrcReg =
3449                 TRI.getMatchingSuperReg(SrcReg, SpillSubreg, SpillRC)) {
3450           storeRegToStackSlot(MBB, InsertPt, WidenedSrcReg, SrcMO.isKill(),
3451                               FrameIndex, SpillRC, &TRI);
3452           return &*--InsertPt;
3453         }
3454     }
3455 
3456     // Handle cases like filling use of:
3457     //
3458     //   %0:sub_32<def,read-undef> = COPY %1; GPR64:%0, GPR32:%1
3459     //
3460     // where we can load the full virtual reg source stack slot, into the subreg
3461     // destination, in this case producing:
3462     //
3463     //   LDRWui %0:sub_32<def,read-undef>, %stack.0
3464     //
3465     if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
3466       const TargetRegisterClass *FillRC;
3467       switch (DstMO.getSubReg()) {
3468       default:
3469         FillRC = nullptr;
3470         break;
3471       case AArch64::sub_32:
3472         FillRC = &AArch64::GPR32RegClass;
3473         break;
3474       case AArch64::ssub:
3475         FillRC = &AArch64::FPR32RegClass;
3476         break;
3477       case AArch64::dsub:
3478         FillRC = &AArch64::FPR64RegClass;
3479         break;
3480       }
3481 
3482       if (FillRC) {
3483         assert(TRI.getRegSizeInBits(*getRegClass(SrcReg)) ==
3484                    TRI.getRegSizeInBits(*FillRC) &&
3485                "Mismatched regclass size on folded subreg COPY");
3486         loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC, &TRI);
3487         MachineInstr &LoadMI = *--InsertPt;
3488         MachineOperand &LoadDst = LoadMI.getOperand(0);
3489         assert(LoadDst.getSubReg() == 0 && "unexpected subreg on fill load");
3490         LoadDst.setSubReg(DstMO.getSubReg());
3491         LoadDst.setIsUndef();
3492         return &LoadMI;
3493       }
3494     }
3495   }
3496 
3497   // Cannot fold.
3498   return nullptr;
3499 }
3500 
3501 int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI,
3502                                     StackOffset &SOffset,
3503                                     bool *OutUseUnscaledOp,
3504                                     unsigned *OutUnscaledOp,
3505                                     int64_t *EmittableOffset) {
3506   // Set output values in case of early exit.
3507   if (EmittableOffset)
3508     *EmittableOffset = 0;
3509   if (OutUseUnscaledOp)
3510     *OutUseUnscaledOp = false;
3511   if (OutUnscaledOp)
3512     *OutUnscaledOp = 0;
3513 
3514   // Exit early for structured vector spills/fills as they can't take an
3515   // immediate offset.
3516   switch (MI.getOpcode()) {
3517   default:
3518     break;
3519   case AArch64::LD1Twov2d:
3520   case AArch64::LD1Threev2d:
3521   case AArch64::LD1Fourv2d:
3522   case AArch64::LD1Twov1d:
3523   case AArch64::LD1Threev1d:
3524   case AArch64::LD1Fourv1d:
3525   case AArch64::ST1Twov2d:
3526   case AArch64::ST1Threev2d:
3527   case AArch64::ST1Fourv2d:
3528   case AArch64::ST1Twov1d:
3529   case AArch64::ST1Threev1d:
3530   case AArch64::ST1Fourv1d:
3531   case AArch64::IRG:
3532   case AArch64::IRGstack:
3533   case AArch64::STGloop:
3534   case AArch64::STZGloop:
3535     return AArch64FrameOffsetCannotUpdate;
3536   }
3537 
3538   // Get the min/max offset and the scale.
3539   TypeSize ScaleValue(0U, false);
3540   unsigned Width;
3541   int64_t MinOff, MaxOff;
3542   if (!AArch64InstrInfo::getMemOpInfo(MI.getOpcode(), ScaleValue, Width, MinOff,
3543                                       MaxOff))
3544     llvm_unreachable("unhandled opcode in isAArch64FrameOffsetLegal");
3545 
3546   // Construct the complete offset.
3547   bool IsMulVL = ScaleValue.isScalable();
3548   unsigned Scale = ScaleValue.getKnownMinSize();
3549   int64_t Offset = IsMulVL ? SOffset.getScalableBytes() : SOffset.getBytes();
3550 
3551   const MachineOperand &ImmOpnd =
3552       MI.getOperand(AArch64InstrInfo::getLoadStoreImmIdx(MI.getOpcode()));
3553   Offset += ImmOpnd.getImm() * Scale;
3554 
3555   // If the offset doesn't match the scale, we rewrite the instruction to
3556   // use the unscaled instruction instead. Likewise, if we have a negative
3557   // offset and there is an unscaled op to use.
3558   Optional<unsigned> UnscaledOp =
3559       AArch64InstrInfo::getUnscaledLdSt(MI.getOpcode());
3560   bool useUnscaledOp = UnscaledOp && (Offset % Scale || Offset < 0);
3561   if (useUnscaledOp &&
3562       !AArch64InstrInfo::getMemOpInfo(*UnscaledOp, ScaleValue, Width, MinOff,
3563                                       MaxOff))
3564     llvm_unreachable("unhandled opcode in isAArch64FrameOffsetLegal");
3565 
3566   Scale = ScaleValue.getKnownMinSize();
3567   assert(IsMulVL == ScaleValue.isScalable() &&
3568          "Unscaled opcode has different value for scalable");
3569 
3570   int64_t Remainder = Offset % Scale;
3571   assert(!(Remainder && useUnscaledOp) &&
3572          "Cannot have remainder when using unscaled op");
3573 
3574   assert(MinOff < MaxOff && "Unexpected Min/Max offsets");
3575   int64_t NewOffset = Offset / Scale;
3576   if (MinOff <= NewOffset && NewOffset <= MaxOff)
3577     Offset = Remainder;
3578   else {
3579     NewOffset = NewOffset < 0 ? MinOff : MaxOff;
3580     Offset = Offset - NewOffset * Scale + Remainder;
3581   }
3582 
3583   if (EmittableOffset)
3584     *EmittableOffset = NewOffset;
3585   if (OutUseUnscaledOp)
3586     *OutUseUnscaledOp = useUnscaledOp;
3587   if (OutUnscaledOp && UnscaledOp)
3588     *OutUnscaledOp = *UnscaledOp;
3589 
3590   if (IsMulVL)
3591     SOffset = StackOffset(Offset, MVT::nxv1i8) +
3592               StackOffset(SOffset.getBytes(), MVT::i8);
3593   else
3594     SOffset = StackOffset(Offset, MVT::i8) +
3595               StackOffset(SOffset.getScalableBytes(), MVT::nxv1i8);
3596   return AArch64FrameOffsetCanUpdate |
3597          (SOffset ? 0 : AArch64FrameOffsetIsLegal);
3598 }
3599 
3600 bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
3601                                     unsigned FrameReg, StackOffset &Offset,
3602                                     const AArch64InstrInfo *TII) {
3603   unsigned Opcode = MI.getOpcode();
3604   unsigned ImmIdx = FrameRegIdx + 1;
3605 
3606   if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) {
3607     Offset += StackOffset(MI.getOperand(ImmIdx).getImm(), MVT::i8);
3608     emitFrameOffset(*MI.getParent(), MI, MI.getDebugLoc(),
3609                     MI.getOperand(0).getReg(), FrameReg, Offset, TII,
3610                     MachineInstr::NoFlags, (Opcode == AArch64::ADDSXri));
3611     MI.eraseFromParent();
3612     Offset = StackOffset();
3613     return true;
3614   }
3615 
3616   int64_t NewOffset;
3617   unsigned UnscaledOp;
3618   bool UseUnscaledOp;
3619   int Status = isAArch64FrameOffsetLegal(MI, Offset, &UseUnscaledOp,
3620                                          &UnscaledOp, &NewOffset);
3621   if (Status & AArch64FrameOffsetCanUpdate) {
3622     if (Status & AArch64FrameOffsetIsLegal)
3623       // Replace the FrameIndex with FrameReg.
3624       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
3625     if (UseUnscaledOp)
3626       MI.setDesc(TII->get(UnscaledOp));
3627 
3628     MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset);
3629     return !Offset;
3630   }
3631 
3632   return false;
3633 }
3634 
3635 void AArch64InstrInfo::getNoop(MCInst &NopInst) const {
3636   NopInst.setOpcode(AArch64::HINT);
3637   NopInst.addOperand(MCOperand::createImm(0));
3638 }
3639 
3640 // AArch64 supports MachineCombiner.
3641 bool AArch64InstrInfo::useMachineCombiner() const { return true; }
3642 
3643 // True when Opc sets flag
3644 static bool isCombineInstrSettingFlag(unsigned Opc) {
3645   switch (Opc) {
3646   case AArch64::ADDSWrr:
3647   case AArch64::ADDSWri:
3648   case AArch64::ADDSXrr:
3649   case AArch64::ADDSXri:
3650   case AArch64::SUBSWrr:
3651   case AArch64::SUBSXrr:
3652   // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
3653   case AArch64::SUBSWri:
3654   case AArch64::SUBSXri:
3655     return true;
3656   default:
3657     break;
3658   }
3659   return false;
3660 }
3661 
3662 // 32b Opcodes that can be combined with a MUL
3663 static bool isCombineInstrCandidate32(unsigned Opc) {
3664   switch (Opc) {
3665   case AArch64::ADDWrr:
3666   case AArch64::ADDWri:
3667   case AArch64::SUBWrr:
3668   case AArch64::ADDSWrr:
3669   case AArch64::ADDSWri:
3670   case AArch64::SUBSWrr:
3671   // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
3672   case AArch64::SUBWri:
3673   case AArch64::SUBSWri:
3674     return true;
3675   default:
3676     break;
3677   }
3678   return false;
3679 }
3680 
3681 // 64b Opcodes that can be combined with a MUL
3682 static bool isCombineInstrCandidate64(unsigned Opc) {
3683   switch (Opc) {
3684   case AArch64::ADDXrr:
3685   case AArch64::ADDXri:
3686   case AArch64::SUBXrr:
3687   case AArch64::ADDSXrr:
3688   case AArch64::ADDSXri:
3689   case AArch64::SUBSXrr:
3690   // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi.
3691   case AArch64::SUBXri:
3692   case AArch64::SUBSXri:
3693   case AArch64::ADDv8i8:
3694   case AArch64::ADDv16i8:
3695   case AArch64::ADDv4i16:
3696   case AArch64::ADDv8i16:
3697   case AArch64::ADDv2i32:
3698   case AArch64::ADDv4i32:
3699   case AArch64::SUBv8i8:
3700   case AArch64::SUBv16i8:
3701   case AArch64::SUBv4i16:
3702   case AArch64::SUBv8i16:
3703   case AArch64::SUBv2i32:
3704   case AArch64::SUBv4i32:
3705     return true;
3706   default:
3707     break;
3708   }
3709   return false;
3710 }
3711 
3712 // FP Opcodes that can be combined with a FMUL
3713 static bool isCombineInstrCandidateFP(const MachineInstr &Inst) {
3714   switch (Inst.getOpcode()) {
3715   default:
3716     break;
3717   case AArch64::FADDHrr:
3718   case AArch64::FADDSrr:
3719   case AArch64::FADDDrr:
3720   case AArch64::FADDv4f16:
3721   case AArch64::FADDv8f16:
3722   case AArch64::FADDv2f32:
3723   case AArch64::FADDv2f64:
3724   case AArch64::FADDv4f32:
3725   case AArch64::FSUBHrr:
3726   case AArch64::FSUBSrr:
3727   case AArch64::FSUBDrr:
3728   case AArch64::FSUBv4f16:
3729   case AArch64::FSUBv8f16:
3730   case AArch64::FSUBv2f32:
3731   case AArch64::FSUBv2f64:
3732   case AArch64::FSUBv4f32:
3733     TargetOptions Options = Inst.getParent()->getParent()->getTarget().Options;
3734     return (Options.UnsafeFPMath ||
3735             Options.AllowFPOpFusion == FPOpFusion::Fast);
3736   }
3737   return false;
3738 }
3739 
3740 // Opcodes that can be combined with a MUL
3741 static bool isCombineInstrCandidate(unsigned Opc) {
3742   return (isCombineInstrCandidate32(Opc) || isCombineInstrCandidate64(Opc));
3743 }
3744 
3745 //
3746 // Utility routine that checks if \param MO is defined by an
3747 // \param CombineOpc instruction in the basic block \param MBB
3748 static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO,
3749                        unsigned CombineOpc, unsigned ZeroReg = 0,
3750                        bool CheckZeroReg = false) {
3751   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3752   MachineInstr *MI = nullptr;
3753 
3754   if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
3755     MI = MRI.getUniqueVRegDef(MO.getReg());
3756   // And it needs to be in the trace (otherwise, it won't have a depth).
3757   if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc)
3758     return false;
3759   // Must only used by the user we combine with.
3760   if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
3761     return false;
3762 
3763   if (CheckZeroReg) {
3764     assert(MI->getNumOperands() >= 4 && MI->getOperand(0).isReg() &&
3765            MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
3766            MI->getOperand(3).isReg() && "MAdd/MSub must have a least 4 regs");
3767     // The third input reg must be zero.
3768     if (MI->getOperand(3).getReg() != ZeroReg)
3769       return false;
3770   }
3771 
3772   return true;
3773 }
3774 
3775 //
3776 // Is \param MO defined by an integer multiply and can be combined?
3777 static bool canCombineWithMUL(MachineBasicBlock &MBB, MachineOperand &MO,
3778                               unsigned MulOpc, unsigned ZeroReg) {
3779   return canCombine(MBB, MO, MulOpc, ZeroReg, true);
3780 }
3781 
3782 //
3783 // Is \param MO defined by a floating-point multiply and can be combined?
3784 static bool canCombineWithFMUL(MachineBasicBlock &MBB, MachineOperand &MO,
3785                                unsigned MulOpc) {
3786   return canCombine(MBB, MO, MulOpc);
3787 }
3788 
3789 // TODO: There are many more machine instruction opcodes to match:
3790 //       1. Other data types (integer, vectors)
3791 //       2. Other math / logic operations (xor, or)
3792 //       3. Other forms of the same operation (intrinsics and other variants)
3793 bool AArch64InstrInfo::isAssociativeAndCommutative(
3794     const MachineInstr &Inst) const {
3795   switch (Inst.getOpcode()) {
3796   case AArch64::FADDDrr:
3797   case AArch64::FADDSrr:
3798   case AArch64::FADDv2f32:
3799   case AArch64::FADDv2f64:
3800   case AArch64::FADDv4f32:
3801   case AArch64::FMULDrr:
3802   case AArch64::FMULSrr:
3803   case AArch64::FMULX32:
3804   case AArch64::FMULX64:
3805   case AArch64::FMULXv2f32:
3806   case AArch64::FMULXv2f64:
3807   case AArch64::FMULXv4f32:
3808   case AArch64::FMULv2f32:
3809   case AArch64::FMULv2f64:
3810   case AArch64::FMULv4f32:
3811     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
3812   default:
3813     return false;
3814   }
3815 }
3816 
3817 /// Find instructions that can be turned into madd.
3818 static bool getMaddPatterns(MachineInstr &Root,
3819                             SmallVectorImpl<MachineCombinerPattern> &Patterns) {
3820   unsigned Opc = Root.getOpcode();
3821   MachineBasicBlock &MBB = *Root.getParent();
3822   bool Found = false;
3823 
3824   if (!isCombineInstrCandidate(Opc))
3825     return false;
3826   if (isCombineInstrSettingFlag(Opc)) {
3827     int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true);
3828     // When NZCV is live bail out.
3829     if (Cmp_NZCV == -1)
3830       return false;
3831     unsigned NewOpc = convertToNonFlagSettingOpc(Root);
3832     // When opcode can't change bail out.
3833     // CHECKME: do we miss any cases for opcode conversion?
3834     if (NewOpc == Opc)
3835       return false;
3836     Opc = NewOpc;
3837   }
3838 
3839   auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg,
3840                       MachineCombinerPattern Pattern) {
3841     if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
3842       Patterns.push_back(Pattern);
3843       Found = true;
3844     }
3845   };
3846 
3847   auto setVFound = [&](int Opcode, int Operand, MachineCombinerPattern Pattern) {
3848     if (canCombine(MBB, Root.getOperand(Operand), Opcode)) {
3849       Patterns.push_back(Pattern);
3850       Found = true;
3851     }
3852   };
3853 
3854   typedef MachineCombinerPattern MCP;
3855 
3856   switch (Opc) {
3857   default:
3858     break;
3859   case AArch64::ADDWrr:
3860     assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3861            "ADDWrr does not have register operands");
3862     setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULADDW_OP1);
3863     setFound(AArch64::MADDWrrr, 2, AArch64::WZR, MCP::MULADDW_OP2);
3864     break;
3865   case AArch64::ADDXrr:
3866     setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULADDX_OP1);
3867     setFound(AArch64::MADDXrrr, 2, AArch64::XZR, MCP::MULADDX_OP2);
3868     break;
3869   case AArch64::SUBWrr:
3870     setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULSUBW_OP1);
3871     setFound(AArch64::MADDWrrr, 2, AArch64::WZR, MCP::MULSUBW_OP2);
3872     break;
3873   case AArch64::SUBXrr:
3874     setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULSUBX_OP1);
3875     setFound(AArch64::MADDXrrr, 2, AArch64::XZR, MCP::MULSUBX_OP2);
3876     break;
3877   case AArch64::ADDWri:
3878     setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULADDWI_OP1);
3879     break;
3880   case AArch64::ADDXri:
3881     setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULADDXI_OP1);
3882     break;
3883   case AArch64::SUBWri:
3884     setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULSUBWI_OP1);
3885     break;
3886   case AArch64::SUBXri:
3887     setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULSUBXI_OP1);
3888     break;
3889   case AArch64::ADDv8i8:
3890     setVFound(AArch64::MULv8i8, 1, MCP::MULADDv8i8_OP1);
3891     setVFound(AArch64::MULv8i8, 2, MCP::MULADDv8i8_OP2);
3892     break;
3893   case AArch64::ADDv16i8:
3894     setVFound(AArch64::MULv16i8, 1, MCP::MULADDv16i8_OP1);
3895     setVFound(AArch64::MULv16i8, 2, MCP::MULADDv16i8_OP2);
3896     break;
3897   case AArch64::ADDv4i16:
3898     setVFound(AArch64::MULv4i16, 1, MCP::MULADDv4i16_OP1);
3899     setVFound(AArch64::MULv4i16, 2, MCP::MULADDv4i16_OP2);
3900     setVFound(AArch64::MULv4i16_indexed, 1, MCP::MULADDv4i16_indexed_OP1);
3901     setVFound(AArch64::MULv4i16_indexed, 2, MCP::MULADDv4i16_indexed_OP2);
3902     break;
3903   case AArch64::ADDv8i16:
3904     setVFound(AArch64::MULv8i16, 1, MCP::MULADDv8i16_OP1);
3905     setVFound(AArch64::MULv8i16, 2, MCP::MULADDv8i16_OP2);
3906     setVFound(AArch64::MULv8i16_indexed, 1, MCP::MULADDv8i16_indexed_OP1);
3907     setVFound(AArch64::MULv8i16_indexed, 2, MCP::MULADDv8i16_indexed_OP2);
3908     break;
3909   case AArch64::ADDv2i32:
3910     setVFound(AArch64::MULv2i32, 1, MCP::MULADDv2i32_OP1);
3911     setVFound(AArch64::MULv2i32, 2, MCP::MULADDv2i32_OP2);
3912     setVFound(AArch64::MULv2i32_indexed, 1, MCP::MULADDv2i32_indexed_OP1);
3913     setVFound(AArch64::MULv2i32_indexed, 2, MCP::MULADDv2i32_indexed_OP2);
3914     break;
3915   case AArch64::ADDv4i32:
3916     setVFound(AArch64::MULv4i32, 1, MCP::MULADDv4i32_OP1);
3917     setVFound(AArch64::MULv4i32, 2, MCP::MULADDv4i32_OP2);
3918     setVFound(AArch64::MULv4i32_indexed, 1, MCP::MULADDv4i32_indexed_OP1);
3919     setVFound(AArch64::MULv4i32_indexed, 2, MCP::MULADDv4i32_indexed_OP2);
3920     break;
3921   case AArch64::SUBv8i8:
3922     setVFound(AArch64::MULv8i8, 1, MCP::MULSUBv8i8_OP1);
3923     setVFound(AArch64::MULv8i8, 2, MCP::MULSUBv8i8_OP2);
3924     break;
3925   case AArch64::SUBv16i8:
3926     setVFound(AArch64::MULv16i8, 1, MCP::MULSUBv16i8_OP1);
3927     setVFound(AArch64::MULv16i8, 2, MCP::MULSUBv16i8_OP2);
3928     break;
3929   case AArch64::SUBv4i16:
3930     setVFound(AArch64::MULv4i16, 1, MCP::MULSUBv4i16_OP1);
3931     setVFound(AArch64::MULv4i16, 2, MCP::MULSUBv4i16_OP2);
3932     setVFound(AArch64::MULv4i16_indexed, 1, MCP::MULSUBv4i16_indexed_OP1);
3933     setVFound(AArch64::MULv4i16_indexed, 2, MCP::MULSUBv4i16_indexed_OP2);
3934     break;
3935   case AArch64::SUBv8i16:
3936     setVFound(AArch64::MULv8i16, 1, MCP::MULSUBv8i16_OP1);
3937     setVFound(AArch64::MULv8i16, 2, MCP::MULSUBv8i16_OP2);
3938     setVFound(AArch64::MULv8i16_indexed, 1, MCP::MULSUBv8i16_indexed_OP1);
3939     setVFound(AArch64::MULv8i16_indexed, 2, MCP::MULSUBv8i16_indexed_OP2);
3940     break;
3941   case AArch64::SUBv2i32:
3942     setVFound(AArch64::MULv2i32, 1, MCP::MULSUBv2i32_OP1);
3943     setVFound(AArch64::MULv2i32, 2, MCP::MULSUBv2i32_OP2);
3944     setVFound(AArch64::MULv2i32_indexed, 1, MCP::MULSUBv2i32_indexed_OP1);
3945     setVFound(AArch64::MULv2i32_indexed, 2, MCP::MULSUBv2i32_indexed_OP2);
3946     break;
3947   case AArch64::SUBv4i32:
3948     setVFound(AArch64::MULv4i32, 1, MCP::MULSUBv4i32_OP1);
3949     setVFound(AArch64::MULv4i32, 2, MCP::MULSUBv4i32_OP2);
3950     setVFound(AArch64::MULv4i32_indexed, 1, MCP::MULSUBv4i32_indexed_OP1);
3951     setVFound(AArch64::MULv4i32_indexed, 2, MCP::MULSUBv4i32_indexed_OP2);
3952     break;
3953   }
3954   return Found;
3955 }
3956 /// Floating-Point Support
3957 
3958 /// Find instructions that can be turned into madd.
3959 static bool getFMAPatterns(MachineInstr &Root,
3960                            SmallVectorImpl<MachineCombinerPattern> &Patterns) {
3961 
3962   if (!isCombineInstrCandidateFP(Root))
3963     return false;
3964 
3965   MachineBasicBlock &MBB = *Root.getParent();
3966   bool Found = false;
3967 
3968   auto Match = [&](int Opcode, int Operand,
3969                    MachineCombinerPattern Pattern) -> bool {
3970     if (canCombineWithFMUL(MBB, Root.getOperand(Operand), Opcode)) {
3971       Patterns.push_back(Pattern);
3972       return true;
3973     }
3974     return false;
3975   };
3976 
3977   typedef MachineCombinerPattern MCP;
3978 
3979   switch (Root.getOpcode()) {
3980   default:
3981     assert(false && "Unsupported FP instruction in combiner\n");
3982     break;
3983   case AArch64::FADDHrr:
3984     assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3985            "FADDHrr does not have register operands");
3986 
3987     Found  = Match(AArch64::FMULHrr, 1, MCP::FMULADDH_OP1);
3988     Found |= Match(AArch64::FMULHrr, 2, MCP::FMULADDH_OP2);
3989     break;
3990   case AArch64::FADDSrr:
3991     assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3992            "FADDSrr does not have register operands");
3993 
3994     Found |= Match(AArch64::FMULSrr, 1, MCP::FMULADDS_OP1) ||
3995              Match(AArch64::FMULv1i32_indexed, 1, MCP::FMLAv1i32_indexed_OP1);
3996 
3997     Found |= Match(AArch64::FMULSrr, 2, MCP::FMULADDS_OP2) ||
3998              Match(AArch64::FMULv1i32_indexed, 2, MCP::FMLAv1i32_indexed_OP2);
3999     break;
4000   case AArch64::FADDDrr:
4001     Found |= Match(AArch64::FMULDrr, 1, MCP::FMULADDD_OP1) ||
4002              Match(AArch64::FMULv1i64_indexed, 1, MCP::FMLAv1i64_indexed_OP1);
4003 
4004     Found |= Match(AArch64::FMULDrr, 2, MCP::FMULADDD_OP2) ||
4005              Match(AArch64::FMULv1i64_indexed, 2, MCP::FMLAv1i64_indexed_OP2);
4006     break;
4007   case AArch64::FADDv4f16:
4008     Found |= Match(AArch64::FMULv4i16_indexed, 1, MCP::FMLAv4i16_indexed_OP1) ||
4009              Match(AArch64::FMULv4f16, 1, MCP::FMLAv4f16_OP1);
4010 
4011     Found |= Match(AArch64::FMULv4i16_indexed, 2, MCP::FMLAv4i16_indexed_OP2) ||
4012              Match(AArch64::FMULv4f16, 2, MCP::FMLAv4f16_OP2);
4013     break;
4014   case AArch64::FADDv8f16:
4015     Found |= Match(AArch64::FMULv8i16_indexed, 1, MCP::FMLAv8i16_indexed_OP1) ||
4016              Match(AArch64::FMULv8f16, 1, MCP::FMLAv8f16_OP1);
4017 
4018     Found |= Match(AArch64::FMULv8i16_indexed, 2, MCP::FMLAv8i16_indexed_OP2) ||
4019              Match(AArch64::FMULv8f16, 2, MCP::FMLAv8f16_OP2);
4020     break;
4021   case AArch64::FADDv2f32:
4022     Found |= Match(AArch64::FMULv2i32_indexed, 1, MCP::FMLAv2i32_indexed_OP1) ||
4023              Match(AArch64::FMULv2f32, 1, MCP::FMLAv2f32_OP1);
4024 
4025     Found |= Match(AArch64::FMULv2i32_indexed, 2, MCP::FMLAv2i32_indexed_OP2) ||
4026              Match(AArch64::FMULv2f32, 2, MCP::FMLAv2f32_OP2);
4027     break;
4028   case AArch64::FADDv2f64:
4029     Found |= Match(AArch64::FMULv2i64_indexed, 1, MCP::FMLAv2i64_indexed_OP1) ||
4030              Match(AArch64::FMULv2f64, 1, MCP::FMLAv2f64_OP1);
4031 
4032     Found |= Match(AArch64::FMULv2i64_indexed, 2, MCP::FMLAv2i64_indexed_OP2) ||
4033              Match(AArch64::FMULv2f64, 2, MCP::FMLAv2f64_OP2);
4034     break;
4035   case AArch64::FADDv4f32:
4036     Found |= Match(AArch64::FMULv4i32_indexed, 1, MCP::FMLAv4i32_indexed_OP1) ||
4037              Match(AArch64::FMULv4f32, 1, MCP::FMLAv4f32_OP1);
4038 
4039     Found |= Match(AArch64::FMULv4i32_indexed, 2, MCP::FMLAv4i32_indexed_OP2) ||
4040              Match(AArch64::FMULv4f32, 2, MCP::FMLAv4f32_OP2);
4041     break;
4042   case AArch64::FSUBHrr:
4043     Found  = Match(AArch64::FMULHrr, 1, MCP::FMULSUBH_OP1);
4044     Found |= Match(AArch64::FMULHrr, 2, MCP::FMULSUBH_OP2);
4045     Found |= Match(AArch64::FNMULHrr, 1, MCP::FNMULSUBH_OP1);
4046     break;
4047   case AArch64::FSUBSrr:
4048     Found = Match(AArch64::FMULSrr, 1, MCP::FMULSUBS_OP1);
4049 
4050     Found |= Match(AArch64::FMULSrr, 2, MCP::FMULSUBS_OP2) ||
4051              Match(AArch64::FMULv1i32_indexed, 2, MCP::FMLSv1i32_indexed_OP2);
4052 
4053     Found |= Match(AArch64::FNMULSrr, 1, MCP::FNMULSUBS_OP1);
4054     break;
4055   case AArch64::FSUBDrr:
4056     Found = Match(AArch64::FMULDrr, 1, MCP::FMULSUBD_OP1);
4057 
4058     Found |= Match(AArch64::FMULDrr, 2, MCP::FMULSUBD_OP2) ||
4059              Match(AArch64::FMULv1i64_indexed, 2, MCP::FMLSv1i64_indexed_OP2);
4060 
4061     Found |= Match(AArch64::FNMULDrr, 1, MCP::FNMULSUBD_OP1);
4062     break;
4063   case AArch64::FSUBv4f16:
4064     Found |= Match(AArch64::FMULv4i16_indexed, 2, MCP::FMLSv4i16_indexed_OP2) ||
4065              Match(AArch64::FMULv4f16, 2, MCP::FMLSv4f16_OP2);
4066 
4067     Found |= Match(AArch64::FMULv4i16_indexed, 1, MCP::FMLSv4i16_indexed_OP1) ||
4068              Match(AArch64::FMULv4f16, 1, MCP::FMLSv4f16_OP1);
4069     break;
4070   case AArch64::FSUBv8f16:
4071     Found |= Match(AArch64::FMULv8i16_indexed, 2, MCP::FMLSv8i16_indexed_OP2) ||
4072              Match(AArch64::FMULv8f16, 2, MCP::FMLSv8f16_OP2);
4073 
4074     Found |= Match(AArch64::FMULv8i16_indexed, 1, MCP::FMLSv8i16_indexed_OP1) ||
4075              Match(AArch64::FMULv8f16, 1, MCP::FMLSv8f16_OP1);
4076     break;
4077   case AArch64::FSUBv2f32:
4078     Found |= Match(AArch64::FMULv2i32_indexed, 2, MCP::FMLSv2i32_indexed_OP2) ||
4079              Match(AArch64::FMULv2f32, 2, MCP::FMLSv2f32_OP2);
4080 
4081     Found |= Match(AArch64::FMULv2i32_indexed, 1, MCP::FMLSv2i32_indexed_OP1) ||
4082              Match(AArch64::FMULv2f32, 1, MCP::FMLSv2f32_OP1);
4083     break;
4084   case AArch64::FSUBv2f64:
4085     Found |= Match(AArch64::FMULv2i64_indexed, 2, MCP::FMLSv2i64_indexed_OP2) ||
4086              Match(AArch64::FMULv2f64, 2, MCP::FMLSv2f64_OP2);
4087 
4088     Found |= Match(AArch64::FMULv2i64_indexed, 1, MCP::FMLSv2i64_indexed_OP1) ||
4089              Match(AArch64::FMULv2f64, 1, MCP::FMLSv2f64_OP1);
4090     break;
4091   case AArch64::FSUBv4f32:
4092     Found |= Match(AArch64::FMULv4i32_indexed, 2, MCP::FMLSv4i32_indexed_OP2) ||
4093              Match(AArch64::FMULv4f32, 2, MCP::FMLSv4f32_OP2);
4094 
4095     Found |= Match(AArch64::FMULv4i32_indexed, 1, MCP::FMLSv4i32_indexed_OP1) ||
4096              Match(AArch64::FMULv4f32, 1, MCP::FMLSv4f32_OP1);
4097     break;
4098   }
4099   return Found;
4100 }
4101 
4102 /// Return true when a code sequence can improve throughput. It
4103 /// should be called only for instructions in loops.
4104 /// \param Pattern - combiner pattern
4105 bool AArch64InstrInfo::isThroughputPattern(
4106     MachineCombinerPattern Pattern) const {
4107   switch (Pattern) {
4108   default:
4109     break;
4110   case MachineCombinerPattern::FMULADDH_OP1:
4111   case MachineCombinerPattern::FMULADDH_OP2:
4112   case MachineCombinerPattern::FMULSUBH_OP1:
4113   case MachineCombinerPattern::FMULSUBH_OP2:
4114   case MachineCombinerPattern::FMULADDS_OP1:
4115   case MachineCombinerPattern::FMULADDS_OP2:
4116   case MachineCombinerPattern::FMULSUBS_OP1:
4117   case MachineCombinerPattern::FMULSUBS_OP2:
4118   case MachineCombinerPattern::FMULADDD_OP1:
4119   case MachineCombinerPattern::FMULADDD_OP2:
4120   case MachineCombinerPattern::FMULSUBD_OP1:
4121   case MachineCombinerPattern::FMULSUBD_OP2:
4122   case MachineCombinerPattern::FNMULSUBH_OP1:
4123   case MachineCombinerPattern::FNMULSUBS_OP1:
4124   case MachineCombinerPattern::FNMULSUBD_OP1:
4125   case MachineCombinerPattern::FMLAv4i16_indexed_OP1:
4126   case MachineCombinerPattern::FMLAv4i16_indexed_OP2:
4127   case MachineCombinerPattern::FMLAv8i16_indexed_OP1:
4128   case MachineCombinerPattern::FMLAv8i16_indexed_OP2:
4129   case MachineCombinerPattern::FMLAv1i32_indexed_OP1:
4130   case MachineCombinerPattern::FMLAv1i32_indexed_OP2:
4131   case MachineCombinerPattern::FMLAv1i64_indexed_OP1:
4132   case MachineCombinerPattern::FMLAv1i64_indexed_OP2:
4133   case MachineCombinerPattern::FMLAv4f16_OP2:
4134   case MachineCombinerPattern::FMLAv4f16_OP1:
4135   case MachineCombinerPattern::FMLAv8f16_OP1:
4136   case MachineCombinerPattern::FMLAv8f16_OP2:
4137   case MachineCombinerPattern::FMLAv2f32_OP2:
4138   case MachineCombinerPattern::FMLAv2f32_OP1:
4139   case MachineCombinerPattern::FMLAv2f64_OP1:
4140   case MachineCombinerPattern::FMLAv2f64_OP2:
4141   case MachineCombinerPattern::FMLAv2i32_indexed_OP1:
4142   case MachineCombinerPattern::FMLAv2i32_indexed_OP2:
4143   case MachineCombinerPattern::FMLAv2i64_indexed_OP1:
4144   case MachineCombinerPattern::FMLAv2i64_indexed_OP2:
4145   case MachineCombinerPattern::FMLAv4f32_OP1:
4146   case MachineCombinerPattern::FMLAv4f32_OP2:
4147   case MachineCombinerPattern::FMLAv4i32_indexed_OP1:
4148   case MachineCombinerPattern::FMLAv4i32_indexed_OP2:
4149   case MachineCombinerPattern::FMLSv4i16_indexed_OP1:
4150   case MachineCombinerPattern::FMLSv4i16_indexed_OP2:
4151   case MachineCombinerPattern::FMLSv8i16_indexed_OP1:
4152   case MachineCombinerPattern::FMLSv8i16_indexed_OP2:
4153   case MachineCombinerPattern::FMLSv1i32_indexed_OP2:
4154   case MachineCombinerPattern::FMLSv1i64_indexed_OP2:
4155   case MachineCombinerPattern::FMLSv2i32_indexed_OP2:
4156   case MachineCombinerPattern::FMLSv2i64_indexed_OP2:
4157   case MachineCombinerPattern::FMLSv4f16_OP1:
4158   case MachineCombinerPattern::FMLSv4f16_OP2:
4159   case MachineCombinerPattern::FMLSv8f16_OP1:
4160   case MachineCombinerPattern::FMLSv8f16_OP2:
4161   case MachineCombinerPattern::FMLSv2f32_OP2:
4162   case MachineCombinerPattern::FMLSv2f64_OP2:
4163   case MachineCombinerPattern::FMLSv4i32_indexed_OP2:
4164   case MachineCombinerPattern::FMLSv4f32_OP2:
4165   case MachineCombinerPattern::MULADDv8i8_OP1:
4166   case MachineCombinerPattern::MULADDv8i8_OP2:
4167   case MachineCombinerPattern::MULADDv16i8_OP1:
4168   case MachineCombinerPattern::MULADDv16i8_OP2:
4169   case MachineCombinerPattern::MULADDv4i16_OP1:
4170   case MachineCombinerPattern::MULADDv4i16_OP2:
4171   case MachineCombinerPattern::MULADDv8i16_OP1:
4172   case MachineCombinerPattern::MULADDv8i16_OP2:
4173   case MachineCombinerPattern::MULADDv2i32_OP1:
4174   case MachineCombinerPattern::MULADDv2i32_OP2:
4175   case MachineCombinerPattern::MULADDv4i32_OP1:
4176   case MachineCombinerPattern::MULADDv4i32_OP2:
4177   case MachineCombinerPattern::MULSUBv8i8_OP1:
4178   case MachineCombinerPattern::MULSUBv8i8_OP2:
4179   case MachineCombinerPattern::MULSUBv16i8_OP1:
4180   case MachineCombinerPattern::MULSUBv16i8_OP2:
4181   case MachineCombinerPattern::MULSUBv4i16_OP1:
4182   case MachineCombinerPattern::MULSUBv4i16_OP2:
4183   case MachineCombinerPattern::MULSUBv8i16_OP1:
4184   case MachineCombinerPattern::MULSUBv8i16_OP2:
4185   case MachineCombinerPattern::MULSUBv2i32_OP1:
4186   case MachineCombinerPattern::MULSUBv2i32_OP2:
4187   case MachineCombinerPattern::MULSUBv4i32_OP1:
4188   case MachineCombinerPattern::MULSUBv4i32_OP2:
4189   case MachineCombinerPattern::MULADDv4i16_indexed_OP1:
4190   case MachineCombinerPattern::MULADDv4i16_indexed_OP2:
4191   case MachineCombinerPattern::MULADDv8i16_indexed_OP1:
4192   case MachineCombinerPattern::MULADDv8i16_indexed_OP2:
4193   case MachineCombinerPattern::MULADDv2i32_indexed_OP1:
4194   case MachineCombinerPattern::MULADDv2i32_indexed_OP2:
4195   case MachineCombinerPattern::MULADDv4i32_indexed_OP1:
4196   case MachineCombinerPattern::MULADDv4i32_indexed_OP2:
4197   case MachineCombinerPattern::MULSUBv4i16_indexed_OP1:
4198   case MachineCombinerPattern::MULSUBv4i16_indexed_OP2:
4199   case MachineCombinerPattern::MULSUBv8i16_indexed_OP1:
4200   case MachineCombinerPattern::MULSUBv8i16_indexed_OP2:
4201   case MachineCombinerPattern::MULSUBv2i32_indexed_OP1:
4202   case MachineCombinerPattern::MULSUBv2i32_indexed_OP2:
4203   case MachineCombinerPattern::MULSUBv4i32_indexed_OP1:
4204   case MachineCombinerPattern::MULSUBv4i32_indexed_OP2:
4205     return true;
4206   } // end switch (Pattern)
4207   return false;
4208 }
4209 /// Return true when there is potentially a faster code sequence for an
4210 /// instruction chain ending in \p Root. All potential patterns are listed in
4211 /// the \p Pattern vector. Pattern should be sorted in priority order since the
4212 /// pattern evaluator stops checking as soon as it finds a faster sequence.
4213 
4214 bool AArch64InstrInfo::getMachineCombinerPatterns(
4215     MachineInstr &Root,
4216     SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
4217   // Integer patterns
4218   if (getMaddPatterns(Root, Patterns))
4219     return true;
4220   // Floating point patterns
4221   if (getFMAPatterns(Root, Patterns))
4222     return true;
4223 
4224   return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
4225 }
4226 
4227 enum class FMAInstKind { Default, Indexed, Accumulator };
4228 /// genFusedMultiply - Generate fused multiply instructions.
4229 /// This function supports both integer and floating point instructions.
4230 /// A typical example:
4231 ///  F|MUL I=A,B,0
4232 ///  F|ADD R,I,C
4233 ///  ==> F|MADD R,A,B,C
4234 /// \param MF Containing MachineFunction
4235 /// \param MRI Register information
4236 /// \param TII Target information
4237 /// \param Root is the F|ADD instruction
4238 /// \param [out] InsInstrs is a vector of machine instructions and will
4239 /// contain the generated madd instruction
4240 /// \param IdxMulOpd is index of operand in Root that is the result of
4241 /// the F|MUL. In the example above IdxMulOpd is 1.
4242 /// \param MaddOpc the opcode fo the f|madd instruction
4243 /// \param RC Register class of operands
4244 /// \param kind of fma instruction (addressing mode) to be generated
4245 /// \param ReplacedAddend is the result register from the instruction
4246 /// replacing the non-combined operand, if any.
4247 static MachineInstr *
4248 genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI,
4249                  const TargetInstrInfo *TII, MachineInstr &Root,
4250                  SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd,
4251                  unsigned MaddOpc, const TargetRegisterClass *RC,
4252                  FMAInstKind kind = FMAInstKind::Default,
4253                  const Register *ReplacedAddend = nullptr) {
4254   assert(IdxMulOpd == 1 || IdxMulOpd == 2);
4255 
4256   unsigned IdxOtherOpd = IdxMulOpd == 1 ? 2 : 1;
4257   MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
4258   Register ResultReg = Root.getOperand(0).getReg();
4259   Register SrcReg0 = MUL->getOperand(1).getReg();
4260   bool Src0IsKill = MUL->getOperand(1).isKill();
4261   Register SrcReg1 = MUL->getOperand(2).getReg();
4262   bool Src1IsKill = MUL->getOperand(2).isKill();
4263 
4264   unsigned SrcReg2;
4265   bool Src2IsKill;
4266   if (ReplacedAddend) {
4267     // If we just generated a new addend, we must be it's only use.
4268     SrcReg2 = *ReplacedAddend;
4269     Src2IsKill = true;
4270   } else {
4271     SrcReg2 = Root.getOperand(IdxOtherOpd).getReg();
4272     Src2IsKill = Root.getOperand(IdxOtherOpd).isKill();
4273   }
4274 
4275   if (Register::isVirtualRegister(ResultReg))
4276     MRI.constrainRegClass(ResultReg, RC);
4277   if (Register::isVirtualRegister(SrcReg0))
4278     MRI.constrainRegClass(SrcReg0, RC);
4279   if (Register::isVirtualRegister(SrcReg1))
4280     MRI.constrainRegClass(SrcReg1, RC);
4281   if (Register::isVirtualRegister(SrcReg2))
4282     MRI.constrainRegClass(SrcReg2, RC);
4283 
4284   MachineInstrBuilder MIB;
4285   if (kind == FMAInstKind::Default)
4286     MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4287               .addReg(SrcReg0, getKillRegState(Src0IsKill))
4288               .addReg(SrcReg1, getKillRegState(Src1IsKill))
4289               .addReg(SrcReg2, getKillRegState(Src2IsKill));
4290   else if (kind == FMAInstKind::Indexed)
4291     MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4292               .addReg(SrcReg2, getKillRegState(Src2IsKill))
4293               .addReg(SrcReg0, getKillRegState(Src0IsKill))
4294               .addReg(SrcReg1, getKillRegState(Src1IsKill))
4295               .addImm(MUL->getOperand(3).getImm());
4296   else if (kind == FMAInstKind::Accumulator)
4297     MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4298               .addReg(SrcReg2, getKillRegState(Src2IsKill))
4299               .addReg(SrcReg0, getKillRegState(Src0IsKill))
4300               .addReg(SrcReg1, getKillRegState(Src1IsKill));
4301   else
4302     assert(false && "Invalid FMA instruction kind \n");
4303   // Insert the MADD (MADD, FMA, FMS, FMLA, FMSL)
4304   InsInstrs.push_back(MIB);
4305   return MUL;
4306 }
4307 
4308 /// genFusedMultiplyAcc - Helper to generate fused multiply accumulate
4309 /// instructions.
4310 ///
4311 /// \see genFusedMultiply
4312 static MachineInstr *genFusedMultiplyAcc(
4313     MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
4314     MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
4315     unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC) {
4316   return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOpd, MaddOpc, RC,
4317                           FMAInstKind::Accumulator);
4318 }
4319 
4320 /// genNeg - Helper to generate an intermediate negation of the second operand
4321 /// of Root
4322 static Register genNeg(MachineFunction &MF, MachineRegisterInfo &MRI,
4323                        const TargetInstrInfo *TII, MachineInstr &Root,
4324                        SmallVectorImpl<MachineInstr *> &InsInstrs,
4325                        DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
4326                        unsigned MnegOpc, const TargetRegisterClass *RC) {
4327   Register NewVR = MRI.createVirtualRegister(RC);
4328   MachineInstrBuilder MIB =
4329       BuildMI(MF, Root.getDebugLoc(), TII->get(MnegOpc), NewVR)
4330           .add(Root.getOperand(2));
4331   InsInstrs.push_back(MIB);
4332 
4333   assert(InstrIdxForVirtReg.empty());
4334   InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
4335 
4336   return NewVR;
4337 }
4338 
4339 /// genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate
4340 /// instructions with an additional negation of the accumulator
4341 static MachineInstr *genFusedMultiplyAccNeg(
4342     MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
4343     MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
4344     DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
4345     unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC) {
4346   assert(IdxMulOpd == 1);
4347 
4348   Register NewVR =
4349       genNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, MnegOpc, RC);
4350   return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOpd, MaddOpc, RC,
4351                           FMAInstKind::Accumulator, &NewVR);
4352 }
4353 
4354 /// genFusedMultiplyIdx - Helper to generate fused multiply accumulate
4355 /// instructions.
4356 ///
4357 /// \see genFusedMultiply
4358 static MachineInstr *genFusedMultiplyIdx(
4359     MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
4360     MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
4361     unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC) {
4362   return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOpd, MaddOpc, RC,
4363                           FMAInstKind::Indexed);
4364 }
4365 
4366 /// genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate
4367 /// instructions with an additional negation of the accumulator
4368 static MachineInstr *genFusedMultiplyIdxNeg(
4369     MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
4370     MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
4371     DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
4372     unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC) {
4373   assert(IdxMulOpd == 1);
4374 
4375   Register NewVR =
4376       genNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, MnegOpc, RC);
4377 
4378   return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOpd, MaddOpc, RC,
4379                           FMAInstKind::Indexed, &NewVR);
4380 }
4381 
4382 /// genMaddR - Generate madd instruction and combine mul and add using
4383 /// an extra virtual register
4384 /// Example - an ADD intermediate needs to be stored in a register:
4385 ///   MUL I=A,B,0
4386 ///   ADD R,I,Imm
4387 ///   ==> ORR  V, ZR, Imm
4388 ///   ==> MADD R,A,B,V
4389 /// \param MF Containing MachineFunction
4390 /// \param MRI Register information
4391 /// \param TII Target information
4392 /// \param Root is the ADD instruction
4393 /// \param [out] InsInstrs is a vector of machine instructions and will
4394 /// contain the generated madd instruction
4395 /// \param IdxMulOpd is index of operand in Root that is the result of
4396 /// the MUL. In the example above IdxMulOpd is 1.
4397 /// \param MaddOpc the opcode fo the madd instruction
4398 /// \param VR is a virtual register that holds the value of an ADD operand
4399 /// (V in the example above).
4400 /// \param RC Register class of operands
4401 static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
4402                               const TargetInstrInfo *TII, MachineInstr &Root,
4403                               SmallVectorImpl<MachineInstr *> &InsInstrs,
4404                               unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR,
4405                               const TargetRegisterClass *RC) {
4406   assert(IdxMulOpd == 1 || IdxMulOpd == 2);
4407 
4408   MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
4409   Register ResultReg = Root.getOperand(0).getReg();
4410   Register SrcReg0 = MUL->getOperand(1).getReg();
4411   bool Src0IsKill = MUL->getOperand(1).isKill();
4412   Register SrcReg1 = MUL->getOperand(2).getReg();
4413   bool Src1IsKill = MUL->getOperand(2).isKill();
4414 
4415   if (Register::isVirtualRegister(ResultReg))
4416     MRI.constrainRegClass(ResultReg, RC);
4417   if (Register::isVirtualRegister(SrcReg0))
4418     MRI.constrainRegClass(SrcReg0, RC);
4419   if (Register::isVirtualRegister(SrcReg1))
4420     MRI.constrainRegClass(SrcReg1, RC);
4421   if (Register::isVirtualRegister(VR))
4422     MRI.constrainRegClass(VR, RC);
4423 
4424   MachineInstrBuilder MIB =
4425       BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4426           .addReg(SrcReg0, getKillRegState(Src0IsKill))
4427           .addReg(SrcReg1, getKillRegState(Src1IsKill))
4428           .addReg(VR);
4429   // Insert the MADD
4430   InsInstrs.push_back(MIB);
4431   return MUL;
4432 }
4433 
4434 /// When getMachineCombinerPatterns() finds potential patterns,
4435 /// this function generates the instructions that could replace the
4436 /// original code sequence
4437 void AArch64InstrInfo::genAlternativeCodeSequence(
4438     MachineInstr &Root, MachineCombinerPattern Pattern,
4439     SmallVectorImpl<MachineInstr *> &InsInstrs,
4440     SmallVectorImpl<MachineInstr *> &DelInstrs,
4441     DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
4442   MachineBasicBlock &MBB = *Root.getParent();
4443   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4444   MachineFunction &MF = *MBB.getParent();
4445   const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
4446 
4447   MachineInstr *MUL;
4448   const TargetRegisterClass *RC;
4449   unsigned Opc;
4450   switch (Pattern) {
4451   default:
4452     // Reassociate instructions.
4453     TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
4454                                                 DelInstrs, InstrIdxForVirtReg);
4455     return;
4456   case MachineCombinerPattern::MULADDW_OP1:
4457   case MachineCombinerPattern::MULADDX_OP1:
4458     // MUL I=A,B,0
4459     // ADD R,I,C
4460     // ==> MADD R,A,B,C
4461     // --- Create(MADD);
4462     if (Pattern == MachineCombinerPattern::MULADDW_OP1) {
4463       Opc = AArch64::MADDWrrr;
4464       RC = &AArch64::GPR32RegClass;
4465     } else {
4466       Opc = AArch64::MADDXrrr;
4467       RC = &AArch64::GPR64RegClass;
4468     }
4469     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4470     break;
4471   case MachineCombinerPattern::MULADDW_OP2:
4472   case MachineCombinerPattern::MULADDX_OP2:
4473     // MUL I=A,B,0
4474     // ADD R,C,I
4475     // ==> MADD R,A,B,C
4476     // --- Create(MADD);
4477     if (Pattern == MachineCombinerPattern::MULADDW_OP2) {
4478       Opc = AArch64::MADDWrrr;
4479       RC = &AArch64::GPR32RegClass;
4480     } else {
4481       Opc = AArch64::MADDXrrr;
4482       RC = &AArch64::GPR64RegClass;
4483     }
4484     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4485     break;
4486   case MachineCombinerPattern::MULADDWI_OP1:
4487   case MachineCombinerPattern::MULADDXI_OP1: {
4488     // MUL I=A,B,0
4489     // ADD R,I,Imm
4490     // ==> ORR  V, ZR, Imm
4491     // ==> MADD R,A,B,V
4492     // --- Create(MADD);
4493     const TargetRegisterClass *OrrRC;
4494     unsigned BitSize, OrrOpc, ZeroReg;
4495     if (Pattern == MachineCombinerPattern::MULADDWI_OP1) {
4496       OrrOpc = AArch64::ORRWri;
4497       OrrRC = &AArch64::GPR32spRegClass;
4498       BitSize = 32;
4499       ZeroReg = AArch64::WZR;
4500       Opc = AArch64::MADDWrrr;
4501       RC = &AArch64::GPR32RegClass;
4502     } else {
4503       OrrOpc = AArch64::ORRXri;
4504       OrrRC = &AArch64::GPR64spRegClass;
4505       BitSize = 64;
4506       ZeroReg = AArch64::XZR;
4507       Opc = AArch64::MADDXrrr;
4508       RC = &AArch64::GPR64RegClass;
4509     }
4510     Register NewVR = MRI.createVirtualRegister(OrrRC);
4511     uint64_t Imm = Root.getOperand(2).getImm();
4512 
4513     if (Root.getOperand(3).isImm()) {
4514       unsigned Val = Root.getOperand(3).getImm();
4515       Imm = Imm << Val;
4516     }
4517     uint64_t UImm = SignExtend64(Imm, BitSize);
4518     uint64_t Encoding;
4519     if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
4520       MachineInstrBuilder MIB1 =
4521           BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
4522               .addReg(ZeroReg)
4523               .addImm(Encoding);
4524       InsInstrs.push_back(MIB1);
4525       InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
4526       MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
4527     }
4528     break;
4529   }
4530   case MachineCombinerPattern::MULSUBW_OP1:
4531   case MachineCombinerPattern::MULSUBX_OP1: {
4532     // MUL I=A,B,0
4533     // SUB R,I, C
4534     // ==> SUB  V, 0, C
4535     // ==> MADD R,A,B,V // = -C + A*B
4536     // --- Create(MADD);
4537     const TargetRegisterClass *SubRC;
4538     unsigned SubOpc, ZeroReg;
4539     if (Pattern == MachineCombinerPattern::MULSUBW_OP1) {
4540       SubOpc = AArch64::SUBWrr;
4541       SubRC = &AArch64::GPR32spRegClass;
4542       ZeroReg = AArch64::WZR;
4543       Opc = AArch64::MADDWrrr;
4544       RC = &AArch64::GPR32RegClass;
4545     } else {
4546       SubOpc = AArch64::SUBXrr;
4547       SubRC = &AArch64::GPR64spRegClass;
4548       ZeroReg = AArch64::XZR;
4549       Opc = AArch64::MADDXrrr;
4550       RC = &AArch64::GPR64RegClass;
4551     }
4552     Register NewVR = MRI.createVirtualRegister(SubRC);
4553     // SUB NewVR, 0, C
4554     MachineInstrBuilder MIB1 =
4555         BuildMI(MF, Root.getDebugLoc(), TII->get(SubOpc), NewVR)
4556             .addReg(ZeroReg)
4557             .add(Root.getOperand(2));
4558     InsInstrs.push_back(MIB1);
4559     InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
4560     MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
4561     break;
4562   }
4563   case MachineCombinerPattern::MULSUBW_OP2:
4564   case MachineCombinerPattern::MULSUBX_OP2:
4565     // MUL I=A,B,0
4566     // SUB R,C,I
4567     // ==> MSUB R,A,B,C (computes C - A*B)
4568     // --- Create(MSUB);
4569     if (Pattern == MachineCombinerPattern::MULSUBW_OP2) {
4570       Opc = AArch64::MSUBWrrr;
4571       RC = &AArch64::GPR32RegClass;
4572     } else {
4573       Opc = AArch64::MSUBXrrr;
4574       RC = &AArch64::GPR64RegClass;
4575     }
4576     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4577     break;
4578   case MachineCombinerPattern::MULSUBWI_OP1:
4579   case MachineCombinerPattern::MULSUBXI_OP1: {
4580     // MUL I=A,B,0
4581     // SUB R,I, Imm
4582     // ==> ORR  V, ZR, -Imm
4583     // ==> MADD R,A,B,V // = -Imm + A*B
4584     // --- Create(MADD);
4585     const TargetRegisterClass *OrrRC;
4586     unsigned BitSize, OrrOpc, ZeroReg;
4587     if (Pattern == MachineCombinerPattern::MULSUBWI_OP1) {
4588       OrrOpc = AArch64::ORRWri;
4589       OrrRC = &AArch64::GPR32spRegClass;
4590       BitSize = 32;
4591       ZeroReg = AArch64::WZR;
4592       Opc = AArch64::MADDWrrr;
4593       RC = &AArch64::GPR32RegClass;
4594     } else {
4595       OrrOpc = AArch64::ORRXri;
4596       OrrRC = &AArch64::GPR64spRegClass;
4597       BitSize = 64;
4598       ZeroReg = AArch64::XZR;
4599       Opc = AArch64::MADDXrrr;
4600       RC = &AArch64::GPR64RegClass;
4601     }
4602     Register NewVR = MRI.createVirtualRegister(OrrRC);
4603     uint64_t Imm = Root.getOperand(2).getImm();
4604     if (Root.getOperand(3).isImm()) {
4605       unsigned Val = Root.getOperand(3).getImm();
4606       Imm = Imm << Val;
4607     }
4608     uint64_t UImm = SignExtend64(-Imm, BitSize);
4609     uint64_t Encoding;
4610     if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
4611       MachineInstrBuilder MIB1 =
4612           BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
4613               .addReg(ZeroReg)
4614               .addImm(Encoding);
4615       InsInstrs.push_back(MIB1);
4616       InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
4617       MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
4618     }
4619     break;
4620   }
4621 
4622   case MachineCombinerPattern::MULADDv8i8_OP1:
4623     Opc = AArch64::MLAv8i8;
4624     RC = &AArch64::FPR64RegClass;
4625     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4626     break;
4627   case MachineCombinerPattern::MULADDv8i8_OP2:
4628     Opc = AArch64::MLAv8i8;
4629     RC = &AArch64::FPR64RegClass;
4630     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4631     break;
4632   case MachineCombinerPattern::MULADDv16i8_OP1:
4633     Opc = AArch64::MLAv16i8;
4634     RC = &AArch64::FPR128RegClass;
4635     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4636     break;
4637   case MachineCombinerPattern::MULADDv16i8_OP2:
4638     Opc = AArch64::MLAv16i8;
4639     RC = &AArch64::FPR128RegClass;
4640     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4641     break;
4642   case MachineCombinerPattern::MULADDv4i16_OP1:
4643     Opc = AArch64::MLAv4i16;
4644     RC = &AArch64::FPR64RegClass;
4645     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4646     break;
4647   case MachineCombinerPattern::MULADDv4i16_OP2:
4648     Opc = AArch64::MLAv4i16;
4649     RC = &AArch64::FPR64RegClass;
4650     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4651     break;
4652   case MachineCombinerPattern::MULADDv8i16_OP1:
4653     Opc = AArch64::MLAv8i16;
4654     RC = &AArch64::FPR128RegClass;
4655     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4656     break;
4657   case MachineCombinerPattern::MULADDv8i16_OP2:
4658     Opc = AArch64::MLAv8i16;
4659     RC = &AArch64::FPR128RegClass;
4660     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4661     break;
4662   case MachineCombinerPattern::MULADDv2i32_OP1:
4663     Opc = AArch64::MLAv2i32;
4664     RC = &AArch64::FPR64RegClass;
4665     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4666     break;
4667   case MachineCombinerPattern::MULADDv2i32_OP2:
4668     Opc = AArch64::MLAv2i32;
4669     RC = &AArch64::FPR64RegClass;
4670     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4671     break;
4672   case MachineCombinerPattern::MULADDv4i32_OP1:
4673     Opc = AArch64::MLAv4i32;
4674     RC = &AArch64::FPR128RegClass;
4675     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4676     break;
4677   case MachineCombinerPattern::MULADDv4i32_OP2:
4678     Opc = AArch64::MLAv4i32;
4679     RC = &AArch64::FPR128RegClass;
4680     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4681     break;
4682 
4683   case MachineCombinerPattern::MULSUBv8i8_OP1:
4684     Opc = AArch64::MLAv8i8;
4685     RC = &AArch64::FPR64RegClass;
4686     MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
4687                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i8,
4688                                  RC);
4689     break;
4690   case MachineCombinerPattern::MULSUBv8i8_OP2:
4691     Opc = AArch64::MLSv8i8;
4692     RC = &AArch64::FPR64RegClass;
4693     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4694     break;
4695   case MachineCombinerPattern::MULSUBv16i8_OP1:
4696     Opc = AArch64::MLAv16i8;
4697     RC = &AArch64::FPR128RegClass;
4698     MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
4699                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv16i8,
4700                                  RC);
4701     break;
4702   case MachineCombinerPattern::MULSUBv16i8_OP2:
4703     Opc = AArch64::MLSv16i8;
4704     RC = &AArch64::FPR128RegClass;
4705     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4706     break;
4707   case MachineCombinerPattern::MULSUBv4i16_OP1:
4708     Opc = AArch64::MLAv4i16;
4709     RC = &AArch64::FPR64RegClass;
4710     MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
4711                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i16,
4712                                  RC);
4713     break;
4714   case MachineCombinerPattern::MULSUBv4i16_OP2:
4715     Opc = AArch64::MLSv4i16;
4716     RC = &AArch64::FPR64RegClass;
4717     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4718     break;
4719   case MachineCombinerPattern::MULSUBv8i16_OP1:
4720     Opc = AArch64::MLAv8i16;
4721     RC = &AArch64::FPR128RegClass;
4722     MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
4723                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i16,
4724                                  RC);
4725     break;
4726   case MachineCombinerPattern::MULSUBv8i16_OP2:
4727     Opc = AArch64::MLSv8i16;
4728     RC = &AArch64::FPR128RegClass;
4729     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4730     break;
4731   case MachineCombinerPattern::MULSUBv2i32_OP1:
4732     Opc = AArch64::MLAv2i32;
4733     RC = &AArch64::FPR64RegClass;
4734     MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
4735                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv2i32,
4736                                  RC);
4737     break;
4738   case MachineCombinerPattern::MULSUBv2i32_OP2:
4739     Opc = AArch64::MLSv2i32;
4740     RC = &AArch64::FPR64RegClass;
4741     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4742     break;
4743   case MachineCombinerPattern::MULSUBv4i32_OP1:
4744     Opc = AArch64::MLAv4i32;
4745     RC = &AArch64::FPR128RegClass;
4746     MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
4747                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i32,
4748                                  RC);
4749     break;
4750   case MachineCombinerPattern::MULSUBv4i32_OP2:
4751     Opc = AArch64::MLSv4i32;
4752     RC = &AArch64::FPR128RegClass;
4753     MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4754     break;
4755 
4756   case MachineCombinerPattern::MULADDv4i16_indexed_OP1:
4757     Opc = AArch64::MLAv4i16_indexed;
4758     RC = &AArch64::FPR64RegClass;
4759     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4760     break;
4761   case MachineCombinerPattern::MULADDv4i16_indexed_OP2:
4762     Opc = AArch64::MLAv4i16_indexed;
4763     RC = &AArch64::FPR64RegClass;
4764     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4765     break;
4766   case MachineCombinerPattern::MULADDv8i16_indexed_OP1:
4767     Opc = AArch64::MLAv8i16_indexed;
4768     RC = &AArch64::FPR128RegClass;
4769     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4770     break;
4771   case MachineCombinerPattern::MULADDv8i16_indexed_OP2:
4772     Opc = AArch64::MLAv8i16_indexed;
4773     RC = &AArch64::FPR128RegClass;
4774     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4775     break;
4776   case MachineCombinerPattern::MULADDv2i32_indexed_OP1:
4777     Opc = AArch64::MLAv2i32_indexed;
4778     RC = &AArch64::FPR64RegClass;
4779     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4780     break;
4781   case MachineCombinerPattern::MULADDv2i32_indexed_OP2:
4782     Opc = AArch64::MLAv2i32_indexed;
4783     RC = &AArch64::FPR64RegClass;
4784     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4785     break;
4786   case MachineCombinerPattern::MULADDv4i32_indexed_OP1:
4787     Opc = AArch64::MLAv4i32_indexed;
4788     RC = &AArch64::FPR128RegClass;
4789     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4790     break;
4791   case MachineCombinerPattern::MULADDv4i32_indexed_OP2:
4792     Opc = AArch64::MLAv4i32_indexed;
4793     RC = &AArch64::FPR128RegClass;
4794     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4795     break;
4796 
4797   case MachineCombinerPattern::MULSUBv4i16_indexed_OP1:
4798     Opc = AArch64::MLAv4i16_indexed;
4799     RC = &AArch64::FPR64RegClass;
4800     MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs,
4801                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i16,
4802                                  RC);
4803     break;
4804   case MachineCombinerPattern::MULSUBv4i16_indexed_OP2:
4805     Opc = AArch64::MLSv4i16_indexed;
4806     RC = &AArch64::FPR64RegClass;
4807     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4808     break;
4809   case MachineCombinerPattern::MULSUBv8i16_indexed_OP1:
4810     Opc = AArch64::MLAv8i16_indexed;
4811     RC = &AArch64::FPR128RegClass;
4812     MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs,
4813                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i16,
4814                                  RC);
4815     break;
4816   case MachineCombinerPattern::MULSUBv8i16_indexed_OP2:
4817     Opc = AArch64::MLSv8i16_indexed;
4818     RC = &AArch64::FPR128RegClass;
4819     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4820     break;
4821   case MachineCombinerPattern::MULSUBv2i32_indexed_OP1:
4822     Opc = AArch64::MLAv2i32_indexed;
4823     RC = &AArch64::FPR64RegClass;
4824     MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs,
4825                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv2i32,
4826                                  RC);
4827     break;
4828   case MachineCombinerPattern::MULSUBv2i32_indexed_OP2:
4829     Opc = AArch64::MLSv2i32_indexed;
4830     RC = &AArch64::FPR64RegClass;
4831     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4832     break;
4833   case MachineCombinerPattern::MULSUBv4i32_indexed_OP1:
4834     Opc = AArch64::MLAv4i32_indexed;
4835     RC = &AArch64::FPR128RegClass;
4836     MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs,
4837                                  InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i32,
4838                                  RC);
4839     break;
4840   case MachineCombinerPattern::MULSUBv4i32_indexed_OP2:
4841     Opc = AArch64::MLSv4i32_indexed;
4842     RC = &AArch64::FPR128RegClass;
4843     MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4844     break;
4845 
4846   // Floating Point Support
4847   case MachineCombinerPattern::FMULADDH_OP1:
4848     Opc = AArch64::FMADDHrrr;
4849     RC = &AArch64::FPR16RegClass;
4850     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4851     break;
4852   case MachineCombinerPattern::FMULADDS_OP1:
4853     Opc = AArch64::FMADDSrrr;
4854     RC = &AArch64::FPR32RegClass;
4855     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4856     break;
4857   case MachineCombinerPattern::FMULADDD_OP1:
4858     Opc = AArch64::FMADDDrrr;
4859     RC = &AArch64::FPR64RegClass;
4860     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
4861     break;
4862 
4863   case MachineCombinerPattern::FMULADDH_OP2:
4864     Opc = AArch64::FMADDHrrr;
4865     RC = &AArch64::FPR16RegClass;
4866     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4867     break;
4868   case MachineCombinerPattern::FMULADDS_OP2:
4869     Opc = AArch64::FMADDSrrr;
4870     RC = &AArch64::FPR32RegClass;
4871     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4872     break;
4873   case MachineCombinerPattern::FMULADDD_OP2:
4874     Opc = AArch64::FMADDDrrr;
4875     RC = &AArch64::FPR64RegClass;
4876     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
4877     break;
4878 
4879   case MachineCombinerPattern::FMLAv1i32_indexed_OP1:
4880     Opc = AArch64::FMLAv1i32_indexed;
4881     RC = &AArch64::FPR32RegClass;
4882     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4883                            FMAInstKind::Indexed);
4884     break;
4885   case MachineCombinerPattern::FMLAv1i32_indexed_OP2:
4886     Opc = AArch64::FMLAv1i32_indexed;
4887     RC = &AArch64::FPR32RegClass;
4888     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
4889                            FMAInstKind::Indexed);
4890     break;
4891 
4892   case MachineCombinerPattern::FMLAv1i64_indexed_OP1:
4893     Opc = AArch64::FMLAv1i64_indexed;
4894     RC = &AArch64::FPR64RegClass;
4895     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4896                            FMAInstKind::Indexed);
4897     break;
4898   case MachineCombinerPattern::FMLAv1i64_indexed_OP2:
4899     Opc = AArch64::FMLAv1i64_indexed;
4900     RC = &AArch64::FPR64RegClass;
4901     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
4902                            FMAInstKind::Indexed);
4903     break;
4904 
4905   case MachineCombinerPattern::FMLAv4i16_indexed_OP1:
4906     RC = &AArch64::FPR64RegClass;
4907     Opc = AArch64::FMLAv4i16_indexed;
4908     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4909                            FMAInstKind::Indexed);
4910     break;
4911   case MachineCombinerPattern::FMLAv4f16_OP1:
4912     RC = &AArch64::FPR64RegClass;
4913     Opc = AArch64::FMLAv4f16;
4914     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4915                            FMAInstKind::Accumulator);
4916     break;
4917   case MachineCombinerPattern::FMLAv4i16_indexed_OP2:
4918     RC = &AArch64::FPR64RegClass;
4919     Opc = AArch64::FMLAv4i16_indexed;
4920     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
4921                            FMAInstKind::Indexed);
4922     break;
4923   case MachineCombinerPattern::FMLAv4f16_OP2:
4924     RC = &AArch64::FPR64RegClass;
4925     Opc = AArch64::FMLAv4f16;
4926     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
4927                            FMAInstKind::Accumulator);
4928     break;
4929 
4930   case MachineCombinerPattern::FMLAv2i32_indexed_OP1:
4931   case MachineCombinerPattern::FMLAv2f32_OP1:
4932     RC = &AArch64::FPR64RegClass;
4933     if (Pattern == MachineCombinerPattern::FMLAv2i32_indexed_OP1) {
4934       Opc = AArch64::FMLAv2i32_indexed;
4935       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4936                              FMAInstKind::Indexed);
4937     } else {
4938       Opc = AArch64::FMLAv2f32;
4939       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4940                              FMAInstKind::Accumulator);
4941     }
4942     break;
4943   case MachineCombinerPattern::FMLAv2i32_indexed_OP2:
4944   case MachineCombinerPattern::FMLAv2f32_OP2:
4945     RC = &AArch64::FPR64RegClass;
4946     if (Pattern == MachineCombinerPattern::FMLAv2i32_indexed_OP2) {
4947       Opc = AArch64::FMLAv2i32_indexed;
4948       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
4949                              FMAInstKind::Indexed);
4950     } else {
4951       Opc = AArch64::FMLAv2f32;
4952       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
4953                              FMAInstKind::Accumulator);
4954     }
4955     break;
4956 
4957   case MachineCombinerPattern::FMLAv8i16_indexed_OP1:
4958     RC = &AArch64::FPR128RegClass;
4959     Opc = AArch64::FMLAv8i16_indexed;
4960     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4961                            FMAInstKind::Indexed);
4962     break;
4963   case MachineCombinerPattern::FMLAv8f16_OP1:
4964     RC = &AArch64::FPR128RegClass;
4965     Opc = AArch64::FMLAv8f16;
4966     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4967                            FMAInstKind::Accumulator);
4968     break;
4969   case MachineCombinerPattern::FMLAv8i16_indexed_OP2:
4970     RC = &AArch64::FPR128RegClass;
4971     Opc = AArch64::FMLAv8i16_indexed;
4972     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
4973                            FMAInstKind::Indexed);
4974     break;
4975   case MachineCombinerPattern::FMLAv8f16_OP2:
4976     RC = &AArch64::FPR128RegClass;
4977     Opc = AArch64::FMLAv8f16;
4978     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
4979                            FMAInstKind::Accumulator);
4980     break;
4981 
4982   case MachineCombinerPattern::FMLAv2i64_indexed_OP1:
4983   case MachineCombinerPattern::FMLAv2f64_OP1:
4984     RC = &AArch64::FPR128RegClass;
4985     if (Pattern == MachineCombinerPattern::FMLAv2i64_indexed_OP1) {
4986       Opc = AArch64::FMLAv2i64_indexed;
4987       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4988                              FMAInstKind::Indexed);
4989     } else {
4990       Opc = AArch64::FMLAv2f64;
4991       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
4992                              FMAInstKind::Accumulator);
4993     }
4994     break;
4995   case MachineCombinerPattern::FMLAv2i64_indexed_OP2:
4996   case MachineCombinerPattern::FMLAv2f64_OP2:
4997     RC = &AArch64::FPR128RegClass;
4998     if (Pattern == MachineCombinerPattern::FMLAv2i64_indexed_OP2) {
4999       Opc = AArch64::FMLAv2i64_indexed;
5000       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5001                              FMAInstKind::Indexed);
5002     } else {
5003       Opc = AArch64::FMLAv2f64;
5004       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5005                              FMAInstKind::Accumulator);
5006     }
5007     break;
5008 
5009   case MachineCombinerPattern::FMLAv4i32_indexed_OP1:
5010   case MachineCombinerPattern::FMLAv4f32_OP1:
5011     RC = &AArch64::FPR128RegClass;
5012     if (Pattern == MachineCombinerPattern::FMLAv4i32_indexed_OP1) {
5013       Opc = AArch64::FMLAv4i32_indexed;
5014       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5015                              FMAInstKind::Indexed);
5016     } else {
5017       Opc = AArch64::FMLAv4f32;
5018       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5019                              FMAInstKind::Accumulator);
5020     }
5021     break;
5022 
5023   case MachineCombinerPattern::FMLAv4i32_indexed_OP2:
5024   case MachineCombinerPattern::FMLAv4f32_OP2:
5025     RC = &AArch64::FPR128RegClass;
5026     if (Pattern == MachineCombinerPattern::FMLAv4i32_indexed_OP2) {
5027       Opc = AArch64::FMLAv4i32_indexed;
5028       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5029                              FMAInstKind::Indexed);
5030     } else {
5031       Opc = AArch64::FMLAv4f32;
5032       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5033                              FMAInstKind::Accumulator);
5034     }
5035     break;
5036 
5037   case MachineCombinerPattern::FMULSUBH_OP1:
5038     Opc = AArch64::FNMSUBHrrr;
5039     RC = &AArch64::FPR16RegClass;
5040     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
5041     break;
5042   case MachineCombinerPattern::FMULSUBS_OP1:
5043     Opc = AArch64::FNMSUBSrrr;
5044     RC = &AArch64::FPR32RegClass;
5045     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
5046     break;
5047   case MachineCombinerPattern::FMULSUBD_OP1:
5048     Opc = AArch64::FNMSUBDrrr;
5049     RC = &AArch64::FPR64RegClass;
5050     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
5051     break;
5052 
5053   case MachineCombinerPattern::FNMULSUBH_OP1:
5054     Opc = AArch64::FNMADDHrrr;
5055     RC = &AArch64::FPR16RegClass;
5056     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
5057     break;
5058   case MachineCombinerPattern::FNMULSUBS_OP1:
5059     Opc = AArch64::FNMADDSrrr;
5060     RC = &AArch64::FPR32RegClass;
5061     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
5062     break;
5063   case MachineCombinerPattern::FNMULSUBD_OP1:
5064     Opc = AArch64::FNMADDDrrr;
5065     RC = &AArch64::FPR64RegClass;
5066     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
5067     break;
5068 
5069   case MachineCombinerPattern::FMULSUBH_OP2:
5070     Opc = AArch64::FMSUBHrrr;
5071     RC = &AArch64::FPR16RegClass;
5072     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
5073     break;
5074   case MachineCombinerPattern::FMULSUBS_OP2:
5075     Opc = AArch64::FMSUBSrrr;
5076     RC = &AArch64::FPR32RegClass;
5077     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
5078     break;
5079   case MachineCombinerPattern::FMULSUBD_OP2:
5080     Opc = AArch64::FMSUBDrrr;
5081     RC = &AArch64::FPR64RegClass;
5082     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
5083     break;
5084 
5085   case MachineCombinerPattern::FMLSv1i32_indexed_OP2:
5086     Opc = AArch64::FMLSv1i32_indexed;
5087     RC = &AArch64::FPR32RegClass;
5088     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5089                            FMAInstKind::Indexed);
5090     break;
5091 
5092   case MachineCombinerPattern::FMLSv1i64_indexed_OP2:
5093     Opc = AArch64::FMLSv1i64_indexed;
5094     RC = &AArch64::FPR64RegClass;
5095     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5096                            FMAInstKind::Indexed);
5097     break;
5098 
5099   case MachineCombinerPattern::FMLSv4f16_OP1:
5100   case MachineCombinerPattern::FMLSv4i16_indexed_OP1: {
5101     RC = &AArch64::FPR64RegClass;
5102     Register NewVR = MRI.createVirtualRegister(RC);
5103     MachineInstrBuilder MIB1 =
5104         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv4f16), NewVR)
5105             .add(Root.getOperand(2));
5106     InsInstrs.push_back(MIB1);
5107     InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
5108     if (Pattern == MachineCombinerPattern::FMLSv4f16_OP1) {
5109       Opc = AArch64::FMLAv4f16;
5110       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5111                              FMAInstKind::Accumulator, &NewVR);
5112     } else {
5113       Opc = AArch64::FMLAv4i16_indexed;
5114       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5115                              FMAInstKind::Indexed, &NewVR);
5116     }
5117     break;
5118   }
5119   case MachineCombinerPattern::FMLSv4f16_OP2:
5120     RC = &AArch64::FPR64RegClass;
5121     Opc = AArch64::FMLSv4f16;
5122     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5123                            FMAInstKind::Accumulator);
5124     break;
5125   case MachineCombinerPattern::FMLSv4i16_indexed_OP2:
5126     RC = &AArch64::FPR64RegClass;
5127     Opc = AArch64::FMLSv4i16_indexed;
5128     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5129                            FMAInstKind::Indexed);
5130     break;
5131 
5132   case MachineCombinerPattern::FMLSv2f32_OP2:
5133   case MachineCombinerPattern::FMLSv2i32_indexed_OP2:
5134     RC = &AArch64::FPR64RegClass;
5135     if (Pattern == MachineCombinerPattern::FMLSv2i32_indexed_OP2) {
5136       Opc = AArch64::FMLSv2i32_indexed;
5137       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5138                              FMAInstKind::Indexed);
5139     } else {
5140       Opc = AArch64::FMLSv2f32;
5141       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5142                              FMAInstKind::Accumulator);
5143     }
5144     break;
5145 
5146   case MachineCombinerPattern::FMLSv8f16_OP1:
5147   case MachineCombinerPattern::FMLSv8i16_indexed_OP1: {
5148     RC = &AArch64::FPR128RegClass;
5149     Register NewVR = MRI.createVirtualRegister(RC);
5150     MachineInstrBuilder MIB1 =
5151         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv8f16), NewVR)
5152             .add(Root.getOperand(2));
5153     InsInstrs.push_back(MIB1);
5154     InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
5155     if (Pattern == MachineCombinerPattern::FMLSv8f16_OP1) {
5156       Opc = AArch64::FMLAv8f16;
5157       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5158                              FMAInstKind::Accumulator, &NewVR);
5159     } else {
5160       Opc = AArch64::FMLAv8i16_indexed;
5161       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5162                              FMAInstKind::Indexed, &NewVR);
5163     }
5164     break;
5165   }
5166   case MachineCombinerPattern::FMLSv8f16_OP2:
5167     RC = &AArch64::FPR128RegClass;
5168     Opc = AArch64::FMLSv8f16;
5169     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5170                            FMAInstKind::Accumulator);
5171     break;
5172   case MachineCombinerPattern::FMLSv8i16_indexed_OP2:
5173     RC = &AArch64::FPR128RegClass;
5174     Opc = AArch64::FMLSv8i16_indexed;
5175     MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5176                            FMAInstKind::Indexed);
5177     break;
5178 
5179   case MachineCombinerPattern::FMLSv2f64_OP2:
5180   case MachineCombinerPattern::FMLSv2i64_indexed_OP2:
5181     RC = &AArch64::FPR128RegClass;
5182     if (Pattern == MachineCombinerPattern::FMLSv2i64_indexed_OP2) {
5183       Opc = AArch64::FMLSv2i64_indexed;
5184       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5185                              FMAInstKind::Indexed);
5186     } else {
5187       Opc = AArch64::FMLSv2f64;
5188       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5189                              FMAInstKind::Accumulator);
5190     }
5191     break;
5192 
5193   case MachineCombinerPattern::FMLSv4f32_OP2:
5194   case MachineCombinerPattern::FMLSv4i32_indexed_OP2:
5195     RC = &AArch64::FPR128RegClass;
5196     if (Pattern == MachineCombinerPattern::FMLSv4i32_indexed_OP2) {
5197       Opc = AArch64::FMLSv4i32_indexed;
5198       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5199                              FMAInstKind::Indexed);
5200     } else {
5201       Opc = AArch64::FMLSv4f32;
5202       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
5203                              FMAInstKind::Accumulator);
5204     }
5205     break;
5206   case MachineCombinerPattern::FMLSv2f32_OP1:
5207   case MachineCombinerPattern::FMLSv2i32_indexed_OP1: {
5208     RC = &AArch64::FPR64RegClass;
5209     Register NewVR = MRI.createVirtualRegister(RC);
5210     MachineInstrBuilder MIB1 =
5211         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv2f32), NewVR)
5212             .add(Root.getOperand(2));
5213     InsInstrs.push_back(MIB1);
5214     InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
5215     if (Pattern == MachineCombinerPattern::FMLSv2i32_indexed_OP1) {
5216       Opc = AArch64::FMLAv2i32_indexed;
5217       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5218                              FMAInstKind::Indexed, &NewVR);
5219     } else {
5220       Opc = AArch64::FMLAv2f32;
5221       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5222                              FMAInstKind::Accumulator, &NewVR);
5223     }
5224     break;
5225   }
5226   case MachineCombinerPattern::FMLSv4f32_OP1:
5227   case MachineCombinerPattern::FMLSv4i32_indexed_OP1: {
5228     RC = &AArch64::FPR128RegClass;
5229     Register NewVR = MRI.createVirtualRegister(RC);
5230     MachineInstrBuilder MIB1 =
5231         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv4f32), NewVR)
5232             .add(Root.getOperand(2));
5233     InsInstrs.push_back(MIB1);
5234     InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
5235     if (Pattern == MachineCombinerPattern::FMLSv4i32_indexed_OP1) {
5236       Opc = AArch64::FMLAv4i32_indexed;
5237       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5238                              FMAInstKind::Indexed, &NewVR);
5239     } else {
5240       Opc = AArch64::FMLAv4f32;
5241       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5242                              FMAInstKind::Accumulator, &NewVR);
5243     }
5244     break;
5245   }
5246   case MachineCombinerPattern::FMLSv2f64_OP1:
5247   case MachineCombinerPattern::FMLSv2i64_indexed_OP1: {
5248     RC = &AArch64::FPR128RegClass;
5249     Register NewVR = MRI.createVirtualRegister(RC);
5250     MachineInstrBuilder MIB1 =
5251         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv2f64), NewVR)
5252             .add(Root.getOperand(2));
5253     InsInstrs.push_back(MIB1);
5254     InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
5255     if (Pattern == MachineCombinerPattern::FMLSv2i64_indexed_OP1) {
5256       Opc = AArch64::FMLAv2i64_indexed;
5257       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5258                              FMAInstKind::Indexed, &NewVR);
5259     } else {
5260       Opc = AArch64::FMLAv2f64;
5261       MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
5262                              FMAInstKind::Accumulator, &NewVR);
5263     }
5264     break;
5265   }
5266   } // end switch (Pattern)
5267   // Record MUL and ADD/SUB for deletion
5268   DelInstrs.push_back(MUL);
5269   DelInstrs.push_back(&Root);
5270 }
5271 
5272 /// Replace csincr-branch sequence by simple conditional branch
5273 ///
5274 /// Examples:
5275 /// 1. \code
5276 ///   csinc  w9, wzr, wzr, <condition code>
5277 ///   tbnz   w9, #0, 0x44
5278 ///    \endcode
5279 /// to
5280 ///    \code
5281 ///   b.<inverted condition code>
5282 ///    \endcode
5283 ///
5284 /// 2. \code
5285 ///   csinc w9, wzr, wzr, <condition code>
5286 ///   tbz   w9, #0, 0x44
5287 ///    \endcode
5288 /// to
5289 ///    \code
5290 ///   b.<condition code>
5291 ///    \endcode
5292 ///
5293 /// Replace compare and branch sequence by TBZ/TBNZ instruction when the
5294 /// compare's constant operand is power of 2.
5295 ///
5296 /// Examples:
5297 ///    \code
5298 ///   and  w8, w8, #0x400
5299 ///   cbnz w8, L1
5300 ///    \endcode
5301 /// to
5302 ///    \code
5303 ///   tbnz w8, #10, L1
5304 ///    \endcode
5305 ///
5306 /// \param  MI Conditional Branch
5307 /// \return True when the simple conditional branch is generated
5308 ///
5309 bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const {
5310   bool IsNegativeBranch = false;
5311   bool IsTestAndBranch = false;
5312   unsigned TargetBBInMI = 0;
5313   switch (MI.getOpcode()) {
5314   default:
5315     llvm_unreachable("Unknown branch instruction?");
5316   case AArch64::Bcc:
5317     return false;
5318   case AArch64::CBZW:
5319   case AArch64::CBZX:
5320     TargetBBInMI = 1;
5321     break;
5322   case AArch64::CBNZW:
5323   case AArch64::CBNZX:
5324     TargetBBInMI = 1;
5325     IsNegativeBranch = true;
5326     break;
5327   case AArch64::TBZW:
5328   case AArch64::TBZX:
5329     TargetBBInMI = 2;
5330     IsTestAndBranch = true;
5331     break;
5332   case AArch64::TBNZW:
5333   case AArch64::TBNZX:
5334     TargetBBInMI = 2;
5335     IsNegativeBranch = true;
5336     IsTestAndBranch = true;
5337     break;
5338   }
5339   // So we increment a zero register and test for bits other
5340   // than bit 0? Conservatively bail out in case the verifier
5341   // missed this case.
5342   if (IsTestAndBranch && MI.getOperand(1).getImm())
5343     return false;
5344 
5345   // Find Definition.
5346   assert(MI.getParent() && "Incomplete machine instruciton\n");
5347   MachineBasicBlock *MBB = MI.getParent();
5348   MachineFunction *MF = MBB->getParent();
5349   MachineRegisterInfo *MRI = &MF->getRegInfo();
5350   Register VReg = MI.getOperand(0).getReg();
5351   if (!Register::isVirtualRegister(VReg))
5352     return false;
5353 
5354   MachineInstr *DefMI = MRI->getVRegDef(VReg);
5355 
5356   // Look through COPY instructions to find definition.
5357   while (DefMI->isCopy()) {
5358     Register CopyVReg = DefMI->getOperand(1).getReg();
5359     if (!MRI->hasOneNonDBGUse(CopyVReg))
5360       return false;
5361     if (!MRI->hasOneDef(CopyVReg))
5362       return false;
5363     DefMI = MRI->getVRegDef(CopyVReg);
5364   }
5365 
5366   switch (DefMI->getOpcode()) {
5367   default:
5368     return false;
5369   // Fold AND into a TBZ/TBNZ if constant operand is power of 2.
5370   case AArch64::ANDWri:
5371   case AArch64::ANDXri: {
5372     if (IsTestAndBranch)
5373       return false;
5374     if (DefMI->getParent() != MBB)
5375       return false;
5376     if (!MRI->hasOneNonDBGUse(VReg))
5377       return false;
5378 
5379     bool Is32Bit = (DefMI->getOpcode() == AArch64::ANDWri);
5380     uint64_t Mask = AArch64_AM::decodeLogicalImmediate(
5381         DefMI->getOperand(2).getImm(), Is32Bit ? 32 : 64);
5382     if (!isPowerOf2_64(Mask))
5383       return false;
5384 
5385     MachineOperand &MO = DefMI->getOperand(1);
5386     Register NewReg = MO.getReg();
5387     if (!Register::isVirtualRegister(NewReg))
5388       return false;
5389 
5390     assert(!MRI->def_empty(NewReg) && "Register must be defined.");
5391 
5392     MachineBasicBlock &RefToMBB = *MBB;
5393     MachineBasicBlock *TBB = MI.getOperand(1).getMBB();
5394     DebugLoc DL = MI.getDebugLoc();
5395     unsigned Imm = Log2_64(Mask);
5396     unsigned Opc = (Imm < 32)
5397                        ? (IsNegativeBranch ? AArch64::TBNZW : AArch64::TBZW)
5398                        : (IsNegativeBranch ? AArch64::TBNZX : AArch64::TBZX);
5399     MachineInstr *NewMI = BuildMI(RefToMBB, MI, DL, get(Opc))
5400                               .addReg(NewReg)
5401                               .addImm(Imm)
5402                               .addMBB(TBB);
5403     // Register lives on to the CBZ now.
5404     MO.setIsKill(false);
5405 
5406     // For immediate smaller than 32, we need to use the 32-bit
5407     // variant (W) in all cases. Indeed the 64-bit variant does not
5408     // allow to encode them.
5409     // Therefore, if the input register is 64-bit, we need to take the
5410     // 32-bit sub-part.
5411     if (!Is32Bit && Imm < 32)
5412       NewMI->getOperand(0).setSubReg(AArch64::sub_32);
5413     MI.eraseFromParent();
5414     return true;
5415   }
5416   // Look for CSINC
5417   case AArch64::CSINCWr:
5418   case AArch64::CSINCXr: {
5419     if (!(DefMI->getOperand(1).getReg() == AArch64::WZR &&
5420           DefMI->getOperand(2).getReg() == AArch64::WZR) &&
5421         !(DefMI->getOperand(1).getReg() == AArch64::XZR &&
5422           DefMI->getOperand(2).getReg() == AArch64::XZR))
5423       return false;
5424 
5425     if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1)
5426       return false;
5427 
5428     AArch64CC::CondCode CC = (AArch64CC::CondCode)DefMI->getOperand(3).getImm();
5429     // Convert only when the condition code is not modified between
5430     // the CSINC and the branch. The CC may be used by other
5431     // instructions in between.
5432     if (areCFlagsAccessedBetweenInstrs(DefMI, MI, &getRegisterInfo(), AK_Write))
5433       return false;
5434     MachineBasicBlock &RefToMBB = *MBB;
5435     MachineBasicBlock *TBB = MI.getOperand(TargetBBInMI).getMBB();
5436     DebugLoc DL = MI.getDebugLoc();
5437     if (IsNegativeBranch)
5438       CC = AArch64CC::getInvertedCondCode(CC);
5439     BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB);
5440     MI.eraseFromParent();
5441     return true;
5442   }
5443   }
5444 }
5445 
5446 std::pair<unsigned, unsigned>
5447 AArch64InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
5448   const unsigned Mask = AArch64II::MO_FRAGMENT;
5449   return std::make_pair(TF & Mask, TF & ~Mask);
5450 }
5451 
5452 ArrayRef<std::pair<unsigned, const char *>>
5453 AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
5454   using namespace AArch64II;
5455 
5456   static const std::pair<unsigned, const char *> TargetFlags[] = {
5457       {MO_PAGE, "aarch64-page"}, {MO_PAGEOFF, "aarch64-pageoff"},
5458       {MO_G3, "aarch64-g3"},     {MO_G2, "aarch64-g2"},
5459       {MO_G1, "aarch64-g1"},     {MO_G0, "aarch64-g0"},
5460       {MO_HI12, "aarch64-hi12"}};
5461   return makeArrayRef(TargetFlags);
5462 }
5463 
5464 ArrayRef<std::pair<unsigned, const char *>>
5465 AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
5466   using namespace AArch64II;
5467 
5468   static const std::pair<unsigned, const char *> TargetFlags[] = {
5469       {MO_COFFSTUB, "aarch64-coffstub"},
5470       {MO_GOT, "aarch64-got"},
5471       {MO_NC, "aarch64-nc"},
5472       {MO_S, "aarch64-s"},
5473       {MO_TLS, "aarch64-tls"},
5474       {MO_DLLIMPORT, "aarch64-dllimport"},
5475       {MO_PREL, "aarch64-prel"},
5476       {MO_TAGGED, "aarch64-tagged"}};
5477   return makeArrayRef(TargetFlags);
5478 }
5479 
5480 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
5481 AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags() const {
5482   static const std::pair<MachineMemOperand::Flags, const char *> TargetFlags[] =
5483       {{MOSuppressPair, "aarch64-suppress-pair"},
5484        {MOStridedAccess, "aarch64-strided-access"}};
5485   return makeArrayRef(TargetFlags);
5486 }
5487 
5488 /// Constants defining how certain sequences should be outlined.
5489 /// This encompasses how an outlined function should be called, and what kind of
5490 /// frame should be emitted for that outlined function.
5491 ///
5492 /// \p MachineOutlinerDefault implies that the function should be called with
5493 /// a save and restore of LR to the stack.
5494 ///
5495 /// That is,
5496 ///
5497 /// I1     Save LR                    OUTLINED_FUNCTION:
5498 /// I2 --> BL OUTLINED_FUNCTION       I1
5499 /// I3     Restore LR                 I2
5500 ///                                   I3
5501 ///                                   RET
5502 ///
5503 /// * Call construction overhead: 3 (save + BL + restore)
5504 /// * Frame construction overhead: 1 (ret)
5505 /// * Requires stack fixups? Yes
5506 ///
5507 /// \p MachineOutlinerTailCall implies that the function is being created from
5508 /// a sequence of instructions ending in a return.
5509 ///
5510 /// That is,
5511 ///
5512 /// I1                             OUTLINED_FUNCTION:
5513 /// I2 --> B OUTLINED_FUNCTION     I1
5514 /// RET                            I2
5515 ///                                RET
5516 ///
5517 /// * Call construction overhead: 1 (B)
5518 /// * Frame construction overhead: 0 (Return included in sequence)
5519 /// * Requires stack fixups? No
5520 ///
5521 /// \p MachineOutlinerNoLRSave implies that the function should be called using
5522 /// a BL instruction, but doesn't require LR to be saved and restored. This
5523 /// happens when LR is known to be dead.
5524 ///
5525 /// That is,
5526 ///
5527 /// I1                                OUTLINED_FUNCTION:
5528 /// I2 --> BL OUTLINED_FUNCTION       I1
5529 /// I3                                I2
5530 ///                                   I3
5531 ///                                   RET
5532 ///
5533 /// * Call construction overhead: 1 (BL)
5534 /// * Frame construction overhead: 1 (RET)
5535 /// * Requires stack fixups? No
5536 ///
5537 /// \p MachineOutlinerThunk implies that the function is being created from
5538 /// a sequence of instructions ending in a call. The outlined function is
5539 /// called with a BL instruction, and the outlined function tail-calls the
5540 /// original call destination.
5541 ///
5542 /// That is,
5543 ///
5544 /// I1                                OUTLINED_FUNCTION:
5545 /// I2 --> BL OUTLINED_FUNCTION       I1
5546 /// BL f                              I2
5547 ///                                   B f
5548 /// * Call construction overhead: 1 (BL)
5549 /// * Frame construction overhead: 0
5550 /// * Requires stack fixups? No
5551 ///
5552 /// \p MachineOutlinerRegSave implies that the function should be called with a
5553 /// save and restore of LR to an available register. This allows us to avoid
5554 /// stack fixups. Note that this outlining variant is compatible with the
5555 /// NoLRSave case.
5556 ///
5557 /// That is,
5558 ///
5559 /// I1     Save LR                    OUTLINED_FUNCTION:
5560 /// I2 --> BL OUTLINED_FUNCTION       I1
5561 /// I3     Restore LR                 I2
5562 ///                                   I3
5563 ///                                   RET
5564 ///
5565 /// * Call construction overhead: 3 (save + BL + restore)
5566 /// * Frame construction overhead: 1 (ret)
5567 /// * Requires stack fixups? No
5568 enum MachineOutlinerClass {
5569   MachineOutlinerDefault,  /// Emit a save, restore, call, and return.
5570   MachineOutlinerTailCall, /// Only emit a branch.
5571   MachineOutlinerNoLRSave, /// Emit a call and return.
5572   MachineOutlinerThunk,    /// Emit a call and tail-call.
5573   MachineOutlinerRegSave   /// Same as default, but save to a register.
5574 };
5575 
5576 enum MachineOutlinerMBBFlags {
5577   LRUnavailableSomewhere = 0x2,
5578   HasCalls = 0x4,
5579   UnsafeRegsDead = 0x8
5580 };
5581 
5582 unsigned
5583 AArch64InstrInfo::findRegisterToSaveLRTo(const outliner::Candidate &C) const {
5584   assert(C.LRUWasSet && "LRU wasn't set?");
5585   MachineFunction *MF = C.getMF();
5586   const AArch64RegisterInfo *ARI = static_cast<const AArch64RegisterInfo *>(
5587       MF->getSubtarget().getRegisterInfo());
5588 
5589   // Check if there is an available register across the sequence that we can
5590   // use.
5591   for (unsigned Reg : AArch64::GPR64RegClass) {
5592     if (!ARI->isReservedReg(*MF, Reg) &&
5593         Reg != AArch64::LR &&  // LR is not reserved, but don't use it.
5594         Reg != AArch64::X16 && // X16 is not guaranteed to be preserved.
5595         Reg != AArch64::X17 && // Ditto for X17.
5596         C.LRU.available(Reg) && C.UsedInSequence.available(Reg))
5597       return Reg;
5598   }
5599 
5600   // No suitable register. Return 0.
5601   return 0u;
5602 }
5603 
5604 static bool
5605 outliningCandidatesSigningScopeConsensus(const outliner::Candidate &a,
5606                                          const outliner::Candidate &b) {
5607   const Function &Fa = a.getMF()->getFunction();
5608   const Function &Fb = b.getMF()->getFunction();
5609 
5610   // If none of the functions have the "sign-return-address" attribute their
5611   // signing behaviour is equal
5612   if (!Fa.hasFnAttribute("sign-return-address") &&
5613       !Fb.hasFnAttribute("sign-return-address")) {
5614     return true;
5615   }
5616 
5617   // If both functions have the "sign-return-address" attribute their signing
5618   // behaviour is equal, if the values of the attributes are equal
5619   if (Fa.hasFnAttribute("sign-return-address") &&
5620       Fb.hasFnAttribute("sign-return-address")) {
5621     StringRef ScopeA =
5622         Fa.getFnAttribute("sign-return-address").getValueAsString();
5623     StringRef ScopeB =
5624         Fb.getFnAttribute("sign-return-address").getValueAsString();
5625     return ScopeA.equals(ScopeB);
5626   }
5627 
5628   // If function B doesn't have the "sign-return-address" attribute but A does,
5629   // the functions' signing behaviour is equal if A's value for
5630   // "sign-return-address" is "none" and vice versa.
5631   if (Fa.hasFnAttribute("sign-return-address")) {
5632     StringRef ScopeA =
5633         Fa.getFnAttribute("sign-return-address").getValueAsString();
5634     return ScopeA.equals("none");
5635   }
5636 
5637   if (Fb.hasFnAttribute("sign-return-address")) {
5638     StringRef ScopeB =
5639         Fb.getFnAttribute("sign-return-address").getValueAsString();
5640     return ScopeB.equals("none");
5641   }
5642 
5643   llvm_unreachable("Unkown combination of sign-return-address attributes");
5644 }
5645 
5646 static bool
5647 outliningCandidatesSigningKeyConsensus(const outliner::Candidate &a,
5648                                        const outliner::Candidate &b) {
5649   const Function &Fa = a.getMF()->getFunction();
5650   const Function &Fb = b.getMF()->getFunction();
5651 
5652   // If none of the functions have the "sign-return-address-key" attribute
5653   // their keys are equal
5654   if (!Fa.hasFnAttribute("sign-return-address-key") &&
5655       !Fb.hasFnAttribute("sign-return-address-key")) {
5656     return true;
5657   }
5658 
5659   // If both functions have the "sign-return-address-key" attribute their
5660   // keys are equal if the values of "sign-return-address-key" are equal
5661   if (Fa.hasFnAttribute("sign-return-address-key") &&
5662       Fb.hasFnAttribute("sign-return-address-key")) {
5663     StringRef KeyA =
5664         Fa.getFnAttribute("sign-return-address-key").getValueAsString();
5665     StringRef KeyB =
5666         Fb.getFnAttribute("sign-return-address-key").getValueAsString();
5667     return KeyA.equals(KeyB);
5668   }
5669 
5670   // If B doesn't have the "sign-return-address-key" attribute, both keys are
5671   // equal, if function a has the default key (a_key)
5672   if (Fa.hasFnAttribute("sign-return-address-key")) {
5673     StringRef KeyA =
5674         Fa.getFnAttribute("sign-return-address-key").getValueAsString();
5675     return KeyA.equals_lower("a_key");
5676   }
5677 
5678   if (Fb.hasFnAttribute("sign-return-address-key")) {
5679     StringRef KeyB =
5680         Fb.getFnAttribute("sign-return-address-key").getValueAsString();
5681     return KeyB.equals_lower("a_key");
5682   }
5683 
5684   llvm_unreachable("Unkown combination of sign-return-address-key attributes");
5685 }
5686 
5687 static bool outliningCandidatesV8_3OpsConsensus(const outliner::Candidate &a,
5688                                                 const outliner::Candidate &b) {
5689   const AArch64Subtarget &SubtargetA =
5690       a.getMF()->getSubtarget<AArch64Subtarget>();
5691   const AArch64Subtarget &SubtargetB =
5692       b.getMF()->getSubtarget<AArch64Subtarget>();
5693   return SubtargetA.hasV8_3aOps() == SubtargetB.hasV8_3aOps();
5694 }
5695 
5696 outliner::OutlinedFunction AArch64InstrInfo::getOutliningCandidateInfo(
5697     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
5698   outliner::Candidate &FirstCand = RepeatedSequenceLocs[0];
5699   unsigned SequenceSize =
5700       std::accumulate(FirstCand.front(), std::next(FirstCand.back()), 0,
5701                       [this](unsigned Sum, const MachineInstr &MI) {
5702                         return Sum + getInstSizeInBytes(MI);
5703                       });
5704   unsigned NumBytesToCreateFrame = 0;
5705 
5706   // We only allow outlining for functions having exactly matching return
5707   // address signing attributes, i.e., all share the same value for the
5708   // attribute "sign-return-address" and all share the same type of key they
5709   // are signed with.
5710   // Additionally we require all functions to simultaniously either support
5711   // v8.3a features or not. Otherwise an outlined function could get signed
5712   // using dedicated v8.3 instructions and a call from a function that doesn't
5713   // support v8.3 instructions would therefore be invalid.
5714   if (std::adjacent_find(
5715           RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
5716           [](const outliner::Candidate &a, const outliner::Candidate &b) {
5717             // Return true if a and b are non-equal w.r.t. return address
5718             // signing or support of v8.3a features
5719             if (outliningCandidatesSigningScopeConsensus(a, b) &&
5720                 outliningCandidatesSigningKeyConsensus(a, b) &&
5721                 outliningCandidatesV8_3OpsConsensus(a, b)) {
5722               return false;
5723             }
5724             return true;
5725           }) != RepeatedSequenceLocs.end()) {
5726     return outliner::OutlinedFunction();
5727   }
5728 
5729   // Since at this point all candidates agree on their return address signing
5730   // picking just one is fine. If the candidate functions potentially sign their
5731   // return addresses, the outlined function should do the same. Note that in
5732   // the case of "sign-return-address"="non-leaf" this is an assumption: It is
5733   // not certainly true that the outlined function will have to sign its return
5734   // address but this decision is made later, when the decision to outline
5735   // has already been made.
5736   // The same holds for the number of additional instructions we need: On
5737   // v8.3a RET can be replaced by RETAA/RETAB and no AUT instruction is
5738   // necessary. However, at this point we don't know if the outlined function
5739   // will have a RET instruction so we assume the worst.
5740   const Function &FCF = FirstCand.getMF()->getFunction();
5741   const TargetRegisterInfo &TRI = getRegisterInfo();
5742   if (FCF.hasFnAttribute("sign-return-address")) {
5743     // One PAC and one AUT instructions
5744     NumBytesToCreateFrame += 8;
5745 
5746     // We have to check if sp modifying instructions would get outlined.
5747     // If so we only allow outlining if sp is unchanged overall, so matching
5748     // sub and add instructions are okay to outline, all other sp modifications
5749     // are not
5750     auto hasIllegalSPModification = [&TRI](outliner::Candidate &C) {
5751       int SPValue = 0;
5752       MachineBasicBlock::iterator MBBI = C.front();
5753       for (;;) {
5754         if (MBBI->modifiesRegister(AArch64::SP, &TRI)) {
5755           switch (MBBI->getOpcode()) {
5756           case AArch64::ADDXri:
5757           case AArch64::ADDWri:
5758             assert(MBBI->getNumOperands() == 4 && "Wrong number of operands");
5759             assert(MBBI->getOperand(2).isImm() &&
5760                    "Expected operand to be immediate");
5761             assert(MBBI->getOperand(1).isReg() &&
5762                    "Expected operand to be a register");
5763             // Check if the add just increments sp. If so, we search for
5764             // matching sub instructions that decrement sp. If not, the
5765             // modification is illegal
5766             if (MBBI->getOperand(1).getReg() == AArch64::SP)
5767               SPValue += MBBI->getOperand(2).getImm();
5768             else
5769               return true;
5770             break;
5771           case AArch64::SUBXri:
5772           case AArch64::SUBWri:
5773             assert(MBBI->getNumOperands() == 4 && "Wrong number of operands");
5774             assert(MBBI->getOperand(2).isImm() &&
5775                    "Expected operand to be immediate");
5776             assert(MBBI->getOperand(1).isReg() &&
5777                    "Expected operand to be a register");
5778             // Check if the sub just decrements sp. If so, we search for
5779             // matching add instructions that increment sp. If not, the
5780             // modification is illegal
5781             if (MBBI->getOperand(1).getReg() == AArch64::SP)
5782               SPValue -= MBBI->getOperand(2).getImm();
5783             else
5784               return true;
5785             break;
5786           default:
5787             return true;
5788           }
5789         }
5790         if (MBBI == C.back())
5791           break;
5792         ++MBBI;
5793       }
5794       if (SPValue)
5795         return true;
5796       return false;
5797     };
5798     // Remove candidates with illegal stack modifying instructions
5799     RepeatedSequenceLocs.erase(std::remove_if(RepeatedSequenceLocs.begin(),
5800                                               RepeatedSequenceLocs.end(),
5801                                               hasIllegalSPModification),
5802                                RepeatedSequenceLocs.end());
5803 
5804     // If the sequence doesn't have enough candidates left, then we're done.
5805     if (RepeatedSequenceLocs.size() < 2)
5806       return outliner::OutlinedFunction();
5807   }
5808 
5809   // Properties about candidate MBBs that hold for all of them.
5810   unsigned FlagsSetInAll = 0xF;
5811 
5812   // Compute liveness information for each candidate, and set FlagsSetInAll.
5813   std::for_each(RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
5814                 [&FlagsSetInAll](outliner::Candidate &C) {
5815                   FlagsSetInAll &= C.Flags;
5816                 });
5817 
5818   // According to the AArch64 Procedure Call Standard, the following are
5819   // undefined on entry/exit from a function call:
5820   //
5821   // * Registers x16, x17, (and thus w16, w17)
5822   // * Condition codes (and thus the NZCV register)
5823   //
5824   // Because if this, we can't outline any sequence of instructions where
5825   // one
5826   // of these registers is live into/across it. Thus, we need to delete
5827   // those
5828   // candidates.
5829   auto CantGuaranteeValueAcrossCall = [&TRI](outliner::Candidate &C) {
5830     // If the unsafe registers in this block are all dead, then we don't need
5831     // to compute liveness here.
5832     if (C.Flags & UnsafeRegsDead)
5833       return false;
5834     C.initLRU(TRI);
5835     LiveRegUnits LRU = C.LRU;
5836     return (!LRU.available(AArch64::W16) || !LRU.available(AArch64::W17) ||
5837             !LRU.available(AArch64::NZCV));
5838   };
5839 
5840   // Are there any candidates where those registers are live?
5841   if (!(FlagsSetInAll & UnsafeRegsDead)) {
5842     // Erase every candidate that violates the restrictions above. (It could be
5843     // true that we have viable candidates, so it's not worth bailing out in
5844     // the case that, say, 1 out of 20 candidates violate the restructions.)
5845     RepeatedSequenceLocs.erase(std::remove_if(RepeatedSequenceLocs.begin(),
5846                                               RepeatedSequenceLocs.end(),
5847                                               CantGuaranteeValueAcrossCall),
5848                                RepeatedSequenceLocs.end());
5849 
5850     // If the sequence doesn't have enough candidates left, then we're done.
5851     if (RepeatedSequenceLocs.size() < 2)
5852       return outliner::OutlinedFunction();
5853   }
5854 
5855   // At this point, we have only "safe" candidates to outline. Figure out
5856   // frame + call instruction information.
5857 
5858   unsigned LastInstrOpcode = RepeatedSequenceLocs[0].back()->getOpcode();
5859 
5860   // Helper lambda which sets call information for every candidate.
5861   auto SetCandidateCallInfo =
5862       [&RepeatedSequenceLocs](unsigned CallID, unsigned NumBytesForCall) {
5863         for (outliner::Candidate &C : RepeatedSequenceLocs)
5864           C.setCallInfo(CallID, NumBytesForCall);
5865       };
5866 
5867   unsigned FrameID = MachineOutlinerDefault;
5868   NumBytesToCreateFrame += 4;
5869 
5870   bool HasBTI = any_of(RepeatedSequenceLocs, [](outliner::Candidate &C) {
5871     return C.getMF()->getFunction().hasFnAttribute("branch-target-enforcement");
5872   });
5873 
5874   // We check to see if CFI Instructions are present, and if they are
5875   // we find the number of CFI Instructions in the candidates.
5876   unsigned CFICount = 0;
5877   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
5878   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
5879        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
5880     const std::vector<MCCFIInstruction> &CFIInstructions =
5881         RepeatedSequenceLocs[0].getMF()->getFrameInstructions();
5882     if (MBBI->isCFIInstruction()) {
5883       unsigned CFIIndex = MBBI->getOperand(0).getCFIIndex();
5884       MCCFIInstruction CFI = CFIInstructions[CFIIndex];
5885       CFICount++;
5886     }
5887     MBBI++;
5888   }
5889 
5890   // We compare the number of found CFI Instructions to  the number of CFI
5891   // instructions in the parent function for each candidate.  We must check this
5892   // since if we outline one of the CFI instructions in a function, we have to
5893   // outline them all for correctness. If we do not, the address offsets will be
5894   // incorrect between the two sections of the program.
5895   for (outliner::Candidate &C : RepeatedSequenceLocs) {
5896     std::vector<MCCFIInstruction> CFIInstructions =
5897         C.getMF()->getFrameInstructions();
5898 
5899     if (CFICount > 0 && CFICount != CFIInstructions.size())
5900       return outliner::OutlinedFunction();
5901   }
5902 
5903   // Returns true if an instructions is safe to fix up, false otherwise.
5904   auto IsSafeToFixup = [this, &TRI](MachineInstr &MI) {
5905     if (MI.isCall())
5906       return true;
5907 
5908     if (!MI.modifiesRegister(AArch64::SP, &TRI) &&
5909         !MI.readsRegister(AArch64::SP, &TRI))
5910       return true;
5911 
5912     // Any modification of SP will break our code to save/restore LR.
5913     // FIXME: We could handle some instructions which add a constant
5914     // offset to SP, with a bit more work.
5915     if (MI.modifiesRegister(AArch64::SP, &TRI))
5916       return false;
5917 
5918     // At this point, we have a stack instruction that we might need to
5919     // fix up. We'll handle it if it's a load or store.
5920     if (MI.mayLoadOrStore()) {
5921       const MachineOperand *Base; // Filled with the base operand of MI.
5922       int64_t Offset;             // Filled with the offset of MI.
5923       bool OffsetIsScalable;
5924 
5925       // Does it allow us to offset the base operand and is the base the
5926       // register SP?
5927       if (!getMemOperandWithOffset(MI, Base, Offset, OffsetIsScalable, &TRI) ||
5928           !Base->isReg() || Base->getReg() != AArch64::SP)
5929         return false;
5930 
5931       // Fixe-up code below assumes bytes.
5932       if (OffsetIsScalable)
5933         return false;
5934 
5935       // Find the minimum/maximum offset for this instruction and check
5936       // if fixing it up would be in range.
5937       int64_t MinOffset,
5938           MaxOffset;  // Unscaled offsets for the instruction.
5939       TypeSize Scale(0U, false); // The scale to multiply the offsets by.
5940       unsigned DummyWidth;
5941       getMemOpInfo(MI.getOpcode(), Scale, DummyWidth, MinOffset, MaxOffset);
5942 
5943       Offset += 16; // Update the offset to what it would be if we outlined.
5944       if (Offset < MinOffset * (int64_t)Scale.getFixedSize() ||
5945           Offset > MaxOffset * (int64_t)Scale.getFixedSize())
5946         return false;
5947 
5948       // It's in range, so we can outline it.
5949       return true;
5950     }
5951 
5952     // FIXME: Add handling for instructions like "add x0, sp, #8".
5953 
5954     // We can't fix it up, so don't outline it.
5955     return false;
5956   };
5957 
5958   // True if it's possible to fix up each stack instruction in this sequence.
5959   // Important for frames/call variants that modify the stack.
5960   bool AllStackInstrsSafe = std::all_of(
5961       FirstCand.front(), std::next(FirstCand.back()), IsSafeToFixup);
5962 
5963   // If the last instruction in any candidate is a terminator, then we should
5964   // tail call all of the candidates.
5965   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
5966     FrameID = MachineOutlinerTailCall;
5967     NumBytesToCreateFrame = 0;
5968     SetCandidateCallInfo(MachineOutlinerTailCall, 4);
5969   }
5970 
5971   else if (LastInstrOpcode == AArch64::BL ||
5972            (LastInstrOpcode == AArch64::BLR && !HasBTI)) {
5973     // FIXME: Do we need to check if the code after this uses the value of LR?
5974     FrameID = MachineOutlinerThunk;
5975     NumBytesToCreateFrame = 0;
5976     SetCandidateCallInfo(MachineOutlinerThunk, 4);
5977   }
5978 
5979   else {
5980     // We need to decide how to emit calls + frames. We can always emit the same
5981     // frame if we don't need to save to the stack. If we have to save to the
5982     // stack, then we need a different frame.
5983     unsigned NumBytesNoStackCalls = 0;
5984     std::vector<outliner::Candidate> CandidatesWithoutStackFixups;
5985 
5986     // Check if we have to save LR.
5987     for (outliner::Candidate &C : RepeatedSequenceLocs) {
5988       C.initLRU(TRI);
5989 
5990       // If we have a noreturn caller, then we're going to be conservative and
5991       // say that we have to save LR. If we don't have a ret at the end of the
5992       // block, then we can't reason about liveness accurately.
5993       //
5994       // FIXME: We can probably do better than always disabling this in
5995       // noreturn functions by fixing up the liveness info.
5996       bool IsNoReturn =
5997           C.getMF()->getFunction().hasFnAttribute(Attribute::NoReturn);
5998 
5999       // Is LR available? If so, we don't need a save.
6000       if (C.LRU.available(AArch64::LR) && !IsNoReturn) {
6001         NumBytesNoStackCalls += 4;
6002         C.setCallInfo(MachineOutlinerNoLRSave, 4);
6003         CandidatesWithoutStackFixups.push_back(C);
6004       }
6005 
6006       // Is an unused register available? If so, we won't modify the stack, so
6007       // we can outline with the same frame type as those that don't save LR.
6008       else if (findRegisterToSaveLRTo(C)) {
6009         NumBytesNoStackCalls += 12;
6010         C.setCallInfo(MachineOutlinerRegSave, 12);
6011         CandidatesWithoutStackFixups.push_back(C);
6012       }
6013 
6014       // Is SP used in the sequence at all? If not, we don't have to modify
6015       // the stack, so we are guaranteed to get the same frame.
6016       else if (C.UsedInSequence.available(AArch64::SP)) {
6017         NumBytesNoStackCalls += 12;
6018         C.setCallInfo(MachineOutlinerDefault, 12);
6019         CandidatesWithoutStackFixups.push_back(C);
6020       }
6021 
6022       // If we outline this, we need to modify the stack. Pretend we don't
6023       // outline this by saving all of its bytes.
6024       else {
6025         NumBytesNoStackCalls += SequenceSize;
6026       }
6027     }
6028 
6029     // If there are no places where we have to save LR, then note that we
6030     // don't have to update the stack. Otherwise, give every candidate the
6031     // default call type, as long as it's safe to do so.
6032     if (!AllStackInstrsSafe ||
6033         NumBytesNoStackCalls <= RepeatedSequenceLocs.size() * 12) {
6034       RepeatedSequenceLocs = CandidatesWithoutStackFixups;
6035       FrameID = MachineOutlinerNoLRSave;
6036     } else {
6037       SetCandidateCallInfo(MachineOutlinerDefault, 12);
6038     }
6039 
6040     // If we dropped all of the candidates, bail out here.
6041     if (RepeatedSequenceLocs.size() < 2) {
6042       RepeatedSequenceLocs.clear();
6043       return outliner::OutlinedFunction();
6044     }
6045   }
6046 
6047   // Does every candidate's MBB contain a call? If so, then we might have a call
6048   // in the range.
6049   if (FlagsSetInAll & MachineOutlinerMBBFlags::HasCalls) {
6050     // Check if the range contains a call. These require a save + restore of the
6051     // link register.
6052     bool ModStackToSaveLR = false;
6053     if (std::any_of(FirstCand.front(), FirstCand.back(),
6054                     [](const MachineInstr &MI) { return MI.isCall(); }))
6055       ModStackToSaveLR = true;
6056 
6057     // Handle the last instruction separately. If this is a tail call, then the
6058     // last instruction is a call. We don't want to save + restore in this case.
6059     // However, it could be possible that the last instruction is a call without
6060     // it being valid to tail call this sequence. We should consider this as
6061     // well.
6062     else if (FrameID != MachineOutlinerThunk &&
6063              FrameID != MachineOutlinerTailCall && FirstCand.back()->isCall())
6064       ModStackToSaveLR = true;
6065 
6066     if (ModStackToSaveLR) {
6067       // We can't fix up the stack. Bail out.
6068       if (!AllStackInstrsSafe) {
6069         RepeatedSequenceLocs.clear();
6070         return outliner::OutlinedFunction();
6071       }
6072 
6073       // Save + restore LR.
6074       NumBytesToCreateFrame += 8;
6075     }
6076   }
6077 
6078   // If we have CFI instructions, we can only outline if the outlined section
6079   // can be a tail call
6080   if (FrameID != MachineOutlinerTailCall && CFICount > 0)
6081     return outliner::OutlinedFunction();
6082 
6083   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
6084                                     NumBytesToCreateFrame, FrameID);
6085 }
6086 
6087 bool AArch64InstrInfo::isFunctionSafeToOutlineFrom(
6088     MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
6089   const Function &F = MF.getFunction();
6090 
6091   // Can F be deduplicated by the linker? If it can, don't outline from it.
6092   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
6093     return false;
6094 
6095   // Don't outline from functions with section markings; the program could
6096   // expect that all the code is in the named section.
6097   // FIXME: Allow outlining from multiple functions with the same section
6098   // marking.
6099   if (F.hasSection())
6100     return false;
6101 
6102   // Outlining from functions with redzones is unsafe since the outliner may
6103   // modify the stack. Check if hasRedZone is true or unknown; if yes, don't
6104   // outline from it.
6105   AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
6106   if (!AFI || AFI->hasRedZone().getValueOr(true))
6107     return false;
6108 
6109   // It's safe to outline from MF.
6110   return true;
6111 }
6112 
6113 bool AArch64InstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
6114                                               unsigned &Flags) const {
6115   // Check if LR is available through all of the MBB. If it's not, then set
6116   // a flag.
6117   assert(MBB.getParent()->getRegInfo().tracksLiveness() &&
6118          "Suitable Machine Function for outlining must track liveness");
6119   LiveRegUnits LRU(getRegisterInfo());
6120 
6121   std::for_each(MBB.rbegin(), MBB.rend(),
6122                 [&LRU](MachineInstr &MI) { LRU.accumulate(MI); });
6123 
6124   // Check if each of the unsafe registers are available...
6125   bool W16AvailableInBlock = LRU.available(AArch64::W16);
6126   bool W17AvailableInBlock = LRU.available(AArch64::W17);
6127   bool NZCVAvailableInBlock = LRU.available(AArch64::NZCV);
6128 
6129   // If all of these are dead (and not live out), we know we don't have to check
6130   // them later.
6131   if (W16AvailableInBlock && W17AvailableInBlock && NZCVAvailableInBlock)
6132     Flags |= MachineOutlinerMBBFlags::UnsafeRegsDead;
6133 
6134   // Now, add the live outs to the set.
6135   LRU.addLiveOuts(MBB);
6136 
6137   // If any of these registers is available in the MBB, but also a live out of
6138   // the block, then we know outlining is unsafe.
6139   if (W16AvailableInBlock && !LRU.available(AArch64::W16))
6140     return false;
6141   if (W17AvailableInBlock && !LRU.available(AArch64::W17))
6142     return false;
6143   if (NZCVAvailableInBlock && !LRU.available(AArch64::NZCV))
6144     return false;
6145 
6146   // Check if there's a call inside this MachineBasicBlock. If there is, then
6147   // set a flag.
6148   if (any_of(MBB, [](MachineInstr &MI) { return MI.isCall(); }))
6149     Flags |= MachineOutlinerMBBFlags::HasCalls;
6150 
6151   MachineFunction *MF = MBB.getParent();
6152 
6153   // In the event that we outline, we may have to save LR. If there is an
6154   // available register in the MBB, then we'll always save LR there. Check if
6155   // this is true.
6156   bool CanSaveLR = false;
6157   const AArch64RegisterInfo *ARI = static_cast<const AArch64RegisterInfo *>(
6158       MF->getSubtarget().getRegisterInfo());
6159 
6160   // Check if there is an available register across the sequence that we can
6161   // use.
6162   for (unsigned Reg : AArch64::GPR64RegClass) {
6163     if (!ARI->isReservedReg(*MF, Reg) && Reg != AArch64::LR &&
6164         Reg != AArch64::X16 && Reg != AArch64::X17 && LRU.available(Reg)) {
6165       CanSaveLR = true;
6166       break;
6167     }
6168   }
6169 
6170   // Check if we have a register we can save LR to, and if LR was used
6171   // somewhere. If both of those things are true, then we need to evaluate the
6172   // safety of outlining stack instructions later.
6173   if (!CanSaveLR && !LRU.available(AArch64::LR))
6174     Flags |= MachineOutlinerMBBFlags::LRUnavailableSomewhere;
6175 
6176   return true;
6177 }
6178 
6179 outliner::InstrType
6180 AArch64InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,
6181                                    unsigned Flags) const {
6182   MachineInstr &MI = *MIT;
6183   MachineBasicBlock *MBB = MI.getParent();
6184   MachineFunction *MF = MBB->getParent();
6185   AArch64FunctionInfo *FuncInfo = MF->getInfo<AArch64FunctionInfo>();
6186 
6187   // Don't outline anything used for return address signing. The outlined
6188   // function will get signed later if needed
6189   switch (MI.getOpcode()) {
6190   case AArch64::PACIASP:
6191   case AArch64::PACIBSP:
6192   case AArch64::AUTIASP:
6193   case AArch64::AUTIBSP:
6194   case AArch64::RETAA:
6195   case AArch64::RETAB:
6196   case AArch64::EMITBKEY:
6197     return outliner::InstrType::Illegal;
6198   }
6199 
6200   // Don't outline LOHs.
6201   if (FuncInfo->getLOHRelated().count(&MI))
6202     return outliner::InstrType::Illegal;
6203 
6204   // We can only outline these if we will tail call the outlined function, or
6205   // fix up the CFI offsets. Currently, CFI instructions are outlined only if
6206   // in a tail call.
6207   //
6208   // FIXME: If the proper fixups for the offset are implemented, this should be
6209   // possible.
6210   if (MI.isCFIInstruction())
6211     return outliner::InstrType::Legal;
6212 
6213   // Don't allow debug values to impact outlining type.
6214   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
6215     return outliner::InstrType::Invisible;
6216 
6217   // At this point, KILL instructions don't really tell us much so we can go
6218   // ahead and skip over them.
6219   if (MI.isKill())
6220     return outliner::InstrType::Invisible;
6221 
6222   // Is this a terminator for a basic block?
6223   if (MI.isTerminator()) {
6224 
6225     // Is this the end of a function?
6226     if (MI.getParent()->succ_empty())
6227       return outliner::InstrType::Legal;
6228 
6229     // It's not, so don't outline it.
6230     return outliner::InstrType::Illegal;
6231   }
6232 
6233   // Make sure none of the operands are un-outlinable.
6234   for (const MachineOperand &MOP : MI.operands()) {
6235     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
6236         MOP.isTargetIndex())
6237       return outliner::InstrType::Illegal;
6238 
6239     // If it uses LR or W30 explicitly, then don't touch it.
6240     if (MOP.isReg() && !MOP.isImplicit() &&
6241         (MOP.getReg() == AArch64::LR || MOP.getReg() == AArch64::W30))
6242       return outliner::InstrType::Illegal;
6243   }
6244 
6245   // Special cases for instructions that can always be outlined, but will fail
6246   // the later tests. e.g, ADRPs, which are PC-relative use LR, but can always
6247   // be outlined because they don't require a *specific* value to be in LR.
6248   if (MI.getOpcode() == AArch64::ADRP)
6249     return outliner::InstrType::Legal;
6250 
6251   // If MI is a call we might be able to outline it. We don't want to outline
6252   // any calls that rely on the position of items on the stack. When we outline
6253   // something containing a call, we have to emit a save and restore of LR in
6254   // the outlined function. Currently, this always happens by saving LR to the
6255   // stack. Thus, if we outline, say, half the parameters for a function call
6256   // plus the call, then we'll break the callee's expectations for the layout
6257   // of the stack.
6258   //
6259   // FIXME: Allow calls to functions which construct a stack frame, as long
6260   // as they don't access arguments on the stack.
6261   // FIXME: Figure out some way to analyze functions defined in other modules.
6262   // We should be able to compute the memory usage based on the IR calling
6263   // convention, even if we can't see the definition.
6264   if (MI.isCall()) {
6265     // Get the function associated with the call. Look at each operand and find
6266     // the one that represents the callee and get its name.
6267     const Function *Callee = nullptr;
6268     for (const MachineOperand &MOP : MI.operands()) {
6269       if (MOP.isGlobal()) {
6270         Callee = dyn_cast<Function>(MOP.getGlobal());
6271         break;
6272       }
6273     }
6274 
6275     // Never outline calls to mcount.  There isn't any rule that would require
6276     // this, but the Linux kernel's "ftrace" feature depends on it.
6277     if (Callee && Callee->getName() == "\01_mcount")
6278       return outliner::InstrType::Illegal;
6279 
6280     // If we don't know anything about the callee, assume it depends on the
6281     // stack layout of the caller. In that case, it's only legal to outline
6282     // as a tail-call.  Whitelist the call instructions we know about so we
6283     // don't get unexpected results with call pseudo-instructions.
6284     auto UnknownCallOutlineType = outliner::InstrType::Illegal;
6285     if (MI.getOpcode() == AArch64::BLR || MI.getOpcode() == AArch64::BL)
6286       UnknownCallOutlineType = outliner::InstrType::LegalTerminator;
6287 
6288     if (!Callee)
6289       return UnknownCallOutlineType;
6290 
6291     // We have a function we have information about. Check it if it's something
6292     // can safely outline.
6293     MachineFunction *CalleeMF = MF->getMMI().getMachineFunction(*Callee);
6294 
6295     // We don't know what's going on with the callee at all. Don't touch it.
6296     if (!CalleeMF)
6297       return UnknownCallOutlineType;
6298 
6299     // Check if we know anything about the callee saves on the function. If we
6300     // don't, then don't touch it, since that implies that we haven't
6301     // computed anything about its stack frame yet.
6302     MachineFrameInfo &MFI = CalleeMF->getFrameInfo();
6303     if (!MFI.isCalleeSavedInfoValid() || MFI.getStackSize() > 0 ||
6304         MFI.getNumObjects() > 0)
6305       return UnknownCallOutlineType;
6306 
6307     // At this point, we can say that CalleeMF ought to not pass anything on the
6308     // stack. Therefore, we can outline it.
6309     return outliner::InstrType::Legal;
6310   }
6311 
6312   // Don't outline positions.
6313   if (MI.isPosition())
6314     return outliner::InstrType::Illegal;
6315 
6316   // Don't touch the link register or W30.
6317   if (MI.readsRegister(AArch64::W30, &getRegisterInfo()) ||
6318       MI.modifiesRegister(AArch64::W30, &getRegisterInfo()))
6319     return outliner::InstrType::Illegal;
6320 
6321   // Don't outline BTI instructions, because that will prevent the outlining
6322   // site from being indirectly callable.
6323   if (MI.getOpcode() == AArch64::HINT) {
6324     int64_t Imm = MI.getOperand(0).getImm();
6325     if (Imm == 32 || Imm == 34 || Imm == 36 || Imm == 38)
6326       return outliner::InstrType::Illegal;
6327   }
6328 
6329   return outliner::InstrType::Legal;
6330 }
6331 
6332 void AArch64InstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const {
6333   for (MachineInstr &MI : MBB) {
6334     const MachineOperand *Base;
6335     unsigned Width;
6336     int64_t Offset;
6337     bool OffsetIsScalable;
6338 
6339     // Is this a load or store with an immediate offset with SP as the base?
6340     if (!MI.mayLoadOrStore() ||
6341         !getMemOperandWithOffsetWidth(MI, Base, Offset, OffsetIsScalable, Width,
6342                                       &RI) ||
6343         (Base->isReg() && Base->getReg() != AArch64::SP))
6344       continue;
6345 
6346     // It is, so we have to fix it up.
6347     TypeSize Scale(0U, false);
6348     int64_t Dummy1, Dummy2;
6349 
6350     MachineOperand &StackOffsetOperand = getMemOpBaseRegImmOfsOffsetOperand(MI);
6351     assert(StackOffsetOperand.isImm() && "Stack offset wasn't immediate!");
6352     getMemOpInfo(MI.getOpcode(), Scale, Width, Dummy1, Dummy2);
6353     assert(Scale != 0 && "Unexpected opcode!");
6354     assert(!OffsetIsScalable && "Expected offset to be a byte offset");
6355 
6356     // We've pushed the return address to the stack, so add 16 to the offset.
6357     // This is safe, since we already checked if it would overflow when we
6358     // checked if this instruction was legal to outline.
6359     int64_t NewImm = (Offset + 16) / (int64_t)Scale.getFixedSize();
6360     StackOffsetOperand.setImm(NewImm);
6361   }
6362 }
6363 
6364 static void signOutlinedFunction(MachineFunction &MF, MachineBasicBlock &MBB,
6365                                  bool ShouldSignReturnAddr,
6366                                  bool ShouldSignReturnAddrWithAKey) {
6367   if (ShouldSignReturnAddr) {
6368     MachineBasicBlock::iterator MBBPAC = MBB.begin();
6369     MachineBasicBlock::iterator MBBAUT = MBB.getFirstTerminator();
6370     const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
6371     const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6372     DebugLoc DL;
6373 
6374     if (MBBAUT != MBB.end())
6375       DL = MBBAUT->getDebugLoc();
6376 
6377     // At the very beginning of the basic block we insert the following
6378     // depending on the key type
6379     //
6380     // a_key:                   b_key:
6381     //    PACIASP                   EMITBKEY
6382     //    CFI_INSTRUCTION           PACIBSP
6383     //                              CFI_INSTRUCTION
6384     if (ShouldSignReturnAddrWithAKey) {
6385       BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::PACIASP))
6386           .setMIFlag(MachineInstr::FrameSetup);
6387     } else {
6388       BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::EMITBKEY))
6389           .setMIFlag(MachineInstr::FrameSetup);
6390       BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::PACIBSP))
6391           .setMIFlag(MachineInstr::FrameSetup);
6392     }
6393     unsigned CFIIndex =
6394         MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
6395     BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::CFI_INSTRUCTION))
6396         .addCFIIndex(CFIIndex)
6397         .setMIFlags(MachineInstr::FrameSetup);
6398 
6399     // If v8.3a features are available we can replace a RET instruction by
6400     // RETAA or RETAB and omit the AUT instructions
6401     if (Subtarget.hasV8_3aOps() && MBBAUT != MBB.end() &&
6402         MBBAUT->getOpcode() == AArch64::RET) {
6403       BuildMI(MBB, MBBAUT, DL,
6404               TII->get(ShouldSignReturnAddrWithAKey ? AArch64::RETAA
6405                                                     : AArch64::RETAB))
6406           .copyImplicitOps(*MBBAUT);
6407       MBB.erase(MBBAUT);
6408     } else {
6409       BuildMI(MBB, MBBAUT, DL,
6410               TII->get(ShouldSignReturnAddrWithAKey ? AArch64::AUTIASP
6411                                                     : AArch64::AUTIBSP))
6412           .setMIFlag(MachineInstr::FrameDestroy);
6413     }
6414   }
6415 }
6416 
6417 void AArch64InstrInfo::buildOutlinedFrame(
6418     MachineBasicBlock &MBB, MachineFunction &MF,
6419     const outliner::OutlinedFunction &OF) const {
6420 
6421   AArch64FunctionInfo *FI = MF.getInfo<AArch64FunctionInfo>();
6422 
6423   if (OF.FrameConstructionID == MachineOutlinerTailCall)
6424     FI->setOutliningStyle("Tail Call");
6425   else if (OF.FrameConstructionID == MachineOutlinerThunk) {
6426     // For thunk outlining, rewrite the last instruction from a call to a
6427     // tail-call.
6428     MachineInstr *Call = &*--MBB.instr_end();
6429     unsigned TailOpcode;
6430     if (Call->getOpcode() == AArch64::BL) {
6431       TailOpcode = AArch64::TCRETURNdi;
6432     } else {
6433       assert(Call->getOpcode() == AArch64::BLR);
6434       TailOpcode = AArch64::TCRETURNriALL;
6435     }
6436     MachineInstr *TC = BuildMI(MF, DebugLoc(), get(TailOpcode))
6437                            .add(Call->getOperand(0))
6438                            .addImm(0);
6439     MBB.insert(MBB.end(), TC);
6440     Call->eraseFromParent();
6441 
6442     FI->setOutliningStyle("Thunk");
6443   }
6444 
6445   bool IsLeafFunction = true;
6446 
6447   // Is there a call in the outlined range?
6448   auto IsNonTailCall = [](const MachineInstr &MI) {
6449     return MI.isCall() && !MI.isReturn();
6450   };
6451 
6452   if (std::any_of(MBB.instr_begin(), MBB.instr_end(), IsNonTailCall)) {
6453     // Fix up the instructions in the range, since we're going to modify the
6454     // stack.
6455     assert(OF.FrameConstructionID != MachineOutlinerDefault &&
6456            "Can only fix up stack references once");
6457     fixupPostOutline(MBB);
6458 
6459     IsLeafFunction = false;
6460 
6461     // LR has to be a live in so that we can save it.
6462     if (!MBB.isLiveIn(AArch64::LR))
6463       MBB.addLiveIn(AArch64::LR);
6464 
6465     MachineBasicBlock::iterator It = MBB.begin();
6466     MachineBasicBlock::iterator Et = MBB.end();
6467 
6468     if (OF.FrameConstructionID == MachineOutlinerTailCall ||
6469         OF.FrameConstructionID == MachineOutlinerThunk)
6470       Et = std::prev(MBB.end());
6471 
6472     // Insert a save before the outlined region
6473     MachineInstr *STRXpre = BuildMI(MF, DebugLoc(), get(AArch64::STRXpre))
6474                                 .addReg(AArch64::SP, RegState::Define)
6475                                 .addReg(AArch64::LR)
6476                                 .addReg(AArch64::SP)
6477                                 .addImm(-16);
6478     It = MBB.insert(It, STRXpre);
6479 
6480     const TargetSubtargetInfo &STI = MF.getSubtarget();
6481     const MCRegisterInfo *MRI = STI.getRegisterInfo();
6482     unsigned DwarfReg = MRI->getDwarfRegNum(AArch64::LR, true);
6483 
6484     // Add a CFI saying the stack was moved 16 B down.
6485     int64_t StackPosEntry =
6486         MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 16));
6487     BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
6488         .addCFIIndex(StackPosEntry)
6489         .setMIFlags(MachineInstr::FrameSetup);
6490 
6491     // Add a CFI saying that the LR that we want to find is now 16 B higher than
6492     // before.
6493     int64_t LRPosEntry =
6494         MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg, 16));
6495     BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
6496         .addCFIIndex(LRPosEntry)
6497         .setMIFlags(MachineInstr::FrameSetup);
6498 
6499     // Insert a restore before the terminator for the function.
6500     MachineInstr *LDRXpost = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost))
6501                                  .addReg(AArch64::SP, RegState::Define)
6502                                  .addReg(AArch64::LR, RegState::Define)
6503                                  .addReg(AArch64::SP)
6504                                  .addImm(16);
6505     Et = MBB.insert(Et, LDRXpost);
6506   }
6507 
6508   // If a bunch of candidates reach this point they must agree on their return
6509   // address signing. It is therefore enough to just consider the signing
6510   // behaviour of one of them
6511   const Function &CF = OF.Candidates.front().getMF()->getFunction();
6512   bool ShouldSignReturnAddr = false;
6513   if (CF.hasFnAttribute("sign-return-address")) {
6514     StringRef Scope =
6515         CF.getFnAttribute("sign-return-address").getValueAsString();
6516     if (Scope.equals("all"))
6517       ShouldSignReturnAddr = true;
6518     else if (Scope.equals("non-leaf") && !IsLeafFunction)
6519       ShouldSignReturnAddr = true;
6520   }
6521 
6522   // a_key is the default
6523   bool ShouldSignReturnAddrWithAKey = true;
6524   if (CF.hasFnAttribute("sign-return-address-key")) {
6525     const StringRef Key =
6526         CF.getFnAttribute("sign-return-address-key").getValueAsString();
6527     // Key can either be a_key or b_key
6528     assert((Key.equals_lower("a_key") || Key.equals_lower("b_key")) &&
6529            "Return address signing key must be either a_key or b_key");
6530     ShouldSignReturnAddrWithAKey = Key.equals_lower("a_key");
6531   }
6532 
6533   // If this is a tail call outlined function, then there's already a return.
6534   if (OF.FrameConstructionID == MachineOutlinerTailCall ||
6535       OF.FrameConstructionID == MachineOutlinerThunk) {
6536     signOutlinedFunction(MF, MBB, ShouldSignReturnAddr,
6537                          ShouldSignReturnAddrWithAKey);
6538     return;
6539   }
6540 
6541   // It's not a tail call, so we have to insert the return ourselves.
6542 
6543   // LR has to be a live in so that we can return to it.
6544   if (!MBB.isLiveIn(AArch64::LR))
6545     MBB.addLiveIn(AArch64::LR);
6546 
6547   MachineInstr *ret = BuildMI(MF, DebugLoc(), get(AArch64::RET))
6548                           .addReg(AArch64::LR);
6549   MBB.insert(MBB.end(), ret);
6550 
6551   signOutlinedFunction(MF, MBB, ShouldSignReturnAddr,
6552                        ShouldSignReturnAddrWithAKey);
6553 
6554   FI->setOutliningStyle("Function");
6555 
6556   // Did we have to modify the stack by saving the link register?
6557   if (OF.FrameConstructionID != MachineOutlinerDefault)
6558     return;
6559 
6560   // We modified the stack.
6561   // Walk over the basic block and fix up all the stack accesses.
6562   fixupPostOutline(MBB);
6563 }
6564 
6565 MachineBasicBlock::iterator AArch64InstrInfo::insertOutlinedCall(
6566     Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
6567     MachineFunction &MF, const outliner::Candidate &C) const {
6568 
6569   // Are we tail calling?
6570   if (C.CallConstructionID == MachineOutlinerTailCall) {
6571     // If yes, then we can just branch to the label.
6572     It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::TCRETURNdi))
6573                             .addGlobalAddress(M.getNamedValue(MF.getName()))
6574                             .addImm(0));
6575     return It;
6576   }
6577 
6578   // Are we saving the link register?
6579   if (C.CallConstructionID == MachineOutlinerNoLRSave ||
6580       C.CallConstructionID == MachineOutlinerThunk) {
6581     // No, so just insert the call.
6582     It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::BL))
6583                             .addGlobalAddress(M.getNamedValue(MF.getName())));
6584     return It;
6585   }
6586 
6587   // We want to return the spot where we inserted the call.
6588   MachineBasicBlock::iterator CallPt;
6589 
6590   // Instructions for saving and restoring LR around the call instruction we're
6591   // going to insert.
6592   MachineInstr *Save;
6593   MachineInstr *Restore;
6594   // Can we save to a register?
6595   if (C.CallConstructionID == MachineOutlinerRegSave) {
6596     // FIXME: This logic should be sunk into a target-specific interface so that
6597     // we don't have to recompute the register.
6598     unsigned Reg = findRegisterToSaveLRTo(C);
6599     assert(Reg != 0 && "No callee-saved register available?");
6600 
6601     // Save and restore LR from that register.
6602     Save = BuildMI(MF, DebugLoc(), get(AArch64::ORRXrs), Reg)
6603                .addReg(AArch64::XZR)
6604                .addReg(AArch64::LR)
6605                .addImm(0);
6606     Restore = BuildMI(MF, DebugLoc(), get(AArch64::ORRXrs), AArch64::LR)
6607                 .addReg(AArch64::XZR)
6608                 .addReg(Reg)
6609                 .addImm(0);
6610   } else {
6611     // We have the default case. Save and restore from SP.
6612     Save = BuildMI(MF, DebugLoc(), get(AArch64::STRXpre))
6613                .addReg(AArch64::SP, RegState::Define)
6614                .addReg(AArch64::LR)
6615                .addReg(AArch64::SP)
6616                .addImm(-16);
6617     Restore = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost))
6618                   .addReg(AArch64::SP, RegState::Define)
6619                   .addReg(AArch64::LR, RegState::Define)
6620                   .addReg(AArch64::SP)
6621                   .addImm(16);
6622   }
6623 
6624   It = MBB.insert(It, Save);
6625   It++;
6626 
6627   // Insert the call.
6628   It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::BL))
6629                           .addGlobalAddress(M.getNamedValue(MF.getName())));
6630   CallPt = It;
6631   It++;
6632 
6633   It = MBB.insert(It, Restore);
6634   return CallPt;
6635 }
6636 
6637 bool AArch64InstrInfo::shouldOutlineFromFunctionByDefault(
6638   MachineFunction &MF) const {
6639   return MF.getFunction().hasMinSize();
6640 }
6641 
6642 Optional<DestSourcePair>
6643 AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
6644 
6645   // AArch64::ORRWrs and AArch64::ORRXrs with WZR/XZR reg
6646   // and zero immediate operands used as an alias for mov instruction.
6647   if (MI.getOpcode() == AArch64::ORRWrs &&
6648       MI.getOperand(1).getReg() == AArch64::WZR &&
6649       MI.getOperand(3).getImm() == 0x0) {
6650     return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
6651   }
6652 
6653   if (MI.getOpcode() == AArch64::ORRXrs &&
6654       MI.getOperand(1).getReg() == AArch64::XZR &&
6655       MI.getOperand(3).getImm() == 0x0) {
6656     return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
6657   }
6658 
6659   return None;
6660 }
6661 
6662 Optional<RegImmPair> AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
6663                                                       Register Reg) const {
6664   int Sign = 1;
6665   int64_t Offset = 0;
6666 
6667   // TODO: Handle cases where Reg is a super- or sub-register of the
6668   // destination register.
6669   const MachineOperand &Op0 = MI.getOperand(0);
6670   if (!Op0.isReg() || Reg != Op0.getReg())
6671     return None;
6672 
6673   switch (MI.getOpcode()) {
6674   default:
6675     return None;
6676   case AArch64::SUBWri:
6677   case AArch64::SUBXri:
6678   case AArch64::SUBSWri:
6679   case AArch64::SUBSXri:
6680     Sign *= -1;
6681     LLVM_FALLTHROUGH;
6682   case AArch64::ADDSWri:
6683   case AArch64::ADDSXri:
6684   case AArch64::ADDWri:
6685   case AArch64::ADDXri: {
6686     // TODO: Third operand can be global address (usually some string).
6687     if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
6688         !MI.getOperand(2).isImm())
6689       return None;
6690     Offset = MI.getOperand(2).getImm() * Sign;
6691     int Shift = MI.getOperand(3).getImm();
6692     assert((Shift == 0 || Shift == 12) && "Shift can be either 0 or 12");
6693     Offset = Offset << Shift;
6694   }
6695   }
6696   return RegImmPair{MI.getOperand(1).getReg(), Offset};
6697 }
6698 
6699 /// If the given ORR instruction is a copy, and \p DescribedReg overlaps with
6700 /// the destination register then, if possible, describe the value in terms of
6701 /// the source register.
6702 static Optional<ParamLoadedValue>
6703 describeORRLoadedValue(const MachineInstr &MI, Register DescribedReg,
6704                        const TargetInstrInfo *TII,
6705                        const TargetRegisterInfo *TRI) {
6706   auto DestSrc = TII->isCopyInstr(MI);
6707   if (!DestSrc)
6708     return None;
6709 
6710   Register DestReg = DestSrc->Destination->getReg();
6711   Register SrcReg = DestSrc->Source->getReg();
6712 
6713   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
6714 
6715   // If the described register is the destination, just return the source.
6716   if (DestReg == DescribedReg)
6717     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
6718 
6719   // ORRWrs zero-extends to 64-bits, so we need to consider such cases.
6720   if (MI.getOpcode() == AArch64::ORRWrs &&
6721       TRI->isSuperRegister(DestReg, DescribedReg))
6722     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
6723 
6724   // We may need to describe the lower part of a ORRXrs move.
6725   if (MI.getOpcode() == AArch64::ORRXrs &&
6726       TRI->isSubRegister(DestReg, DescribedReg)) {
6727     Register SrcSubReg = TRI->getSubReg(SrcReg, AArch64::sub_32);
6728     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
6729   }
6730 
6731   assert(!TRI->isSuperOrSubRegisterEq(DestReg, DescribedReg) &&
6732          "Unhandled ORR[XW]rs copy case");
6733 
6734   return None;
6735 }
6736 
6737 Optional<ParamLoadedValue>
6738 AArch64InstrInfo::describeLoadedValue(const MachineInstr &MI,
6739                                       Register Reg) const {
6740   const MachineFunction *MF = MI.getMF();
6741   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
6742   switch (MI.getOpcode()) {
6743   case AArch64::MOVZWi:
6744   case AArch64::MOVZXi: {
6745     // MOVZWi may be used for producing zero-extended 32-bit immediates in
6746     // 64-bit parameters, so we need to consider super-registers.
6747     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
6748       return None;
6749 
6750     if (!MI.getOperand(1).isImm())
6751       return None;
6752     int64_t Immediate = MI.getOperand(1).getImm();
6753     int Shift = MI.getOperand(2).getImm();
6754     return ParamLoadedValue(MachineOperand::CreateImm(Immediate << Shift),
6755                             nullptr);
6756   }
6757   case AArch64::ORRWrs:
6758   case AArch64::ORRXrs:
6759     return describeORRLoadedValue(MI, Reg, this, TRI);
6760   }
6761 
6762   return TargetInstrInfo::describeLoadedValue(MI, Reg);
6763 }
6764 
6765 uint64_t AArch64InstrInfo::getElementSizeForOpcode(unsigned Opc) const {
6766   return get(Opc).TSFlags & AArch64::ElementSizeMask;
6767 }
6768 
6769 #define GET_INSTRINFO_HELPERS
6770 #define GET_INSTRMAP_INFO
6771 #include "AArch64GenInstrInfo.inc"
6772