1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the AArch64TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AArch64ISelLowering.h" 15 #include "AArch64MachineFunctionInfo.h" 16 #include "AArch64PerfectShuffle.h" 17 #include "AArch64Subtarget.h" 18 #include "AArch64TargetMachine.h" 19 #include "AArch64TargetObjectFile.h" 20 #include "MCTargetDesc/AArch64AddressingModes.h" 21 #include "llvm/ADT/Statistic.h" 22 #include "llvm/CodeGen/CallingConvLower.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/IR/Intrinsics.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/Support/CommandLine.h" 30 #include "llvm/Support/Debug.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include "llvm/Target/TargetOptions.h" 34 using namespace llvm; 35 36 #define DEBUG_TYPE "aarch64-lower" 37 38 STATISTIC(NumTailCalls, "Number of tail calls"); 39 STATISTIC(NumShiftInserts, "Number of vector shift inserts"); 40 41 namespace { 42 enum AlignMode { 43 StrictAlign, 44 NoStrictAlign 45 }; 46 } 47 48 static cl::opt<AlignMode> 49 Align(cl::desc("Load/store alignment support"), 50 cl::Hidden, cl::init(NoStrictAlign), 51 cl::values( 52 clEnumValN(StrictAlign, "aarch64-strict-align", 53 "Disallow all unaligned memory accesses"), 54 clEnumValN(NoStrictAlign, "aarch64-no-strict-align", 55 "Allow unaligned memory accesses"), 56 clEnumValEnd)); 57 58 // Place holder until extr generation is tested fully. 59 static cl::opt<bool> 60 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden, 61 cl::desc("Allow AArch64 (or (shift)(shift))->extract"), 62 cl::init(true)); 63 64 static cl::opt<bool> 65 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden, 66 cl::desc("Allow AArch64 SLI/SRI formation"), 67 cl::init(false)); 68 69 //===----------------------------------------------------------------------===// 70 // AArch64 Lowering public interface. 71 //===----------------------------------------------------------------------===// 72 static TargetLoweringObjectFile *createTLOF(const Triple &TT) { 73 if (TT.isOSBinFormatMachO()) 74 return new AArch64_MachoTargetObjectFile(); 75 76 return new AArch64_ELFTargetObjectFile(); 77 } 78 79 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM) 80 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) { 81 Subtarget = &TM.getSubtarget<AArch64Subtarget>(); 82 83 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so 84 // we have to make something up. Arbitrarily, choose ZeroOrOne. 85 setBooleanContents(ZeroOrOneBooleanContent); 86 // When comparing vectors the result sets the different elements in the 87 // vector to all-one or all-zero. 88 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 89 90 // Set up the register classes. 91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); 92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); 93 94 if (Subtarget->hasFPARMv8()) { 95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); 96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); 97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); 98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); 99 } 100 101 if (Subtarget->hasNEON()) { 102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); 103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); 104 // Someone set us up the NEON. 105 addDRTypeForNEON(MVT::v2f32); 106 addDRTypeForNEON(MVT::v8i8); 107 addDRTypeForNEON(MVT::v4i16); 108 addDRTypeForNEON(MVT::v2i32); 109 addDRTypeForNEON(MVT::v1i64); 110 addDRTypeForNEON(MVT::v1f64); 111 addDRTypeForNEON(MVT::v4f16); 112 113 addQRTypeForNEON(MVT::v4f32); 114 addQRTypeForNEON(MVT::v2f64); 115 addQRTypeForNEON(MVT::v16i8); 116 addQRTypeForNEON(MVT::v8i16); 117 addQRTypeForNEON(MVT::v4i32); 118 addQRTypeForNEON(MVT::v2i64); 119 addQRTypeForNEON(MVT::v8f16); 120 } 121 122 // Compute derived properties from the register classes 123 computeRegisterProperties(); 124 125 // Provide all sorts of operation actions 126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 127 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 128 setOperationAction(ISD::SETCC, MVT::i32, Custom); 129 setOperationAction(ISD::SETCC, MVT::i64, Custom); 130 setOperationAction(ISD::SETCC, MVT::f32, Custom); 131 setOperationAction(ISD::SETCC, MVT::f64, Custom); 132 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 133 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 134 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 135 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 136 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 137 setOperationAction(ISD::SELECT, MVT::i32, Custom); 138 setOperationAction(ISD::SELECT, MVT::i64, Custom); 139 setOperationAction(ISD::SELECT, MVT::f32, Custom); 140 setOperationAction(ISD::SELECT, MVT::f64, Custom); 141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 145 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 146 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 147 148 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 149 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 150 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 151 152 setOperationAction(ISD::FREM, MVT::f32, Expand); 153 setOperationAction(ISD::FREM, MVT::f64, Expand); 154 setOperationAction(ISD::FREM, MVT::f80, Expand); 155 156 // Custom lowering hooks are needed for XOR 157 // to fold it into CSINC/CSINV. 158 setOperationAction(ISD::XOR, MVT::i32, Custom); 159 setOperationAction(ISD::XOR, MVT::i64, Custom); 160 161 // Virtually no operation on f128 is legal, but LLVM can't expand them when 162 // there's a valid register class, so we need custom operations in most cases. 163 setOperationAction(ISD::FABS, MVT::f128, Expand); 164 setOperationAction(ISD::FADD, MVT::f128, Custom); 165 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); 166 setOperationAction(ISD::FCOS, MVT::f128, Expand); 167 setOperationAction(ISD::FDIV, MVT::f128, Custom); 168 setOperationAction(ISD::FMA, MVT::f128, Expand); 169 setOperationAction(ISD::FMUL, MVT::f128, Custom); 170 setOperationAction(ISD::FNEG, MVT::f128, Expand); 171 setOperationAction(ISD::FPOW, MVT::f128, Expand); 172 setOperationAction(ISD::FREM, MVT::f128, Expand); 173 setOperationAction(ISD::FRINT, MVT::f128, Expand); 174 setOperationAction(ISD::FSIN, MVT::f128, Expand); 175 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); 176 setOperationAction(ISD::FSQRT, MVT::f128, Expand); 177 setOperationAction(ISD::FSUB, MVT::f128, Custom); 178 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 179 setOperationAction(ISD::SETCC, MVT::f128, Custom); 180 setOperationAction(ISD::BR_CC, MVT::f128, Custom); 181 setOperationAction(ISD::SELECT, MVT::f128, Custom); 182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 183 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); 184 185 // Lowering for many of the conversions is actually specified by the non-f128 186 // type. The LowerXXX function will be trivial when f128 isn't involved. 187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 188 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 189 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); 190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 191 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 192 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom); 193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 194 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 195 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); 196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 197 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 198 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); 199 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); 200 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); 201 202 // Variable arguments. 203 setOperationAction(ISD::VASTART, MVT::Other, Custom); 204 setOperationAction(ISD::VAARG, MVT::Other, Custom); 205 setOperationAction(ISD::VACOPY, MVT::Other, Custom); 206 setOperationAction(ISD::VAEND, MVT::Other, Expand); 207 208 // Variable-sized objects. 209 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 210 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 211 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 212 213 // Exception handling. 214 // FIXME: These are guesses. Has this been defined yet? 215 setExceptionPointerRegister(AArch64::X0); 216 setExceptionSelectorRegister(AArch64::X1); 217 218 // Constant pool entries 219 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 220 221 // BlockAddress 222 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 223 224 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences. 225 setOperationAction(ISD::ADDC, MVT::i32, Custom); 226 setOperationAction(ISD::ADDE, MVT::i32, Custom); 227 setOperationAction(ISD::SUBC, MVT::i32, Custom); 228 setOperationAction(ISD::SUBE, MVT::i32, Custom); 229 setOperationAction(ISD::ADDC, MVT::i64, Custom); 230 setOperationAction(ISD::ADDE, MVT::i64, Custom); 231 setOperationAction(ISD::SUBC, MVT::i64, Custom); 232 setOperationAction(ISD::SUBE, MVT::i64, Custom); 233 234 // AArch64 lacks both left-rotate and popcount instructions. 235 setOperationAction(ISD::ROTL, MVT::i32, Expand); 236 setOperationAction(ISD::ROTL, MVT::i64, Expand); 237 238 // AArch64 doesn't have {U|S}MUL_LOHI. 239 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 240 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 241 242 243 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero 244 // counterparts, which AArch64 supports directly. 245 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 249 250 setOperationAction(ISD::CTPOP, MVT::i32, Custom); 251 setOperationAction(ISD::CTPOP, MVT::i64, Custom); 252 253 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 254 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 255 setOperationAction(ISD::SREM, MVT::i32, Expand); 256 setOperationAction(ISD::SREM, MVT::i64, Expand); 257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 258 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 259 setOperationAction(ISD::UREM, MVT::i32, Expand); 260 setOperationAction(ISD::UREM, MVT::i64, Expand); 261 262 // Custom lower Add/Sub/Mul with overflow. 263 setOperationAction(ISD::SADDO, MVT::i32, Custom); 264 setOperationAction(ISD::SADDO, MVT::i64, Custom); 265 setOperationAction(ISD::UADDO, MVT::i32, Custom); 266 setOperationAction(ISD::UADDO, MVT::i64, Custom); 267 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 268 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 269 setOperationAction(ISD::USUBO, MVT::i32, Custom); 270 setOperationAction(ISD::USUBO, MVT::i64, Custom); 271 setOperationAction(ISD::SMULO, MVT::i32, Custom); 272 setOperationAction(ISD::SMULO, MVT::i64, Custom); 273 setOperationAction(ISD::UMULO, MVT::i32, Custom); 274 setOperationAction(ISD::UMULO, MVT::i64, Custom); 275 276 setOperationAction(ISD::FSIN, MVT::f32, Expand); 277 setOperationAction(ISD::FSIN, MVT::f64, Expand); 278 setOperationAction(ISD::FCOS, MVT::f32, Expand); 279 setOperationAction(ISD::FCOS, MVT::f64, Expand); 280 setOperationAction(ISD::FPOW, MVT::f32, Expand); 281 setOperationAction(ISD::FPOW, MVT::f64, Expand); 282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 284 285 // f16 is storage-only, so we promote operations to f32 if we know this is 286 // valid, and ignore them otherwise. The operations not mentioned here will 287 // fail to select, but this is not a major problem as no source language 288 // should be emitting native f16 operations yet. 289 setOperationAction(ISD::FADD, MVT::f16, Promote); 290 setOperationAction(ISD::FDIV, MVT::f16, Promote); 291 setOperationAction(ISD::FMUL, MVT::f16, Promote); 292 setOperationAction(ISD::FSUB, MVT::f16, Promote); 293 294 // v4f16 is also a storage-only type, so promote it to v4f32 when that is 295 // known to be safe. 296 setOperationAction(ISD::FADD, MVT::v4f16, Promote); 297 setOperationAction(ISD::FSUB, MVT::v4f16, Promote); 298 setOperationAction(ISD::FMUL, MVT::v4f16, Promote); 299 setOperationAction(ISD::FDIV, MVT::v4f16, Promote); 300 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); 301 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); 302 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32); 303 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32); 304 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32); 305 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32); 306 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); 307 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); 308 309 // Expand all other v4f16 operations. 310 // FIXME: We could generate better code by promoting some operations to 311 // a pair of v4f32s 312 setOperationAction(ISD::FABS, MVT::v4f16, Expand); 313 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand); 314 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand); 315 setOperationAction(ISD::FCOS, MVT::v4f16, Expand); 316 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand); 317 setOperationAction(ISD::FMA, MVT::v4f16, Expand); 318 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand); 319 setOperationAction(ISD::FNEG, MVT::v4f16, Expand); 320 setOperationAction(ISD::FPOW, MVT::v4f16, Expand); 321 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand); 322 setOperationAction(ISD::FREM, MVT::v4f16, Expand); 323 setOperationAction(ISD::FROUND, MVT::v4f16, Expand); 324 setOperationAction(ISD::FRINT, MVT::v4f16, Expand); 325 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); 326 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand); 327 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand); 328 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand); 329 setOperationAction(ISD::SETCC, MVT::v4f16, Expand); 330 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand); 331 setOperationAction(ISD::SELECT, MVT::v4f16, Expand); 332 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand); 333 setOperationAction(ISD::FEXP, MVT::v4f16, Expand); 334 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand); 335 setOperationAction(ISD::FLOG, MVT::v4f16, Expand); 336 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand); 337 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand); 338 339 340 // v8f16 is also a storage-only type, so expand it. 341 setOperationAction(ISD::FABS, MVT::v8f16, Expand); 342 setOperationAction(ISD::FADD, MVT::v8f16, Expand); 343 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand); 344 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand); 345 setOperationAction(ISD::FCOS, MVT::v8f16, Expand); 346 setOperationAction(ISD::FDIV, MVT::v8f16, Expand); 347 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand); 348 setOperationAction(ISD::FMA, MVT::v8f16, Expand); 349 setOperationAction(ISD::FMUL, MVT::v8f16, Expand); 350 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand); 351 setOperationAction(ISD::FNEG, MVT::v8f16, Expand); 352 setOperationAction(ISD::FPOW, MVT::v8f16, Expand); 353 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand); 354 setOperationAction(ISD::FREM, MVT::v8f16, Expand); 355 setOperationAction(ISD::FROUND, MVT::v8f16, Expand); 356 setOperationAction(ISD::FRINT, MVT::v8f16, Expand); 357 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); 358 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); 359 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand); 360 setOperationAction(ISD::FSUB, MVT::v8f16, Expand); 361 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand); 362 setOperationAction(ISD::SETCC, MVT::v8f16, Expand); 363 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand); 364 setOperationAction(ISD::SELECT, MVT::v8f16, Expand); 365 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand); 366 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); 367 setOperationAction(ISD::FEXP, MVT::v8f16, Expand); 368 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand); 369 setOperationAction(ISD::FLOG, MVT::v8f16, Expand); 370 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand); 371 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand); 372 373 // AArch64 has implementations of a lot of rounding-like FP operations. 374 static MVT RoundingTypes[] = { MVT::f32, MVT::f64}; 375 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) { 376 MVT Ty = RoundingTypes[I]; 377 setOperationAction(ISD::FFLOOR, Ty, Legal); 378 setOperationAction(ISD::FNEARBYINT, Ty, Legal); 379 setOperationAction(ISD::FCEIL, Ty, Legal); 380 setOperationAction(ISD::FRINT, Ty, Legal); 381 setOperationAction(ISD::FTRUNC, Ty, Legal); 382 setOperationAction(ISD::FROUND, Ty, Legal); 383 } 384 385 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 386 387 if (Subtarget->isTargetMachO()) { 388 // For iOS, we don't want to the normal expansion of a libcall to 389 // sincos. We want to issue a libcall to __sincos_stret to avoid memory 390 // traffic. 391 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); 392 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); 393 } else { 394 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 395 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 396 } 397 398 // AArch64 does not have floating-point extending loads, i1 sign-extending 399 // load, floating-point truncating stores, or v2i32->v2i16 truncating store. 400 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand); 401 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 402 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 403 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand); 404 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand); 405 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 406 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 407 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 408 setTruncStoreAction(MVT::f128, MVT::f80, Expand); 409 setTruncStoreAction(MVT::f128, MVT::f64, Expand); 410 setTruncStoreAction(MVT::f128, MVT::f32, Expand); 411 setTruncStoreAction(MVT::f128, MVT::f16, Expand); 412 413 setOperationAction(ISD::BITCAST, MVT::i16, Custom); 414 setOperationAction(ISD::BITCAST, MVT::f16, Custom); 415 416 // Indexed loads and stores are supported. 417 for (unsigned im = (unsigned)ISD::PRE_INC; 418 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 419 setIndexedLoadAction(im, MVT::i8, Legal); 420 setIndexedLoadAction(im, MVT::i16, Legal); 421 setIndexedLoadAction(im, MVT::i32, Legal); 422 setIndexedLoadAction(im, MVT::i64, Legal); 423 setIndexedLoadAction(im, MVT::f64, Legal); 424 setIndexedLoadAction(im, MVT::f32, Legal); 425 setIndexedStoreAction(im, MVT::i8, Legal); 426 setIndexedStoreAction(im, MVT::i16, Legal); 427 setIndexedStoreAction(im, MVT::i32, Legal); 428 setIndexedStoreAction(im, MVT::i64, Legal); 429 setIndexedStoreAction(im, MVT::f64, Legal); 430 setIndexedStoreAction(im, MVT::f32, Legal); 431 } 432 433 // Trap. 434 setOperationAction(ISD::TRAP, MVT::Other, Legal); 435 436 // We combine OR nodes for bitfield operations. 437 setTargetDAGCombine(ISD::OR); 438 439 // Vector add and sub nodes may conceal a high-half opportunity. 440 // Also, try to fold ADD into CSINC/CSINV.. 441 setTargetDAGCombine(ISD::ADD); 442 setTargetDAGCombine(ISD::SUB); 443 444 setTargetDAGCombine(ISD::XOR); 445 setTargetDAGCombine(ISD::SINT_TO_FP); 446 setTargetDAGCombine(ISD::UINT_TO_FP); 447 448 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 449 450 setTargetDAGCombine(ISD::ANY_EXTEND); 451 setTargetDAGCombine(ISD::ZERO_EXTEND); 452 setTargetDAGCombine(ISD::SIGN_EXTEND); 453 setTargetDAGCombine(ISD::BITCAST); 454 setTargetDAGCombine(ISD::CONCAT_VECTORS); 455 setTargetDAGCombine(ISD::STORE); 456 457 setTargetDAGCombine(ISD::MUL); 458 459 setTargetDAGCombine(ISD::SELECT); 460 setTargetDAGCombine(ISD::VSELECT); 461 462 setTargetDAGCombine(ISD::INTRINSIC_VOID); 463 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 464 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 465 466 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8; 467 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4; 468 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4; 469 470 setStackPointerRegisterToSaveRestore(AArch64::SP); 471 472 setSchedulingPreference(Sched::Hybrid); 473 474 // Enable TBZ/TBNZ 475 MaskAndBranchFoldingIsLegal = true; 476 477 setMinFunctionAlignment(2); 478 479 RequireStrictAlign = (Align == StrictAlign); 480 481 setHasExtractBitsInsn(true); 482 483 if (Subtarget->hasNEON()) { 484 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to 485 // silliness like this: 486 setOperationAction(ISD::FABS, MVT::v1f64, Expand); 487 setOperationAction(ISD::FADD, MVT::v1f64, Expand); 488 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); 489 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); 490 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); 491 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); 492 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand); 493 setOperationAction(ISD::FMA, MVT::v1f64, Expand); 494 setOperationAction(ISD::FMUL, MVT::v1f64, Expand); 495 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand); 496 setOperationAction(ISD::FNEG, MVT::v1f64, Expand); 497 setOperationAction(ISD::FPOW, MVT::v1f64, Expand); 498 setOperationAction(ISD::FREM, MVT::v1f64, Expand); 499 setOperationAction(ISD::FROUND, MVT::v1f64, Expand); 500 setOperationAction(ISD::FRINT, MVT::v1f64, Expand); 501 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); 502 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); 503 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand); 504 setOperationAction(ISD::FSUB, MVT::v1f64, Expand); 505 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand); 506 setOperationAction(ISD::SETCC, MVT::v1f64, Expand); 507 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand); 508 setOperationAction(ISD::SELECT, MVT::v1f64, Expand); 509 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand); 510 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); 511 512 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); 513 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand); 514 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); 515 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); 516 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); 517 518 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 519 520 // AArch64 doesn't have a direct vector ->f32 conversion instructions for 521 // elements smaller than i32, so promote the input to i32 first. 522 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote); 523 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); 524 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote); 525 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); 526 // Similarly, there is no direct i32 -> f64 vector conversion instruction. 527 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 528 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom); 529 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom); 530 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom); 531 532 // AArch64 doesn't have MUL.2d: 533 setOperationAction(ISD::MUL, MVT::v2i64, Expand); 534 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); 535 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); 536 // Likewise, narrowing and extending vector loads/stores aren't handled 537 // directly. 538 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 539 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 540 541 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 542 Expand); 543 544 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand); 545 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 546 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand); 547 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 548 549 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 550 551 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 552 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 553 setTruncStoreAction((MVT::SimpleValueType)VT, 554 (MVT::SimpleValueType)InnerVT, Expand); 555 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 556 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 557 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 558 } 559 560 // AArch64 has implementations of a lot of rounding-like FP operations. 561 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 }; 562 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) { 563 MVT Ty = RoundingVecTypes[I]; 564 setOperationAction(ISD::FFLOOR, Ty, Legal); 565 setOperationAction(ISD::FNEARBYINT, Ty, Legal); 566 setOperationAction(ISD::FCEIL, Ty, Legal); 567 setOperationAction(ISD::FRINT, Ty, Legal); 568 setOperationAction(ISD::FTRUNC, Ty, Legal); 569 setOperationAction(ISD::FROUND, Ty, Legal); 570 } 571 } 572 573 // Prefer likely predicted branches to selects on out-of-order cores. 574 if (Subtarget->isCortexA57()) 575 PredictableSelectIsExpensive = true; 576 } 577 578 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) { 579 if (VT == MVT::v2f32 || VT == MVT::v4f16) { 580 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 581 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32); 582 583 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 584 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32); 585 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) { 586 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 587 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64); 588 589 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 590 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64); 591 } 592 593 // Mark vector float intrinsics as expand. 594 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) { 595 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand); 596 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand); 597 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand); 598 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand); 599 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand); 600 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand); 601 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand); 602 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand); 603 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand); 604 } 605 606 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 607 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom); 608 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 609 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 610 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom); 611 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 612 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 613 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 614 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom); 615 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom); 616 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 617 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 618 619 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 620 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 621 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand); 622 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 623 624 // CNT supports only B element sizes. 625 if (VT != MVT::v8i8 && VT != MVT::v16i8) 626 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand); 627 628 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 629 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 630 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 631 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 632 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 633 634 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom); 635 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom); 636 637 if (Subtarget->isLittleEndian()) { 638 for (unsigned im = (unsigned)ISD::PRE_INC; 639 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 640 setIndexedLoadAction(im, VT.getSimpleVT(), Legal); 641 setIndexedStoreAction(im, VT.getSimpleVT(), Legal); 642 } 643 } 644 } 645 646 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { 647 addRegisterClass(VT, &AArch64::FPR64RegClass); 648 addTypeForNEON(VT, MVT::v2i32); 649 } 650 651 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) { 652 addRegisterClass(VT, &AArch64::FPR128RegClass); 653 addTypeForNEON(VT, MVT::v4i32); 654 } 655 656 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 657 if (!VT.isVector()) 658 return MVT::i32; 659 return VT.changeVectorElementTypeToInteger(); 660 } 661 662 /// computeKnownBitsForTargetNode - Determine which of the bits specified in 663 /// Mask are known to be either zero or one and return them in the 664 /// KnownZero/KnownOne bitsets. 665 void AArch64TargetLowering::computeKnownBitsForTargetNode( 666 const SDValue Op, APInt &KnownZero, APInt &KnownOne, 667 const SelectionDAG &DAG, unsigned Depth) const { 668 switch (Op.getOpcode()) { 669 default: 670 break; 671 case AArch64ISD::CSEL: { 672 APInt KnownZero2, KnownOne2; 673 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1); 674 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1); 675 KnownZero &= KnownZero2; 676 KnownOne &= KnownOne2; 677 break; 678 } 679 case ISD::INTRINSIC_W_CHAIN: { 680 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1)); 681 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue()); 682 switch (IntID) { 683 default: return; 684 case Intrinsic::aarch64_ldaxr: 685 case Intrinsic::aarch64_ldxr: { 686 unsigned BitWidth = KnownOne.getBitWidth(); 687 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); 688 unsigned MemBits = VT.getScalarType().getSizeInBits(); 689 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits); 690 return; 691 } 692 } 693 break; 694 } 695 case ISD::INTRINSIC_WO_CHAIN: 696 case ISD::INTRINSIC_VOID: { 697 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 698 switch (IntNo) { 699 default: 700 break; 701 case Intrinsic::aarch64_neon_umaxv: 702 case Intrinsic::aarch64_neon_uminv: { 703 // Figure out the datatype of the vector operand. The UMINV instruction 704 // will zero extend the result, so we can mark as known zero all the 705 // bits larger than the element datatype. 32-bit or larget doesn't need 706 // this as those are legal types and will be handled by isel directly. 707 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); 708 unsigned BitWidth = KnownZero.getBitWidth(); 709 if (VT == MVT::v8i8 || VT == MVT::v16i8) { 710 assert(BitWidth >= 8 && "Unexpected width!"); 711 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8); 712 KnownZero |= Mask; 713 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) { 714 assert(BitWidth >= 16 && "Unexpected width!"); 715 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16); 716 KnownZero |= Mask; 717 } 718 break; 719 } break; 720 } 721 } 722 } 723 } 724 725 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const { 726 return MVT::i64; 727 } 728 729 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const { 730 // FIXME: On AArch64, this depends on the type. 731 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes(). 732 // and the offset has to be a multiple of the related size in bytes. 733 return 4095; 734 } 735 736 FastISel * 737 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 738 const TargetLibraryInfo *libInfo) const { 739 return AArch64::createFastISel(funcInfo, libInfo); 740 } 741 742 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { 743 switch (Opcode) { 744 default: 745 return nullptr; 746 case AArch64ISD::CALL: return "AArch64ISD::CALL"; 747 case AArch64ISD::ADRP: return "AArch64ISD::ADRP"; 748 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow"; 749 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot"; 750 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG"; 751 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND"; 752 case AArch64ISD::CSEL: return "AArch64ISD::CSEL"; 753 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL"; 754 case AArch64ISD::CSINV: return "AArch64ISD::CSINV"; 755 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG"; 756 case AArch64ISD::CSINC: return "AArch64ISD::CSINC"; 757 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER"; 758 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL"; 759 case AArch64ISD::ADC: return "AArch64ISD::ADC"; 760 case AArch64ISD::SBC: return "AArch64ISD::SBC"; 761 case AArch64ISD::ADDS: return "AArch64ISD::ADDS"; 762 case AArch64ISD::SUBS: return "AArch64ISD::SUBS"; 763 case AArch64ISD::ADCS: return "AArch64ISD::ADCS"; 764 case AArch64ISD::SBCS: return "AArch64ISD::SBCS"; 765 case AArch64ISD::ANDS: return "AArch64ISD::ANDS"; 766 case AArch64ISD::FCMP: return "AArch64ISD::FCMP"; 767 case AArch64ISD::FMIN: return "AArch64ISD::FMIN"; 768 case AArch64ISD::FMAX: return "AArch64ISD::FMAX"; 769 case AArch64ISD::DUP: return "AArch64ISD::DUP"; 770 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8"; 771 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16"; 772 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32"; 773 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64"; 774 case AArch64ISD::MOVI: return "AArch64ISD::MOVI"; 775 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift"; 776 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit"; 777 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl"; 778 case AArch64ISD::FMOV: return "AArch64ISD::FMOV"; 779 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift"; 780 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl"; 781 case AArch64ISD::BICi: return "AArch64ISD::BICi"; 782 case AArch64ISD::ORRi: return "AArch64ISD::ORRi"; 783 case AArch64ISD::BSL: return "AArch64ISD::BSL"; 784 case AArch64ISD::NEG: return "AArch64ISD::NEG"; 785 case AArch64ISD::EXTR: return "AArch64ISD::EXTR"; 786 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1"; 787 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2"; 788 case AArch64ISD::UZP1: return "AArch64ISD::UZP1"; 789 case AArch64ISD::UZP2: return "AArch64ISD::UZP2"; 790 case AArch64ISD::TRN1: return "AArch64ISD::TRN1"; 791 case AArch64ISD::TRN2: return "AArch64ISD::TRN2"; 792 case AArch64ISD::REV16: return "AArch64ISD::REV16"; 793 case AArch64ISD::REV32: return "AArch64ISD::REV32"; 794 case AArch64ISD::REV64: return "AArch64ISD::REV64"; 795 case AArch64ISD::EXT: return "AArch64ISD::EXT"; 796 case AArch64ISD::VSHL: return "AArch64ISD::VSHL"; 797 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR"; 798 case AArch64ISD::VASHR: return "AArch64ISD::VASHR"; 799 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ"; 800 case AArch64ISD::CMGE: return "AArch64ISD::CMGE"; 801 case AArch64ISD::CMGT: return "AArch64ISD::CMGT"; 802 case AArch64ISD::CMHI: return "AArch64ISD::CMHI"; 803 case AArch64ISD::CMHS: return "AArch64ISD::CMHS"; 804 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ"; 805 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE"; 806 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT"; 807 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz"; 808 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz"; 809 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz"; 810 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz"; 811 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz"; 812 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz"; 813 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz"; 814 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz"; 815 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz"; 816 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz"; 817 case AArch64ISD::NOT: return "AArch64ISD::NOT"; 818 case AArch64ISD::BIT: return "AArch64ISD::BIT"; 819 case AArch64ISD::CBZ: return "AArch64ISD::CBZ"; 820 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ"; 821 case AArch64ISD::TBZ: return "AArch64ISD::TBZ"; 822 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ"; 823 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN"; 824 case AArch64ISD::SITOF: return "AArch64ISD::SITOF"; 825 case AArch64ISD::UITOF: return "AArch64ISD::UITOF"; 826 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST"; 827 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I"; 828 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I"; 829 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I"; 830 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I"; 831 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I"; 832 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge"; 833 case AArch64ISD::LD2post: return "AArch64ISD::LD2post"; 834 case AArch64ISD::LD3post: return "AArch64ISD::LD3post"; 835 case AArch64ISD::LD4post: return "AArch64ISD::LD4post"; 836 case AArch64ISD::ST2post: return "AArch64ISD::ST2post"; 837 case AArch64ISD::ST3post: return "AArch64ISD::ST3post"; 838 case AArch64ISD::ST4post: return "AArch64ISD::ST4post"; 839 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post"; 840 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post"; 841 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post"; 842 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post"; 843 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post"; 844 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post"; 845 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost"; 846 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost"; 847 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost"; 848 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost"; 849 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost"; 850 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost"; 851 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost"; 852 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost"; 853 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost"; 854 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost"; 855 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost"; 856 } 857 } 858 859 MachineBasicBlock * 860 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI, 861 MachineBasicBlock *MBB) const { 862 // We materialise the F128CSEL pseudo-instruction as some control flow and a 863 // phi node: 864 865 // OrigBB: 866 // [... previous instrs leading to comparison ...] 867 // b.ne TrueBB 868 // b EndBB 869 // TrueBB: 870 // ; Fallthrough 871 // EndBB: 872 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB] 873 874 const TargetInstrInfo *TII = 875 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 876 MachineFunction *MF = MBB->getParent(); 877 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 878 DebugLoc DL = MI->getDebugLoc(); 879 MachineFunction::iterator It = MBB; 880 ++It; 881 882 unsigned DestReg = MI->getOperand(0).getReg(); 883 unsigned IfTrueReg = MI->getOperand(1).getReg(); 884 unsigned IfFalseReg = MI->getOperand(2).getReg(); 885 unsigned CondCode = MI->getOperand(3).getImm(); 886 bool NZCVKilled = MI->getOperand(4).isKill(); 887 888 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB); 889 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB); 890 MF->insert(It, TrueBB); 891 MF->insert(It, EndBB); 892 893 // Transfer rest of current basic-block to EndBB 894 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)), 895 MBB->end()); 896 EndBB->transferSuccessorsAndUpdatePHIs(MBB); 897 898 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); 899 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB); 900 MBB->addSuccessor(TrueBB); 901 MBB->addSuccessor(EndBB); 902 903 // TrueBB falls through to the end. 904 TrueBB->addSuccessor(EndBB); 905 906 if (!NZCVKilled) { 907 TrueBB->addLiveIn(AArch64::NZCV); 908 EndBB->addLiveIn(AArch64::NZCV); 909 } 910 911 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg) 912 .addReg(IfTrueReg) 913 .addMBB(TrueBB) 914 .addReg(IfFalseReg) 915 .addMBB(MBB); 916 917 MI->eraseFromParent(); 918 return EndBB; 919 } 920 921 MachineBasicBlock * 922 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 923 MachineBasicBlock *BB) const { 924 switch (MI->getOpcode()) { 925 default: 926 #ifndef NDEBUG 927 MI->dump(); 928 #endif 929 llvm_unreachable("Unexpected instruction for custom inserter!"); 930 931 case AArch64::F128CSEL: 932 return EmitF128CSEL(MI, BB); 933 934 case TargetOpcode::STACKMAP: 935 case TargetOpcode::PATCHPOINT: 936 return emitPatchPoint(MI, BB); 937 } 938 } 939 940 //===----------------------------------------------------------------------===// 941 // AArch64 Lowering private implementation. 942 //===----------------------------------------------------------------------===// 943 944 //===----------------------------------------------------------------------===// 945 // Lowering Code 946 //===----------------------------------------------------------------------===// 947 948 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 949 /// CC 950 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { 951 switch (CC) { 952 default: 953 llvm_unreachable("Unknown condition code!"); 954 case ISD::SETNE: 955 return AArch64CC::NE; 956 case ISD::SETEQ: 957 return AArch64CC::EQ; 958 case ISD::SETGT: 959 return AArch64CC::GT; 960 case ISD::SETGE: 961 return AArch64CC::GE; 962 case ISD::SETLT: 963 return AArch64CC::LT; 964 case ISD::SETLE: 965 return AArch64CC::LE; 966 case ISD::SETUGT: 967 return AArch64CC::HI; 968 case ISD::SETUGE: 969 return AArch64CC::HS; 970 case ISD::SETULT: 971 return AArch64CC::LO; 972 case ISD::SETULE: 973 return AArch64CC::LS; 974 } 975 } 976 977 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC. 978 static void changeFPCCToAArch64CC(ISD::CondCode CC, 979 AArch64CC::CondCode &CondCode, 980 AArch64CC::CondCode &CondCode2) { 981 CondCode2 = AArch64CC::AL; 982 switch (CC) { 983 default: 984 llvm_unreachable("Unknown FP condition!"); 985 case ISD::SETEQ: 986 case ISD::SETOEQ: 987 CondCode = AArch64CC::EQ; 988 break; 989 case ISD::SETGT: 990 case ISD::SETOGT: 991 CondCode = AArch64CC::GT; 992 break; 993 case ISD::SETGE: 994 case ISD::SETOGE: 995 CondCode = AArch64CC::GE; 996 break; 997 case ISD::SETOLT: 998 CondCode = AArch64CC::MI; 999 break; 1000 case ISD::SETOLE: 1001 CondCode = AArch64CC::LS; 1002 break; 1003 case ISD::SETONE: 1004 CondCode = AArch64CC::MI; 1005 CondCode2 = AArch64CC::GT; 1006 break; 1007 case ISD::SETO: 1008 CondCode = AArch64CC::VC; 1009 break; 1010 case ISD::SETUO: 1011 CondCode = AArch64CC::VS; 1012 break; 1013 case ISD::SETUEQ: 1014 CondCode = AArch64CC::EQ; 1015 CondCode2 = AArch64CC::VS; 1016 break; 1017 case ISD::SETUGT: 1018 CondCode = AArch64CC::HI; 1019 break; 1020 case ISD::SETUGE: 1021 CondCode = AArch64CC::PL; 1022 break; 1023 case ISD::SETLT: 1024 case ISD::SETULT: 1025 CondCode = AArch64CC::LT; 1026 break; 1027 case ISD::SETLE: 1028 case ISD::SETULE: 1029 CondCode = AArch64CC::LE; 1030 break; 1031 case ISD::SETNE: 1032 case ISD::SETUNE: 1033 CondCode = AArch64CC::NE; 1034 break; 1035 } 1036 } 1037 1038 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 1039 /// CC usable with the vector instructions. Fewer operations are available 1040 /// without a real NZCV register, so we have to use less efficient combinations 1041 /// to get the same effect. 1042 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC, 1043 AArch64CC::CondCode &CondCode, 1044 AArch64CC::CondCode &CondCode2, 1045 bool &Invert) { 1046 Invert = false; 1047 switch (CC) { 1048 default: 1049 // Mostly the scalar mappings work fine. 1050 changeFPCCToAArch64CC(CC, CondCode, CondCode2); 1051 break; 1052 case ISD::SETUO: 1053 Invert = true; // Fallthrough 1054 case ISD::SETO: 1055 CondCode = AArch64CC::MI; 1056 CondCode2 = AArch64CC::GE; 1057 break; 1058 case ISD::SETUEQ: 1059 case ISD::SETULT: 1060 case ISD::SETULE: 1061 case ISD::SETUGT: 1062 case ISD::SETUGE: 1063 // All of the compare-mask comparisons are ordered, but we can switch 1064 // between the two by a double inversion. E.g. ULE == !OGT. 1065 Invert = true; 1066 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2); 1067 break; 1068 } 1069 } 1070 1071 static bool isLegalArithImmed(uint64_t C) { 1072 // Matches AArch64DAGToDAGISel::SelectArithImmed(). 1073 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0); 1074 } 1075 1076 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, 1077 SDLoc dl, SelectionDAG &DAG) { 1078 EVT VT = LHS.getValueType(); 1079 1080 if (VT.isFloatingPoint()) 1081 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); 1082 1083 // The CMP instruction is just an alias for SUBS, and representing it as 1084 // SUBS means that it's possible to get CSE with subtract operations. 1085 // A later phase can perform the optimization of setting the destination 1086 // register to WZR/XZR if it ends up being unused. 1087 unsigned Opcode = AArch64ISD::SUBS; 1088 1089 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) && 1090 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 && 1091 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1092 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on 1093 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags 1094 // can be set differently by this operation. It comes down to whether 1095 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then 1096 // everything is fine. If not then the optimization is wrong. Thus general 1097 // comparisons are only valid if op2 != 0. 1098 1099 // So, finally, the only LLVM-native comparisons that don't mention C and V 1100 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in 1101 // the absence of information about op2. 1102 Opcode = AArch64ISD::ADDS; 1103 RHS = RHS.getOperand(1); 1104 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) && 1105 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 && 1106 !isUnsignedIntSetCC(CC)) { 1107 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST 1108 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one 1109 // of the signed comparisons. 1110 Opcode = AArch64ISD::ANDS; 1111 RHS = LHS.getOperand(1); 1112 LHS = LHS.getOperand(0); 1113 } 1114 1115 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS) 1116 .getValue(1); 1117 } 1118 1119 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 1120 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) { 1121 SDValue Cmp; 1122 AArch64CC::CondCode AArch64CC; 1123 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 1124 EVT VT = RHS.getValueType(); 1125 uint64_t C = RHSC->getZExtValue(); 1126 if (!isLegalArithImmed(C)) { 1127 // Constant does not fit, try adjusting it by one? 1128 switch (CC) { 1129 default: 1130 break; 1131 case ISD::SETLT: 1132 case ISD::SETGE: 1133 if ((VT == MVT::i32 && C != 0x80000000 && 1134 isLegalArithImmed((uint32_t)(C - 1))) || 1135 (VT == MVT::i64 && C != 0x80000000ULL && 1136 isLegalArithImmed(C - 1ULL))) { 1137 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1138 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1; 1139 RHS = DAG.getConstant(C, VT); 1140 } 1141 break; 1142 case ISD::SETULT: 1143 case ISD::SETUGE: 1144 if ((VT == MVT::i32 && C != 0 && 1145 isLegalArithImmed((uint32_t)(C - 1))) || 1146 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) { 1147 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1148 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1; 1149 RHS = DAG.getConstant(C, VT); 1150 } 1151 break; 1152 case ISD::SETLE: 1153 case ISD::SETGT: 1154 if ((VT == MVT::i32 && C != 0x7fffffff && 1155 isLegalArithImmed((uint32_t)(C + 1))) || 1156 (VT == MVT::i64 && C != 0x7ffffffffffffffULL && 1157 isLegalArithImmed(C + 1ULL))) { 1158 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1159 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1; 1160 RHS = DAG.getConstant(C, VT); 1161 } 1162 break; 1163 case ISD::SETULE: 1164 case ISD::SETUGT: 1165 if ((VT == MVT::i32 && C != 0xffffffff && 1166 isLegalArithImmed((uint32_t)(C + 1))) || 1167 (VT == MVT::i64 && C != 0xfffffffffffffffULL && 1168 isLegalArithImmed(C + 1ULL))) { 1169 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1170 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1; 1171 RHS = DAG.getConstant(C, VT); 1172 } 1173 break; 1174 } 1175 } 1176 } 1177 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095. 1178 // For the i8 operand, the largest immediate is 255, so this can be easily 1179 // encoded in the compare instruction. For the i16 operand, however, the 1180 // largest immediate cannot be encoded in the compare. 1181 // Therefore, use a sign extending load and cmn to avoid materializing the -1 1182 // constant. For example, 1183 // movz w1, #65535 1184 // ldrh w0, [x0, #0] 1185 // cmp w0, w1 1186 // > 1187 // ldrsh w0, [x0, #0] 1188 // cmn w0, #1 1189 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS) 1190 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure 1191 // both the LHS and RHS are truely zero extended and to make sure the 1192 // transformation is profitable. 1193 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) { 1194 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) && 1195 isa<LoadSDNode>(LHS)) { 1196 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD && 1197 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 && 1198 LHS.getNode()->hasNUsesOfValue(1, 0)) { 1199 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue(); 1200 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) { 1201 SDValue SExt = 1202 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS, 1203 DAG.getValueType(MVT::i16)); 1204 Cmp = emitComparison(SExt, 1205 DAG.getConstant(ValueofRHS, RHS.getValueType()), 1206 CC, dl, DAG); 1207 AArch64CC = changeIntCCToAArch64CC(CC); 1208 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32); 1209 return Cmp; 1210 } 1211 } 1212 } 1213 } 1214 Cmp = emitComparison(LHS, RHS, CC, dl, DAG); 1215 AArch64CC = changeIntCCToAArch64CC(CC); 1216 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32); 1217 return Cmp; 1218 } 1219 1220 static std::pair<SDValue, SDValue> 1221 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) { 1222 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) && 1223 "Unsupported value type"); 1224 SDValue Value, Overflow; 1225 SDLoc DL(Op); 1226 SDValue LHS = Op.getOperand(0); 1227 SDValue RHS = Op.getOperand(1); 1228 unsigned Opc = 0; 1229 switch (Op.getOpcode()) { 1230 default: 1231 llvm_unreachable("Unknown overflow instruction!"); 1232 case ISD::SADDO: 1233 Opc = AArch64ISD::ADDS; 1234 CC = AArch64CC::VS; 1235 break; 1236 case ISD::UADDO: 1237 Opc = AArch64ISD::ADDS; 1238 CC = AArch64CC::HS; 1239 break; 1240 case ISD::SSUBO: 1241 Opc = AArch64ISD::SUBS; 1242 CC = AArch64CC::VS; 1243 break; 1244 case ISD::USUBO: 1245 Opc = AArch64ISD::SUBS; 1246 CC = AArch64CC::LO; 1247 break; 1248 // Multiply needs a little bit extra work. 1249 case ISD::SMULO: 1250 case ISD::UMULO: { 1251 CC = AArch64CC::NE; 1252 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false; 1253 if (Op.getValueType() == MVT::i32) { 1254 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1255 // For a 32 bit multiply with overflow check we want the instruction 1256 // selector to generate a widening multiply (SMADDL/UMADDL). For that we 1257 // need to generate the following pattern: 1258 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b)) 1259 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS); 1260 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS); 1261 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); 1262 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul, 1263 DAG.getConstant(0, MVT::i64)); 1264 // On AArch64 the upper 32 bits are always zero extended for a 32 bit 1265 // operation. We need to clear out the upper 32 bits, because we used a 1266 // widening multiply that wrote all 64 bits. In the end this should be a 1267 // noop. 1268 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add); 1269 if (IsSigned) { 1270 // The signed overflow check requires more than just a simple check for 1271 // any bit set in the upper 32 bits of the result. These bits could be 1272 // just the sign bits of a negative number. To perform the overflow 1273 // check we have to arithmetic shift right the 32nd bit of the result by 1274 // 31 bits. Then we compare the result to the upper 32 bits. 1275 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add, 1276 DAG.getConstant(32, MVT::i64)); 1277 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits); 1278 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value, 1279 DAG.getConstant(31, MVT::i64)); 1280 // It is important that LowerBits is last, otherwise the arithmetic 1281 // shift will not be folded into the compare (SUBS). 1282 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32); 1283 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) 1284 .getValue(1); 1285 } else { 1286 // The overflow check for unsigned multiply is easy. We only need to 1287 // check if any of the upper 32 bits are set. This can be done with a 1288 // CMP (shifted register). For that we need to generate the following 1289 // pattern: 1290 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32) 1291 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, 1292 DAG.getConstant(32, MVT::i64)); 1293 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); 1294 Overflow = 1295 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64), 1296 UpperBits).getValue(1); 1297 } 1298 break; 1299 } 1300 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type"); 1301 // For the 64 bit multiply 1302 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); 1303 if (IsSigned) { 1304 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS); 1305 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value, 1306 DAG.getConstant(63, MVT::i64)); 1307 // It is important that LowerBits is last, otherwise the arithmetic 1308 // shift will not be folded into the compare (SUBS). 1309 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); 1310 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) 1311 .getValue(1); 1312 } else { 1313 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS); 1314 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); 1315 Overflow = 1316 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64), 1317 UpperBits).getValue(1); 1318 } 1319 break; 1320 } 1321 } // switch (...) 1322 1323 if (Opc) { 1324 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32); 1325 1326 // Emit the AArch64 operation with overflow check. 1327 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS); 1328 Overflow = Value.getValue(1); 1329 } 1330 return std::make_pair(Value, Overflow); 1331 } 1332 1333 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG, 1334 RTLIB::Libcall Call) const { 1335 SmallVector<SDValue, 2> Ops; 1336 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) 1337 Ops.push_back(Op.getOperand(i)); 1338 1339 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false, 1340 SDLoc(Op)).first; 1341 } 1342 1343 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) { 1344 SDValue Sel = Op.getOperand(0); 1345 SDValue Other = Op.getOperand(1); 1346 1347 // If neither operand is a SELECT_CC, give up. 1348 if (Sel.getOpcode() != ISD::SELECT_CC) 1349 std::swap(Sel, Other); 1350 if (Sel.getOpcode() != ISD::SELECT_CC) 1351 return Op; 1352 1353 // The folding we want to perform is: 1354 // (xor x, (select_cc a, b, cc, 0, -1) ) 1355 // --> 1356 // (csel x, (xor x, -1), cc ...) 1357 // 1358 // The latter will get matched to a CSINV instruction. 1359 1360 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get(); 1361 SDValue LHS = Sel.getOperand(0); 1362 SDValue RHS = Sel.getOperand(1); 1363 SDValue TVal = Sel.getOperand(2); 1364 SDValue FVal = Sel.getOperand(3); 1365 SDLoc dl(Sel); 1366 1367 // FIXME: This could be generalized to non-integer comparisons. 1368 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64) 1369 return Op; 1370 1371 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal); 1372 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal); 1373 1374 // The the values aren't constants, this isn't the pattern we're looking for. 1375 if (!CFVal || !CTVal) 1376 return Op; 1377 1378 // We can commute the SELECT_CC by inverting the condition. This 1379 // might be needed to make this fit into a CSINV pattern. 1380 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) { 1381 std::swap(TVal, FVal); 1382 std::swap(CTVal, CFVal); 1383 CC = ISD::getSetCCInverse(CC, true); 1384 } 1385 1386 // If the constants line up, perform the transform! 1387 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) { 1388 SDValue CCVal; 1389 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); 1390 1391 FVal = Other; 1392 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other, 1393 DAG.getConstant(-1ULL, Other.getValueType())); 1394 1395 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal, 1396 CCVal, Cmp); 1397 } 1398 1399 return Op; 1400 } 1401 1402 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 1403 EVT VT = Op.getValueType(); 1404 1405 // Let legalize expand this if it isn't a legal type yet. 1406 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 1407 return SDValue(); 1408 1409 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 1410 1411 unsigned Opc; 1412 bool ExtraOp = false; 1413 switch (Op.getOpcode()) { 1414 default: 1415 llvm_unreachable("Invalid code"); 1416 case ISD::ADDC: 1417 Opc = AArch64ISD::ADDS; 1418 break; 1419 case ISD::SUBC: 1420 Opc = AArch64ISD::SUBS; 1421 break; 1422 case ISD::ADDE: 1423 Opc = AArch64ISD::ADCS; 1424 ExtraOp = true; 1425 break; 1426 case ISD::SUBE: 1427 Opc = AArch64ISD::SBCS; 1428 ExtraOp = true; 1429 break; 1430 } 1431 1432 if (!ExtraOp) 1433 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1)); 1434 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1), 1435 Op.getOperand(2)); 1436 } 1437 1438 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) { 1439 // Let legalize expand this if it isn't a legal type yet. 1440 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType())) 1441 return SDValue(); 1442 1443 AArch64CC::CondCode CC; 1444 // The actual operation that sets the overflow or carry flag. 1445 SDValue Value, Overflow; 1446 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG); 1447 1448 // We use 0 and 1 as false and true values. 1449 SDValue TVal = DAG.getConstant(1, MVT::i32); 1450 SDValue FVal = DAG.getConstant(0, MVT::i32); 1451 1452 // We use an inverted condition, because the conditional select is inverted 1453 // too. This will allow it to be selected to a single instruction: 1454 // CSINC Wd, WZR, WZR, invert(cond). 1455 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32); 1456 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal, 1457 CCVal, Overflow); 1458 1459 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 1460 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow); 1461 } 1462 1463 // Prefetch operands are: 1464 // 1: Address to prefetch 1465 // 2: bool isWrite 1466 // 3: int locality (0 = no locality ... 3 = extreme locality) 1467 // 4: bool isDataCache 1468 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) { 1469 SDLoc DL(Op); 1470 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 1471 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 1472 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 1473 1474 bool IsStream = !Locality; 1475 // When the locality number is set 1476 if (Locality) { 1477 // The front-end should have filtered out the out-of-range values 1478 assert(Locality <= 3 && "Prefetch locality out-of-range"); 1479 // The locality degree is the opposite of the cache speed. 1480 // Put the number the other way around. 1481 // The encoding starts at 0 for level 1 1482 Locality = 3 - Locality; 1483 } 1484 1485 // built the mask value encoding the expected behavior. 1486 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit 1487 (!IsData << 3) | // IsDataCache bit 1488 (Locality << 1) | // Cache level bits 1489 (unsigned)IsStream; // Stream bit 1490 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0), 1491 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1)); 1492 } 1493 1494 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, 1495 SelectionDAG &DAG) const { 1496 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering"); 1497 1498 RTLIB::Libcall LC; 1499 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType()); 1500 1501 return LowerF128Call(Op, DAG, LC); 1502 } 1503 1504 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op, 1505 SelectionDAG &DAG) const { 1506 if (Op.getOperand(0).getValueType() != MVT::f128) { 1507 // It's legal except when f128 is involved 1508 return Op; 1509 } 1510 1511 RTLIB::Libcall LC; 1512 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType()); 1513 1514 // FP_ROUND node has a second operand indicating whether it is known to be 1515 // precise. That doesn't take part in the LibCall so we can't directly use 1516 // LowerF128Call. 1517 SDValue SrcVal = Op.getOperand(0); 1518 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1, 1519 /*isSigned*/ false, SDLoc(Op)).first; 1520 } 1521 1522 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 1523 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp. 1524 // Any additional optimization in this function should be recorded 1525 // in the cost tables. 1526 EVT InVT = Op.getOperand(0).getValueType(); 1527 EVT VT = Op.getValueType(); 1528 1529 if (VT.getSizeInBits() < InVT.getSizeInBits()) { 1530 SDLoc dl(Op); 1531 SDValue Cv = 1532 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(), 1533 Op.getOperand(0)); 1534 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv); 1535 } 1536 1537 if (VT.getSizeInBits() > InVT.getSizeInBits()) { 1538 SDLoc dl(Op); 1539 MVT ExtVT = 1540 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()), 1541 VT.getVectorNumElements()); 1542 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0)); 1543 return DAG.getNode(Op.getOpcode(), dl, VT, Ext); 1544 } 1545 1546 // Type changing conversions are illegal. 1547 return Op; 1548 } 1549 1550 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, 1551 SelectionDAG &DAG) const { 1552 if (Op.getOperand(0).getValueType().isVector()) 1553 return LowerVectorFP_TO_INT(Op, DAG); 1554 1555 if (Op.getOperand(0).getValueType() != MVT::f128) { 1556 // It's legal except when f128 is involved 1557 return Op; 1558 } 1559 1560 RTLIB::Libcall LC; 1561 if (Op.getOpcode() == ISD::FP_TO_SINT) 1562 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType()); 1563 else 1564 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType()); 1565 1566 SmallVector<SDValue, 2> Ops; 1567 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) 1568 Ops.push_back(Op.getOperand(i)); 1569 1570 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false, 1571 SDLoc(Op)).first; 1572 } 1573 1574 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1575 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp. 1576 // Any additional optimization in this function should be recorded 1577 // in the cost tables. 1578 EVT VT = Op.getValueType(); 1579 SDLoc dl(Op); 1580 SDValue In = Op.getOperand(0); 1581 EVT InVT = In.getValueType(); 1582 1583 if (VT.getSizeInBits() < InVT.getSizeInBits()) { 1584 MVT CastVT = 1585 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()), 1586 InVT.getVectorNumElements()); 1587 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In); 1588 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0)); 1589 } 1590 1591 if (VT.getSizeInBits() > InVT.getSizeInBits()) { 1592 unsigned CastOpc = 1593 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1594 EVT CastVT = VT.changeVectorElementTypeToInteger(); 1595 In = DAG.getNode(CastOpc, dl, CastVT, In); 1596 return DAG.getNode(Op.getOpcode(), dl, VT, In); 1597 } 1598 1599 return Op; 1600 } 1601 1602 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, 1603 SelectionDAG &DAG) const { 1604 if (Op.getValueType().isVector()) 1605 return LowerVectorINT_TO_FP(Op, DAG); 1606 1607 // i128 conversions are libcalls. 1608 if (Op.getOperand(0).getValueType() == MVT::i128) 1609 return SDValue(); 1610 1611 // Other conversions are legal, unless it's to the completely software-based 1612 // fp128. 1613 if (Op.getValueType() != MVT::f128) 1614 return Op; 1615 1616 RTLIB::Libcall LC; 1617 if (Op.getOpcode() == ISD::SINT_TO_FP) 1618 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType()); 1619 else 1620 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType()); 1621 1622 return LowerF128Call(Op, DAG, LC); 1623 } 1624 1625 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op, 1626 SelectionDAG &DAG) const { 1627 // For iOS, we want to call an alternative entry point: __sincos_stret, 1628 // which returns the values in two S / D registers. 1629 SDLoc dl(Op); 1630 SDValue Arg = Op.getOperand(0); 1631 EVT ArgVT = Arg.getValueType(); 1632 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1633 1634 ArgListTy Args; 1635 ArgListEntry Entry; 1636 1637 Entry.Node = Arg; 1638 Entry.Ty = ArgTy; 1639 Entry.isSExt = false; 1640 Entry.isZExt = false; 1641 Args.push_back(Entry); 1642 1643 const char *LibcallName = 1644 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret"; 1645 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy()); 1646 1647 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL); 1648 TargetLowering::CallLoweringInfo CLI(DAG); 1649 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) 1650 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0); 1651 1652 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1653 return CallResult.first; 1654 } 1655 1656 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) { 1657 if (Op.getValueType() != MVT::f16) 1658 return SDValue(); 1659 1660 assert(Op.getOperand(0).getValueType() == MVT::i16); 1661 SDLoc DL(Op); 1662 1663 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0)); 1664 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op); 1665 return SDValue( 1666 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op, 1667 DAG.getTargetConstant(AArch64::hsub, MVT::i32)), 1668 0); 1669 } 1670 1671 1672 SDValue AArch64TargetLowering::LowerOperation(SDValue Op, 1673 SelectionDAG &DAG) const { 1674 switch (Op.getOpcode()) { 1675 default: 1676 llvm_unreachable("unimplemented operand"); 1677 return SDValue(); 1678 case ISD::BITCAST: 1679 return LowerBITCAST(Op, DAG); 1680 case ISD::GlobalAddress: 1681 return LowerGlobalAddress(Op, DAG); 1682 case ISD::GlobalTLSAddress: 1683 return LowerGlobalTLSAddress(Op, DAG); 1684 case ISD::SETCC: 1685 return LowerSETCC(Op, DAG); 1686 case ISD::BR_CC: 1687 return LowerBR_CC(Op, DAG); 1688 case ISD::SELECT: 1689 return LowerSELECT(Op, DAG); 1690 case ISD::SELECT_CC: 1691 return LowerSELECT_CC(Op, DAG); 1692 case ISD::JumpTable: 1693 return LowerJumpTable(Op, DAG); 1694 case ISD::ConstantPool: 1695 return LowerConstantPool(Op, DAG); 1696 case ISD::BlockAddress: 1697 return LowerBlockAddress(Op, DAG); 1698 case ISD::VASTART: 1699 return LowerVASTART(Op, DAG); 1700 case ISD::VACOPY: 1701 return LowerVACOPY(Op, DAG); 1702 case ISD::VAARG: 1703 return LowerVAARG(Op, DAG); 1704 case ISD::ADDC: 1705 case ISD::ADDE: 1706 case ISD::SUBC: 1707 case ISD::SUBE: 1708 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 1709 case ISD::SADDO: 1710 case ISD::UADDO: 1711 case ISD::SSUBO: 1712 case ISD::USUBO: 1713 case ISD::SMULO: 1714 case ISD::UMULO: 1715 return LowerXALUO(Op, DAG); 1716 case ISD::FADD: 1717 return LowerF128Call(Op, DAG, RTLIB::ADD_F128); 1718 case ISD::FSUB: 1719 return LowerF128Call(Op, DAG, RTLIB::SUB_F128); 1720 case ISD::FMUL: 1721 return LowerF128Call(Op, DAG, RTLIB::MUL_F128); 1722 case ISD::FDIV: 1723 return LowerF128Call(Op, DAG, RTLIB::DIV_F128); 1724 case ISD::FP_ROUND: 1725 return LowerFP_ROUND(Op, DAG); 1726 case ISD::FP_EXTEND: 1727 return LowerFP_EXTEND(Op, DAG); 1728 case ISD::FRAMEADDR: 1729 return LowerFRAMEADDR(Op, DAG); 1730 case ISD::RETURNADDR: 1731 return LowerRETURNADDR(Op, DAG); 1732 case ISD::INSERT_VECTOR_ELT: 1733 return LowerINSERT_VECTOR_ELT(Op, DAG); 1734 case ISD::EXTRACT_VECTOR_ELT: 1735 return LowerEXTRACT_VECTOR_ELT(Op, DAG); 1736 case ISD::BUILD_VECTOR: 1737 return LowerBUILD_VECTOR(Op, DAG); 1738 case ISD::VECTOR_SHUFFLE: 1739 return LowerVECTOR_SHUFFLE(Op, DAG); 1740 case ISD::EXTRACT_SUBVECTOR: 1741 return LowerEXTRACT_SUBVECTOR(Op, DAG); 1742 case ISD::SRA: 1743 case ISD::SRL: 1744 case ISD::SHL: 1745 return LowerVectorSRA_SRL_SHL(Op, DAG); 1746 case ISD::SHL_PARTS: 1747 return LowerShiftLeftParts(Op, DAG); 1748 case ISD::SRL_PARTS: 1749 case ISD::SRA_PARTS: 1750 return LowerShiftRightParts(Op, DAG); 1751 case ISD::CTPOP: 1752 return LowerCTPOP(Op, DAG); 1753 case ISD::FCOPYSIGN: 1754 return LowerFCOPYSIGN(Op, DAG); 1755 case ISD::AND: 1756 return LowerVectorAND(Op, DAG); 1757 case ISD::OR: 1758 return LowerVectorOR(Op, DAG); 1759 case ISD::XOR: 1760 return LowerXOR(Op, DAG); 1761 case ISD::PREFETCH: 1762 return LowerPREFETCH(Op, DAG); 1763 case ISD::SINT_TO_FP: 1764 case ISD::UINT_TO_FP: 1765 return LowerINT_TO_FP(Op, DAG); 1766 case ISD::FP_TO_SINT: 1767 case ISD::FP_TO_UINT: 1768 return LowerFP_TO_INT(Op, DAG); 1769 case ISD::FSINCOS: 1770 return LowerFSINCOS(Op, DAG); 1771 } 1772 } 1773 1774 /// getFunctionAlignment - Return the Log2 alignment of this function. 1775 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const { 1776 return 2; 1777 } 1778 1779 //===----------------------------------------------------------------------===// 1780 // Calling Convention Implementation 1781 //===----------------------------------------------------------------------===// 1782 1783 #include "AArch64GenCallingConv.inc" 1784 1785 /// Selects the correct CCAssignFn for a given CallingConvention value. 1786 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC, 1787 bool IsVarArg) const { 1788 switch (CC) { 1789 default: 1790 llvm_unreachable("Unsupported calling convention."); 1791 case CallingConv::WebKit_JS: 1792 return CC_AArch64_WebKit_JS; 1793 case CallingConv::C: 1794 case CallingConv::Fast: 1795 if (!Subtarget->isTargetDarwin()) 1796 return CC_AArch64_AAPCS; 1797 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS; 1798 } 1799 } 1800 1801 SDValue AArch64TargetLowering::LowerFormalArguments( 1802 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1803 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 1804 SmallVectorImpl<SDValue> &InVals) const { 1805 MachineFunction &MF = DAG.getMachineFunction(); 1806 MachineFrameInfo *MFI = MF.getFrameInfo(); 1807 1808 // Assign locations to all of the incoming arguments. 1809 SmallVector<CCValAssign, 16> ArgLocs; 1810 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1811 *DAG.getContext()); 1812 1813 // At this point, Ins[].VT may already be promoted to i32. To correctly 1814 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and 1815 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT. 1816 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here 1817 // we use a special version of AnalyzeFormalArguments to pass in ValVT and 1818 // LocVT. 1819 unsigned NumArgs = Ins.size(); 1820 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin(); 1821 unsigned CurArgIdx = 0; 1822 for (unsigned i = 0; i != NumArgs; ++i) { 1823 MVT ValVT = Ins[i].VT; 1824 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx); 1825 CurArgIdx = Ins[i].OrigArgIndex; 1826 1827 // Get type of the original argument. 1828 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true); 1829 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other; 1830 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16. 1831 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) 1832 ValVT = MVT::i8; 1833 else if (ActualMVT == MVT::i16) 1834 ValVT = MVT::i16; 1835 1836 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false); 1837 bool Res = 1838 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo); 1839 assert(!Res && "Call operand has unhandled type"); 1840 (void)Res; 1841 } 1842 assert(ArgLocs.size() == Ins.size()); 1843 SmallVector<SDValue, 16> ArgValues; 1844 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1845 CCValAssign &VA = ArgLocs[i]; 1846 1847 if (Ins[i].Flags.isByVal()) { 1848 // Byval is used for HFAs in the PCS, but the system should work in a 1849 // non-compliant manner for larger structs. 1850 EVT PtrTy = getPointerTy(); 1851 int Size = Ins[i].Flags.getByValSize(); 1852 unsigned NumRegs = (Size + 7) / 8; 1853 1854 // FIXME: This works on big-endian for composite byvals, which are the common 1855 // case. It should also work for fundamental types too. 1856 unsigned FrameIdx = 1857 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false); 1858 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy); 1859 InVals.push_back(FrameIdxN); 1860 1861 continue; 1862 } 1863 1864 if (VA.isRegLoc()) { 1865 // Arguments stored in registers. 1866 EVT RegVT = VA.getLocVT(); 1867 1868 SDValue ArgValue; 1869 const TargetRegisterClass *RC; 1870 1871 if (RegVT == MVT::i32) 1872 RC = &AArch64::GPR32RegClass; 1873 else if (RegVT == MVT::i64) 1874 RC = &AArch64::GPR64RegClass; 1875 else if (RegVT == MVT::f16) 1876 RC = &AArch64::FPR16RegClass; 1877 else if (RegVT == MVT::f32) 1878 RC = &AArch64::FPR32RegClass; 1879 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) 1880 RC = &AArch64::FPR64RegClass; 1881 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) 1882 RC = &AArch64::FPR128RegClass; 1883 else 1884 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 1885 1886 // Transform the arguments in physical registers into virtual ones. 1887 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1888 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 1889 1890 // If this is an 8, 16 or 32-bit value, it is really passed promoted 1891 // to 64 bits. Insert an assert[sz]ext to capture this, then 1892 // truncate to the right size. 1893 switch (VA.getLocInfo()) { 1894 default: 1895 llvm_unreachable("Unknown loc info!"); 1896 case CCValAssign::Full: 1897 break; 1898 case CCValAssign::BCvt: 1899 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue); 1900 break; 1901 case CCValAssign::AExt: 1902 case CCValAssign::SExt: 1903 case CCValAssign::ZExt: 1904 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt 1905 // nodes after our lowering. 1906 assert(RegVT == Ins[i].VT && "incorrect register location selected"); 1907 break; 1908 } 1909 1910 InVals.push_back(ArgValue); 1911 1912 } else { // VA.isRegLoc() 1913 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem"); 1914 unsigned ArgOffset = VA.getLocMemOffset(); 1915 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8; 1916 1917 uint32_t BEAlign = 0; 1918 if (ArgSize < 8 && !Subtarget->isLittleEndian()) 1919 BEAlign = 8 - ArgSize; 1920 1921 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true); 1922 1923 // Create load nodes to retrieve arguments from the stack. 1924 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1925 SDValue ArgValue; 1926 1927 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT) 1928 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 1929 MVT MemVT = VA.getValVT(); 1930 1931 switch (VA.getLocInfo()) { 1932 default: 1933 break; 1934 case CCValAssign::BCvt: 1935 MemVT = VA.getLocVT(); 1936 break; 1937 case CCValAssign::SExt: 1938 ExtType = ISD::SEXTLOAD; 1939 break; 1940 case CCValAssign::ZExt: 1941 ExtType = ISD::ZEXTLOAD; 1942 break; 1943 case CCValAssign::AExt: 1944 ExtType = ISD::EXTLOAD; 1945 break; 1946 } 1947 1948 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN, 1949 MachinePointerInfo::getFixedStack(FI), 1950 MemVT, false, false, false, 0, nullptr); 1951 1952 InVals.push_back(ArgValue); 1953 } 1954 } 1955 1956 // varargs 1957 if (isVarArg) { 1958 if (!Subtarget->isTargetDarwin()) { 1959 // The AAPCS variadic function ABI is identical to the non-variadic 1960 // one. As a result there may be more arguments in registers and we should 1961 // save them for future reference. 1962 saveVarArgRegisters(CCInfo, DAG, DL, Chain); 1963 } 1964 1965 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); 1966 // This will point to the next argument passed via stack. 1967 unsigned StackOffset = CCInfo.getNextStackOffset(); 1968 // We currently pass all varargs at 8-byte alignment. 1969 StackOffset = ((StackOffset + 7) & ~7); 1970 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true)); 1971 } 1972 1973 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 1974 unsigned StackArgSize = CCInfo.getNextStackOffset(); 1975 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; 1976 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) { 1977 // This is a non-standard ABI so by fiat I say we're allowed to make full 1978 // use of the stack area to be popped, which must be aligned to 16 bytes in 1979 // any case: 1980 StackArgSize = RoundUpToAlignment(StackArgSize, 16); 1981 1982 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding 1983 // a multiple of 16. 1984 FuncInfo->setArgumentStackToRestore(StackArgSize); 1985 1986 // This realignment carries over to the available bytes below. Our own 1987 // callers will guarantee the space is free by giving an aligned value to 1988 // CALLSEQ_START. 1989 } 1990 // Even if we're not expected to free up the space, it's useful to know how 1991 // much is there while considering tail calls (because we can reuse it). 1992 FuncInfo->setBytesInStackArgArea(StackArgSize); 1993 1994 return Chain; 1995 } 1996 1997 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo, 1998 SelectionDAG &DAG, SDLoc DL, 1999 SDValue &Chain) const { 2000 MachineFunction &MF = DAG.getMachineFunction(); 2001 MachineFrameInfo *MFI = MF.getFrameInfo(); 2002 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 2003 2004 SmallVector<SDValue, 8> MemOps; 2005 2006 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2, 2007 AArch64::X3, AArch64::X4, AArch64::X5, 2008 AArch64::X6, AArch64::X7 }; 2009 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs); 2010 unsigned FirstVariadicGPR = 2011 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs); 2012 2013 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR); 2014 int GPRIdx = 0; 2015 if (GPRSaveSize != 0) { 2016 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false); 2017 2018 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy()); 2019 2020 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) { 2021 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); 2022 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 2023 SDValue Store = 2024 DAG.getStore(Val.getValue(1), DL, Val, FIN, 2025 MachinePointerInfo::getStack(i * 8), false, false, 0); 2026 MemOps.push_back(Store); 2027 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, 2028 DAG.getConstant(8, getPointerTy())); 2029 } 2030 } 2031 FuncInfo->setVarArgsGPRIndex(GPRIdx); 2032 FuncInfo->setVarArgsGPRSize(GPRSaveSize); 2033 2034 if (Subtarget->hasFPARMv8()) { 2035 static const MCPhysReg FPRArgRegs[] = { 2036 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, 2037 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7}; 2038 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs); 2039 unsigned FirstVariadicFPR = 2040 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs); 2041 2042 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR); 2043 int FPRIdx = 0; 2044 if (FPRSaveSize != 0) { 2045 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false); 2046 2047 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy()); 2048 2049 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) { 2050 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass); 2051 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128); 2052 2053 SDValue Store = 2054 DAG.getStore(Val.getValue(1), DL, Val, FIN, 2055 MachinePointerInfo::getStack(i * 16), false, false, 0); 2056 MemOps.push_back(Store); 2057 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, 2058 DAG.getConstant(16, getPointerTy())); 2059 } 2060 } 2061 FuncInfo->setVarArgsFPRIndex(FPRIdx); 2062 FuncInfo->setVarArgsFPRSize(FPRSaveSize); 2063 } 2064 2065 if (!MemOps.empty()) { 2066 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); 2067 } 2068 } 2069 2070 /// LowerCallResult - Lower the result values of a call into the 2071 /// appropriate copies out of appropriate physical registers. 2072 SDValue AArch64TargetLowering::LowerCallResult( 2073 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, 2074 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 2075 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 2076 SDValue ThisVal) const { 2077 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS 2078 ? RetCC_AArch64_WebKit_JS 2079 : RetCC_AArch64_AAPCS; 2080 // Assign locations to each value returned by this call. 2081 SmallVector<CCValAssign, 16> RVLocs; 2082 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 2083 *DAG.getContext()); 2084 CCInfo.AnalyzeCallResult(Ins, RetCC); 2085 2086 // Copy all of the result registers out of their specified physreg. 2087 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2088 CCValAssign VA = RVLocs[i]; 2089 2090 // Pass 'this' value directly from the argument to return value, to avoid 2091 // reg unit interference 2092 if (i == 0 && isThisReturn) { 2093 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 && 2094 "unexpected return calling convention register assignment"); 2095 InVals.push_back(ThisVal); 2096 continue; 2097 } 2098 2099 SDValue Val = 2100 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag); 2101 Chain = Val.getValue(1); 2102 InFlag = Val.getValue(2); 2103 2104 switch (VA.getLocInfo()) { 2105 default: 2106 llvm_unreachable("Unknown loc info!"); 2107 case CCValAssign::Full: 2108 break; 2109 case CCValAssign::BCvt: 2110 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 2111 break; 2112 } 2113 2114 InVals.push_back(Val); 2115 } 2116 2117 return Chain; 2118 } 2119 2120 bool AArch64TargetLowering::isEligibleForTailCallOptimization( 2121 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 2122 bool isCalleeStructRet, bool isCallerStructRet, 2123 const SmallVectorImpl<ISD::OutputArg> &Outs, 2124 const SmallVectorImpl<SDValue> &OutVals, 2125 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const { 2126 // For CallingConv::C this function knows whether the ABI needs 2127 // changing. That's not true for other conventions so they will have to opt in 2128 // manually. 2129 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 2130 return false; 2131 2132 const MachineFunction &MF = DAG.getMachineFunction(); 2133 const Function *CallerF = MF.getFunction(); 2134 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2135 bool CCMatch = CallerCC == CalleeCC; 2136 2137 // Byval parameters hand the function a pointer directly into the stack area 2138 // we want to reuse during a tail call. Working around this *is* possible (see 2139 // X86) but less efficient and uglier in LowerCall. 2140 for (Function::const_arg_iterator i = CallerF->arg_begin(), 2141 e = CallerF->arg_end(); 2142 i != e; ++i) 2143 if (i->hasByValAttr()) 2144 return false; 2145 2146 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2147 if (IsTailCallConvention(CalleeCC) && CCMatch) 2148 return true; 2149 return false; 2150 } 2151 2152 // Externally-defined functions with weak linkage should not be 2153 // tail-called on AArch64 when the OS does not support dynamic 2154 // pre-emption of symbols, as the AAELF spec requires normal calls 2155 // to undefined weak functions to be replaced with a NOP or jump to the 2156 // next instruction. The behaviour of branch instructions in this 2157 // situation (as used for tail calls) is implementation-defined, so we 2158 // cannot rely on the linker replacing the tail call with a return. 2159 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2160 const GlobalValue *GV = G->getGlobal(); 2161 if (GV->hasExternalWeakLinkage()) 2162 return false; 2163 } 2164 2165 // Now we search for cases where we can use a tail call without changing the 2166 // ABI. Sibcall is used in some places (particularly gcc) to refer to this 2167 // concept. 2168 2169 // I want anyone implementing a new calling convention to think long and hard 2170 // about this assert. 2171 assert((!isVarArg || CalleeCC == CallingConv::C) && 2172 "Unexpected variadic calling convention"); 2173 2174 if (isVarArg && !Outs.empty()) { 2175 // At least two cases here: if caller is fastcc then we can't have any 2176 // memory arguments (we'd be expected to clean up the stack afterwards). If 2177 // caller is C then we could potentially use its argument area. 2178 2179 // FIXME: for now we take the most conservative of these in both cases: 2180 // disallow all variadic memory operands. 2181 SmallVector<CCValAssign, 16> ArgLocs; 2182 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, 2183 *DAG.getContext()); 2184 2185 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true)); 2186 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2187 if (!ArgLocs[i].isRegLoc()) 2188 return false; 2189 } 2190 2191 // If the calling conventions do not match, then we'd better make sure the 2192 // results are returned in the same way as what the caller expects. 2193 if (!CCMatch) { 2194 SmallVector<CCValAssign, 16> RVLocs1; 2195 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1, 2196 *DAG.getContext()); 2197 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg)); 2198 2199 SmallVector<CCValAssign, 16> RVLocs2; 2200 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2, 2201 *DAG.getContext()); 2202 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg)); 2203 2204 if (RVLocs1.size() != RVLocs2.size()) 2205 return false; 2206 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2207 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2208 return false; 2209 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2210 return false; 2211 if (RVLocs1[i].isRegLoc()) { 2212 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2213 return false; 2214 } else { 2215 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2216 return false; 2217 } 2218 } 2219 } 2220 2221 // Nothing more to check if the callee is taking no arguments 2222 if (Outs.empty()) 2223 return true; 2224 2225 SmallVector<CCValAssign, 16> ArgLocs; 2226 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, 2227 *DAG.getContext()); 2228 2229 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg)); 2230 2231 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 2232 2233 // If the stack arguments for this call would fit into our own save area then 2234 // the call can be made tail. 2235 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea(); 2236 } 2237 2238 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain, 2239 SelectionDAG &DAG, 2240 MachineFrameInfo *MFI, 2241 int ClobberedFI) const { 2242 SmallVector<SDValue, 8> ArgChains; 2243 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI); 2244 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1; 2245 2246 // Include the original chain at the beginning of the list. When this is 2247 // used by target LowerCall hooks, this helps legalize find the 2248 // CALLSEQ_BEGIN node. 2249 ArgChains.push_back(Chain); 2250 2251 // Add a chain value for each stack argument corresponding 2252 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(), 2253 UE = DAG.getEntryNode().getNode()->use_end(); 2254 U != UE; ++U) 2255 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) 2256 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) 2257 if (FI->getIndex() < 0) { 2258 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex()); 2259 int64_t InLastByte = InFirstByte; 2260 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1; 2261 2262 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) || 2263 (FirstByte <= InFirstByte && InFirstByte <= LastByte)) 2264 ArgChains.push_back(SDValue(L, 1)); 2265 } 2266 2267 // Build a tokenfactor for all the chains. 2268 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); 2269 } 2270 2271 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC, 2272 bool TailCallOpt) const { 2273 return CallCC == CallingConv::Fast && TailCallOpt; 2274 } 2275 2276 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const { 2277 return CallCC == CallingConv::Fast; 2278 } 2279 2280 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain, 2281 /// and add input and output parameter nodes. 2282 SDValue 2283 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, 2284 SmallVectorImpl<SDValue> &InVals) const { 2285 SelectionDAG &DAG = CLI.DAG; 2286 SDLoc &DL = CLI.DL; 2287 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2288 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2289 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2290 SDValue Chain = CLI.Chain; 2291 SDValue Callee = CLI.Callee; 2292 bool &IsTailCall = CLI.IsTailCall; 2293 CallingConv::ID CallConv = CLI.CallConv; 2294 bool IsVarArg = CLI.IsVarArg; 2295 2296 MachineFunction &MF = DAG.getMachineFunction(); 2297 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 2298 bool IsThisReturn = false; 2299 2300 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 2301 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; 2302 bool IsSibCall = false; 2303 2304 if (IsTailCall) { 2305 // Check if it's really possible to do a tail call. 2306 IsTailCall = isEligibleForTailCallOptimization( 2307 Callee, CallConv, IsVarArg, IsStructRet, 2308 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG); 2309 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2310 report_fatal_error("failed to perform tail call elimination on a call " 2311 "site marked musttail"); 2312 2313 // A sibling call is one where we're under the usual C ABI and not planning 2314 // to change that but can still do a tail call: 2315 if (!TailCallOpt && IsTailCall) 2316 IsSibCall = true; 2317 2318 if (IsTailCall) 2319 ++NumTailCalls; 2320 } 2321 2322 // Analyze operands of the call, assigning locations to each operand. 2323 SmallVector<CCValAssign, 16> ArgLocs; 2324 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 2325 *DAG.getContext()); 2326 2327 if (IsVarArg) { 2328 // Handle fixed and variable vector arguments differently. 2329 // Variable vector arguments always go into memory. 2330 unsigned NumArgs = Outs.size(); 2331 2332 for (unsigned i = 0; i != NumArgs; ++i) { 2333 MVT ArgVT = Outs[i].VT; 2334 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2335 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, 2336 /*IsVarArg=*/ !Outs[i].IsFixed); 2337 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 2338 assert(!Res && "Call operand has unhandled type"); 2339 (void)Res; 2340 } 2341 } else { 2342 // At this point, Outs[].VT may already be promoted to i32. To correctly 2343 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and 2344 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT. 2345 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here 2346 // we use a special version of AnalyzeCallOperands to pass in ValVT and 2347 // LocVT. 2348 unsigned NumArgs = Outs.size(); 2349 for (unsigned i = 0; i != NumArgs; ++i) { 2350 MVT ValVT = Outs[i].VT; 2351 // Get type of the original argument. 2352 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty, 2353 /*AllowUnknown*/ true); 2354 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT; 2355 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2356 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16. 2357 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) 2358 ValVT = MVT::i8; 2359 else if (ActualMVT == MVT::i16) 2360 ValVT = MVT::i16; 2361 2362 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false); 2363 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo); 2364 assert(!Res && "Call operand has unhandled type"); 2365 (void)Res; 2366 } 2367 } 2368 2369 // Get a count of how many bytes are to be pushed on the stack. 2370 unsigned NumBytes = CCInfo.getNextStackOffset(); 2371 2372 if (IsSibCall) { 2373 // Since we're not changing the ABI to make this a tail call, the memory 2374 // operands are already available in the caller's incoming argument space. 2375 NumBytes = 0; 2376 } 2377 2378 // FPDiff is the byte offset of the call's argument area from the callee's. 2379 // Stores to callee stack arguments will be placed in FixedStackSlots offset 2380 // by this amount for a tail call. In a sibling call it must be 0 because the 2381 // caller will deallocate the entire stack and the callee still expects its 2382 // arguments to begin at SP+0. Completely unused for non-tail calls. 2383 int FPDiff = 0; 2384 2385 if (IsTailCall && !IsSibCall) { 2386 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea(); 2387 2388 // Since callee will pop argument stack as a tail call, we must keep the 2389 // popped size 16-byte aligned. 2390 NumBytes = RoundUpToAlignment(NumBytes, 16); 2391 2392 // FPDiff will be negative if this tail call requires more space than we 2393 // would automatically have in our incoming argument space. Positive if we 2394 // can actually shrink the stack. 2395 FPDiff = NumReusableBytes - NumBytes; 2396 2397 // The stack pointer must be 16-byte aligned at all times it's used for a 2398 // memory operation, which in practice means at *all* times and in 2399 // particular across call boundaries. Therefore our own arguments started at 2400 // a 16-byte aligned SP and the delta applied for the tail call should 2401 // satisfy the same constraint. 2402 assert(FPDiff % 16 == 0 && "unaligned stack on tail call"); 2403 } 2404 2405 // Adjust the stack pointer for the new arguments... 2406 // These operations are automatically eliminated by the prolog/epilog pass 2407 if (!IsSibCall) 2408 Chain = 2409 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL); 2410 2411 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy()); 2412 2413 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2414 SmallVector<SDValue, 8> MemOpChains; 2415 2416 // Walk the register/memloc assignments, inserting copies/loads. 2417 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e; 2418 ++i, ++realArgIdx) { 2419 CCValAssign &VA = ArgLocs[i]; 2420 SDValue Arg = OutVals[realArgIdx]; 2421 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 2422 2423 // Promote the value if needed. 2424 switch (VA.getLocInfo()) { 2425 default: 2426 llvm_unreachable("Unknown loc info!"); 2427 case CCValAssign::Full: 2428 break; 2429 case CCValAssign::SExt: 2430 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 2431 break; 2432 case CCValAssign::ZExt: 2433 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 2434 break; 2435 case CCValAssign::AExt: 2436 if (Outs[realArgIdx].ArgVT == MVT::i1) { 2437 // AAPCS requires i1 to be zero-extended to 8-bits by the caller. 2438 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg); 2439 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg); 2440 } 2441 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 2442 break; 2443 case CCValAssign::BCvt: 2444 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 2445 break; 2446 case CCValAssign::FPExt: 2447 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); 2448 break; 2449 } 2450 2451 if (VA.isRegLoc()) { 2452 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) { 2453 assert(VA.getLocVT() == MVT::i64 && 2454 "unexpected calling convention register assignment"); 2455 assert(!Ins.empty() && Ins[0].VT == MVT::i64 && 2456 "unexpected use of 'returned'"); 2457 IsThisReturn = true; 2458 } 2459 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2460 } else { 2461 assert(VA.isMemLoc()); 2462 2463 SDValue DstAddr; 2464 MachinePointerInfo DstInfo; 2465 2466 // FIXME: This works on big-endian for composite byvals, which are the 2467 // common case. It should also work for fundamental types too. 2468 uint32_t BEAlign = 0; 2469 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8 2470 : VA.getValVT().getSizeInBits(); 2471 OpSize = (OpSize + 7) / 8; 2472 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) { 2473 if (OpSize < 8) 2474 BEAlign = 8 - OpSize; 2475 } 2476 unsigned LocMemOffset = VA.getLocMemOffset(); 2477 int32_t Offset = LocMemOffset + BEAlign; 2478 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 2479 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 2480 2481 if (IsTailCall) { 2482 Offset = Offset + FPDiff; 2483 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2484 2485 DstAddr = DAG.getFrameIndex(FI, getPointerTy()); 2486 DstInfo = MachinePointerInfo::getFixedStack(FI); 2487 2488 // Make sure any stack arguments overlapping with where we're storing 2489 // are loaded before this eventual operation. Otherwise they'll be 2490 // clobbered. 2491 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI); 2492 } else { 2493 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 2494 2495 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 2496 DstInfo = MachinePointerInfo::getStack(LocMemOffset); 2497 } 2498 2499 if (Outs[i].Flags.isByVal()) { 2500 SDValue SizeNode = 2501 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64); 2502 SDValue Cpy = DAG.getMemcpy( 2503 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(), 2504 /*isVol = */ false, 2505 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo()); 2506 2507 MemOpChains.push_back(Cpy); 2508 } else { 2509 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already 2510 // promoted to a legal register type i32, we should truncate Arg back to 2511 // i1/i8/i16. 2512 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 || 2513 VA.getValVT() == MVT::i16) 2514 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); 2515 2516 SDValue Store = 2517 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0); 2518 MemOpChains.push_back(Store); 2519 } 2520 } 2521 } 2522 2523 if (!MemOpChains.empty()) 2524 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2525 2526 // Build a sequence of copy-to-reg nodes chained together with token chain 2527 // and flag operands which copy the outgoing args into the appropriate regs. 2528 SDValue InFlag; 2529 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2530 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first, 2531 RegsToPass[i].second, InFlag); 2532 InFlag = Chain.getValue(1); 2533 } 2534 2535 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2536 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2537 // node so that legalize doesn't hack it. 2538 if (getTargetMachine().getCodeModel() == CodeModel::Large && 2539 Subtarget->isTargetMachO()) { 2540 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2541 const GlobalValue *GV = G->getGlobal(); 2542 bool InternalLinkage = GV->hasInternalLinkage(); 2543 if (InternalLinkage) 2544 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0); 2545 else { 2546 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 2547 AArch64II::MO_GOT); 2548 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee); 2549 } 2550 } else if (ExternalSymbolSDNode *S = 2551 dyn_cast<ExternalSymbolSDNode>(Callee)) { 2552 const char *Sym = S->getSymbol(); 2553 Callee = 2554 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT); 2555 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee); 2556 } 2557 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2558 const GlobalValue *GV = G->getGlobal(); 2559 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0); 2560 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2561 const char *Sym = S->getSymbol(); 2562 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0); 2563 } 2564 2565 // We don't usually want to end the call-sequence here because we would tidy 2566 // the frame up *after* the call, however in the ABI-changing tail-call case 2567 // we've carefully laid out the parameters so that when sp is reset they'll be 2568 // in the correct location. 2569 if (IsTailCall && !IsSibCall) { 2570 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2571 DAG.getIntPtrConstant(0, true), InFlag, DL); 2572 InFlag = Chain.getValue(1); 2573 } 2574 2575 std::vector<SDValue> Ops; 2576 Ops.push_back(Chain); 2577 Ops.push_back(Callee); 2578 2579 if (IsTailCall) { 2580 // Each tail call may have to adjust the stack by a different amount, so 2581 // this information must travel along with the operation for eventual 2582 // consumption by emitEpilogue. 2583 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32)); 2584 } 2585 2586 // Add argument registers to the end of the list so that they are known live 2587 // into the call. 2588 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2589 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2590 RegsToPass[i].second.getValueType())); 2591 2592 // Add a register mask operand representing the call-preserved registers. 2593 const uint32_t *Mask; 2594 const TargetRegisterInfo *TRI = 2595 getTargetMachine().getSubtargetImpl()->getRegisterInfo(); 2596 const AArch64RegisterInfo *ARI = 2597 static_cast<const AArch64RegisterInfo *>(TRI); 2598 if (IsThisReturn) { 2599 // For 'this' returns, use the X0-preserving mask if applicable 2600 Mask = ARI->getThisReturnPreservedMask(CallConv); 2601 if (!Mask) { 2602 IsThisReturn = false; 2603 Mask = ARI->getCallPreservedMask(CallConv); 2604 } 2605 } else 2606 Mask = ARI->getCallPreservedMask(CallConv); 2607 2608 assert(Mask && "Missing call preserved mask for calling convention"); 2609 Ops.push_back(DAG.getRegisterMask(Mask)); 2610 2611 if (InFlag.getNode()) 2612 Ops.push_back(InFlag); 2613 2614 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2615 2616 // If we're doing a tall call, use a TC_RETURN here rather than an 2617 // actual call instruction. 2618 if (IsTailCall) 2619 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops); 2620 2621 // Returns a chain and a flag for retval copy to use. 2622 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops); 2623 InFlag = Chain.getValue(1); 2624 2625 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt) 2626 ? RoundUpToAlignment(NumBytes, 16) 2627 : 0; 2628 2629 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2630 DAG.getIntPtrConstant(CalleePopBytes, true), 2631 InFlag, DL); 2632 if (!Ins.empty()) 2633 InFlag = Chain.getValue(1); 2634 2635 // Handle result values, copying them out of physregs into vregs that we 2636 // return. 2637 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2638 InVals, IsThisReturn, 2639 IsThisReturn ? OutVals[0] : SDValue()); 2640 } 2641 2642 bool AArch64TargetLowering::CanLowerReturn( 2643 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, 2644 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { 2645 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS 2646 ? RetCC_AArch64_WebKit_JS 2647 : RetCC_AArch64_AAPCS; 2648 SmallVector<CCValAssign, 16> RVLocs; 2649 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 2650 return CCInfo.CheckReturn(Outs, RetCC); 2651 } 2652 2653 SDValue 2654 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 2655 bool isVarArg, 2656 const SmallVectorImpl<ISD::OutputArg> &Outs, 2657 const SmallVectorImpl<SDValue> &OutVals, 2658 SDLoc DL, SelectionDAG &DAG) const { 2659 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS 2660 ? RetCC_AArch64_WebKit_JS 2661 : RetCC_AArch64_AAPCS; 2662 SmallVector<CCValAssign, 16> RVLocs; 2663 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 2664 *DAG.getContext()); 2665 CCInfo.AnalyzeReturn(Outs, RetCC); 2666 2667 // Copy the result values into the output registers. 2668 SDValue Flag; 2669 SmallVector<SDValue, 4> RetOps(1, Chain); 2670 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size(); 2671 ++i, ++realRVLocIdx) { 2672 CCValAssign &VA = RVLocs[i]; 2673 assert(VA.isRegLoc() && "Can only return in registers!"); 2674 SDValue Arg = OutVals[realRVLocIdx]; 2675 2676 switch (VA.getLocInfo()) { 2677 default: 2678 llvm_unreachable("Unknown loc info!"); 2679 case CCValAssign::Full: 2680 if (Outs[i].ArgVT == MVT::i1) { 2681 // AAPCS requires i1 to be zero-extended to i8 by the producer of the 2682 // value. This is strictly redundant on Darwin (which uses "zeroext 2683 // i1"), but will be optimised out before ISel. 2684 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg); 2685 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 2686 } 2687 break; 2688 case CCValAssign::BCvt: 2689 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 2690 break; 2691 } 2692 2693 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); 2694 Flag = Chain.getValue(1); 2695 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2696 } 2697 2698 RetOps[0] = Chain; // Update chain. 2699 2700 // Add the flag if we have it. 2701 if (Flag.getNode()) 2702 RetOps.push_back(Flag); 2703 2704 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps); 2705 } 2706 2707 //===----------------------------------------------------------------------===// 2708 // Other Lowering Code 2709 //===----------------------------------------------------------------------===// 2710 2711 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op, 2712 SelectionDAG &DAG) const { 2713 EVT PtrVT = getPointerTy(); 2714 SDLoc DL(Op); 2715 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op); 2716 const GlobalValue *GV = GN->getGlobal(); 2717 unsigned char OpFlags = 2718 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 2719 2720 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 && 2721 "unexpected offset in global node"); 2722 2723 // This also catched the large code model case for Darwin. 2724 if ((OpFlags & AArch64II::MO_GOT) != 0) { 2725 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags); 2726 // FIXME: Once remat is capable of dealing with instructions with register 2727 // operands, expand this into two nodes instead of using a wrapper node. 2728 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr); 2729 } 2730 2731 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) { 2732 assert(getTargetMachine().getCodeModel() == CodeModel::Small && 2733 "use of MO_CONSTPOOL only supported on small model"); 2734 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE); 2735 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 2736 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC; 2737 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags); 2738 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 2739 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr, 2740 MachinePointerInfo::getConstantPool(), 2741 /*isVolatile=*/ false, 2742 /*isNonTemporal=*/ true, 2743 /*isInvariant=*/ true, 8); 2744 if (GN->getOffset() != 0) 2745 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr, 2746 DAG.getConstant(GN->getOffset(), PtrVT)); 2747 return GlobalAddr; 2748 } 2749 2750 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2751 const unsigned char MO_NC = AArch64II::MO_NC; 2752 return DAG.getNode( 2753 AArch64ISD::WrapperLarge, DL, PtrVT, 2754 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3), 2755 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC), 2756 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC), 2757 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC)); 2758 } else { 2759 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and 2760 // the only correct model on Darwin. 2761 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2762 OpFlags | AArch64II::MO_PAGE); 2763 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC; 2764 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags); 2765 2766 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 2767 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 2768 } 2769 } 2770 2771 /// \brief Convert a TLS address reference into the correct sequence of loads 2772 /// and calls to compute the variable's address (for Darwin, currently) and 2773 /// return an SDValue containing the final node. 2774 2775 /// Darwin only has one TLS scheme which must be capable of dealing with the 2776 /// fully general situation, in the worst case. This means: 2777 /// + "extern __thread" declaration. 2778 /// + Defined in a possibly unknown dynamic library. 2779 /// 2780 /// The general system is that each __thread variable has a [3 x i64] descriptor 2781 /// which contains information used by the runtime to calculate the address. The 2782 /// only part of this the compiler needs to know about is the first xword, which 2783 /// contains a function pointer that must be called with the address of the 2784 /// entire descriptor in "x0". 2785 /// 2786 /// Since this descriptor may be in a different unit, in general even the 2787 /// descriptor must be accessed via an indirect load. The "ideal" code sequence 2788 /// is: 2789 /// adrp x0, _var@TLVPPAGE 2790 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor 2791 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor, 2792 /// ; the function pointer 2793 /// blr x1 ; Uses descriptor address in x0 2794 /// ; Address of _var is now in x0. 2795 /// 2796 /// If the address of _var's descriptor *is* known to the linker, then it can 2797 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for 2798 /// a slight efficiency gain. 2799 SDValue 2800 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op, 2801 SelectionDAG &DAG) const { 2802 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin"); 2803 2804 SDLoc DL(Op); 2805 MVT PtrVT = getPointerTy(); 2806 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2807 2808 SDValue TLVPAddr = 2809 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS); 2810 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr); 2811 2812 // The first entry in the descriptor is a function pointer that we must call 2813 // to obtain the address of the variable. 2814 SDValue Chain = DAG.getEntryNode(); 2815 SDValue FuncTLVGet = 2816 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(), 2817 false, true, true, 8); 2818 Chain = FuncTLVGet.getValue(1); 2819 2820 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2821 MFI->setAdjustsStack(true); 2822 2823 // TLS calls preserve all registers except those that absolutely must be 2824 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be 2825 // silly). 2826 const TargetRegisterInfo *TRI = 2827 getTargetMachine().getSubtargetImpl()->getRegisterInfo(); 2828 const AArch64RegisterInfo *ARI = 2829 static_cast<const AArch64RegisterInfo *>(TRI); 2830 const uint32_t *Mask = ARI->getTLSCallPreservedMask(); 2831 2832 // Finally, we can make the call. This is just a degenerate version of a 2833 // normal AArch64 call node: x0 takes the address of the descriptor, and 2834 // returns the address of the variable in this thread. 2835 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue()); 2836 Chain = 2837 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue), 2838 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64), 2839 DAG.getRegisterMask(Mask), Chain.getValue(1)); 2840 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1)); 2841 } 2842 2843 /// When accessing thread-local variables under either the general-dynamic or 2844 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will 2845 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry 2846 /// is a function pointer to carry out the resolution. This function takes the 2847 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All 2848 /// other registers (except LR, NZCV) are preserved. 2849 /// 2850 /// Thus, the ideal call sequence on AArch64 is: 2851 /// 2852 /// adrp x0, :tlsdesc:thread_var 2853 /// ldr x8, [x0, :tlsdesc_lo12:thread_var] 2854 /// add x0, x0, :tlsdesc_lo12:thread_var 2855 /// .tlsdesccall thread_var 2856 /// blr x8 2857 /// (TPIDR_EL0 offset now in x0). 2858 /// 2859 /// The ".tlsdesccall" directive instructs the assembler to insert a particular 2860 /// relocation to help the linker relax this sequence if it turns out to be too 2861 /// conservative. 2862 /// 2863 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this 2864 /// is harmless. 2865 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr, 2866 SDValue DescAddr, SDLoc DL, 2867 SelectionDAG &DAG) const { 2868 EVT PtrVT = getPointerTy(); 2869 2870 // The function we need to call is simply the first entry in the GOT for this 2871 // descriptor, load it in preparation. 2872 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr); 2873 2874 // TLS calls preserve all registers except those that absolutely must be 2875 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be 2876 // silly). 2877 const TargetRegisterInfo *TRI = 2878 getTargetMachine().getSubtargetImpl()->getRegisterInfo(); 2879 const AArch64RegisterInfo *ARI = 2880 static_cast<const AArch64RegisterInfo *>(TRI); 2881 const uint32_t *Mask = ARI->getTLSCallPreservedMask(); 2882 2883 // The function takes only one argument: the address of the descriptor itself 2884 // in X0. 2885 SDValue Glue, Chain; 2886 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue); 2887 Glue = Chain.getValue(1); 2888 2889 // We're now ready to populate the argument list, as with a normal call: 2890 SmallVector<SDValue, 6> Ops; 2891 Ops.push_back(Chain); 2892 Ops.push_back(Func); 2893 Ops.push_back(SymAddr); 2894 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT)); 2895 Ops.push_back(DAG.getRegisterMask(Mask)); 2896 Ops.push_back(Glue); 2897 2898 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2899 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops); 2900 Glue = Chain.getValue(1); 2901 2902 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue); 2903 } 2904 2905 SDValue 2906 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op, 2907 SelectionDAG &DAG) const { 2908 assert(Subtarget->isTargetELF() && "This function expects an ELF target"); 2909 assert(getTargetMachine().getCodeModel() == CodeModel::Small && 2910 "ELF TLS only supported in small memory model"); 2911 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2912 2913 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal()); 2914 2915 SDValue TPOff; 2916 EVT PtrVT = getPointerTy(); 2917 SDLoc DL(Op); 2918 const GlobalValue *GV = GA->getGlobal(); 2919 2920 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT); 2921 2922 if (Model == TLSModel::LocalExec) { 2923 SDValue HiVar = DAG.getTargetGlobalAddress( 2924 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1); 2925 SDValue LoVar = DAG.getTargetGlobalAddress( 2926 GV, DL, PtrVT, 0, 2927 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC); 2928 2929 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar, 2930 DAG.getTargetConstant(16, MVT::i32)), 2931 0); 2932 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar, 2933 DAG.getTargetConstant(0, MVT::i32)), 2934 0); 2935 } else if (Model == TLSModel::InitialExec) { 2936 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS); 2937 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff); 2938 } else if (Model == TLSModel::LocalDynamic) { 2939 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS 2940 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate 2941 // the beginning of the module's TLS region, followed by a DTPREL offset 2942 // calculation. 2943 2944 // These accesses will need deduplicating if there's more than one. 2945 AArch64FunctionInfo *MFI = 2946 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>(); 2947 MFI->incNumLocalDynamicTLSAccesses(); 2948 2949 // Accesses used in this sequence go via the TLS descriptor which lives in 2950 // the GOT. Prepare an address we can use to handle this. 2951 SDValue HiDesc = DAG.getTargetExternalSymbol( 2952 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE); 2953 SDValue LoDesc = DAG.getTargetExternalSymbol( 2954 "_TLS_MODULE_BASE_", PtrVT, 2955 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC); 2956 2957 // First argument to the descriptor call is the address of the descriptor 2958 // itself. 2959 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc); 2960 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc); 2961 2962 // The call needs a relocation too for linker relaxation. It doesn't make 2963 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of 2964 // the address. 2965 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT, 2966 AArch64II::MO_TLS); 2967 2968 // Now we can calculate the offset from TPIDR_EL0 to this module's 2969 // thread-local area. 2970 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG); 2971 2972 // Now use :dtprel_whatever: operations to calculate this variable's offset 2973 // in its thread-storage area. 2974 SDValue HiVar = DAG.getTargetGlobalAddress( 2975 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1); 2976 SDValue LoVar = DAG.getTargetGlobalAddress( 2977 GV, DL, MVT::i64, 0, 2978 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC); 2979 2980 SDValue DTPOff = 2981 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar, 2982 DAG.getTargetConstant(16, MVT::i32)), 2983 0); 2984 DTPOff = 2985 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar, 2986 DAG.getTargetConstant(0, MVT::i32)), 2987 0); 2988 2989 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff); 2990 } else if (Model == TLSModel::GeneralDynamic) { 2991 // Accesses used in this sequence go via the TLS descriptor which lives in 2992 // the GOT. Prepare an address we can use to handle this. 2993 SDValue HiDesc = DAG.getTargetGlobalAddress( 2994 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE); 2995 SDValue LoDesc = DAG.getTargetGlobalAddress( 2996 GV, DL, PtrVT, 0, 2997 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC); 2998 2999 // First argument to the descriptor call is the address of the descriptor 3000 // itself. 3001 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc); 3002 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc); 3003 3004 // The call needs a relocation too for linker relaxation. It doesn't make 3005 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of 3006 // the address. 3007 SDValue SymAddr = 3008 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS); 3009 3010 // Finally we can make a call to calculate the offset from tpidr_el0. 3011 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG); 3012 } else 3013 llvm_unreachable("Unsupported ELF TLS access model"); 3014 3015 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff); 3016 } 3017 3018 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op, 3019 SelectionDAG &DAG) const { 3020 if (Subtarget->isTargetDarwin()) 3021 return LowerDarwinGlobalTLSAddress(Op, DAG); 3022 else if (Subtarget->isTargetELF()) 3023 return LowerELFGlobalTLSAddress(Op, DAG); 3024 3025 llvm_unreachable("Unexpected platform trying to use TLS"); 3026 } 3027 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 3028 SDValue Chain = Op.getOperand(0); 3029 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 3030 SDValue LHS = Op.getOperand(2); 3031 SDValue RHS = Op.getOperand(3); 3032 SDValue Dest = Op.getOperand(4); 3033 SDLoc dl(Op); 3034 3035 // Handle f128 first, since lowering it will result in comparing the return 3036 // value of a libcall against zero, which is just what the rest of LowerBR_CC 3037 // is expecting to deal with. 3038 if (LHS.getValueType() == MVT::f128) { 3039 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 3040 3041 // If softenSetCCOperands returned a scalar, we need to compare the result 3042 // against zero to select between true and false values. 3043 if (!RHS.getNode()) { 3044 RHS = DAG.getConstant(0, LHS.getValueType()); 3045 CC = ISD::SETNE; 3046 } 3047 } 3048 3049 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch 3050 // instruction. 3051 unsigned Opc = LHS.getOpcode(); 3052 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) && 3053 cast<ConstantSDNode>(RHS)->isOne() && 3054 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || 3055 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { 3056 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && 3057 "Unexpected condition code."); 3058 // Only lower legal XALUO ops. 3059 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0))) 3060 return SDValue(); 3061 3062 // The actual operation with overflow check. 3063 AArch64CC::CondCode OFCC; 3064 SDValue Value, Overflow; 3065 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG); 3066 3067 if (CC == ISD::SETNE) 3068 OFCC = getInvertedCondCode(OFCC); 3069 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32); 3070 3071 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest, 3072 CCVal, Overflow); 3073 } 3074 3075 if (LHS.getValueType().isInteger()) { 3076 assert((LHS.getValueType() == RHS.getValueType()) && 3077 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)); 3078 3079 // If the RHS of the comparison is zero, we can potentially fold this 3080 // to a specialized branch. 3081 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS); 3082 if (RHSC && RHSC->getZExtValue() == 0) { 3083 if (CC == ISD::SETEQ) { 3084 // See if we can use a TBZ to fold in an AND as well. 3085 // TBZ has a smaller branch displacement than CBZ. If the offset is 3086 // out of bounds, a late MI-layer pass rewrites branches. 3087 // 403.gcc is an example that hits this case. 3088 if (LHS.getOpcode() == ISD::AND && 3089 isa<ConstantSDNode>(LHS.getOperand(1)) && 3090 isPowerOf2_64(LHS.getConstantOperandVal(1))) { 3091 SDValue Test = LHS.getOperand(0); 3092 uint64_t Mask = LHS.getConstantOperandVal(1); 3093 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test, 3094 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest); 3095 } 3096 3097 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest); 3098 } else if (CC == ISD::SETNE) { 3099 // See if we can use a TBZ to fold in an AND as well. 3100 // TBZ has a smaller branch displacement than CBZ. If the offset is 3101 // out of bounds, a late MI-layer pass rewrites branches. 3102 // 403.gcc is an example that hits this case. 3103 if (LHS.getOpcode() == ISD::AND && 3104 isa<ConstantSDNode>(LHS.getOperand(1)) && 3105 isPowerOf2_64(LHS.getConstantOperandVal(1))) { 3106 SDValue Test = LHS.getOperand(0); 3107 uint64_t Mask = LHS.getConstantOperandVal(1); 3108 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test, 3109 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest); 3110 } 3111 3112 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest); 3113 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) { 3114 // Don't combine AND since emitComparison converts the AND to an ANDS 3115 // (a.k.a. TST) and the test in the test bit and branch instruction 3116 // becomes redundant. This would also increase register pressure. 3117 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1; 3118 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS, 3119 DAG.getConstant(Mask, MVT::i64), Dest); 3120 } 3121 } 3122 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT && 3123 LHS.getOpcode() != ISD::AND) { 3124 // Don't combine AND since emitComparison converts the AND to an ANDS 3125 // (a.k.a. TST) and the test in the test bit and branch instruction 3126 // becomes redundant. This would also increase register pressure. 3127 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1; 3128 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS, 3129 DAG.getConstant(Mask, MVT::i64), Dest); 3130 } 3131 3132 SDValue CCVal; 3133 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); 3134 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, 3135 Cmp); 3136 } 3137 3138 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 3139 3140 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally 3141 // clean. Some of them require two branches to implement. 3142 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG); 3143 AArch64CC::CondCode CC1, CC2; 3144 changeFPCCToAArch64CC(CC, CC1, CC2); 3145 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32); 3146 SDValue BR1 = 3147 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp); 3148 if (CC2 != AArch64CC::AL) { 3149 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32); 3150 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val, 3151 Cmp); 3152 } 3153 3154 return BR1; 3155 } 3156 3157 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op, 3158 SelectionDAG &DAG) const { 3159 EVT VT = Op.getValueType(); 3160 SDLoc DL(Op); 3161 3162 SDValue In1 = Op.getOperand(0); 3163 SDValue In2 = Op.getOperand(1); 3164 EVT SrcVT = In2.getValueType(); 3165 if (SrcVT != VT) { 3166 if (SrcVT == MVT::f32 && VT == MVT::f64) 3167 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2); 3168 else if (SrcVT == MVT::f64 && VT == MVT::f32) 3169 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0)); 3170 else 3171 // FIXME: Src type is different, bail out for now. Can VT really be a 3172 // vector type? 3173 return SDValue(); 3174 } 3175 3176 EVT VecVT; 3177 EVT EltVT; 3178 SDValue EltMask, VecVal1, VecVal2; 3179 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) { 3180 EltVT = MVT::i32; 3181 VecVT = MVT::v4i32; 3182 EltMask = DAG.getConstant(0x80000000ULL, EltVT); 3183 3184 if (!VT.isVector()) { 3185 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT, 3186 DAG.getUNDEF(VecVT), In1); 3187 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT, 3188 DAG.getUNDEF(VecVT), In2); 3189 } else { 3190 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); 3191 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); 3192 } 3193 } else if (VT == MVT::f64 || VT == MVT::v2f64) { 3194 EltVT = MVT::i64; 3195 VecVT = MVT::v2i64; 3196 3197 // We want to materialize a mask with the the high bit set, but the AdvSIMD 3198 // immediate moves cannot materialize that in a single instruction for 3199 // 64-bit elements. Instead, materialize zero and then negate it. 3200 EltMask = DAG.getConstant(0, EltVT); 3201 3202 if (!VT.isVector()) { 3203 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT, 3204 DAG.getUNDEF(VecVT), In1); 3205 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT, 3206 DAG.getUNDEF(VecVT), In2); 3207 } else { 3208 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); 3209 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); 3210 } 3211 } else { 3212 llvm_unreachable("Invalid type for copysign!"); 3213 } 3214 3215 std::vector<SDValue> BuildVectorOps; 3216 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) 3217 BuildVectorOps.push_back(EltMask); 3218 3219 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps); 3220 3221 // If we couldn't materialize the mask above, then the mask vector will be 3222 // the zero vector, and we need to negate it here. 3223 if (VT == MVT::f64 || VT == MVT::v2f64) { 3224 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec); 3225 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec); 3226 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec); 3227 } 3228 3229 SDValue Sel = 3230 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec); 3231 3232 if (VT == MVT::f32) 3233 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel); 3234 else if (VT == MVT::f64) 3235 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel); 3236 else 3237 return DAG.getNode(ISD::BITCAST, DL, VT, Sel); 3238 } 3239 3240 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const { 3241 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute( 3242 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat)) 3243 return SDValue(); 3244 3245 // While there is no integer popcount instruction, it can 3246 // be more efficiently lowered to the following sequence that uses 3247 // AdvSIMD registers/instructions as long as the copies to/from 3248 // the AdvSIMD registers are cheap. 3249 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd 3250 // CNT V0.8B, V0.8B // 8xbyte pop-counts 3251 // ADDV B0, V0.8B // sum 8xbyte pop-counts 3252 // UMOV X0, V0.B[0] // copy byte result back to integer reg 3253 SDValue Val = Op.getOperand(0); 3254 SDLoc DL(Op); 3255 EVT VT = Op.getValueType(); 3256 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8); 3257 3258 SDValue VecVal; 3259 if (VT == MVT::i32) { 3260 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val); 3261 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec, 3262 VecVal); 3263 } else { 3264 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val); 3265 } 3266 3267 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal); 3268 SDValue UaddLV = DAG.getNode( 3269 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, 3270 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop); 3271 3272 if (VT == MVT::i64) 3273 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV); 3274 return UaddLV; 3275 } 3276 3277 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 3278 3279 if (Op.getValueType().isVector()) 3280 return LowerVSETCC(Op, DAG); 3281 3282 SDValue LHS = Op.getOperand(0); 3283 SDValue RHS = Op.getOperand(1); 3284 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 3285 SDLoc dl(Op); 3286 3287 // We chose ZeroOrOneBooleanContents, so use zero and one. 3288 EVT VT = Op.getValueType(); 3289 SDValue TVal = DAG.getConstant(1, VT); 3290 SDValue FVal = DAG.getConstant(0, VT); 3291 3292 // Handle f128 first, since one possible outcome is a normal integer 3293 // comparison which gets picked up by the next if statement. 3294 if (LHS.getValueType() == MVT::f128) { 3295 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 3296 3297 // If softenSetCCOperands returned a scalar, use it. 3298 if (!RHS.getNode()) { 3299 assert(LHS.getValueType() == Op.getValueType() && 3300 "Unexpected setcc expansion!"); 3301 return LHS; 3302 } 3303 } 3304 3305 if (LHS.getValueType().isInteger()) { 3306 SDValue CCVal; 3307 SDValue Cmp = 3308 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl); 3309 3310 // Note that we inverted the condition above, so we reverse the order of 3311 // the true and false operands here. This will allow the setcc to be 3312 // matched to a single CSINC instruction. 3313 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp); 3314 } 3315 3316 // Now we know we're dealing with FP values. 3317 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 3318 3319 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead 3320 // and do the comparison. 3321 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG); 3322 3323 AArch64CC::CondCode CC1, CC2; 3324 changeFPCCToAArch64CC(CC, CC1, CC2); 3325 if (CC2 == AArch64CC::AL) { 3326 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2); 3327 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32); 3328 3329 // Note that we inverted the condition above, so we reverse the order of 3330 // the true and false operands here. This will allow the setcc to be 3331 // matched to a single CSINC instruction. 3332 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp); 3333 } else { 3334 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't 3335 // totally clean. Some of them require two CSELs to implement. As is in 3336 // this case, we emit the first CSEL and then emit a second using the output 3337 // of the first as the RHS. We're effectively OR'ing the two CC's together. 3338 3339 // FIXME: It would be nice if we could match the two CSELs to two CSINCs. 3340 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32); 3341 SDValue CS1 = 3342 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); 3343 3344 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32); 3345 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); 3346 } 3347 } 3348 3349 /// A SELECT_CC operation is really some kind of max or min if both values being 3350 /// compared are, in some sense, equal to the results in either case. However, 3351 /// it is permissible to compare f32 values and produce directly extended f64 3352 /// values. 3353 /// 3354 /// Extending the comparison operands would also be allowed, but is less likely 3355 /// to happen in practice since their use is right here. Note that truncate 3356 /// operations would *not* be semantically equivalent. 3357 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) { 3358 if (Cmp == Result) 3359 return true; 3360 3361 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp); 3362 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result); 3363 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 && 3364 Result.getValueType() == MVT::f64) { 3365 bool Lossy; 3366 APFloat CmpVal = CCmp->getValueAPF(); 3367 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy); 3368 return CResult->getValueAPF().bitwiseIsEqual(CmpVal); 3369 } 3370 3371 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp; 3372 } 3373 3374 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op, 3375 SelectionDAG &DAG) const { 3376 SDValue CC = Op->getOperand(0); 3377 SDValue TVal = Op->getOperand(1); 3378 SDValue FVal = Op->getOperand(2); 3379 SDLoc DL(Op); 3380 3381 unsigned Opc = CC.getOpcode(); 3382 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select 3383 // instruction. 3384 if (CC.getResNo() == 1 && 3385 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || 3386 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { 3387 // Only lower legal XALUO ops. 3388 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0))) 3389 return SDValue(); 3390 3391 AArch64CC::CondCode OFCC; 3392 SDValue Value, Overflow; 3393 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG); 3394 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32); 3395 3396 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal, 3397 CCVal, Overflow); 3398 } 3399 3400 if (CC.getOpcode() == ISD::SETCC) 3401 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal, 3402 cast<CondCodeSDNode>(CC.getOperand(2))->get()); 3403 else 3404 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal, 3405 FVal, ISD::SETNE); 3406 } 3407 3408 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op, 3409 SelectionDAG &DAG) const { 3410 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3411 SDValue LHS = Op.getOperand(0); 3412 SDValue RHS = Op.getOperand(1); 3413 SDValue TVal = Op.getOperand(2); 3414 SDValue FVal = Op.getOperand(3); 3415 SDLoc dl(Op); 3416 3417 // Handle f128 first, because it will result in a comparison of some RTLIB 3418 // call result against zero. 3419 if (LHS.getValueType() == MVT::f128) { 3420 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 3421 3422 // If softenSetCCOperands returned a scalar, we need to compare the result 3423 // against zero to select between true and false values. 3424 if (!RHS.getNode()) { 3425 RHS = DAG.getConstant(0, LHS.getValueType()); 3426 CC = ISD::SETNE; 3427 } 3428 } 3429 3430 // Handle integers first. 3431 if (LHS.getValueType().isInteger()) { 3432 assert((LHS.getValueType() == RHS.getValueType()) && 3433 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)); 3434 3435 unsigned Opcode = AArch64ISD::CSEL; 3436 3437 // If both the TVal and the FVal are constants, see if we can swap them in 3438 // order to for a CSINV or CSINC out of them. 3439 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal); 3440 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal); 3441 3442 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) { 3443 std::swap(TVal, FVal); 3444 std::swap(CTVal, CFVal); 3445 CC = ISD::getSetCCInverse(CC, true); 3446 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) { 3447 std::swap(TVal, FVal); 3448 std::swap(CTVal, CFVal); 3449 CC = ISD::getSetCCInverse(CC, true); 3450 } else if (TVal.getOpcode() == ISD::XOR) { 3451 // If TVal is a NOT we want to swap TVal and FVal so that we can match 3452 // with a CSINV rather than a CSEL. 3453 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1)); 3454 3455 if (CVal && CVal->isAllOnesValue()) { 3456 std::swap(TVal, FVal); 3457 std::swap(CTVal, CFVal); 3458 CC = ISD::getSetCCInverse(CC, true); 3459 } 3460 } else if (TVal.getOpcode() == ISD::SUB) { 3461 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so 3462 // that we can match with a CSNEG rather than a CSEL. 3463 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0)); 3464 3465 if (CVal && CVal->isNullValue()) { 3466 std::swap(TVal, FVal); 3467 std::swap(CTVal, CFVal); 3468 CC = ISD::getSetCCInverse(CC, true); 3469 } 3470 } else if (CTVal && CFVal) { 3471 const int64_t TrueVal = CTVal->getSExtValue(); 3472 const int64_t FalseVal = CFVal->getSExtValue(); 3473 bool Swap = false; 3474 3475 // If both TVal and FVal are constants, see if FVal is the 3476 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC 3477 // instead of a CSEL in that case. 3478 if (TrueVal == ~FalseVal) { 3479 Opcode = AArch64ISD::CSINV; 3480 } else if (TrueVal == -FalseVal) { 3481 Opcode = AArch64ISD::CSNEG; 3482 } else if (TVal.getValueType() == MVT::i32) { 3483 // If our operands are only 32-bit wide, make sure we use 32-bit 3484 // arithmetic for the check whether we can use CSINC. This ensures that 3485 // the addition in the check will wrap around properly in case there is 3486 // an overflow (which would not be the case if we do the check with 3487 // 64-bit arithmetic). 3488 const uint32_t TrueVal32 = CTVal->getZExtValue(); 3489 const uint32_t FalseVal32 = CFVal->getZExtValue(); 3490 3491 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) { 3492 Opcode = AArch64ISD::CSINC; 3493 3494 if (TrueVal32 > FalseVal32) { 3495 Swap = true; 3496 } 3497 } 3498 // 64-bit check whether we can use CSINC. 3499 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) { 3500 Opcode = AArch64ISD::CSINC; 3501 3502 if (TrueVal > FalseVal) { 3503 Swap = true; 3504 } 3505 } 3506 3507 // Swap TVal and FVal if necessary. 3508 if (Swap) { 3509 std::swap(TVal, FVal); 3510 std::swap(CTVal, CFVal); 3511 CC = ISD::getSetCCInverse(CC, true); 3512 } 3513 3514 if (Opcode != AArch64ISD::CSEL) { 3515 // Drop FVal since we can get its value by simply inverting/negating 3516 // TVal. 3517 FVal = TVal; 3518 } 3519 } 3520 3521 SDValue CCVal; 3522 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); 3523 3524 EVT VT = Op.getValueType(); 3525 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp); 3526 } 3527 3528 // Now we know we're dealing with FP values. 3529 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 3530 assert(LHS.getValueType() == RHS.getValueType()); 3531 EVT VT = Op.getValueType(); 3532 3533 // Try to match this select into a max/min operation, which have dedicated 3534 // opcode in the instruction set. 3535 // FIXME: This is not correct in the presence of NaNs, so we only enable this 3536 // in no-NaNs mode. 3537 if (getTargetMachine().Options.NoNaNsFPMath) { 3538 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal; 3539 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) && 3540 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) { 3541 CC = ISD::getSetCCSwappedOperands(CC); 3542 std::swap(MinMaxLHS, MinMaxRHS); 3543 } 3544 3545 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) && 3546 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) { 3547 switch (CC) { 3548 default: 3549 break; 3550 case ISD::SETGT: 3551 case ISD::SETGE: 3552 case ISD::SETUGT: 3553 case ISD::SETUGE: 3554 case ISD::SETOGT: 3555 case ISD::SETOGE: 3556 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS); 3557 break; 3558 case ISD::SETLT: 3559 case ISD::SETLE: 3560 case ISD::SETULT: 3561 case ISD::SETULE: 3562 case ISD::SETOLT: 3563 case ISD::SETOLE: 3564 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS); 3565 break; 3566 } 3567 } 3568 } 3569 3570 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead 3571 // and do the comparison. 3572 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG); 3573 3574 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally 3575 // clean. Some of them require two CSELs to implement. 3576 AArch64CC::CondCode CC1, CC2; 3577 changeFPCCToAArch64CC(CC, CC1, CC2); 3578 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32); 3579 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); 3580 3581 // If we need a second CSEL, emit it, using the output of the first as the 3582 // RHS. We're effectively OR'ing the two CC's together. 3583 if (CC2 != AArch64CC::AL) { 3584 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32); 3585 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); 3586 } 3587 3588 // Otherwise, return the output of the first CSEL. 3589 return CS1; 3590 } 3591 3592 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op, 3593 SelectionDAG &DAG) const { 3594 // Jump table entries as PC relative offsets. No additional tweaking 3595 // is necessary here. Just get the address of the jump table. 3596 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 3597 EVT PtrVT = getPointerTy(); 3598 SDLoc DL(Op); 3599 3600 if (getTargetMachine().getCodeModel() == CodeModel::Large && 3601 !Subtarget->isTargetMachO()) { 3602 const unsigned char MO_NC = AArch64II::MO_NC; 3603 return DAG.getNode( 3604 AArch64ISD::WrapperLarge, DL, PtrVT, 3605 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3), 3606 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC), 3607 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC), 3608 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 3609 AArch64II::MO_G0 | MO_NC)); 3610 } 3611 3612 SDValue Hi = 3613 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE); 3614 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 3615 AArch64II::MO_PAGEOFF | AArch64II::MO_NC); 3616 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 3617 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 3618 } 3619 3620 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op, 3621 SelectionDAG &DAG) const { 3622 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 3623 EVT PtrVT = getPointerTy(); 3624 SDLoc DL(Op); 3625 3626 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 3627 // Use the GOT for the large code model on iOS. 3628 if (Subtarget->isTargetMachO()) { 3629 SDValue GotAddr = DAG.getTargetConstantPool( 3630 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), 3631 AArch64II::MO_GOT); 3632 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr); 3633 } 3634 3635 const unsigned char MO_NC = AArch64II::MO_NC; 3636 return DAG.getNode( 3637 AArch64ISD::WrapperLarge, DL, PtrVT, 3638 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3639 CP->getOffset(), AArch64II::MO_G3), 3640 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3641 CP->getOffset(), AArch64II::MO_G2 | MO_NC), 3642 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3643 CP->getOffset(), AArch64II::MO_G1 | MO_NC), 3644 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3645 CP->getOffset(), AArch64II::MO_G0 | MO_NC)); 3646 } else { 3647 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on 3648 // ELF, the only valid one on Darwin. 3649 SDValue Hi = 3650 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3651 CP->getOffset(), AArch64II::MO_PAGE); 3652 SDValue Lo = DAG.getTargetConstantPool( 3653 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), 3654 AArch64II::MO_PAGEOFF | AArch64II::MO_NC); 3655 3656 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 3657 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 3658 } 3659 } 3660 3661 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op, 3662 SelectionDAG &DAG) const { 3663 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 3664 EVT PtrVT = getPointerTy(); 3665 SDLoc DL(Op); 3666 if (getTargetMachine().getCodeModel() == CodeModel::Large && 3667 !Subtarget->isTargetMachO()) { 3668 const unsigned char MO_NC = AArch64II::MO_NC; 3669 return DAG.getNode( 3670 AArch64ISD::WrapperLarge, DL, PtrVT, 3671 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3), 3672 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC), 3673 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC), 3674 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC)); 3675 } else { 3676 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE); 3677 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF | 3678 AArch64II::MO_NC); 3679 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 3680 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 3681 } 3682 } 3683 3684 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op, 3685 SelectionDAG &DAG) const { 3686 AArch64FunctionInfo *FuncInfo = 3687 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>(); 3688 3689 SDLoc DL(Op); 3690 SDValue FR = 3691 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy()); 3692 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 3693 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 3694 MachinePointerInfo(SV), false, false, 0); 3695 } 3696 3697 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op, 3698 SelectionDAG &DAG) const { 3699 // The layout of the va_list struct is specified in the AArch64 Procedure Call 3700 // Standard, section B.3. 3701 MachineFunction &MF = DAG.getMachineFunction(); 3702 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 3703 SDLoc DL(Op); 3704 3705 SDValue Chain = Op.getOperand(0); 3706 SDValue VAList = Op.getOperand(1); 3707 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 3708 SmallVector<SDValue, 4> MemOps; 3709 3710 // void *__stack at offset 0 3711 SDValue Stack = 3712 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy()); 3713 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList, 3714 MachinePointerInfo(SV), false, false, 8)); 3715 3716 // void *__gr_top at offset 8 3717 int GPRSize = FuncInfo->getVarArgsGPRSize(); 3718 if (GPRSize > 0) { 3719 SDValue GRTop, GRTopAddr; 3720 3721 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3722 DAG.getConstant(8, getPointerTy())); 3723 3724 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy()); 3725 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop, 3726 DAG.getConstant(GPRSize, getPointerTy())); 3727 3728 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr, 3729 MachinePointerInfo(SV, 8), false, false, 8)); 3730 } 3731 3732 // void *__vr_top at offset 16 3733 int FPRSize = FuncInfo->getVarArgsFPRSize(); 3734 if (FPRSize > 0) { 3735 SDValue VRTop, VRTopAddr; 3736 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3737 DAG.getConstant(16, getPointerTy())); 3738 3739 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy()); 3740 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop, 3741 DAG.getConstant(FPRSize, getPointerTy())); 3742 3743 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr, 3744 MachinePointerInfo(SV, 16), false, false, 8)); 3745 } 3746 3747 // int __gr_offs at offset 24 3748 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3749 DAG.getConstant(24, getPointerTy())); 3750 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32), 3751 GROffsAddr, MachinePointerInfo(SV, 24), false, 3752 false, 4)); 3753 3754 // int __vr_offs at offset 28 3755 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3756 DAG.getConstant(28, getPointerTy())); 3757 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32), 3758 VROffsAddr, MachinePointerInfo(SV, 28), false, 3759 false, 4)); 3760 3761 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); 3762 } 3763 3764 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op, 3765 SelectionDAG &DAG) const { 3766 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG) 3767 : LowerAAPCS_VASTART(Op, DAG); 3768 } 3769 3770 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op, 3771 SelectionDAG &DAG) const { 3772 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single 3773 // pointer. 3774 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32; 3775 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 3776 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 3777 3778 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1), 3779 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32), 3780 8, false, false, MachinePointerInfo(DestSV), 3781 MachinePointerInfo(SrcSV)); 3782 } 3783 3784 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 3785 assert(Subtarget->isTargetDarwin() && 3786 "automatic va_arg instruction only works on Darwin"); 3787 3788 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 3789 EVT VT = Op.getValueType(); 3790 SDLoc DL(Op); 3791 SDValue Chain = Op.getOperand(0); 3792 SDValue Addr = Op.getOperand(1); 3793 unsigned Align = Op.getConstantOperandVal(3); 3794 3795 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr, 3796 MachinePointerInfo(V), false, false, false, 0); 3797 Chain = VAList.getValue(1); 3798 3799 if (Align > 8) { 3800 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2"); 3801 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3802 DAG.getConstant(Align - 1, getPointerTy())); 3803 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList, 3804 DAG.getConstant(-(int64_t)Align, getPointerTy())); 3805 } 3806 3807 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 3808 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy); 3809 3810 // Scalar integer and FP values smaller than 64 bits are implicitly extended 3811 // up to 64 bits. At the very least, we have to increase the striding of the 3812 // vaargs list to match this, and for FP values we need to introduce 3813 // FP_ROUND nodes as well. 3814 if (VT.isInteger() && !VT.isVector()) 3815 ArgSize = 8; 3816 bool NeedFPTrunc = false; 3817 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) { 3818 ArgSize = 8; 3819 NeedFPTrunc = true; 3820 } 3821 3822 // Increment the pointer, VAList, to the next vaarg 3823 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3824 DAG.getConstant(ArgSize, getPointerTy())); 3825 // Store the incremented VAList to the legalized pointer 3826 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V), 3827 false, false, 0); 3828 3829 // Load the actual argument out of the pointer VAList 3830 if (NeedFPTrunc) { 3831 // Load the value as an f64. 3832 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList, 3833 MachinePointerInfo(), false, false, false, 0); 3834 // Round the value down to an f32. 3835 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), 3836 DAG.getIntPtrConstant(1)); 3837 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) }; 3838 // Merge the rounded value with the chain output of the load. 3839 return DAG.getMergeValues(Ops, DL); 3840 } 3841 3842 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false, 3843 false, false, 0); 3844 } 3845 3846 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, 3847 SelectionDAG &DAG) const { 3848 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3849 MFI->setFrameAddressIsTaken(true); 3850 3851 EVT VT = Op.getValueType(); 3852 SDLoc DL(Op); 3853 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3854 SDValue FrameAddr = 3855 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT); 3856 while (Depth--) 3857 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr, 3858 MachinePointerInfo(), false, false, false, 0); 3859 return FrameAddr; 3860 } 3861 3862 // FIXME? Maybe this could be a TableGen attribute on some registers and 3863 // this table could be generated automatically from RegInfo. 3864 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, 3865 EVT VT) const { 3866 unsigned Reg = StringSwitch<unsigned>(RegName) 3867 .Case("sp", AArch64::SP) 3868 .Default(0); 3869 if (Reg) 3870 return Reg; 3871 report_fatal_error("Invalid register name global variable"); 3872 } 3873 3874 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op, 3875 SelectionDAG &DAG) const { 3876 MachineFunction &MF = DAG.getMachineFunction(); 3877 MachineFrameInfo *MFI = MF.getFrameInfo(); 3878 MFI->setReturnAddressIsTaken(true); 3879 3880 EVT VT = Op.getValueType(); 3881 SDLoc DL(Op); 3882 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3883 if (Depth) { 3884 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3885 SDValue Offset = DAG.getConstant(8, getPointerTy()); 3886 return DAG.getLoad(VT, DL, DAG.getEntryNode(), 3887 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), 3888 MachinePointerInfo(), false, false, false, 0); 3889 } 3890 3891 // Return LR, which contains the return address. Mark it an implicit live-in. 3892 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); 3893 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT); 3894 } 3895 3896 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3897 /// i64 values and take a 2 x i64 value to shift plus a shift amount. 3898 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op, 3899 SelectionDAG &DAG) const { 3900 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3901 EVT VT = Op.getValueType(); 3902 unsigned VTBits = VT.getSizeInBits(); 3903 SDLoc dl(Op); 3904 SDValue ShOpLo = Op.getOperand(0); 3905 SDValue ShOpHi = Op.getOperand(1); 3906 SDValue ShAmt = Op.getOperand(2); 3907 SDValue ARMcc; 3908 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3909 3910 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3911 3912 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, 3913 DAG.getConstant(VTBits, MVT::i64), ShAmt); 3914 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3915 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt, 3916 DAG.getConstant(VTBits, MVT::i64)); 3917 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3918 3919 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64), 3920 ISD::SETGE, dl, DAG); 3921 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32); 3922 3923 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3924 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3925 SDValue Lo = 3926 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp); 3927 3928 // AArch64 shifts larger than the register width are wrapped rather than 3929 // clamped, so we can't just emit "hi >> x". 3930 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3931 SDValue TrueValHi = Opc == ISD::SRA 3932 ? DAG.getNode(Opc, dl, VT, ShOpHi, 3933 DAG.getConstant(VTBits - 1, MVT::i64)) 3934 : DAG.getConstant(0, VT); 3935 SDValue Hi = 3936 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp); 3937 3938 SDValue Ops[2] = { Lo, Hi }; 3939 return DAG.getMergeValues(Ops, dl); 3940 } 3941 3942 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3943 /// i64 values and take a 2 x i64 value to shift plus a shift amount. 3944 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op, 3945 SelectionDAG &DAG) const { 3946 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3947 EVT VT = Op.getValueType(); 3948 unsigned VTBits = VT.getSizeInBits(); 3949 SDLoc dl(Op); 3950 SDValue ShOpLo = Op.getOperand(0); 3951 SDValue ShOpHi = Op.getOperand(1); 3952 SDValue ShAmt = Op.getOperand(2); 3953 SDValue ARMcc; 3954 3955 assert(Op.getOpcode() == ISD::SHL_PARTS); 3956 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, 3957 DAG.getConstant(VTBits, MVT::i64), ShAmt); 3958 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3959 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt, 3960 DAG.getConstant(VTBits, MVT::i64)); 3961 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3962 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3963 3964 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3965 3966 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64), 3967 ISD::SETGE, dl, DAG); 3968 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32); 3969 SDValue Hi = 3970 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp); 3971 3972 // AArch64 shifts of larger than register sizes are wrapped rather than 3973 // clamped, so we can't just emit "lo << a" if a is too big. 3974 SDValue TrueValLo = DAG.getConstant(0, VT); 3975 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3976 SDValue Lo = 3977 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp); 3978 3979 SDValue Ops[2] = { Lo, Hi }; 3980 return DAG.getMergeValues(Ops, dl); 3981 } 3982 3983 bool AArch64TargetLowering::isOffsetFoldingLegal( 3984 const GlobalAddressSDNode *GA) const { 3985 // The AArch64 target doesn't support folding offsets into global addresses. 3986 return false; 3987 } 3988 3989 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3990 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases. 3991 // FIXME: We should be able to handle f128 as well with a clever lowering. 3992 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32)) 3993 return true; 3994 3995 if (VT == MVT::f64) 3996 return AArch64_AM::getFP64Imm(Imm) != -1; 3997 else if (VT == MVT::f32) 3998 return AArch64_AM::getFP32Imm(Imm) != -1; 3999 return false; 4000 } 4001 4002 //===----------------------------------------------------------------------===// 4003 // AArch64 Optimization Hooks 4004 //===----------------------------------------------------------------------===// 4005 4006 //===----------------------------------------------------------------------===// 4007 // AArch64 Inline Assembly Support 4008 //===----------------------------------------------------------------------===// 4009 4010 // Table of Constraints 4011 // TODO: This is the current set of constraints supported by ARM for the 4012 // compiler, not all of them may make sense, e.g. S may be difficult to support. 4013 // 4014 // r - A general register 4015 // w - An FP/SIMD register of some size in the range v0-v31 4016 // x - An FP/SIMD register of some size in the range v0-v15 4017 // I - Constant that can be used with an ADD instruction 4018 // J - Constant that can be used with a SUB instruction 4019 // K - Constant that can be used with a 32-bit logical instruction 4020 // L - Constant that can be used with a 64-bit logical instruction 4021 // M - Constant that can be used as a 32-bit MOV immediate 4022 // N - Constant that can be used as a 64-bit MOV immediate 4023 // Q - A memory reference with base register and no offset 4024 // S - A symbolic address 4025 // Y - Floating point constant zero 4026 // Z - Integer constant zero 4027 // 4028 // Note that general register operands will be output using their 64-bit x 4029 // register name, whatever the size of the variable, unless the asm operand 4030 // is prefixed by the %w modifier. Floating-point and SIMD register operands 4031 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or 4032 // %q modifier. 4033 4034 /// getConstraintType - Given a constraint letter, return the type of 4035 /// constraint it is for this target. 4036 AArch64TargetLowering::ConstraintType 4037 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const { 4038 if (Constraint.size() == 1) { 4039 switch (Constraint[0]) { 4040 default: 4041 break; 4042 case 'z': 4043 return C_Other; 4044 case 'x': 4045 case 'w': 4046 return C_RegisterClass; 4047 // An address with a single base register. Due to the way we 4048 // currently handle addresses it is the same as 'r'. 4049 case 'Q': 4050 return C_Memory; 4051 } 4052 } 4053 return TargetLowering::getConstraintType(Constraint); 4054 } 4055 4056 /// Examine constraint type and operand type and determine a weight value. 4057 /// This object must already have been set up with the operand type 4058 /// and the current alternative constraint selected. 4059 TargetLowering::ConstraintWeight 4060 AArch64TargetLowering::getSingleConstraintMatchWeight( 4061 AsmOperandInfo &info, const char *constraint) const { 4062 ConstraintWeight weight = CW_Invalid; 4063 Value *CallOperandVal = info.CallOperandVal; 4064 // If we don't have a value, we can't do a match, 4065 // but allow it at the lowest weight. 4066 if (!CallOperandVal) 4067 return CW_Default; 4068 Type *type = CallOperandVal->getType(); 4069 // Look at the constraint type. 4070 switch (*constraint) { 4071 default: 4072 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 4073 break; 4074 case 'x': 4075 case 'w': 4076 if (type->isFloatingPointTy() || type->isVectorTy()) 4077 weight = CW_Register; 4078 break; 4079 case 'z': 4080 weight = CW_Constant; 4081 break; 4082 } 4083 return weight; 4084 } 4085 4086 std::pair<unsigned, const TargetRegisterClass *> 4087 AArch64TargetLowering::getRegForInlineAsmConstraint( 4088 const std::string &Constraint, MVT VT) const { 4089 if (Constraint.size() == 1) { 4090 switch (Constraint[0]) { 4091 case 'r': 4092 if (VT.getSizeInBits() == 64) 4093 return std::make_pair(0U, &AArch64::GPR64commonRegClass); 4094 return std::make_pair(0U, &AArch64::GPR32commonRegClass); 4095 case 'w': 4096 if (VT == MVT::f32) 4097 return std::make_pair(0U, &AArch64::FPR32RegClass); 4098 if (VT.getSizeInBits() == 64) 4099 return std::make_pair(0U, &AArch64::FPR64RegClass); 4100 if (VT.getSizeInBits() == 128) 4101 return std::make_pair(0U, &AArch64::FPR128RegClass); 4102 break; 4103 // The instructions that this constraint is designed for can 4104 // only take 128-bit registers so just use that regclass. 4105 case 'x': 4106 if (VT.getSizeInBits() == 128) 4107 return std::make_pair(0U, &AArch64::FPR128_loRegClass); 4108 break; 4109 } 4110 } 4111 if (StringRef("{cc}").equals_lower(Constraint)) 4112 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass); 4113 4114 // Use the default implementation in TargetLowering to convert the register 4115 // constraint into a member of a register class. 4116 std::pair<unsigned, const TargetRegisterClass *> Res; 4117 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 4118 4119 // Not found as a standard register? 4120 if (!Res.second) { 4121 unsigned Size = Constraint.size(); 4122 if ((Size == 4 || Size == 5) && Constraint[0] == '{' && 4123 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') { 4124 const std::string Reg = 4125 std::string(&Constraint[2], &Constraint[Size - 1]); 4126 int RegNo = atoi(Reg.c_str()); 4127 if (RegNo >= 0 && RegNo <= 31) { 4128 // v0 - v31 are aliases of q0 - q31. 4129 // By default we'll emit v0-v31 for this unless there's a modifier where 4130 // we'll emit the correct register as well. 4131 Res.first = AArch64::FPR128RegClass.getRegister(RegNo); 4132 Res.second = &AArch64::FPR128RegClass; 4133 } 4134 } 4135 } 4136 4137 return Res; 4138 } 4139 4140 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4141 /// vector. If it is invalid, don't add anything to Ops. 4142 void AArch64TargetLowering::LowerAsmOperandForConstraint( 4143 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, 4144 SelectionDAG &DAG) const { 4145 SDValue Result; 4146 4147 // Currently only support length 1 constraints. 4148 if (Constraint.length() != 1) 4149 return; 4150 4151 char ConstraintLetter = Constraint[0]; 4152 switch (ConstraintLetter) { 4153 default: 4154 break; 4155 4156 // This set of constraints deal with valid constants for various instructions. 4157 // Validate and return a target constant for them if we can. 4158 case 'z': { 4159 // 'z' maps to xzr or wzr so it needs an input of 0. 4160 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 4161 if (!C || C->getZExtValue() != 0) 4162 return; 4163 4164 if (Op.getValueType() == MVT::i64) 4165 Result = DAG.getRegister(AArch64::XZR, MVT::i64); 4166 else 4167 Result = DAG.getRegister(AArch64::WZR, MVT::i32); 4168 break; 4169 } 4170 4171 case 'I': 4172 case 'J': 4173 case 'K': 4174 case 'L': 4175 case 'M': 4176 case 'N': 4177 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 4178 if (!C) 4179 return; 4180 4181 // Grab the value and do some validation. 4182 uint64_t CVal = C->getZExtValue(); 4183 switch (ConstraintLetter) { 4184 // The I constraint applies only to simple ADD or SUB immediate operands: 4185 // i.e. 0 to 4095 with optional shift by 12 4186 // The J constraint applies only to ADD or SUB immediates that would be 4187 // valid when negated, i.e. if [an add pattern] were to be output as a SUB 4188 // instruction [or vice versa], in other words -1 to -4095 with optional 4189 // left shift by 12. 4190 case 'I': 4191 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal)) 4192 break; 4193 return; 4194 case 'J': { 4195 uint64_t NVal = -C->getSExtValue(); 4196 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) { 4197 CVal = C->getSExtValue(); 4198 break; 4199 } 4200 return; 4201 } 4202 // The K and L constraints apply *only* to logical immediates, including 4203 // what used to be the MOVI alias for ORR (though the MOVI alias has now 4204 // been removed and MOV should be used). So these constraints have to 4205 // distinguish between bit patterns that are valid 32-bit or 64-bit 4206 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but 4207 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice 4208 // versa. 4209 case 'K': 4210 if (AArch64_AM::isLogicalImmediate(CVal, 32)) 4211 break; 4212 return; 4213 case 'L': 4214 if (AArch64_AM::isLogicalImmediate(CVal, 64)) 4215 break; 4216 return; 4217 // The M and N constraints are a superset of K and L respectively, for use 4218 // with the MOV (immediate) alias. As well as the logical immediates they 4219 // also match 32 or 64-bit immediates that can be loaded either using a 4220 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca 4221 // (M) or 64-bit 0x1234000000000000 (N) etc. 4222 // As a note some of this code is liberally stolen from the asm parser. 4223 case 'M': { 4224 if (!isUInt<32>(CVal)) 4225 return; 4226 if (AArch64_AM::isLogicalImmediate(CVal, 32)) 4227 break; 4228 if ((CVal & 0xFFFF) == CVal) 4229 break; 4230 if ((CVal & 0xFFFF0000ULL) == CVal) 4231 break; 4232 uint64_t NCVal = ~(uint32_t)CVal; 4233 if ((NCVal & 0xFFFFULL) == NCVal) 4234 break; 4235 if ((NCVal & 0xFFFF0000ULL) == NCVal) 4236 break; 4237 return; 4238 } 4239 case 'N': { 4240 if (AArch64_AM::isLogicalImmediate(CVal, 64)) 4241 break; 4242 if ((CVal & 0xFFFFULL) == CVal) 4243 break; 4244 if ((CVal & 0xFFFF0000ULL) == CVal) 4245 break; 4246 if ((CVal & 0xFFFF00000000ULL) == CVal) 4247 break; 4248 if ((CVal & 0xFFFF000000000000ULL) == CVal) 4249 break; 4250 uint64_t NCVal = ~CVal; 4251 if ((NCVal & 0xFFFFULL) == NCVal) 4252 break; 4253 if ((NCVal & 0xFFFF0000ULL) == NCVal) 4254 break; 4255 if ((NCVal & 0xFFFF00000000ULL) == NCVal) 4256 break; 4257 if ((NCVal & 0xFFFF000000000000ULL) == NCVal) 4258 break; 4259 return; 4260 } 4261 default: 4262 return; 4263 } 4264 4265 // All assembler immediates are 64-bit integers. 4266 Result = DAG.getTargetConstant(CVal, MVT::i64); 4267 break; 4268 } 4269 4270 if (Result.getNode()) { 4271 Ops.push_back(Result); 4272 return; 4273 } 4274 4275 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4276 } 4277 4278 //===----------------------------------------------------------------------===// 4279 // AArch64 Advanced SIMD Support 4280 //===----------------------------------------------------------------------===// 4281 4282 /// WidenVector - Given a value in the V64 register class, produce the 4283 /// equivalent value in the V128 register class. 4284 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) { 4285 EVT VT = V64Reg.getValueType(); 4286 unsigned NarrowSize = VT.getVectorNumElements(); 4287 MVT EltTy = VT.getVectorElementType().getSimpleVT(); 4288 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize); 4289 SDLoc DL(V64Reg); 4290 4291 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), 4292 V64Reg, DAG.getConstant(0, MVT::i32)); 4293 } 4294 4295 /// getExtFactor - Determine the adjustment factor for the position when 4296 /// generating an "extract from vector registers" instruction. 4297 static unsigned getExtFactor(SDValue &V) { 4298 EVT EltType = V.getValueType().getVectorElementType(); 4299 return EltType.getSizeInBits() / 8; 4300 } 4301 4302 /// NarrowVector - Given a value in the V128 register class, produce the 4303 /// equivalent value in the V64 register class. 4304 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) { 4305 EVT VT = V128Reg.getValueType(); 4306 unsigned WideSize = VT.getVectorNumElements(); 4307 MVT EltTy = VT.getVectorElementType().getSimpleVT(); 4308 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2); 4309 SDLoc DL(V128Reg); 4310 4311 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg); 4312 } 4313 4314 // Gather data to see if the operation can be modelled as a 4315 // shuffle in combination with VEXTs. 4316 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, 4317 SelectionDAG &DAG) const { 4318 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!"); 4319 SDLoc dl(Op); 4320 EVT VT = Op.getValueType(); 4321 unsigned NumElts = VT.getVectorNumElements(); 4322 4323 struct ShuffleSourceInfo { 4324 SDValue Vec; 4325 unsigned MinElt; 4326 unsigned MaxElt; 4327 4328 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to 4329 // be compatible with the shuffle we intend to construct. As a result 4330 // ShuffleVec will be some sliding window into the original Vec. 4331 SDValue ShuffleVec; 4332 4333 // Code should guarantee that element i in Vec starts at element "WindowBase 4334 // + i * WindowScale in ShuffleVec". 4335 int WindowBase; 4336 int WindowScale; 4337 4338 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; } 4339 ShuffleSourceInfo(SDValue Vec) 4340 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0), 4341 WindowScale(1) {} 4342 }; 4343 4344 // First gather all vectors used as an immediate source for this BUILD_VECTOR 4345 // node. 4346 SmallVector<ShuffleSourceInfo, 2> Sources; 4347 for (unsigned i = 0; i < NumElts; ++i) { 4348 SDValue V = Op.getOperand(i); 4349 if (V.getOpcode() == ISD::UNDEF) 4350 continue; 4351 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4352 // A shuffle can only come from building a vector from various 4353 // elements of other vectors. 4354 return SDValue(); 4355 } 4356 4357 // Add this element source to the list if it's not already there. 4358 SDValue SourceVec = V.getOperand(0); 4359 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec); 4360 if (Source == Sources.end()) 4361 Sources.push_back(ShuffleSourceInfo(SourceVec)); 4362 4363 // Update the minimum and maximum lane number seen. 4364 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4365 Source->MinElt = std::min(Source->MinElt, EltNo); 4366 Source->MaxElt = std::max(Source->MaxElt, EltNo); 4367 } 4368 4369 // Currently only do something sane when at most two source vectors 4370 // are involved. 4371 if (Sources.size() > 2) 4372 return SDValue(); 4373 4374 // Find out the smallest element size among result and two sources, and use 4375 // it as element size to build the shuffle_vector. 4376 EVT SmallestEltTy = VT.getVectorElementType(); 4377 for (auto &Source : Sources) { 4378 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType(); 4379 if (SrcEltTy.bitsLT(SmallestEltTy)) { 4380 SmallestEltTy = SrcEltTy; 4381 } 4382 } 4383 unsigned ResMultiplier = 4384 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits(); 4385 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits(); 4386 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts); 4387 4388 // If the source vector is too wide or too narrow, we may nevertheless be able 4389 // to construct a compatible shuffle either by concatenating it with UNDEF or 4390 // extracting a suitable range of elements. 4391 for (auto &Src : Sources) { 4392 EVT SrcVT = Src.ShuffleVec.getValueType(); 4393 4394 if (SrcVT.getSizeInBits() == VT.getSizeInBits()) 4395 continue; 4396 4397 // This stage of the search produces a source with the same element type as 4398 // the original, but with a total width matching the BUILD_VECTOR output. 4399 EVT EltVT = SrcVT.getVectorElementType(); 4400 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, 4401 VT.getSizeInBits() / EltVT.getSizeInBits()); 4402 4403 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) { 4404 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits()); 4405 // We can pad out the smaller vector for free, so if it's part of a 4406 // shuffle... 4407 Src.ShuffleVec = 4408 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, 4409 DAG.getUNDEF(Src.ShuffleVec.getValueType())); 4410 continue; 4411 } 4412 4413 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits()); 4414 4415 if (Src.MaxElt - Src.MinElt >= NumElts) { 4416 // Span too large for a VEXT to cope 4417 return SDValue(); 4418 } 4419 4420 if (Src.MinElt >= NumElts) { 4421 // The extraction can just take the second half 4422 Src.ShuffleVec = 4423 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 4424 DAG.getIntPtrConstant(NumElts)); 4425 Src.WindowBase = -NumElts; 4426 } else if (Src.MaxElt < NumElts) { 4427 // The extraction can just take the first half 4428 Src.ShuffleVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, 4429 Src.ShuffleVec, DAG.getIntPtrConstant(0)); 4430 } else { 4431 // An actual VEXT is needed 4432 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, 4433 Src.ShuffleVec, DAG.getIntPtrConstant(0)); 4434 SDValue VEXTSrc2 = 4435 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 4436 DAG.getIntPtrConstant(NumElts)); 4437 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1); 4438 4439 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, 4440 VEXTSrc2, DAG.getConstant(Imm, MVT::i32)); 4441 Src.WindowBase = -Src.MinElt; 4442 } 4443 } 4444 4445 // Another possible incompatibility occurs from the vector element types. We 4446 // can fix this by bitcasting the source vectors to the same type we intend 4447 // for the shuffle. 4448 for (auto &Src : Sources) { 4449 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType(); 4450 if (SrcEltTy == SmallestEltTy) 4451 continue; 4452 assert(ShuffleVT.getVectorElementType() == SmallestEltTy); 4453 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec); 4454 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits(); 4455 Src.WindowBase *= Src.WindowScale; 4456 } 4457 4458 // Final sanity check before we try to actually produce a shuffle. 4459 DEBUG( 4460 for (auto Src : Sources) 4461 assert(Src.ShuffleVec.getValueType() == ShuffleVT); 4462 ); 4463 4464 // The stars all align, our next step is to produce the mask for the shuffle. 4465 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1); 4466 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits(); 4467 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { 4468 SDValue Entry = Op.getOperand(i); 4469 if (Entry.getOpcode() == ISD::UNDEF) 4470 continue; 4471 4472 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0)); 4473 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue(); 4474 4475 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit 4476 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this 4477 // segment. 4478 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType(); 4479 int BitsDefined = std::min(OrigEltTy.getSizeInBits(), 4480 VT.getVectorElementType().getSizeInBits()); 4481 int LanesDefined = BitsDefined / BitsPerShuffleLane; 4482 4483 // This source is expected to fill ResMultiplier lanes of the final shuffle, 4484 // starting at the appropriate offset. 4485 int *LaneMask = &Mask[i * ResMultiplier]; 4486 4487 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase; 4488 ExtractBase += NumElts * (Src - Sources.begin()); 4489 for (int j = 0; j < LanesDefined; ++j) 4490 LaneMask[j] = ExtractBase + j; 4491 } 4492 4493 // Final check before we try to produce nonsense... 4494 if (!isShuffleMaskLegal(Mask, ShuffleVT)) 4495 return SDValue(); 4496 4497 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) }; 4498 for (unsigned i = 0; i < Sources.size(); ++i) 4499 ShuffleOps[i] = Sources[i].ShuffleVec; 4500 4501 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0], 4502 ShuffleOps[1], &Mask[0]); 4503 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 4504 } 4505 4506 // check if an EXT instruction can handle the shuffle mask when the 4507 // vector sources of the shuffle are the same. 4508 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) { 4509 unsigned NumElts = VT.getVectorNumElements(); 4510 4511 // Assume that the first shuffle index is not UNDEF. Fail if it is. 4512 if (M[0] < 0) 4513 return false; 4514 4515 Imm = M[0]; 4516 4517 // If this is a VEXT shuffle, the immediate value is the index of the first 4518 // element. The other shuffle indices must be the successive elements after 4519 // the first one. 4520 unsigned ExpectedElt = Imm; 4521 for (unsigned i = 1; i < NumElts; ++i) { 4522 // Increment the expected index. If it wraps around, just follow it 4523 // back to index zero and keep going. 4524 ++ExpectedElt; 4525 if (ExpectedElt == NumElts) 4526 ExpectedElt = 0; 4527 4528 if (M[i] < 0) 4529 continue; // ignore UNDEF indices 4530 if (ExpectedElt != static_cast<unsigned>(M[i])) 4531 return false; 4532 } 4533 4534 return true; 4535 } 4536 4537 // check if an EXT instruction can handle the shuffle mask when the 4538 // vector sources of the shuffle are different. 4539 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT, 4540 unsigned &Imm) { 4541 // Look for the first non-undef element. 4542 const int *FirstRealElt = std::find_if(M.begin(), M.end(), 4543 [](int Elt) {return Elt >= 0;}); 4544 4545 // Benefit form APInt to handle overflow when calculating expected element. 4546 unsigned NumElts = VT.getVectorNumElements(); 4547 unsigned MaskBits = APInt(32, NumElts * 2).logBase2(); 4548 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1); 4549 // The following shuffle indices must be the successive elements after the 4550 // first real element. 4551 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(), 4552 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;}); 4553 if (FirstWrongElt != M.end()) 4554 return false; 4555 4556 // The index of an EXT is the first element if it is not UNDEF. 4557 // Watch out for the beginning UNDEFs. The EXT index should be the expected 4558 // value of the first element. E.g. 4559 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>. 4560 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>. 4561 // ExpectedElt is the last mask index plus 1. 4562 Imm = ExpectedElt.getZExtValue(); 4563 4564 // There are two difference cases requiring to reverse input vectors. 4565 // For example, for vector <4 x i32> we have the following cases, 4566 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>) 4567 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>) 4568 // For both cases, we finally use mask <5, 6, 7, 0>, which requires 4569 // to reverse two input vectors. 4570 if (Imm < NumElts) 4571 ReverseEXT = true; 4572 else 4573 Imm -= NumElts; 4574 4575 return true; 4576 } 4577 4578 /// isREVMask - Check if a vector shuffle corresponds to a REV 4579 /// instruction with the specified blocksize. (The order of the elements 4580 /// within each block of the vector is reversed.) 4581 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) { 4582 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) && 4583 "Only possible block sizes for REV are: 16, 32, 64"); 4584 4585 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 4586 if (EltSz == 64) 4587 return false; 4588 4589 unsigned NumElts = VT.getVectorNumElements(); 4590 unsigned BlockElts = M[0] + 1; 4591 // If the first shuffle index is UNDEF, be optimistic. 4592 if (M[0] < 0) 4593 BlockElts = BlockSize / EltSz; 4594 4595 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 4596 return false; 4597 4598 for (unsigned i = 0; i < NumElts; ++i) { 4599 if (M[i] < 0) 4600 continue; // ignore UNDEF indices 4601 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts)) 4602 return false; 4603 } 4604 4605 return true; 4606 } 4607 4608 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4609 unsigned NumElts = VT.getVectorNumElements(); 4610 WhichResult = (M[0] == 0 ? 0 : 1); 4611 unsigned Idx = WhichResult * NumElts / 2; 4612 for (unsigned i = 0; i != NumElts; i += 2) { 4613 if ((M[i] >= 0 && (unsigned)M[i] != Idx) || 4614 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts)) 4615 return false; 4616 Idx += 1; 4617 } 4618 4619 return true; 4620 } 4621 4622 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4623 unsigned NumElts = VT.getVectorNumElements(); 4624 WhichResult = (M[0] == 0 ? 0 : 1); 4625 for (unsigned i = 0; i != NumElts; ++i) { 4626 if (M[i] < 0) 4627 continue; // ignore UNDEF indices 4628 if ((unsigned)M[i] != 2 * i + WhichResult) 4629 return false; 4630 } 4631 4632 return true; 4633 } 4634 4635 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4636 unsigned NumElts = VT.getVectorNumElements(); 4637 WhichResult = (M[0] == 0 ? 0 : 1); 4638 for (unsigned i = 0; i < NumElts; i += 2) { 4639 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) || 4640 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult)) 4641 return false; 4642 } 4643 return true; 4644 } 4645 4646 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of 4647 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4648 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 4649 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4650 unsigned NumElts = VT.getVectorNumElements(); 4651 WhichResult = (M[0] == 0 ? 0 : 1); 4652 unsigned Idx = WhichResult * NumElts / 2; 4653 for (unsigned i = 0; i != NumElts; i += 2) { 4654 if ((M[i] >= 0 && (unsigned)M[i] != Idx) || 4655 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx)) 4656 return false; 4657 Idx += 1; 4658 } 4659 4660 return true; 4661 } 4662 4663 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of 4664 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4665 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 4666 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4667 unsigned Half = VT.getVectorNumElements() / 2; 4668 WhichResult = (M[0] == 0 ? 0 : 1); 4669 for (unsigned j = 0; j != 2; ++j) { 4670 unsigned Idx = WhichResult; 4671 for (unsigned i = 0; i != Half; ++i) { 4672 int MIdx = M[i + j * Half]; 4673 if (MIdx >= 0 && (unsigned)MIdx != Idx) 4674 return false; 4675 Idx += 2; 4676 } 4677 } 4678 4679 return true; 4680 } 4681 4682 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of 4683 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4684 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 4685 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4686 unsigned NumElts = VT.getVectorNumElements(); 4687 WhichResult = (M[0] == 0 ? 0 : 1); 4688 for (unsigned i = 0; i < NumElts; i += 2) { 4689 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) || 4690 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult)) 4691 return false; 4692 } 4693 return true; 4694 } 4695 4696 static bool isINSMask(ArrayRef<int> M, int NumInputElements, 4697 bool &DstIsLeft, int &Anomaly) { 4698 if (M.size() != static_cast<size_t>(NumInputElements)) 4699 return false; 4700 4701 int NumLHSMatch = 0, NumRHSMatch = 0; 4702 int LastLHSMismatch = -1, LastRHSMismatch = -1; 4703 4704 for (int i = 0; i < NumInputElements; ++i) { 4705 if (M[i] == -1) { 4706 ++NumLHSMatch; 4707 ++NumRHSMatch; 4708 continue; 4709 } 4710 4711 if (M[i] == i) 4712 ++NumLHSMatch; 4713 else 4714 LastLHSMismatch = i; 4715 4716 if (M[i] == i + NumInputElements) 4717 ++NumRHSMatch; 4718 else 4719 LastRHSMismatch = i; 4720 } 4721 4722 if (NumLHSMatch == NumInputElements - 1) { 4723 DstIsLeft = true; 4724 Anomaly = LastLHSMismatch; 4725 return true; 4726 } else if (NumRHSMatch == NumInputElements - 1) { 4727 DstIsLeft = false; 4728 Anomaly = LastRHSMismatch; 4729 return true; 4730 } 4731 4732 return false; 4733 } 4734 4735 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) { 4736 if (VT.getSizeInBits() != 128) 4737 return false; 4738 4739 unsigned NumElts = VT.getVectorNumElements(); 4740 4741 for (int I = 0, E = NumElts / 2; I != E; I++) { 4742 if (Mask[I] != I) 4743 return false; 4744 } 4745 4746 int Offset = NumElts / 2; 4747 for (int I = NumElts / 2, E = NumElts; I != E; I++) { 4748 if (Mask[I] != I + SplitLHS * Offset) 4749 return false; 4750 } 4751 4752 return true; 4753 } 4754 4755 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) { 4756 SDLoc DL(Op); 4757 EVT VT = Op.getValueType(); 4758 SDValue V0 = Op.getOperand(0); 4759 SDValue V1 = Op.getOperand(1); 4760 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask(); 4761 4762 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() || 4763 VT.getVectorElementType() != V1.getValueType().getVectorElementType()) 4764 return SDValue(); 4765 4766 bool SplitV0 = V0.getValueType().getSizeInBits() == 128; 4767 4768 if (!isConcatMask(Mask, VT, SplitV0)) 4769 return SDValue(); 4770 4771 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4772 VT.getVectorNumElements() / 2); 4773 if (SplitV0) { 4774 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, 4775 DAG.getConstant(0, MVT::i64)); 4776 } 4777 if (V1.getValueType().getSizeInBits() == 128) { 4778 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, 4779 DAG.getConstant(0, MVT::i64)); 4780 } 4781 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); 4782 } 4783 4784 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4785 /// the specified operations to build the shuffle. 4786 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4787 SDValue RHS, SelectionDAG &DAG, 4788 SDLoc dl) { 4789 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4790 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1); 4791 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1); 4792 4793 enum { 4794 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4795 OP_VREV, 4796 OP_VDUP0, 4797 OP_VDUP1, 4798 OP_VDUP2, 4799 OP_VDUP3, 4800 OP_VEXT1, 4801 OP_VEXT2, 4802 OP_VEXT3, 4803 OP_VUZPL, // VUZP, left result 4804 OP_VUZPR, // VUZP, right result 4805 OP_VZIPL, // VZIP, left result 4806 OP_VZIPR, // VZIP, right result 4807 OP_VTRNL, // VTRN, left result 4808 OP_VTRNR // VTRN, right result 4809 }; 4810 4811 if (OpNum == OP_COPY) { 4812 if (LHSID == (1 * 9 + 2) * 9 + 3) 4813 return LHS; 4814 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!"); 4815 return RHS; 4816 } 4817 4818 SDValue OpLHS, OpRHS; 4819 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4820 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4821 EVT VT = OpLHS.getValueType(); 4822 4823 switch (OpNum) { 4824 default: 4825 llvm_unreachable("Unknown shuffle opcode!"); 4826 case OP_VREV: 4827 // VREV divides the vector in half and swaps within the half. 4828 if (VT.getVectorElementType() == MVT::i32 || 4829 VT.getVectorElementType() == MVT::f32) 4830 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS); 4831 // vrev <4 x i16> -> REV32 4832 if (VT.getVectorElementType() == MVT::i16 || 4833 VT.getVectorElementType() == MVT::f16) 4834 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS); 4835 // vrev <4 x i8> -> REV16 4836 assert(VT.getVectorElementType() == MVT::i8); 4837 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS); 4838 case OP_VDUP0: 4839 case OP_VDUP1: 4840 case OP_VDUP2: 4841 case OP_VDUP3: { 4842 EVT EltTy = VT.getVectorElementType(); 4843 unsigned Opcode; 4844 if (EltTy == MVT::i8) 4845 Opcode = AArch64ISD::DUPLANE8; 4846 else if (EltTy == MVT::i16) 4847 Opcode = AArch64ISD::DUPLANE16; 4848 else if (EltTy == MVT::i32 || EltTy == MVT::f32) 4849 Opcode = AArch64ISD::DUPLANE32; 4850 else if (EltTy == MVT::i64 || EltTy == MVT::f64) 4851 Opcode = AArch64ISD::DUPLANE64; 4852 else 4853 llvm_unreachable("Invalid vector element type?"); 4854 4855 if (VT.getSizeInBits() == 64) 4856 OpLHS = WidenVector(OpLHS, DAG); 4857 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64); 4858 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane); 4859 } 4860 case OP_VEXT1: 4861 case OP_VEXT2: 4862 case OP_VEXT3: { 4863 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS); 4864 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS, 4865 DAG.getConstant(Imm, MVT::i32)); 4866 } 4867 case OP_VUZPL: 4868 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS, 4869 OpRHS); 4870 case OP_VUZPR: 4871 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS, 4872 OpRHS); 4873 case OP_VZIPL: 4874 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS, 4875 OpRHS); 4876 case OP_VZIPR: 4877 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS, 4878 OpRHS); 4879 case OP_VTRNL: 4880 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS, 4881 OpRHS); 4882 case OP_VTRNR: 4883 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS, 4884 OpRHS); 4885 } 4886 } 4887 4888 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, 4889 SelectionDAG &DAG) { 4890 // Check to see if we can use the TBL instruction. 4891 SDValue V1 = Op.getOperand(0); 4892 SDValue V2 = Op.getOperand(1); 4893 SDLoc DL(Op); 4894 4895 EVT EltVT = Op.getValueType().getVectorElementType(); 4896 unsigned BytesPerElt = EltVT.getSizeInBits() / 8; 4897 4898 SmallVector<SDValue, 8> TBLMask; 4899 for (int Val : ShuffleMask) { 4900 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) { 4901 unsigned Offset = Byte + Val * BytesPerElt; 4902 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32)); 4903 } 4904 } 4905 4906 MVT IndexVT = MVT::v8i8; 4907 unsigned IndexLen = 8; 4908 if (Op.getValueType().getSizeInBits() == 128) { 4909 IndexVT = MVT::v16i8; 4910 IndexLen = 16; 4911 } 4912 4913 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1); 4914 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2); 4915 4916 SDValue Shuffle; 4917 if (V2.getNode()->getOpcode() == ISD::UNDEF) { 4918 if (IndexLen == 8) 4919 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); 4920 Shuffle = DAG.getNode( 4921 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, 4922 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst, 4923 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, 4924 makeArrayRef(TBLMask.data(), IndexLen))); 4925 } else { 4926 if (IndexLen == 8) { 4927 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); 4928 Shuffle = DAG.getNode( 4929 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, 4930 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst, 4931 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, 4932 makeArrayRef(TBLMask.data(), IndexLen))); 4933 } else { 4934 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we 4935 // cannot currently represent the register constraints on the input 4936 // table registers. 4937 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst, 4938 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, 4939 // &TBLMask[0], IndexLen)); 4940 Shuffle = DAG.getNode( 4941 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, 4942 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst, 4943 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, 4944 makeArrayRef(TBLMask.data(), IndexLen))); 4945 } 4946 } 4947 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle); 4948 } 4949 4950 static unsigned getDUPLANEOp(EVT EltType) { 4951 if (EltType == MVT::i8) 4952 return AArch64ISD::DUPLANE8; 4953 if (EltType == MVT::i16 || EltType == MVT::f16) 4954 return AArch64ISD::DUPLANE16; 4955 if (EltType == MVT::i32 || EltType == MVT::f32) 4956 return AArch64ISD::DUPLANE32; 4957 if (EltType == MVT::i64 || EltType == MVT::f64) 4958 return AArch64ISD::DUPLANE64; 4959 4960 llvm_unreachable("Invalid vector element type?"); 4961 } 4962 4963 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4964 SelectionDAG &DAG) const { 4965 SDLoc dl(Op); 4966 EVT VT = Op.getValueType(); 4967 4968 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4969 4970 // Convert shuffles that are directly supported on NEON to target-specific 4971 // DAG nodes, instead of keeping them as shuffles and matching them again 4972 // during code selection. This is more efficient and avoids the possibility 4973 // of inconsistencies between legalization and selection. 4974 ArrayRef<int> ShuffleMask = SVN->getMask(); 4975 4976 SDValue V1 = Op.getOperand(0); 4977 SDValue V2 = Op.getOperand(1); 4978 4979 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], 4980 V1.getValueType().getSimpleVT())) { 4981 int Lane = SVN->getSplatIndex(); 4982 // If this is undef splat, generate it via "just" vdup, if possible. 4983 if (Lane == -1) 4984 Lane = 0; 4985 4986 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) 4987 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(), 4988 V1.getOperand(0)); 4989 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non- 4990 // constant. If so, we can just reference the lane's definition directly. 4991 if (V1.getOpcode() == ISD::BUILD_VECTOR && 4992 !isa<ConstantSDNode>(V1.getOperand(Lane))) 4993 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane)); 4994 4995 // Otherwise, duplicate from the lane of the input vector. 4996 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType()); 4997 4998 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated 4999 // to make a vector of the same size as this SHUFFLE. We can ignore the 5000 // extract entirely, and canonicalise the concat using WidenVector. 5001 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { 5002 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue(); 5003 V1 = V1.getOperand(0); 5004 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) { 5005 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2; 5006 Lane -= Idx * VT.getVectorNumElements() / 2; 5007 V1 = WidenVector(V1.getOperand(Idx), DAG); 5008 } else if (VT.getSizeInBits() == 64) 5009 V1 = WidenVector(V1, DAG); 5010 5011 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64)); 5012 } 5013 5014 if (isREVMask(ShuffleMask, VT, 64)) 5015 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2); 5016 if (isREVMask(ShuffleMask, VT, 32)) 5017 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2); 5018 if (isREVMask(ShuffleMask, VT, 16)) 5019 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2); 5020 5021 bool ReverseEXT = false; 5022 unsigned Imm; 5023 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) { 5024 if (ReverseEXT) 5025 std::swap(V1, V2); 5026 Imm *= getExtFactor(V1); 5027 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2, 5028 DAG.getConstant(Imm, MVT::i32)); 5029 } else if (V2->getOpcode() == ISD::UNDEF && 5030 isSingletonEXTMask(ShuffleMask, VT, Imm)) { 5031 Imm *= getExtFactor(V1); 5032 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1, 5033 DAG.getConstant(Imm, MVT::i32)); 5034 } 5035 5036 unsigned WhichResult; 5037 if (isZIPMask(ShuffleMask, VT, WhichResult)) { 5038 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; 5039 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); 5040 } 5041 if (isUZPMask(ShuffleMask, VT, WhichResult)) { 5042 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; 5043 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); 5044 } 5045 if (isTRNMask(ShuffleMask, VT, WhichResult)) { 5046 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; 5047 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); 5048 } 5049 5050 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) { 5051 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; 5052 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); 5053 } 5054 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) { 5055 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; 5056 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); 5057 } 5058 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) { 5059 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; 5060 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); 5061 } 5062 5063 SDValue Concat = tryFormConcatFromShuffle(Op, DAG); 5064 if (Concat.getNode()) 5065 return Concat; 5066 5067 bool DstIsLeft; 5068 int Anomaly; 5069 int NumInputElements = V1.getValueType().getVectorNumElements(); 5070 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) { 5071 SDValue DstVec = DstIsLeft ? V1 : V2; 5072 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64); 5073 5074 SDValue SrcVec = V1; 5075 int SrcLane = ShuffleMask[Anomaly]; 5076 if (SrcLane >= NumInputElements) { 5077 SrcVec = V2; 5078 SrcLane -= VT.getVectorNumElements(); 5079 } 5080 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64); 5081 5082 EVT ScalarVT = VT.getVectorElementType(); 5083 5084 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger()) 5085 ScalarVT = MVT::i32; 5086 5087 return DAG.getNode( 5088 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, 5089 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), 5090 DstLaneV); 5091 } 5092 5093 // If the shuffle is not directly supported and it has 4 elements, use 5094 // the PerfectShuffle-generated table to synthesize it from other shuffles. 5095 unsigned NumElts = VT.getVectorNumElements(); 5096 if (NumElts == 4) { 5097 unsigned PFIndexes[4]; 5098 for (unsigned i = 0; i != 4; ++i) { 5099 if (ShuffleMask[i] < 0) 5100 PFIndexes[i] = 8; 5101 else 5102 PFIndexes[i] = ShuffleMask[i]; 5103 } 5104 5105 // Compute the index in the perfect shuffle table. 5106 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 + 5107 PFIndexes[2] * 9 + PFIndexes[3]; 5108 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 5109 unsigned Cost = (PFEntry >> 30); 5110 5111 if (Cost <= 4) 5112 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 5113 } 5114 5115 return GenerateTBL(Op, ShuffleMask, DAG); 5116 } 5117 5118 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits, 5119 APInt &UndefBits) { 5120 EVT VT = BVN->getValueType(0); 5121 APInt SplatBits, SplatUndef; 5122 unsigned SplatBitSize; 5123 bool HasAnyUndefs; 5124 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 5125 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize; 5126 5127 for (unsigned i = 0; i < NumSplats; ++i) { 5128 CnstBits <<= SplatBitSize; 5129 UndefBits <<= SplatBitSize; 5130 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits()); 5131 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits()); 5132 } 5133 5134 return true; 5135 } 5136 5137 return false; 5138 } 5139 5140 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op, 5141 SelectionDAG &DAG) const { 5142 BuildVectorSDNode *BVN = 5143 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode()); 5144 SDValue LHS = Op.getOperand(0); 5145 SDLoc dl(Op); 5146 EVT VT = Op.getValueType(); 5147 5148 if (!BVN) 5149 return Op; 5150 5151 APInt CnstBits(VT.getSizeInBits(), 0); 5152 APInt UndefBits(VT.getSizeInBits(), 0); 5153 if (resolveBuildVector(BVN, CnstBits, UndefBits)) { 5154 // We only have BIC vector immediate instruction, which is and-not. 5155 CnstBits = ~CnstBits; 5156 5157 // We make use of a little bit of goto ickiness in order to avoid having to 5158 // duplicate the immediate matching logic for the undef toggled case. 5159 bool SecondTry = false; 5160 AttemptModImm: 5161 5162 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) { 5163 CnstBits = CnstBits.zextOrTrunc(64); 5164 uint64_t CnstVal = CnstBits.getZExtValue(); 5165 5166 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) { 5167 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal); 5168 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5169 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 5170 DAG.getConstant(CnstVal, MVT::i32), 5171 DAG.getConstant(0, MVT::i32)); 5172 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5173 } 5174 5175 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) { 5176 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal); 5177 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5178 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 5179 DAG.getConstant(CnstVal, MVT::i32), 5180 DAG.getConstant(8, MVT::i32)); 5181 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5182 } 5183 5184 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) { 5185 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal); 5186 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5187 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 5188 DAG.getConstant(CnstVal, MVT::i32), 5189 DAG.getConstant(16, MVT::i32)); 5190 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5191 } 5192 5193 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) { 5194 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal); 5195 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5196 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 5197 DAG.getConstant(CnstVal, MVT::i32), 5198 DAG.getConstant(24, MVT::i32)); 5199 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5200 } 5201 5202 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) { 5203 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal); 5204 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5205 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 5206 DAG.getConstant(CnstVal, MVT::i32), 5207 DAG.getConstant(0, MVT::i32)); 5208 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5209 } 5210 5211 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) { 5212 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal); 5213 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5214 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 5215 DAG.getConstant(CnstVal, MVT::i32), 5216 DAG.getConstant(8, MVT::i32)); 5217 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5218 } 5219 } 5220 5221 if (SecondTry) 5222 goto FailedModImm; 5223 SecondTry = true; 5224 CnstBits = ~UndefBits; 5225 goto AttemptModImm; 5226 } 5227 5228 // We can always fall back to a non-immediate AND. 5229 FailedModImm: 5230 return Op; 5231 } 5232 5233 // Specialized code to quickly find if PotentialBVec is a BuildVector that 5234 // consists of only the same constant int value, returned in reference arg 5235 // ConstVal 5236 static bool isAllConstantBuildVector(const SDValue &PotentialBVec, 5237 uint64_t &ConstVal) { 5238 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec); 5239 if (!Bvec) 5240 return false; 5241 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0)); 5242 if (!FirstElt) 5243 return false; 5244 EVT VT = Bvec->getValueType(0); 5245 unsigned NumElts = VT.getVectorNumElements(); 5246 for (unsigned i = 1; i < NumElts; ++i) 5247 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt) 5248 return false; 5249 ConstVal = FirstElt->getZExtValue(); 5250 return true; 5251 } 5252 5253 static unsigned getIntrinsicID(const SDNode *N) { 5254 unsigned Opcode = N->getOpcode(); 5255 switch (Opcode) { 5256 default: 5257 return Intrinsic::not_intrinsic; 5258 case ISD::INTRINSIC_WO_CHAIN: { 5259 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 5260 if (IID < Intrinsic::num_intrinsics) 5261 return IID; 5262 return Intrinsic::not_intrinsic; 5263 } 5264 } 5265 } 5266 5267 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)), 5268 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a 5269 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2. 5270 // Also, logical shift right -> sri, with the same structure. 5271 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) { 5272 EVT VT = N->getValueType(0); 5273 5274 if (!VT.isVector()) 5275 return SDValue(); 5276 5277 SDLoc DL(N); 5278 5279 // Is the first op an AND? 5280 const SDValue And = N->getOperand(0); 5281 if (And.getOpcode() != ISD::AND) 5282 return SDValue(); 5283 5284 // Is the second op an shl or lshr? 5285 SDValue Shift = N->getOperand(1); 5286 // This will have been turned into: AArch64ISD::VSHL vector, #shift 5287 // or AArch64ISD::VLSHR vector, #shift 5288 unsigned ShiftOpc = Shift.getOpcode(); 5289 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR)) 5290 return SDValue(); 5291 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR; 5292 5293 // Is the shift amount constant? 5294 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1)); 5295 if (!C2node) 5296 return SDValue(); 5297 5298 // Is the and mask vector all constant? 5299 uint64_t C1; 5300 if (!isAllConstantBuildVector(And.getOperand(1), C1)) 5301 return SDValue(); 5302 5303 // Is C1 == ~C2, taking into account how much one can shift elements of a 5304 // particular size? 5305 uint64_t C2 = C2node->getZExtValue(); 5306 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits(); 5307 if (C2 > ElemSizeInBits) 5308 return SDValue(); 5309 unsigned ElemMask = (1 << ElemSizeInBits) - 1; 5310 if ((C1 & ElemMask) != (~C2 & ElemMask)) 5311 return SDValue(); 5312 5313 SDValue X = And.getOperand(0); 5314 SDValue Y = Shift.getOperand(0); 5315 5316 unsigned Intrin = 5317 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli; 5318 SDValue ResultSLI = 5319 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 5320 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1)); 5321 5322 DEBUG(dbgs() << "aarch64-lower: transformed: \n"); 5323 DEBUG(N->dump(&DAG)); 5324 DEBUG(dbgs() << "into: \n"); 5325 DEBUG(ResultSLI->dump(&DAG)); 5326 5327 ++NumShiftInserts; 5328 return ResultSLI; 5329 } 5330 5331 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op, 5332 SelectionDAG &DAG) const { 5333 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2)) 5334 if (EnableAArch64SlrGeneration) { 5335 SDValue Res = tryLowerToSLI(Op.getNode(), DAG); 5336 if (Res.getNode()) 5337 return Res; 5338 } 5339 5340 BuildVectorSDNode *BVN = 5341 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode()); 5342 SDValue LHS = Op.getOperand(1); 5343 SDLoc dl(Op); 5344 EVT VT = Op.getValueType(); 5345 5346 // OR commutes, so try swapping the operands. 5347 if (!BVN) { 5348 LHS = Op.getOperand(0); 5349 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode()); 5350 } 5351 if (!BVN) 5352 return Op; 5353 5354 APInt CnstBits(VT.getSizeInBits(), 0); 5355 APInt UndefBits(VT.getSizeInBits(), 0); 5356 if (resolveBuildVector(BVN, CnstBits, UndefBits)) { 5357 // We make use of a little bit of goto ickiness in order to avoid having to 5358 // duplicate the immediate matching logic for the undef toggled case. 5359 bool SecondTry = false; 5360 AttemptModImm: 5361 5362 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) { 5363 CnstBits = CnstBits.zextOrTrunc(64); 5364 uint64_t CnstVal = CnstBits.getZExtValue(); 5365 5366 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) { 5367 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal); 5368 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5369 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5370 DAG.getConstant(CnstVal, MVT::i32), 5371 DAG.getConstant(0, MVT::i32)); 5372 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5373 } 5374 5375 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) { 5376 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal); 5377 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5378 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5379 DAG.getConstant(CnstVal, MVT::i32), 5380 DAG.getConstant(8, MVT::i32)); 5381 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5382 } 5383 5384 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) { 5385 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal); 5386 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5387 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5388 DAG.getConstant(CnstVal, MVT::i32), 5389 DAG.getConstant(16, MVT::i32)); 5390 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5391 } 5392 5393 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) { 5394 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal); 5395 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5396 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5397 DAG.getConstant(CnstVal, MVT::i32), 5398 DAG.getConstant(24, MVT::i32)); 5399 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5400 } 5401 5402 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) { 5403 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal); 5404 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5405 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5406 DAG.getConstant(CnstVal, MVT::i32), 5407 DAG.getConstant(0, MVT::i32)); 5408 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5409 } 5410 5411 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) { 5412 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal); 5413 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5414 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5415 DAG.getConstant(CnstVal, MVT::i32), 5416 DAG.getConstant(8, MVT::i32)); 5417 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5418 } 5419 } 5420 5421 if (SecondTry) 5422 goto FailedModImm; 5423 SecondTry = true; 5424 CnstBits = UndefBits; 5425 goto AttemptModImm; 5426 } 5427 5428 // We can always fall back to a non-immediate OR. 5429 FailedModImm: 5430 return Op; 5431 } 5432 5433 // Normalize the operands of BUILD_VECTOR. The value of constant operands will 5434 // be truncated to fit element width. 5435 static SDValue NormalizeBuildVector(SDValue Op, 5436 SelectionDAG &DAG) { 5437 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!"); 5438 SDLoc dl(Op); 5439 EVT VT = Op.getValueType(); 5440 EVT EltTy= VT.getVectorElementType(); 5441 5442 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16) 5443 return Op; 5444 5445 SmallVector<SDValue, 16> Ops; 5446 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) { 5447 SDValue Lane = Op.getOperand(I); 5448 if (Lane.getOpcode() == ISD::Constant) { 5449 APInt LowBits(EltTy.getSizeInBits(), 5450 cast<ConstantSDNode>(Lane)->getZExtValue()); 5451 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32); 5452 } 5453 Ops.push_back(Lane); 5454 } 5455 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); 5456 } 5457 5458 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, 5459 SelectionDAG &DAG) const { 5460 SDLoc dl(Op); 5461 EVT VT = Op.getValueType(); 5462 Op = NormalizeBuildVector(Op, DAG); 5463 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 5464 5465 APInt CnstBits(VT.getSizeInBits(), 0); 5466 APInt UndefBits(VT.getSizeInBits(), 0); 5467 if (resolveBuildVector(BVN, CnstBits, UndefBits)) { 5468 // We make use of a little bit of goto ickiness in order to avoid having to 5469 // duplicate the immediate matching logic for the undef toggled case. 5470 bool SecondTry = false; 5471 AttemptModImm: 5472 5473 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) { 5474 CnstBits = CnstBits.zextOrTrunc(64); 5475 uint64_t CnstVal = CnstBits.getZExtValue(); 5476 5477 // Certain magic vector constants (used to express things like NOT 5478 // and NEG) are passed through unmodified. This allows codegen patterns 5479 // for these operations to match. Special-purpose patterns will lower 5480 // these immediates to MOVIs if it proves necessary. 5481 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL)) 5482 return Op; 5483 5484 // The many faces of MOVI... 5485 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) { 5486 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal); 5487 if (VT.getSizeInBits() == 128) { 5488 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64, 5489 DAG.getConstant(CnstVal, MVT::i32)); 5490 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5491 } 5492 5493 // Support the V64 version via subregister insertion. 5494 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64, 5495 DAG.getConstant(CnstVal, MVT::i32)); 5496 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5497 } 5498 5499 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) { 5500 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal); 5501 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5502 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5503 DAG.getConstant(CnstVal, MVT::i32), 5504 DAG.getConstant(0, MVT::i32)); 5505 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5506 } 5507 5508 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) { 5509 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal); 5510 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5511 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5512 DAG.getConstant(CnstVal, MVT::i32), 5513 DAG.getConstant(8, MVT::i32)); 5514 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5515 } 5516 5517 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) { 5518 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal); 5519 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5520 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5521 DAG.getConstant(CnstVal, MVT::i32), 5522 DAG.getConstant(16, MVT::i32)); 5523 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5524 } 5525 5526 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) { 5527 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal); 5528 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5529 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5530 DAG.getConstant(CnstVal, MVT::i32), 5531 DAG.getConstant(24, MVT::i32)); 5532 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5533 } 5534 5535 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) { 5536 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal); 5537 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5538 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5539 DAG.getConstant(CnstVal, MVT::i32), 5540 DAG.getConstant(0, MVT::i32)); 5541 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5542 } 5543 5544 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) { 5545 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal); 5546 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5547 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5548 DAG.getConstant(CnstVal, MVT::i32), 5549 DAG.getConstant(8, MVT::i32)); 5550 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5551 } 5552 5553 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) { 5554 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal); 5555 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5556 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy, 5557 DAG.getConstant(CnstVal, MVT::i32), 5558 DAG.getConstant(264, MVT::i32)); 5559 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5560 } 5561 5562 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) { 5563 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal); 5564 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5565 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy, 5566 DAG.getConstant(CnstVal, MVT::i32), 5567 DAG.getConstant(272, MVT::i32)); 5568 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5569 } 5570 5571 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) { 5572 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal); 5573 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8; 5574 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy, 5575 DAG.getConstant(CnstVal, MVT::i32)); 5576 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5577 } 5578 5579 // The few faces of FMOV... 5580 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) { 5581 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal); 5582 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32; 5583 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy, 5584 DAG.getConstant(CnstVal, MVT::i32)); 5585 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5586 } 5587 5588 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) && 5589 VT.getSizeInBits() == 128) { 5590 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal); 5591 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64, 5592 DAG.getConstant(CnstVal, MVT::i32)); 5593 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5594 } 5595 5596 // The many faces of MVNI... 5597 CnstVal = ~CnstVal; 5598 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) { 5599 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal); 5600 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5601 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5602 DAG.getConstant(CnstVal, MVT::i32), 5603 DAG.getConstant(0, MVT::i32)); 5604 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5605 } 5606 5607 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) { 5608 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal); 5609 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5610 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5611 DAG.getConstant(CnstVal, MVT::i32), 5612 DAG.getConstant(8, MVT::i32)); 5613 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5614 } 5615 5616 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) { 5617 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal); 5618 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5619 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5620 DAG.getConstant(CnstVal, MVT::i32), 5621 DAG.getConstant(16, MVT::i32)); 5622 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5623 } 5624 5625 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) { 5626 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal); 5627 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5628 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5629 DAG.getConstant(CnstVal, MVT::i32), 5630 DAG.getConstant(24, MVT::i32)); 5631 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5632 } 5633 5634 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) { 5635 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal); 5636 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5637 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5638 DAG.getConstant(CnstVal, MVT::i32), 5639 DAG.getConstant(0, MVT::i32)); 5640 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5641 } 5642 5643 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) { 5644 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal); 5645 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5646 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5647 DAG.getConstant(CnstVal, MVT::i32), 5648 DAG.getConstant(8, MVT::i32)); 5649 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5650 } 5651 5652 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) { 5653 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal); 5654 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5655 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy, 5656 DAG.getConstant(CnstVal, MVT::i32), 5657 DAG.getConstant(264, MVT::i32)); 5658 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5659 } 5660 5661 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) { 5662 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal); 5663 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5664 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy, 5665 DAG.getConstant(CnstVal, MVT::i32), 5666 DAG.getConstant(272, MVT::i32)); 5667 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); 5668 } 5669 } 5670 5671 if (SecondTry) 5672 goto FailedModImm; 5673 SecondTry = true; 5674 CnstBits = UndefBits; 5675 goto AttemptModImm; 5676 } 5677 FailedModImm: 5678 5679 // Scan through the operands to find some interesting properties we can 5680 // exploit: 5681 // 1) If only one value is used, we can use a DUP, or 5682 // 2) if only the low element is not undef, we can just insert that, or 5683 // 3) if only one constant value is used (w/ some non-constant lanes), 5684 // we can splat the constant value into the whole vector then fill 5685 // in the non-constant lanes. 5686 // 4) FIXME: If different constant values are used, but we can intelligently 5687 // select the values we'll be overwriting for the non-constant 5688 // lanes such that we can directly materialize the vector 5689 // some other way (MOVI, e.g.), we can be sneaky. 5690 unsigned NumElts = VT.getVectorNumElements(); 5691 bool isOnlyLowElement = true; 5692 bool usesOnlyOneValue = true; 5693 bool usesOnlyOneConstantValue = true; 5694 bool isConstant = true; 5695 unsigned NumConstantLanes = 0; 5696 SDValue Value; 5697 SDValue ConstantValue; 5698 for (unsigned i = 0; i < NumElts; ++i) { 5699 SDValue V = Op.getOperand(i); 5700 if (V.getOpcode() == ISD::UNDEF) 5701 continue; 5702 if (i > 0) 5703 isOnlyLowElement = false; 5704 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 5705 isConstant = false; 5706 5707 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) { 5708 ++NumConstantLanes; 5709 if (!ConstantValue.getNode()) 5710 ConstantValue = V; 5711 else if (ConstantValue != V) 5712 usesOnlyOneConstantValue = false; 5713 } 5714 5715 if (!Value.getNode()) 5716 Value = V; 5717 else if (V != Value) 5718 usesOnlyOneValue = false; 5719 } 5720 5721 if (!Value.getNode()) 5722 return DAG.getUNDEF(VT); 5723 5724 if (isOnlyLowElement) 5725 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 5726 5727 // Use DUP for non-constant splats. For f32 constant splats, reduce to 5728 // i32 and try again. 5729 if (usesOnlyOneValue) { 5730 if (!isConstant) { 5731 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5732 Value.getValueType() != VT) 5733 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value); 5734 5735 // This is actually a DUPLANExx operation, which keeps everything vectory. 5736 5737 // DUPLANE works on 128-bit vectors, widen it if necessary. 5738 SDValue Lane = Value.getOperand(1); 5739 Value = Value.getOperand(0); 5740 if (Value.getValueType().getSizeInBits() == 64) 5741 Value = WidenVector(Value, DAG); 5742 5743 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType()); 5744 return DAG.getNode(Opcode, dl, VT, Value, Lane); 5745 } 5746 5747 if (VT.getVectorElementType().isFloatingPoint()) { 5748 SmallVector<SDValue, 8> Ops; 5749 MVT NewType = 5750 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 5751 for (unsigned i = 0; i < NumElts; ++i) 5752 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i))); 5753 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts); 5754 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); 5755 Val = LowerBUILD_VECTOR(Val, DAG); 5756 if (Val.getNode()) 5757 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 5758 } 5759 } 5760 5761 // If there was only one constant value used and for more than one lane, 5762 // start by splatting that value, then replace the non-constant lanes. This 5763 // is better than the default, which will perform a separate initialization 5764 // for each lane. 5765 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) { 5766 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue); 5767 // Now insert the non-constant lanes. 5768 for (unsigned i = 0; i < NumElts; ++i) { 5769 SDValue V = Op.getOperand(i); 5770 SDValue LaneIdx = DAG.getConstant(i, MVT::i64); 5771 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) { 5772 // Note that type legalization likely mucked about with the VT of the 5773 // source operand, so we may have to convert it here before inserting. 5774 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); 5775 } 5776 } 5777 return Val; 5778 } 5779 5780 // If all elements are constants and the case above didn't get hit, fall back 5781 // to the default expansion, which will generate a load from the constant 5782 // pool. 5783 if (isConstant) 5784 return SDValue(); 5785 5786 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 5787 if (NumElts >= 4) { 5788 SDValue shuffle = ReconstructShuffle(Op, DAG); 5789 if (shuffle != SDValue()) 5790 return shuffle; 5791 } 5792 5793 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we 5794 // know the default expansion would otherwise fall back on something even 5795 // worse. For a vector with one or two non-undef values, that's 5796 // scalar_to_vector for the elements followed by a shuffle (provided the 5797 // shuffle is valid for the target) and materialization element by element 5798 // on the stack followed by a load for everything else. 5799 if (!isConstant && !usesOnlyOneValue) { 5800 SDValue Vec = DAG.getUNDEF(VT); 5801 SDValue Op0 = Op.getOperand(0); 5802 unsigned ElemSize = VT.getVectorElementType().getSizeInBits(); 5803 unsigned i = 0; 5804 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to 5805 // a) Avoid a RMW dependency on the full vector register, and 5806 // b) Allow the register coalescer to fold away the copy if the 5807 // value is already in an S or D register. 5808 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) { 5809 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub; 5810 MachineSDNode *N = 5811 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0, 5812 DAG.getTargetConstant(SubIdx, MVT::i32)); 5813 Vec = SDValue(N, 0); 5814 ++i; 5815 } 5816 for (; i < NumElts; ++i) { 5817 SDValue V = Op.getOperand(i); 5818 if (V.getOpcode() == ISD::UNDEF) 5819 continue; 5820 SDValue LaneIdx = DAG.getConstant(i, MVT::i64); 5821 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); 5822 } 5823 return Vec; 5824 } 5825 5826 // Just use the default expansion. We failed to find a better alternative. 5827 return SDValue(); 5828 } 5829 5830 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, 5831 SelectionDAG &DAG) const { 5832 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); 5833 5834 // Check for non-constant or out of range lane. 5835 EVT VT = Op.getOperand(0).getValueType(); 5836 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2)); 5837 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements()) 5838 return SDValue(); 5839 5840 5841 // Insertion/extraction are legal for V128 types. 5842 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || 5843 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 || 5844 VT == MVT::v8f16) 5845 return Op; 5846 5847 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && 5848 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16) 5849 return SDValue(); 5850 5851 // For V64 types, we perform insertion by expanding the value 5852 // to a V128 type and perform the insertion on that. 5853 SDLoc DL(Op); 5854 SDValue WideVec = WidenVector(Op.getOperand(0), DAG); 5855 EVT WideTy = WideVec.getValueType(); 5856 5857 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, 5858 Op.getOperand(1), Op.getOperand(2)); 5859 // Re-narrow the resultant vector. 5860 return NarrowVector(Node, DAG); 5861 } 5862 5863 SDValue 5864 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 5865 SelectionDAG &DAG) const { 5866 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); 5867 5868 // Check for non-constant or out of range lane. 5869 EVT VT = Op.getOperand(0).getValueType(); 5870 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 5871 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements()) 5872 return SDValue(); 5873 5874 5875 // Insertion/extraction are legal for V128 types. 5876 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || 5877 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 || 5878 VT == MVT::v8f16) 5879 return Op; 5880 5881 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && 5882 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16) 5883 return SDValue(); 5884 5885 // For V64 types, we perform extraction by expanding the value 5886 // to a V128 type and perform the extraction on that. 5887 SDLoc DL(Op); 5888 SDValue WideVec = WidenVector(Op.getOperand(0), DAG); 5889 EVT WideTy = WideVec.getValueType(); 5890 5891 EVT ExtrTy = WideTy.getVectorElementType(); 5892 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8) 5893 ExtrTy = MVT::i32; 5894 5895 // For extractions, we just return the result directly. 5896 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec, 5897 Op.getOperand(1)); 5898 } 5899 5900 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, 5901 SelectionDAG &DAG) const { 5902 EVT VT = Op.getOperand(0).getValueType(); 5903 SDLoc dl(Op); 5904 // Just in case... 5905 if (!VT.isVector()) 5906 return SDValue(); 5907 5908 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 5909 if (!Cst) 5910 return SDValue(); 5911 unsigned Val = Cst->getZExtValue(); 5912 5913 unsigned Size = Op.getValueType().getSizeInBits(); 5914 if (Val == 0) { 5915 switch (Size) { 5916 case 8: 5917 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(), 5918 Op.getOperand(0)); 5919 case 16: 5920 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(), 5921 Op.getOperand(0)); 5922 case 32: 5923 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(), 5924 Op.getOperand(0)); 5925 case 64: 5926 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(), 5927 Op.getOperand(0)); 5928 default: 5929 llvm_unreachable("Unexpected vector type in extract_subvector!"); 5930 } 5931 } 5932 // If this is extracting the upper 64-bits of a 128-bit vector, we match 5933 // that directly. 5934 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64) 5935 return Op; 5936 5937 return SDValue(); 5938 } 5939 5940 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 5941 EVT VT) const { 5942 if (VT.getVectorNumElements() == 4 && 5943 (VT.is128BitVector() || VT.is64BitVector())) { 5944 unsigned PFIndexes[4]; 5945 for (unsigned i = 0; i != 4; ++i) { 5946 if (M[i] < 0) 5947 PFIndexes[i] = 8; 5948 else 5949 PFIndexes[i] = M[i]; 5950 } 5951 5952 // Compute the index in the perfect shuffle table. 5953 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 + 5954 PFIndexes[2] * 9 + PFIndexes[3]; 5955 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 5956 unsigned Cost = (PFEntry >> 30); 5957 5958 if (Cost <= 4) 5959 return true; 5960 } 5961 5962 bool DummyBool; 5963 int DummyInt; 5964 unsigned DummyUnsigned; 5965 5966 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) || 5967 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) || 5968 isEXTMask(M, VT, DummyBool, DummyUnsigned) || 5969 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM. 5970 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) || 5971 isZIPMask(M, VT, DummyUnsigned) || 5972 isTRN_v_undef_Mask(M, VT, DummyUnsigned) || 5973 isUZP_v_undef_Mask(M, VT, DummyUnsigned) || 5974 isZIP_v_undef_Mask(M, VT, DummyUnsigned) || 5975 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) || 5976 isConcatMask(M, VT, VT.getSizeInBits() == 128)); 5977 } 5978 5979 /// getVShiftImm - Check if this is a valid build_vector for the immediate 5980 /// operand of a vector shift operation, where all the elements of the 5981 /// build_vector must have the same constant integer value. 5982 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 5983 // Ignore bit_converts. 5984 while (Op.getOpcode() == ISD::BITCAST) 5985 Op = Op.getOperand(0); 5986 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 5987 APInt SplatBits, SplatUndef; 5988 unsigned SplatBitSize; 5989 bool HasAnyUndefs; 5990 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 5991 HasAnyUndefs, ElementBits) || 5992 SplatBitSize > ElementBits) 5993 return false; 5994 Cnt = SplatBits.getSExtValue(); 5995 return true; 5996 } 5997 5998 /// isVShiftLImm - Check if this is a valid build_vector for the immediate 5999 /// operand of a vector shift left operation. That value must be in the range: 6000 /// 0 <= Value < ElementBits for a left shift; or 6001 /// 0 <= Value <= ElementBits for a long left shift. 6002 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 6003 assert(VT.isVector() && "vector shift count is not a vector type"); 6004 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 6005 if (!getVShiftImm(Op, ElementBits, Cnt)) 6006 return false; 6007 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits); 6008 } 6009 6010 /// isVShiftRImm - Check if this is a valid build_vector for the immediate 6011 /// operand of a vector shift right operation. For a shift opcode, the value 6012 /// is positive, but for an intrinsic the value count must be negative. The 6013 /// absolute value must be in the range: 6014 /// 1 <= |Value| <= ElementBits for a right shift; or 6015 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 6016 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 6017 int64_t &Cnt) { 6018 assert(VT.isVector() && "vector shift count is not a vector type"); 6019 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 6020 if (!getVShiftImm(Op, ElementBits, Cnt)) 6021 return false; 6022 if (isIntrinsic) 6023 Cnt = -Cnt; 6024 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits)); 6025 } 6026 6027 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op, 6028 SelectionDAG &DAG) const { 6029 EVT VT = Op.getValueType(); 6030 SDLoc DL(Op); 6031 int64_t Cnt; 6032 6033 if (!Op.getOperand(1).getValueType().isVector()) 6034 return Op; 6035 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 6036 6037 switch (Op.getOpcode()) { 6038 default: 6039 llvm_unreachable("unexpected shift opcode"); 6040 6041 case ISD::SHL: 6042 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) 6043 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0), 6044 DAG.getConstant(Cnt, MVT::i32)); 6045 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 6046 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32), 6047 Op.getOperand(0), Op.getOperand(1)); 6048 case ISD::SRA: 6049 case ISD::SRL: 6050 // Right shift immediate 6051 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) && 6052 Cnt < EltSize) { 6053 unsigned Opc = 6054 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR; 6055 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0), 6056 DAG.getConstant(Cnt, MVT::i32)); 6057 } 6058 6059 // Right shift register. Note, there is not a shift right register 6060 // instruction, but the shift left register instruction takes a signed 6061 // value, where negative numbers specify a right shift. 6062 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl 6063 : Intrinsic::aarch64_neon_ushl; 6064 // negate the shift amount 6065 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1)); 6066 SDValue NegShiftLeft = 6067 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 6068 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift); 6069 return NegShiftLeft; 6070 } 6071 6072 return SDValue(); 6073 } 6074 6075 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS, 6076 AArch64CC::CondCode CC, bool NoNans, EVT VT, 6077 SDLoc dl, SelectionDAG &DAG) { 6078 EVT SrcVT = LHS.getValueType(); 6079 6080 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode()); 6081 APInt CnstBits(VT.getSizeInBits(), 0); 6082 APInt UndefBits(VT.getSizeInBits(), 0); 6083 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits); 6084 bool IsZero = IsCnst && (CnstBits == 0); 6085 6086 if (SrcVT.getVectorElementType().isFloatingPoint()) { 6087 switch (CC) { 6088 default: 6089 return SDValue(); 6090 case AArch64CC::NE: { 6091 SDValue Fcmeq; 6092 if (IsZero) 6093 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS); 6094 else 6095 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS); 6096 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq); 6097 } 6098 case AArch64CC::EQ: 6099 if (IsZero) 6100 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS); 6101 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS); 6102 case AArch64CC::GE: 6103 if (IsZero) 6104 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS); 6105 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS); 6106 case AArch64CC::GT: 6107 if (IsZero) 6108 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS); 6109 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS); 6110 case AArch64CC::LS: 6111 if (IsZero) 6112 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS); 6113 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS); 6114 case AArch64CC::LT: 6115 if (!NoNans) 6116 return SDValue(); 6117 // If we ignore NaNs then we can use to the MI implementation. 6118 // Fallthrough. 6119 case AArch64CC::MI: 6120 if (IsZero) 6121 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS); 6122 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS); 6123 } 6124 } 6125 6126 switch (CC) { 6127 default: 6128 return SDValue(); 6129 case AArch64CC::NE: { 6130 SDValue Cmeq; 6131 if (IsZero) 6132 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS); 6133 else 6134 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS); 6135 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq); 6136 } 6137 case AArch64CC::EQ: 6138 if (IsZero) 6139 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS); 6140 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS); 6141 case AArch64CC::GE: 6142 if (IsZero) 6143 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS); 6144 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS); 6145 case AArch64CC::GT: 6146 if (IsZero) 6147 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS); 6148 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS); 6149 case AArch64CC::LE: 6150 if (IsZero) 6151 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS); 6152 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS); 6153 case AArch64CC::LS: 6154 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS); 6155 case AArch64CC::LO: 6156 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS); 6157 case AArch64CC::LT: 6158 if (IsZero) 6159 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS); 6160 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS); 6161 case AArch64CC::HI: 6162 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS); 6163 case AArch64CC::HS: 6164 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS); 6165 } 6166 } 6167 6168 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op, 6169 SelectionDAG &DAG) const { 6170 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 6171 SDValue LHS = Op.getOperand(0); 6172 SDValue RHS = Op.getOperand(1); 6173 SDLoc dl(Op); 6174 6175 if (LHS.getValueType().getVectorElementType().isInteger()) { 6176 assert(LHS.getValueType() == RHS.getValueType()); 6177 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC); 6178 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(), 6179 dl, DAG); 6180 } 6181 6182 assert(LHS.getValueType().getVectorElementType() == MVT::f32 || 6183 LHS.getValueType().getVectorElementType() == MVT::f64); 6184 6185 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally 6186 // clean. Some of them require two branches to implement. 6187 AArch64CC::CondCode CC1, CC2; 6188 bool ShouldInvert; 6189 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert); 6190 6191 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath; 6192 SDValue Cmp = 6193 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG); 6194 if (!Cmp.getNode()) 6195 return SDValue(); 6196 6197 if (CC2 != AArch64CC::AL) { 6198 SDValue Cmp2 = 6199 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG); 6200 if (!Cmp2.getNode()) 6201 return SDValue(); 6202 6203 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2); 6204 } 6205 6206 if (ShouldInvert) 6207 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType()); 6208 6209 return Cmp; 6210 } 6211 6212 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 6213 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 6214 /// specified in the intrinsic calls. 6215 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 6216 const CallInst &I, 6217 unsigned Intrinsic) const { 6218 switch (Intrinsic) { 6219 case Intrinsic::aarch64_neon_ld2: 6220 case Intrinsic::aarch64_neon_ld3: 6221 case Intrinsic::aarch64_neon_ld4: 6222 case Intrinsic::aarch64_neon_ld1x2: 6223 case Intrinsic::aarch64_neon_ld1x3: 6224 case Intrinsic::aarch64_neon_ld1x4: 6225 case Intrinsic::aarch64_neon_ld2lane: 6226 case Intrinsic::aarch64_neon_ld3lane: 6227 case Intrinsic::aarch64_neon_ld4lane: 6228 case Intrinsic::aarch64_neon_ld2r: 6229 case Intrinsic::aarch64_neon_ld3r: 6230 case Intrinsic::aarch64_neon_ld4r: { 6231 Info.opc = ISD::INTRINSIC_W_CHAIN; 6232 // Conservatively set memVT to the entire set of vectors loaded. 6233 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8; 6234 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 6235 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1); 6236 Info.offset = 0; 6237 Info.align = 0; 6238 Info.vol = false; // volatile loads with NEON intrinsics not supported 6239 Info.readMem = true; 6240 Info.writeMem = false; 6241 return true; 6242 } 6243 case Intrinsic::aarch64_neon_st2: 6244 case Intrinsic::aarch64_neon_st3: 6245 case Intrinsic::aarch64_neon_st4: 6246 case Intrinsic::aarch64_neon_st1x2: 6247 case Intrinsic::aarch64_neon_st1x3: 6248 case Intrinsic::aarch64_neon_st1x4: 6249 case Intrinsic::aarch64_neon_st2lane: 6250 case Intrinsic::aarch64_neon_st3lane: 6251 case Intrinsic::aarch64_neon_st4lane: { 6252 Info.opc = ISD::INTRINSIC_VOID; 6253 // Conservatively set memVT to the entire set of vectors stored. 6254 unsigned NumElts = 0; 6255 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 6256 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 6257 if (!ArgTy->isVectorTy()) 6258 break; 6259 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8; 6260 } 6261 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 6262 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1); 6263 Info.offset = 0; 6264 Info.align = 0; 6265 Info.vol = false; // volatile stores with NEON intrinsics not supported 6266 Info.readMem = false; 6267 Info.writeMem = true; 6268 return true; 6269 } 6270 case Intrinsic::aarch64_ldaxr: 6271 case Intrinsic::aarch64_ldxr: { 6272 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType()); 6273 Info.opc = ISD::INTRINSIC_W_CHAIN; 6274 Info.memVT = MVT::getVT(PtrTy->getElementType()); 6275 Info.ptrVal = I.getArgOperand(0); 6276 Info.offset = 0; 6277 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType()); 6278 Info.vol = true; 6279 Info.readMem = true; 6280 Info.writeMem = false; 6281 return true; 6282 } 6283 case Intrinsic::aarch64_stlxr: 6284 case Intrinsic::aarch64_stxr: { 6285 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType()); 6286 Info.opc = ISD::INTRINSIC_W_CHAIN; 6287 Info.memVT = MVT::getVT(PtrTy->getElementType()); 6288 Info.ptrVal = I.getArgOperand(1); 6289 Info.offset = 0; 6290 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType()); 6291 Info.vol = true; 6292 Info.readMem = false; 6293 Info.writeMem = true; 6294 return true; 6295 } 6296 case Intrinsic::aarch64_ldaxp: 6297 case Intrinsic::aarch64_ldxp: { 6298 Info.opc = ISD::INTRINSIC_W_CHAIN; 6299 Info.memVT = MVT::i128; 6300 Info.ptrVal = I.getArgOperand(0); 6301 Info.offset = 0; 6302 Info.align = 16; 6303 Info.vol = true; 6304 Info.readMem = true; 6305 Info.writeMem = false; 6306 return true; 6307 } 6308 case Intrinsic::aarch64_stlxp: 6309 case Intrinsic::aarch64_stxp: { 6310 Info.opc = ISD::INTRINSIC_W_CHAIN; 6311 Info.memVT = MVT::i128; 6312 Info.ptrVal = I.getArgOperand(2); 6313 Info.offset = 0; 6314 Info.align = 16; 6315 Info.vol = true; 6316 Info.readMem = false; 6317 Info.writeMem = true; 6318 return true; 6319 } 6320 default: 6321 break; 6322 } 6323 6324 return false; 6325 } 6326 6327 // Truncations from 64-bit GPR to 32-bit GPR is free. 6328 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 6329 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 6330 return false; 6331 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 6332 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 6333 return NumBits1 > NumBits2; 6334 } 6335 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 6336 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) 6337 return false; 6338 unsigned NumBits1 = VT1.getSizeInBits(); 6339 unsigned NumBits2 = VT2.getSizeInBits(); 6340 return NumBits1 > NumBits2; 6341 } 6342 6343 // All 32-bit GPR operations implicitly zero the high-half of the corresponding 6344 // 64-bit GPR. 6345 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 6346 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 6347 return false; 6348 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 6349 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 6350 return NumBits1 == 32 && NumBits2 == 64; 6351 } 6352 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 6353 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) 6354 return false; 6355 unsigned NumBits1 = VT1.getSizeInBits(); 6356 unsigned NumBits2 = VT2.getSizeInBits(); 6357 return NumBits1 == 32 && NumBits2 == 64; 6358 } 6359 6360 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 6361 EVT VT1 = Val.getValueType(); 6362 if (isZExtFree(VT1, VT2)) { 6363 return true; 6364 } 6365 6366 if (Val.getOpcode() != ISD::LOAD) 6367 return false; 6368 6369 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend. 6370 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() && 6371 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() && 6372 VT1.getSizeInBits() <= 32); 6373 } 6374 6375 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType, 6376 unsigned &RequiredAligment) const { 6377 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy()) 6378 return false; 6379 // Cyclone supports unaligned accesses. 6380 RequiredAligment = 0; 6381 unsigned NumBits = LoadedType->getPrimitiveSizeInBits(); 6382 return NumBits == 32 || NumBits == 64; 6383 } 6384 6385 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType, 6386 unsigned &RequiredAligment) const { 6387 if (!LoadedType.isSimple() || 6388 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint())) 6389 return false; 6390 // Cyclone supports unaligned accesses. 6391 RequiredAligment = 0; 6392 unsigned NumBits = LoadedType.getSizeInBits(); 6393 return NumBits == 32 || NumBits == 64; 6394 } 6395 6396 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, 6397 unsigned AlignCheck) { 6398 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) && 6399 (DstAlign == 0 || DstAlign % AlignCheck == 0)); 6400 } 6401 6402 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 6403 unsigned SrcAlign, bool IsMemset, 6404 bool ZeroMemset, 6405 bool MemcpyStrSrc, 6406 MachineFunction &MF) const { 6407 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one 6408 // instruction to materialize the v2i64 zero and one store (with restrictive 6409 // addressing mode). Just do two i64 store of zero-registers. 6410 bool Fast; 6411 const Function *F = MF.getFunction(); 6412 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 && 6413 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 6414 Attribute::NoImplicitFloat) && 6415 (memOpAlign(SrcAlign, DstAlign, 16) || 6416 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast))) 6417 return MVT::f128; 6418 6419 return Size >= 8 ? MVT::i64 : MVT::i32; 6420 } 6421 6422 // 12-bit optionally shifted immediates are legal for adds. 6423 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const { 6424 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0)) 6425 return true; 6426 return false; 6427 } 6428 6429 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid 6430 // immediates is the same as for an add or a sub. 6431 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const { 6432 if (Immed < 0) 6433 Immed *= -1; 6434 return isLegalAddImmediate(Immed); 6435 } 6436 6437 /// isLegalAddressingMode - Return true if the addressing mode represented 6438 /// by AM is legal for this target, for a load/store of the specified type. 6439 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM, 6440 Type *Ty) const { 6441 // AArch64 has five basic addressing modes: 6442 // reg 6443 // reg + 9-bit signed offset 6444 // reg + SIZE_IN_BYTES * 12-bit unsigned offset 6445 // reg1 + reg2 6446 // reg + SIZE_IN_BYTES * reg 6447 6448 // No global is ever allowed as a base. 6449 if (AM.BaseGV) 6450 return false; 6451 6452 // No reg+reg+imm addressing. 6453 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) 6454 return false; 6455 6456 // check reg + imm case: 6457 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12 6458 uint64_t NumBytes = 0; 6459 if (Ty->isSized()) { 6460 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty); 6461 NumBytes = NumBits / 8; 6462 if (!isPowerOf2_64(NumBits)) 6463 NumBytes = 0; 6464 } 6465 6466 if (!AM.Scale) { 6467 int64_t Offset = AM.BaseOffs; 6468 6469 // 9-bit signed offset 6470 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1) 6471 return true; 6472 6473 // 12-bit unsigned offset 6474 unsigned shift = Log2_64(NumBytes); 6475 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 && 6476 // Must be a multiple of NumBytes (NumBytes is a power of 2) 6477 (Offset >> shift) << shift == Offset) 6478 return true; 6479 return false; 6480 } 6481 6482 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2 6483 6484 if (!AM.Scale || AM.Scale == 1 || 6485 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes)) 6486 return true; 6487 return false; 6488 } 6489 6490 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM, 6491 Type *Ty) const { 6492 // Scaling factors are not free at all. 6493 // Operands | Rt Latency 6494 // ------------------------------------------- 6495 // Rt, [Xn, Xm] | 4 6496 // ------------------------------------------- 6497 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5 6498 // Rt, [Xn, Wm, <extend> #imm] | 6499 if (isLegalAddressingMode(AM, Ty)) 6500 // Scale represents reg2 * scale, thus account for 1 if 6501 // it is not equal to 0 or 1. 6502 return AM.Scale != 0 && AM.Scale != 1; 6503 return -1; 6504 } 6505 6506 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const { 6507 VT = VT.getScalarType(); 6508 6509 if (!VT.isSimple()) 6510 return false; 6511 6512 switch (VT.getSimpleVT().SimpleTy) { 6513 case MVT::f32: 6514 case MVT::f64: 6515 return true; 6516 default: 6517 break; 6518 } 6519 6520 return false; 6521 } 6522 6523 const MCPhysReg * 6524 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const { 6525 // LR is a callee-save register, but we must treat it as clobbered by any call 6526 // site. Hence we include LR in the scratch registers, which are in turn added 6527 // as implicit-defs for stackmaps and patchpoints. 6528 static const MCPhysReg ScratchRegs[] = { 6529 AArch64::X16, AArch64::X17, AArch64::LR, 0 6530 }; 6531 return ScratchRegs; 6532 } 6533 6534 bool 6535 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const { 6536 EVT VT = N->getValueType(0); 6537 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine 6538 // it with shift to let it be lowered to UBFX. 6539 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) && 6540 isa<ConstantSDNode>(N->getOperand(1))) { 6541 uint64_t TruncMask = N->getConstantOperandVal(1); 6542 if (isMask_64(TruncMask) && 6543 N->getOperand(0).getOpcode() == ISD::SRL && 6544 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1))) 6545 return false; 6546 } 6547 return true; 6548 } 6549 6550 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, 6551 Type *Ty) const { 6552 assert(Ty->isIntegerTy()); 6553 6554 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 6555 if (BitSize == 0) 6556 return false; 6557 6558 int64_t Val = Imm.getSExtValue(); 6559 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize)) 6560 return true; 6561 6562 if ((int64_t)Val < 0) 6563 Val = ~Val; 6564 if (BitSize == 32) 6565 Val &= (1LL << 32) - 1; 6566 6567 unsigned LZ = countLeadingZeros((uint64_t)Val); 6568 unsigned Shift = (63 - LZ) / 16; 6569 // MOVZ is free so return true for one or fewer MOVK. 6570 return (Shift < 3) ? true : false; 6571 } 6572 6573 // Generate SUBS and CSEL for integer abs. 6574 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) { 6575 EVT VT = N->getValueType(0); 6576 6577 SDValue N0 = N->getOperand(0); 6578 SDValue N1 = N->getOperand(1); 6579 SDLoc DL(N); 6580 6581 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1) 6582 // and change it to SUB and CSEL. 6583 if (VT.isInteger() && N->getOpcode() == ISD::XOR && 6584 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 && 6585 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0)) 6586 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 6587 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) { 6588 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), 6589 N0.getOperand(0)); 6590 // Generate SUBS & CSEL. 6591 SDValue Cmp = 6592 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32), 6593 N0.getOperand(0), DAG.getConstant(0, VT)); 6594 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg, 6595 DAG.getConstant(AArch64CC::PL, MVT::i32), 6596 SDValue(Cmp.getNode(), 1)); 6597 } 6598 return SDValue(); 6599 } 6600 6601 // performXorCombine - Attempts to handle integer ABS. 6602 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG, 6603 TargetLowering::DAGCombinerInfo &DCI, 6604 const AArch64Subtarget *Subtarget) { 6605 if (DCI.isBeforeLegalizeOps()) 6606 return SDValue(); 6607 6608 return performIntegerAbsCombine(N, DAG); 6609 } 6610 6611 SDValue 6612 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, 6613 SelectionDAG &DAG, 6614 std::vector<SDNode *> *Created) const { 6615 // fold (sdiv X, pow2) 6616 EVT VT = N->getValueType(0); 6617 if ((VT != MVT::i32 && VT != MVT::i64) || 6618 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2())) 6619 return SDValue(); 6620 6621 SDLoc DL(N); 6622 SDValue N0 = N->getOperand(0); 6623 unsigned Lg2 = Divisor.countTrailingZeros(); 6624 SDValue Zero = DAG.getConstant(0, VT); 6625 SDValue Pow2MinusOne = DAG.getConstant((1 << Lg2) - 1, VT); 6626 6627 // Add (N0 < 0) ? Pow2 - 1 : 0; 6628 SDValue CCVal; 6629 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL); 6630 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); 6631 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp); 6632 6633 if (Created) { 6634 Created->push_back(Cmp.getNode()); 6635 Created->push_back(Add.getNode()); 6636 Created->push_back(CSel.getNode()); 6637 } 6638 6639 // Divide by pow2. 6640 SDValue SRA = 6641 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64)); 6642 6643 // If we're dividing by a positive value, we're done. Otherwise, we must 6644 // negate the result. 6645 if (Divisor.isNonNegative()) 6646 return SRA; 6647 6648 if (Created) 6649 Created->push_back(SRA.getNode()); 6650 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA); 6651 } 6652 6653 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG, 6654 TargetLowering::DAGCombinerInfo &DCI, 6655 const AArch64Subtarget *Subtarget) { 6656 if (DCI.isBeforeLegalizeOps()) 6657 return SDValue(); 6658 6659 // Multiplication of a power of two plus/minus one can be done more 6660 // cheaply as as shift+add/sub. For now, this is true unilaterally. If 6661 // future CPUs have a cheaper MADD instruction, this may need to be 6662 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and 6663 // 64-bit is 5 cycles, so this is always a win. 6664 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 6665 APInt Value = C->getAPIntValue(); 6666 EVT VT = N->getValueType(0); 6667 if (Value.isNonNegative()) { 6668 // (mul x, 2^N + 1) => (add (shl x, N), x) 6669 APInt VM1 = Value - 1; 6670 if (VM1.isPowerOf2()) { 6671 SDValue ShiftedVal = 6672 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), 6673 DAG.getConstant(VM1.logBase2(), MVT::i64)); 6674 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, 6675 N->getOperand(0)); 6676 } 6677 // (mul x, 2^N - 1) => (sub (shl x, N), x) 6678 APInt VP1 = Value + 1; 6679 if (VP1.isPowerOf2()) { 6680 SDValue ShiftedVal = 6681 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), 6682 DAG.getConstant(VP1.logBase2(), MVT::i64)); 6683 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, 6684 N->getOperand(0)); 6685 } 6686 } else { 6687 // (mul x, -(2^N + 1)) => - (add (shl x, N), x) 6688 APInt VNM1 = -Value - 1; 6689 if (VNM1.isPowerOf2()) { 6690 SDValue ShiftedVal = 6691 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), 6692 DAG.getConstant(VNM1.logBase2(), MVT::i64)); 6693 SDValue Add = 6694 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0)); 6695 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add); 6696 } 6697 // (mul x, -(2^N - 1)) => (sub x, (shl x, N)) 6698 APInt VNP1 = -Value + 1; 6699 if (VNP1.isPowerOf2()) { 6700 SDValue ShiftedVal = 6701 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), 6702 DAG.getConstant(VNP1.logBase2(), MVT::i64)); 6703 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0), 6704 ShiftedVal); 6705 } 6706 } 6707 } 6708 return SDValue(); 6709 } 6710 6711 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N, 6712 SelectionDAG &DAG) { 6713 // Take advantage of vector comparisons producing 0 or -1 in each lane to 6714 // optimize away operation when it's from a constant. 6715 // 6716 // The general transformation is: 6717 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) --> 6718 // AND(VECTOR_CMP(x,y), constant2) 6719 // constant2 = UNARYOP(constant) 6720 6721 // Early exit if this isn't a vector operation, the operand of the 6722 // unary operation isn't a bitwise AND, or if the sizes of the operations 6723 // aren't the same. 6724 EVT VT = N->getValueType(0); 6725 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND || 6726 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC || 6727 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits()) 6728 return SDValue(); 6729 6730 // Now check that the other operand of the AND is a constant. We could 6731 // make the transformation for non-constant splats as well, but it's unclear 6732 // that would be a benefit as it would not eliminate any operations, just 6733 // perform one more step in scalar code before moving to the vector unit. 6734 if (BuildVectorSDNode *BV = 6735 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) { 6736 // Bail out if the vector isn't a constant. 6737 if (!BV->isConstant()) 6738 return SDValue(); 6739 6740 // Everything checks out. Build up the new and improved node. 6741 SDLoc DL(N); 6742 EVT IntVT = BV->getValueType(0); 6743 // Create a new constant of the appropriate type for the transformed 6744 // DAG. 6745 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0)); 6746 // The AND node needs bitcasts to/from an integer vector type around it. 6747 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); 6748 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, 6749 N->getOperand(0)->getOperand(0), MaskConst); 6750 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd); 6751 return Res; 6752 } 6753 6754 return SDValue(); 6755 } 6756 6757 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) { 6758 // First try to optimize away the conversion when it's conditionally from 6759 // a constant. Vectors only. 6760 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG); 6761 if (Res != SDValue()) 6762 return Res; 6763 6764 EVT VT = N->getValueType(0); 6765 if (VT != MVT::f32 && VT != MVT::f64) 6766 return SDValue(); 6767 6768 // Only optimize when the source and destination types have the same width. 6769 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits()) 6770 return SDValue(); 6771 6772 // If the result of an integer load is only used by an integer-to-float 6773 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead. 6774 // This eliminates an "integer-to-vector-move UOP and improve throughput. 6775 SDValue N0 = N->getOperand(0); 6776 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6777 // Do not change the width of a volatile load. 6778 !cast<LoadSDNode>(N0)->isVolatile()) { 6779 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6780 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(), 6781 LN0->getPointerInfo(), LN0->isVolatile(), 6782 LN0->isNonTemporal(), LN0->isInvariant(), 6783 LN0->getAlignment()); 6784 6785 // Make sure successors of the original load stay after it by updating them 6786 // to use the new Chain. 6787 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1)); 6788 6789 unsigned Opcode = 6790 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF; 6791 return DAG.getNode(Opcode, SDLoc(N), VT, Load); 6792 } 6793 6794 return SDValue(); 6795 } 6796 6797 /// An EXTR instruction is made up of two shifts, ORed together. This helper 6798 /// searches for and classifies those shifts. 6799 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, 6800 bool &FromHi) { 6801 if (N.getOpcode() == ISD::SHL) 6802 FromHi = false; 6803 else if (N.getOpcode() == ISD::SRL) 6804 FromHi = true; 6805 else 6806 return false; 6807 6808 if (!isa<ConstantSDNode>(N.getOperand(1))) 6809 return false; 6810 6811 ShiftAmount = N->getConstantOperandVal(1); 6812 Src = N->getOperand(0); 6813 return true; 6814 } 6815 6816 /// EXTR instruction extracts a contiguous chunk of bits from two existing 6817 /// registers viewed as a high/low pair. This function looks for the pattern: 6818 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an 6819 /// EXTR. Can't quite be done in TableGen because the two immediates aren't 6820 /// independent. 6821 static SDValue tryCombineToEXTR(SDNode *N, 6822 TargetLowering::DAGCombinerInfo &DCI) { 6823 SelectionDAG &DAG = DCI.DAG; 6824 SDLoc DL(N); 6825 EVT VT = N->getValueType(0); 6826 6827 assert(N->getOpcode() == ISD::OR && "Unexpected root"); 6828 6829 if (VT != MVT::i32 && VT != MVT::i64) 6830 return SDValue(); 6831 6832 SDValue LHS; 6833 uint32_t ShiftLHS = 0; 6834 bool LHSFromHi = 0; 6835 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi)) 6836 return SDValue(); 6837 6838 SDValue RHS; 6839 uint32_t ShiftRHS = 0; 6840 bool RHSFromHi = 0; 6841 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) 6842 return SDValue(); 6843 6844 // If they're both trying to come from the high part of the register, they're 6845 // not really an EXTR. 6846 if (LHSFromHi == RHSFromHi) 6847 return SDValue(); 6848 6849 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) 6850 return SDValue(); 6851 6852 if (LHSFromHi) { 6853 std::swap(LHS, RHS); 6854 std::swap(ShiftLHS, ShiftRHS); 6855 } 6856 6857 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS, 6858 DAG.getConstant(ShiftRHS, MVT::i64)); 6859 } 6860 6861 static SDValue tryCombineToBSL(SDNode *N, 6862 TargetLowering::DAGCombinerInfo &DCI) { 6863 EVT VT = N->getValueType(0); 6864 SelectionDAG &DAG = DCI.DAG; 6865 SDLoc DL(N); 6866 6867 if (!VT.isVector()) 6868 return SDValue(); 6869 6870 SDValue N0 = N->getOperand(0); 6871 if (N0.getOpcode() != ISD::AND) 6872 return SDValue(); 6873 6874 SDValue N1 = N->getOperand(1); 6875 if (N1.getOpcode() != ISD::AND) 6876 return SDValue(); 6877 6878 // We only have to look for constant vectors here since the general, variable 6879 // case can be handled in TableGen. 6880 unsigned Bits = VT.getVectorElementType().getSizeInBits(); 6881 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1); 6882 for (int i = 1; i >= 0; --i) 6883 for (int j = 1; j >= 0; --j) { 6884 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i)); 6885 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j)); 6886 if (!BVN0 || !BVN1) 6887 continue; 6888 6889 bool FoundMatch = true; 6890 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) { 6891 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k)); 6892 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k)); 6893 if (!CN0 || !CN1 || 6894 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) { 6895 FoundMatch = false; 6896 break; 6897 } 6898 } 6899 6900 if (FoundMatch) 6901 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0), 6902 N0->getOperand(1 - i), N1->getOperand(1 - j)); 6903 } 6904 6905 return SDValue(); 6906 } 6907 6908 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, 6909 const AArch64Subtarget *Subtarget) { 6910 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) 6911 if (!EnableAArch64ExtrGeneration) 6912 return SDValue(); 6913 SelectionDAG &DAG = DCI.DAG; 6914 EVT VT = N->getValueType(0); 6915 6916 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6917 return SDValue(); 6918 6919 SDValue Res = tryCombineToEXTR(N, DCI); 6920 if (Res.getNode()) 6921 return Res; 6922 6923 Res = tryCombineToBSL(N, DCI); 6924 if (Res.getNode()) 6925 return Res; 6926 6927 return SDValue(); 6928 } 6929 6930 static SDValue performBitcastCombine(SDNode *N, 6931 TargetLowering::DAGCombinerInfo &DCI, 6932 SelectionDAG &DAG) { 6933 // Wait 'til after everything is legalized to try this. That way we have 6934 // legal vector types and such. 6935 if (DCI.isBeforeLegalizeOps()) 6936 return SDValue(); 6937 6938 // Remove extraneous bitcasts around an extract_subvector. 6939 // For example, 6940 // (v4i16 (bitconvert 6941 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1))))) 6942 // becomes 6943 // (extract_subvector ((v8i16 ...), (i64 4))) 6944 6945 // Only interested in 64-bit vectors as the ultimate result. 6946 EVT VT = N->getValueType(0); 6947 if (!VT.isVector()) 6948 return SDValue(); 6949 if (VT.getSimpleVT().getSizeInBits() != 64) 6950 return SDValue(); 6951 // Is the operand an extract_subvector starting at the beginning or halfway 6952 // point of the vector? A low half may also come through as an 6953 // EXTRACT_SUBREG, so look for that, too. 6954 SDValue Op0 = N->getOperand(0); 6955 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR && 6956 !(Op0->isMachineOpcode() && 6957 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG)) 6958 return SDValue(); 6959 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue(); 6960 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) { 6961 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0) 6962 return SDValue(); 6963 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) { 6964 if (idx != AArch64::dsub) 6965 return SDValue(); 6966 // The dsub reference is equivalent to a lane zero subvector reference. 6967 idx = 0; 6968 } 6969 // Look through the bitcast of the input to the extract. 6970 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST) 6971 return SDValue(); 6972 SDValue Source = Op0->getOperand(0)->getOperand(0); 6973 // If the source type has twice the number of elements as our destination 6974 // type, we know this is an extract of the high or low half of the vector. 6975 EVT SVT = Source->getValueType(0); 6976 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2) 6977 return SDValue(); 6978 6979 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n"); 6980 6981 // Create the simplified form to just extract the low or high half of the 6982 // vector directly rather than bothering with the bitcasts. 6983 SDLoc dl(N); 6984 unsigned NumElements = VT.getVectorNumElements(); 6985 if (idx) { 6986 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64); 6987 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx); 6988 } else { 6989 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32); 6990 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT, 6991 Source, SubReg), 6992 0); 6993 } 6994 } 6995 6996 static SDValue performConcatVectorsCombine(SDNode *N, 6997 TargetLowering::DAGCombinerInfo &DCI, 6998 SelectionDAG &DAG) { 6999 // Wait 'til after everything is legalized to try this. That way we have 7000 // legal vector types and such. 7001 if (DCI.isBeforeLegalizeOps()) 7002 return SDValue(); 7003 7004 SDLoc dl(N); 7005 EVT VT = N->getValueType(0); 7006 7007 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector 7008 // splat. The indexed instructions are going to be expecting a DUPLANE64, so 7009 // canonicalise to that. 7010 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) { 7011 assert(VT.getVectorElementType().getSizeInBits() == 64); 7012 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, 7013 WidenVector(N->getOperand(0), DAG), 7014 DAG.getConstant(0, MVT::i64)); 7015 } 7016 7017 // Canonicalise concat_vectors so that the right-hand vector has as few 7018 // bit-casts as possible before its real operation. The primary matching 7019 // destination for these operations will be the narrowing "2" instructions, 7020 // which depend on the operation being performed on this right-hand vector. 7021 // For example, 7022 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS)))) 7023 // becomes 7024 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS)) 7025 7026 SDValue Op1 = N->getOperand(1); 7027 if (Op1->getOpcode() != ISD::BITCAST) 7028 return SDValue(); 7029 SDValue RHS = Op1->getOperand(0); 7030 MVT RHSTy = RHS.getValueType().getSimpleVT(); 7031 // If the RHS is not a vector, this is not the pattern we're looking for. 7032 if (!RHSTy.isVector()) 7033 return SDValue(); 7034 7035 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n"); 7036 7037 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(), 7038 RHSTy.getVectorNumElements() * 2); 7039 return DAG.getNode( 7040 ISD::BITCAST, dl, VT, 7041 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, 7042 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS)); 7043 } 7044 7045 static SDValue tryCombineFixedPointConvert(SDNode *N, 7046 TargetLowering::DAGCombinerInfo &DCI, 7047 SelectionDAG &DAG) { 7048 // Wait 'til after everything is legalized to try this. That way we have 7049 // legal vector types and such. 7050 if (DCI.isBeforeLegalizeOps()) 7051 return SDValue(); 7052 // Transform a scalar conversion of a value from a lane extract into a 7053 // lane extract of a vector conversion. E.g., from foo1 to foo2: 7054 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); } 7055 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; } 7056 // 7057 // The second form interacts better with instruction selection and the 7058 // register allocator to avoid cross-class register copies that aren't 7059 // coalescable due to a lane reference. 7060 7061 // Check the operand and see if it originates from a lane extract. 7062 SDValue Op1 = N->getOperand(1); 7063 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 7064 // Yep, no additional predication needed. Perform the transform. 7065 SDValue IID = N->getOperand(0); 7066 SDValue Shift = N->getOperand(2); 7067 SDValue Vec = Op1.getOperand(0); 7068 SDValue Lane = Op1.getOperand(1); 7069 EVT ResTy = N->getValueType(0); 7070 EVT VecResTy; 7071 SDLoc DL(N); 7072 7073 // The vector width should be 128 bits by the time we get here, even 7074 // if it started as 64 bits (the extract_vector handling will have 7075 // done so). 7076 assert(Vec.getValueType().getSizeInBits() == 128 && 7077 "unexpected vector size on extract_vector_elt!"); 7078 if (Vec.getValueType() == MVT::v4i32) 7079 VecResTy = MVT::v4f32; 7080 else if (Vec.getValueType() == MVT::v2i64) 7081 VecResTy = MVT::v2f64; 7082 else 7083 llvm_unreachable("unexpected vector type!"); 7084 7085 SDValue Convert = 7086 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift); 7087 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane); 7088 } 7089 return SDValue(); 7090 } 7091 7092 // AArch64 high-vector "long" operations are formed by performing the non-high 7093 // version on an extract_subvector of each operand which gets the high half: 7094 // 7095 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS)) 7096 // 7097 // However, there are cases which don't have an extract_high explicitly, but 7098 // have another operation that can be made compatible with one for free. For 7099 // example: 7100 // 7101 // (dupv64 scalar) --> (extract_high (dup128 scalar)) 7102 // 7103 // This routine does the actual conversion of such DUPs, once outer routines 7104 // have determined that everything else is in order. 7105 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) { 7106 // We can handle most types of duplicate, but the lane ones have an extra 7107 // operand saying *which* lane, so we need to know. 7108 bool IsDUPLANE; 7109 switch (N.getOpcode()) { 7110 case AArch64ISD::DUP: 7111 IsDUPLANE = false; 7112 break; 7113 case AArch64ISD::DUPLANE8: 7114 case AArch64ISD::DUPLANE16: 7115 case AArch64ISD::DUPLANE32: 7116 case AArch64ISD::DUPLANE64: 7117 IsDUPLANE = true; 7118 break; 7119 default: 7120 return SDValue(); 7121 } 7122 7123 MVT NarrowTy = N.getSimpleValueType(); 7124 if (!NarrowTy.is64BitVector()) 7125 return SDValue(); 7126 7127 MVT ElementTy = NarrowTy.getVectorElementType(); 7128 unsigned NumElems = NarrowTy.getVectorNumElements(); 7129 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2); 7130 7131 SDValue NewDUP; 7132 if (IsDUPLANE) 7133 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0), 7134 N.getOperand(1)); 7135 else 7136 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0)); 7137 7138 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy, 7139 NewDUP, DAG.getConstant(NumElems, MVT::i64)); 7140 } 7141 7142 static bool isEssentiallyExtractSubvector(SDValue N) { 7143 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR) 7144 return true; 7145 7146 return N.getOpcode() == ISD::BITCAST && 7147 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR; 7148 } 7149 7150 /// \brief Helper structure to keep track of ISD::SET_CC operands. 7151 struct GenericSetCCInfo { 7152 const SDValue *Opnd0; 7153 const SDValue *Opnd1; 7154 ISD::CondCode CC; 7155 }; 7156 7157 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code. 7158 struct AArch64SetCCInfo { 7159 const SDValue *Cmp; 7160 AArch64CC::CondCode CC; 7161 }; 7162 7163 /// \brief Helper structure to keep track of SetCC information. 7164 union SetCCInfo { 7165 GenericSetCCInfo Generic; 7166 AArch64SetCCInfo AArch64; 7167 }; 7168 7169 /// \brief Helper structure to be able to read SetCC information. If set to 7170 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a 7171 /// GenericSetCCInfo. 7172 struct SetCCInfoAndKind { 7173 SetCCInfo Info; 7174 bool IsAArch64; 7175 }; 7176 7177 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or 7178 /// an 7179 /// AArch64 lowered one. 7180 /// \p SetCCInfo is filled accordingly. 7181 /// \post SetCCInfo is meanginfull only when this function returns true. 7182 /// \return True when Op is a kind of SET_CC operation. 7183 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) { 7184 // If this is a setcc, this is straight forward. 7185 if (Op.getOpcode() == ISD::SETCC) { 7186 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0); 7187 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1); 7188 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 7189 SetCCInfo.IsAArch64 = false; 7190 return true; 7191 } 7192 // Otherwise, check if this is a matching csel instruction. 7193 // In other words: 7194 // - csel 1, 0, cc 7195 // - csel 0, 1, !cc 7196 if (Op.getOpcode() != AArch64ISD::CSEL) 7197 return false; 7198 // Set the information about the operands. 7199 // TODO: we want the operands of the Cmp not the csel 7200 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3); 7201 SetCCInfo.IsAArch64 = true; 7202 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>( 7203 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 7204 7205 // Check that the operands matches the constraints: 7206 // (1) Both operands must be constants. 7207 // (2) One must be 1 and the other must be 0. 7208 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 7209 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 7210 7211 // Check (1). 7212 if (!TValue || !FValue) 7213 return false; 7214 7215 // Check (2). 7216 if (!TValue->isOne()) { 7217 // Update the comparison when we are interested in !cc. 7218 std::swap(TValue, FValue); 7219 SetCCInfo.Info.AArch64.CC = 7220 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC); 7221 } 7222 return TValue->isOne() && FValue->isNullValue(); 7223 } 7224 7225 // Returns true if Op is setcc or zext of setcc. 7226 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) { 7227 if (isSetCC(Op, Info)) 7228 return true; 7229 return ((Op.getOpcode() == ISD::ZERO_EXTEND) && 7230 isSetCC(Op->getOperand(0), Info)); 7231 } 7232 7233 // The folding we want to perform is: 7234 // (add x, [zext] (setcc cc ...) ) 7235 // --> 7236 // (csel x, (add x, 1), !cc ...) 7237 // 7238 // The latter will get matched to a CSINC instruction. 7239 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) { 7240 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!"); 7241 SDValue LHS = Op->getOperand(0); 7242 SDValue RHS = Op->getOperand(1); 7243 SetCCInfoAndKind InfoAndKind; 7244 7245 // If neither operand is a SET_CC, give up. 7246 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) { 7247 std::swap(LHS, RHS); 7248 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) 7249 return SDValue(); 7250 } 7251 7252 // FIXME: This could be generatized to work for FP comparisons. 7253 EVT CmpVT = InfoAndKind.IsAArch64 7254 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType() 7255 : InfoAndKind.Info.Generic.Opnd0->getValueType(); 7256 if (CmpVT != MVT::i32 && CmpVT != MVT::i64) 7257 return SDValue(); 7258 7259 SDValue CCVal; 7260 SDValue Cmp; 7261 SDLoc dl(Op); 7262 if (InfoAndKind.IsAArch64) { 7263 CCVal = DAG.getConstant( 7264 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32); 7265 Cmp = *InfoAndKind.Info.AArch64.Cmp; 7266 } else 7267 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0, 7268 *InfoAndKind.Info.Generic.Opnd1, 7269 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true), 7270 CCVal, DAG, dl); 7271 7272 EVT VT = Op->getValueType(0); 7273 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT)); 7274 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp); 7275 } 7276 7277 // The basic add/sub long vector instructions have variants with "2" on the end 7278 // which act on the high-half of their inputs. They are normally matched by 7279 // patterns like: 7280 // 7281 // (add (zeroext (extract_high LHS)), 7282 // (zeroext (extract_high RHS))) 7283 // -> uaddl2 vD, vN, vM 7284 // 7285 // However, if one of the extracts is something like a duplicate, this 7286 // instruction can still be used profitably. This function puts the DAG into a 7287 // more appropriate form for those patterns to trigger. 7288 static SDValue performAddSubLongCombine(SDNode *N, 7289 TargetLowering::DAGCombinerInfo &DCI, 7290 SelectionDAG &DAG) { 7291 if (DCI.isBeforeLegalizeOps()) 7292 return SDValue(); 7293 7294 MVT VT = N->getSimpleValueType(0); 7295 if (!VT.is128BitVector()) { 7296 if (N->getOpcode() == ISD::ADD) 7297 return performSetccAddFolding(N, DAG); 7298 return SDValue(); 7299 } 7300 7301 // Make sure both branches are extended in the same way. 7302 SDValue LHS = N->getOperand(0); 7303 SDValue RHS = N->getOperand(1); 7304 if ((LHS.getOpcode() != ISD::ZERO_EXTEND && 7305 LHS.getOpcode() != ISD::SIGN_EXTEND) || 7306 LHS.getOpcode() != RHS.getOpcode()) 7307 return SDValue(); 7308 7309 unsigned ExtType = LHS.getOpcode(); 7310 7311 // It's not worth doing if at least one of the inputs isn't already an 7312 // extract, but we don't know which it'll be so we have to try both. 7313 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) { 7314 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG); 7315 if (!RHS.getNode()) 7316 return SDValue(); 7317 7318 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS); 7319 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) { 7320 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG); 7321 if (!LHS.getNode()) 7322 return SDValue(); 7323 7324 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS); 7325 } 7326 7327 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS); 7328 } 7329 7330 // Massage DAGs which we can use the high-half "long" operations on into 7331 // something isel will recognize better. E.g. 7332 // 7333 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) --> 7334 // (aarch64_neon_umull (extract_high (v2i64 vec))) 7335 // (extract_high (v2i64 (dup128 scalar))))) 7336 // 7337 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N, 7338 TargetLowering::DAGCombinerInfo &DCI, 7339 SelectionDAG &DAG) { 7340 if (DCI.isBeforeLegalizeOps()) 7341 return SDValue(); 7342 7343 SDValue LHS = N->getOperand(1); 7344 SDValue RHS = N->getOperand(2); 7345 assert(LHS.getValueType().is64BitVector() && 7346 RHS.getValueType().is64BitVector() && 7347 "unexpected shape for long operation"); 7348 7349 // Either node could be a DUP, but it's not worth doing both of them (you'd 7350 // just as well use the non-high version) so look for a corresponding extract 7351 // operation on the other "wing". 7352 if (isEssentiallyExtractSubvector(LHS)) { 7353 RHS = tryExtendDUPToExtractHigh(RHS, DAG); 7354 if (!RHS.getNode()) 7355 return SDValue(); 7356 } else if (isEssentiallyExtractSubvector(RHS)) { 7357 LHS = tryExtendDUPToExtractHigh(LHS, DAG); 7358 if (!LHS.getNode()) 7359 return SDValue(); 7360 } 7361 7362 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0), 7363 N->getOperand(0), LHS, RHS); 7364 } 7365 7366 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) { 7367 MVT ElemTy = N->getSimpleValueType(0).getScalarType(); 7368 unsigned ElemBits = ElemTy.getSizeInBits(); 7369 7370 int64_t ShiftAmount; 7371 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) { 7372 APInt SplatValue, SplatUndef; 7373 unsigned SplatBitSize; 7374 bool HasAnyUndefs; 7375 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 7376 HasAnyUndefs, ElemBits) || 7377 SplatBitSize != ElemBits) 7378 return SDValue(); 7379 7380 ShiftAmount = SplatValue.getSExtValue(); 7381 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) { 7382 ShiftAmount = CVN->getSExtValue(); 7383 } else 7384 return SDValue(); 7385 7386 unsigned Opcode; 7387 bool IsRightShift; 7388 switch (IID) { 7389 default: 7390 llvm_unreachable("Unknown shift intrinsic"); 7391 case Intrinsic::aarch64_neon_sqshl: 7392 Opcode = AArch64ISD::SQSHL_I; 7393 IsRightShift = false; 7394 break; 7395 case Intrinsic::aarch64_neon_uqshl: 7396 Opcode = AArch64ISD::UQSHL_I; 7397 IsRightShift = false; 7398 break; 7399 case Intrinsic::aarch64_neon_srshl: 7400 Opcode = AArch64ISD::SRSHR_I; 7401 IsRightShift = true; 7402 break; 7403 case Intrinsic::aarch64_neon_urshl: 7404 Opcode = AArch64ISD::URSHR_I; 7405 IsRightShift = true; 7406 break; 7407 case Intrinsic::aarch64_neon_sqshlu: 7408 Opcode = AArch64ISD::SQSHLU_I; 7409 IsRightShift = false; 7410 break; 7411 } 7412 7413 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) 7414 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1), 7415 DAG.getConstant(-ShiftAmount, MVT::i32)); 7416 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) 7417 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1), 7418 DAG.getConstant(ShiftAmount, MVT::i32)); 7419 7420 return SDValue(); 7421 } 7422 7423 // The CRC32[BH] instructions ignore the high bits of their data operand. Since 7424 // the intrinsics must be legal and take an i32, this means there's almost 7425 // certainly going to be a zext in the DAG which we can eliminate. 7426 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) { 7427 SDValue AndN = N->getOperand(2); 7428 if (AndN.getOpcode() != ISD::AND) 7429 return SDValue(); 7430 7431 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1)); 7432 if (!CMask || CMask->getZExtValue() != Mask) 7433 return SDValue(); 7434 7435 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32, 7436 N->getOperand(0), N->getOperand(1), AndN.getOperand(0)); 7437 } 7438 7439 static SDValue performIntrinsicCombine(SDNode *N, 7440 TargetLowering::DAGCombinerInfo &DCI, 7441 const AArch64Subtarget *Subtarget) { 7442 SelectionDAG &DAG = DCI.DAG; 7443 unsigned IID = getIntrinsicID(N); 7444 switch (IID) { 7445 default: 7446 break; 7447 case Intrinsic::aarch64_neon_vcvtfxs2fp: 7448 case Intrinsic::aarch64_neon_vcvtfxu2fp: 7449 return tryCombineFixedPointConvert(N, DCI, DAG); 7450 break; 7451 case Intrinsic::aarch64_neon_fmax: 7452 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0), 7453 N->getOperand(1), N->getOperand(2)); 7454 case Intrinsic::aarch64_neon_fmin: 7455 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0), 7456 N->getOperand(1), N->getOperand(2)); 7457 case Intrinsic::aarch64_neon_smull: 7458 case Intrinsic::aarch64_neon_umull: 7459 case Intrinsic::aarch64_neon_pmull: 7460 case Intrinsic::aarch64_neon_sqdmull: 7461 return tryCombineLongOpWithDup(IID, N, DCI, DAG); 7462 case Intrinsic::aarch64_neon_sqshl: 7463 case Intrinsic::aarch64_neon_uqshl: 7464 case Intrinsic::aarch64_neon_sqshlu: 7465 case Intrinsic::aarch64_neon_srshl: 7466 case Intrinsic::aarch64_neon_urshl: 7467 return tryCombineShiftImm(IID, N, DAG); 7468 case Intrinsic::aarch64_crc32b: 7469 case Intrinsic::aarch64_crc32cb: 7470 return tryCombineCRC32(0xff, N, DAG); 7471 case Intrinsic::aarch64_crc32h: 7472 case Intrinsic::aarch64_crc32ch: 7473 return tryCombineCRC32(0xffff, N, DAG); 7474 } 7475 return SDValue(); 7476 } 7477 7478 static SDValue performExtendCombine(SDNode *N, 7479 TargetLowering::DAGCombinerInfo &DCI, 7480 SelectionDAG &DAG) { 7481 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then 7482 // we can convert that DUP into another extract_high (of a bigger DUP), which 7483 // helps the backend to decide that an sabdl2 would be useful, saving a real 7484 // extract_high operation. 7485 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND && 7486 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) { 7487 SDNode *ABDNode = N->getOperand(0).getNode(); 7488 unsigned IID = getIntrinsicID(ABDNode); 7489 if (IID == Intrinsic::aarch64_neon_sabd || 7490 IID == Intrinsic::aarch64_neon_uabd) { 7491 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG); 7492 if (!NewABD.getNode()) 7493 return SDValue(); 7494 7495 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), 7496 NewABD); 7497 } 7498 } 7499 7500 // This is effectively a custom type legalization for AArch64. 7501 // 7502 // Type legalization will split an extend of a small, legal, type to a larger 7503 // illegal type by first splitting the destination type, often creating 7504 // illegal source types, which then get legalized in isel-confusing ways, 7505 // leading to really terrible codegen. E.g., 7506 // %result = v8i32 sext v8i8 %value 7507 // becomes 7508 // %losrc = extract_subreg %value, ... 7509 // %hisrc = extract_subreg %value, ... 7510 // %lo = v4i32 sext v4i8 %losrc 7511 // %hi = v4i32 sext v4i8 %hisrc 7512 // Things go rapidly downhill from there. 7513 // 7514 // For AArch64, the [sz]ext vector instructions can only go up one element 7515 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32 7516 // take two instructions. 7517 // 7518 // This implies that the most efficient way to do the extend from v8i8 7519 // to two v4i32 values is to first extend the v8i8 to v8i16, then do 7520 // the normal splitting to happen for the v8i16->v8i32. 7521 7522 // This is pre-legalization to catch some cases where the default 7523 // type legalization will create ill-tempered code. 7524 if (!DCI.isBeforeLegalizeOps()) 7525 return SDValue(); 7526 7527 // We're only interested in cleaning things up for non-legal vector types 7528 // here. If both the source and destination are legal, things will just 7529 // work naturally without any fiddling. 7530 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7531 EVT ResVT = N->getValueType(0); 7532 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) 7533 return SDValue(); 7534 // If the vector type isn't a simple VT, it's beyond the scope of what 7535 // we're worried about here. Let legalization do its thing and hope for 7536 // the best. 7537 SDValue Src = N->getOperand(0); 7538 EVT SrcVT = Src->getValueType(0); 7539 if (!ResVT.isSimple() || !SrcVT.isSimple()) 7540 return SDValue(); 7541 7542 // If the source VT is a 64-bit vector, we can play games and get the 7543 // better results we want. 7544 if (SrcVT.getSizeInBits() != 64) 7545 return SDValue(); 7546 7547 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits(); 7548 unsigned ElementCount = SrcVT.getVectorNumElements(); 7549 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount); 7550 SDLoc DL(N); 7551 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src); 7552 7553 // Now split the rest of the operation into two halves, each with a 64 7554 // bit source. 7555 EVT LoVT, HiVT; 7556 SDValue Lo, Hi; 7557 unsigned NumElements = ResVT.getVectorNumElements(); 7558 assert(!(NumElements & 1) && "Splitting vector, but not in half!"); 7559 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(), 7560 ResVT.getVectorElementType(), NumElements / 2); 7561 7562 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(), 7563 LoVT.getVectorNumElements()); 7564 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src, 7565 DAG.getIntPtrConstant(0)); 7566 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src, 7567 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 7568 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo); 7569 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi); 7570 7571 // Now combine the parts back together so we still have a single result 7572 // like the combiner expects. 7573 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 7574 } 7575 7576 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar 7577 /// value. The load store optimizer pass will merge them to store pair stores. 7578 /// This has better performance than a splat of the scalar followed by a split 7579 /// vector store. Even if the stores are not merged it is four stores vs a dup, 7580 /// followed by an ext.b and two stores. 7581 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) { 7582 SDValue StVal = St->getValue(); 7583 EVT VT = StVal.getValueType(); 7584 7585 // Don't replace floating point stores, they possibly won't be transformed to 7586 // stp because of the store pair suppress pass. 7587 if (VT.isFloatingPoint()) 7588 return SDValue(); 7589 7590 // Check for insert vector elements. 7591 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) 7592 return SDValue(); 7593 7594 // We can express a splat as store pair(s) for 2 or 4 elements. 7595 unsigned NumVecElts = VT.getVectorNumElements(); 7596 if (NumVecElts != 4 && NumVecElts != 2) 7597 return SDValue(); 7598 SDValue SplatVal = StVal.getOperand(1); 7599 unsigned RemainInsertElts = NumVecElts - 1; 7600 7601 // Check that this is a splat. 7602 while (--RemainInsertElts) { 7603 SDValue NextInsertElt = StVal.getOperand(0); 7604 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT) 7605 return SDValue(); 7606 if (NextInsertElt.getOperand(1) != SplatVal) 7607 return SDValue(); 7608 StVal = NextInsertElt; 7609 } 7610 unsigned OrigAlignment = St->getAlignment(); 7611 unsigned EltOffset = NumVecElts == 4 ? 4 : 8; 7612 unsigned Alignment = std::min(OrigAlignment, EltOffset); 7613 7614 // Create scalar stores. This is at least as good as the code sequence for a 7615 // split unaligned store wich is a dup.s, ext.b, and two stores. 7616 // Most of the time the three stores should be replaced by store pair 7617 // instructions (stp). 7618 SDLoc DL(St); 7619 SDValue BasePtr = St->getBasePtr(); 7620 SDValue NewST1 = 7621 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(), 7622 St->isVolatile(), St->isNonTemporal(), St->getAlignment()); 7623 7624 unsigned Offset = EltOffset; 7625 while (--NumVecElts) { 7626 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, 7627 DAG.getConstant(Offset, MVT::i64)); 7628 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr, 7629 St->getPointerInfo(), St->isVolatile(), 7630 St->isNonTemporal(), Alignment); 7631 Offset += EltOffset; 7632 } 7633 return NewST1; 7634 } 7635 7636 static SDValue performSTORECombine(SDNode *N, 7637 TargetLowering::DAGCombinerInfo &DCI, 7638 SelectionDAG &DAG, 7639 const AArch64Subtarget *Subtarget) { 7640 if (!DCI.isBeforeLegalize()) 7641 return SDValue(); 7642 7643 StoreSDNode *S = cast<StoreSDNode>(N); 7644 if (S->isVolatile()) 7645 return SDValue(); 7646 7647 // Cyclone has bad performance on unaligned 16B stores when crossing line and 7648 // page boundries. We want to split such stores. 7649 if (!Subtarget->isCyclone()) 7650 return SDValue(); 7651 7652 // Don't split at Oz. 7653 MachineFunction &MF = DAG.getMachineFunction(); 7654 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute( 7655 AttributeSet::FunctionIndex, Attribute::MinSize); 7656 if (IsMinSize) 7657 return SDValue(); 7658 7659 SDValue StVal = S->getValue(); 7660 EVT VT = StVal.getValueType(); 7661 7662 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting 7663 // those up regresses performance on micro-benchmarks and olden/bh. 7664 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64) 7665 return SDValue(); 7666 7667 // Split unaligned 16B stores. They are terrible for performance. 7668 // Don't split stores with alignment of 1 or 2. Code that uses clang vector 7669 // extensions can use this to mark that it does not want splitting to happen 7670 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of 7671 // eliminating alignment hazards is only 1 in 8 for alignment of 2. 7672 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 || 7673 S->getAlignment() <= 2) 7674 return SDValue(); 7675 7676 // If we get a splat of a scalar convert this vector store to a store of 7677 // scalars. They will be merged into store pairs thereby removing two 7678 // instructions. 7679 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S); 7680 if (ReplacedSplat != SDValue()) 7681 return ReplacedSplat; 7682 7683 SDLoc DL(S); 7684 unsigned NumElts = VT.getVectorNumElements() / 2; 7685 // Split VT into two. 7686 EVT HalfVT = 7687 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts); 7688 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, 7689 DAG.getIntPtrConstant(0)); 7690 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, 7691 DAG.getIntPtrConstant(NumElts)); 7692 SDValue BasePtr = S->getBasePtr(); 7693 SDValue NewST1 = 7694 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(), 7695 S->isVolatile(), S->isNonTemporal(), S->getAlignment()); 7696 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, 7697 DAG.getConstant(8, MVT::i64)); 7698 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr, 7699 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(), 7700 S->getAlignment()); 7701 } 7702 7703 /// Target-specific DAG combine function for post-increment LD1 (lane) and 7704 /// post-increment LD1R. 7705 static SDValue performPostLD1Combine(SDNode *N, 7706 TargetLowering::DAGCombinerInfo &DCI, 7707 bool IsLaneOp) { 7708 if (DCI.isBeforeLegalizeOps()) 7709 return SDValue(); 7710 7711 SelectionDAG &DAG = DCI.DAG; 7712 EVT VT = N->getValueType(0); 7713 7714 unsigned LoadIdx = IsLaneOp ? 1 : 0; 7715 SDNode *LD = N->getOperand(LoadIdx).getNode(); 7716 // If it is not LOAD, can not do such combine. 7717 if (LD->getOpcode() != ISD::LOAD) 7718 return SDValue(); 7719 7720 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD); 7721 EVT MemVT = LoadSDN->getMemoryVT(); 7722 // Check if memory operand is the same type as the vector element. 7723 if (MemVT != VT.getVectorElementType()) 7724 return SDValue(); 7725 7726 // Check if there are other uses. If so, do not combine as it will introduce 7727 // an extra load. 7728 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE; 7729 ++UI) { 7730 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result. 7731 continue; 7732 if (*UI != N) 7733 return SDValue(); 7734 } 7735 7736 SDValue Addr = LD->getOperand(1); 7737 SDValue Vector = N->getOperand(0); 7738 // Search for a use of the address operand that is an increment. 7739 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE = 7740 Addr.getNode()->use_end(); UI != UE; ++UI) { 7741 SDNode *User = *UI; 7742 if (User->getOpcode() != ISD::ADD 7743 || UI.getUse().getResNo() != Addr.getResNo()) 7744 continue; 7745 7746 // Check that the add is independent of the load. Otherwise, folding it 7747 // would create a cycle. 7748 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User)) 7749 continue; 7750 // Also check that add is not used in the vector operand. This would also 7751 // create a cycle. 7752 if (User->isPredecessorOf(Vector.getNode())) 7753 continue; 7754 7755 // If the increment is a constant, it must match the memory ref size. 7756 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7757 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7758 uint32_t IncVal = CInc->getZExtValue(); 7759 unsigned NumBytes = VT.getScalarSizeInBits() / 8; 7760 if (IncVal != NumBytes) 7761 continue; 7762 Inc = DAG.getRegister(AArch64::XZR, MVT::i64); 7763 } 7764 7765 SmallVector<SDValue, 8> Ops; 7766 Ops.push_back(LD->getOperand(0)); // Chain 7767 if (IsLaneOp) { 7768 Ops.push_back(Vector); // The vector to be inserted 7769 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector 7770 } 7771 Ops.push_back(Addr); 7772 Ops.push_back(Inc); 7773 7774 EVT Tys[3] = { VT, MVT::i64, MVT::Other }; 7775 SDVTList SDTys = DAG.getVTList(Tys); 7776 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost; 7777 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops, 7778 MemVT, 7779 LoadSDN->getMemOperand()); 7780 7781 // Update the uses. 7782 std::vector<SDValue> NewResults; 7783 NewResults.push_back(SDValue(LD, 0)); // The result of load 7784 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain 7785 DCI.CombineTo(LD, NewResults); 7786 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result 7787 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register 7788 7789 break; 7790 } 7791 return SDValue(); 7792 } 7793 7794 /// Target-specific DAG combine function for NEON load/store intrinsics 7795 /// to merge base address updates. 7796 static SDValue performNEONPostLDSTCombine(SDNode *N, 7797 TargetLowering::DAGCombinerInfo &DCI, 7798 SelectionDAG &DAG) { 7799 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 7800 return SDValue(); 7801 7802 unsigned AddrOpIdx = N->getNumOperands() - 1; 7803 SDValue Addr = N->getOperand(AddrOpIdx); 7804 7805 // Search for a use of the address operand that is an increment. 7806 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 7807 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 7808 SDNode *User = *UI; 7809 if (User->getOpcode() != ISD::ADD || 7810 UI.getUse().getResNo() != Addr.getResNo()) 7811 continue; 7812 7813 // Check that the add is independent of the load/store. Otherwise, folding 7814 // it would create a cycle. 7815 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 7816 continue; 7817 7818 // Find the new opcode for the updating load/store. 7819 bool IsStore = false; 7820 bool IsLaneOp = false; 7821 bool IsDupOp = false; 7822 unsigned NewOpc = 0; 7823 unsigned NumVecs = 0; 7824 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 7825 switch (IntNo) { 7826 default: llvm_unreachable("unexpected intrinsic for Neon base update"); 7827 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post; 7828 NumVecs = 2; break; 7829 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post; 7830 NumVecs = 3; break; 7831 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post; 7832 NumVecs = 4; break; 7833 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post; 7834 NumVecs = 2; IsStore = true; break; 7835 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post; 7836 NumVecs = 3; IsStore = true; break; 7837 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post; 7838 NumVecs = 4; IsStore = true; break; 7839 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post; 7840 NumVecs = 2; break; 7841 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post; 7842 NumVecs = 3; break; 7843 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post; 7844 NumVecs = 4; break; 7845 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post; 7846 NumVecs = 2; IsStore = true; break; 7847 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post; 7848 NumVecs = 3; IsStore = true; break; 7849 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post; 7850 NumVecs = 4; IsStore = true; break; 7851 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost; 7852 NumVecs = 2; IsDupOp = true; break; 7853 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost; 7854 NumVecs = 3; IsDupOp = true; break; 7855 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost; 7856 NumVecs = 4; IsDupOp = true; break; 7857 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost; 7858 NumVecs = 2; IsLaneOp = true; break; 7859 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost; 7860 NumVecs = 3; IsLaneOp = true; break; 7861 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost; 7862 NumVecs = 4; IsLaneOp = true; break; 7863 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost; 7864 NumVecs = 2; IsStore = true; IsLaneOp = true; break; 7865 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost; 7866 NumVecs = 3; IsStore = true; IsLaneOp = true; break; 7867 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost; 7868 NumVecs = 4; IsStore = true; IsLaneOp = true; break; 7869 } 7870 7871 EVT VecTy; 7872 if (IsStore) 7873 VecTy = N->getOperand(2).getValueType(); 7874 else 7875 VecTy = N->getValueType(0); 7876 7877 // If the increment is a constant, it must match the memory ref size. 7878 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7879 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7880 uint32_t IncVal = CInc->getZExtValue(); 7881 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 7882 if (IsLaneOp || IsDupOp) 7883 NumBytes /= VecTy.getVectorNumElements(); 7884 if (IncVal != NumBytes) 7885 continue; 7886 Inc = DAG.getRegister(AArch64::XZR, MVT::i64); 7887 } 7888 SmallVector<SDValue, 8> Ops; 7889 Ops.push_back(N->getOperand(0)); // Incoming chain 7890 // Load lane and store have vector list as input. 7891 if (IsLaneOp || IsStore) 7892 for (unsigned i = 2; i < AddrOpIdx; ++i) 7893 Ops.push_back(N->getOperand(i)); 7894 Ops.push_back(Addr); // Base register 7895 Ops.push_back(Inc); 7896 7897 // Return Types. 7898 EVT Tys[6]; 7899 unsigned NumResultVecs = (IsStore ? 0 : NumVecs); 7900 unsigned n; 7901 for (n = 0; n < NumResultVecs; ++n) 7902 Tys[n] = VecTy; 7903 Tys[n++] = MVT::i64; // Type of write back register 7904 Tys[n] = MVT::Other; // Type of the chain 7905 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2)); 7906 7907 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 7908 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops, 7909 MemInt->getMemoryVT(), 7910 MemInt->getMemOperand()); 7911 7912 // Update the uses. 7913 std::vector<SDValue> NewResults; 7914 for (unsigned i = 0; i < NumResultVecs; ++i) { 7915 NewResults.push_back(SDValue(UpdN.getNode(), i)); 7916 } 7917 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1)); 7918 DCI.CombineTo(N, NewResults); 7919 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 7920 7921 break; 7922 } 7923 return SDValue(); 7924 } 7925 7926 // Checks to see if the value is the prescribed width and returns information 7927 // about its extension mode. 7928 static 7929 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) { 7930 ExtType = ISD::NON_EXTLOAD; 7931 switch(V.getNode()->getOpcode()) { 7932 default: 7933 return false; 7934 case ISD::LOAD: { 7935 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode()); 7936 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8) 7937 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) { 7938 ExtType = LoadNode->getExtensionType(); 7939 return true; 7940 } 7941 return false; 7942 } 7943 case ISD::AssertSext: { 7944 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1)); 7945 if ((TypeNode->getVT() == MVT::i8 && width == 8) 7946 || (TypeNode->getVT() == MVT::i16 && width == 16)) { 7947 ExtType = ISD::SEXTLOAD; 7948 return true; 7949 } 7950 return false; 7951 } 7952 case ISD::AssertZext: { 7953 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1)); 7954 if ((TypeNode->getVT() == MVT::i8 && width == 8) 7955 || (TypeNode->getVT() == MVT::i16 && width == 16)) { 7956 ExtType = ISD::ZEXTLOAD; 7957 return true; 7958 } 7959 return false; 7960 } 7961 case ISD::Constant: 7962 case ISD::TargetConstant: { 7963 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) < 7964 1LL << (width - 1)) 7965 return true; 7966 return false; 7967 } 7968 } 7969 7970 return true; 7971 } 7972 7973 // This function does a whole lot of voodoo to determine if the tests are 7974 // equivalent without and with a mask. Essentially what happens is that given a 7975 // DAG resembling: 7976 // 7977 // +-------------+ +-------------+ +-------------+ +-------------+ 7978 // | Input | | AddConstant | | CompConstant| | CC | 7979 // +-------------+ +-------------+ +-------------+ +-------------+ 7980 // | | | | 7981 // V V | +----------+ 7982 // +-------------+ +----+ | | 7983 // | ADD | |0xff| | | 7984 // +-------------+ +----+ | | 7985 // | | | | 7986 // V V | | 7987 // +-------------+ | | 7988 // | AND | | | 7989 // +-------------+ | | 7990 // | | | 7991 // +-----+ | | 7992 // | | | 7993 // V V V 7994 // +-------------+ 7995 // | CMP | 7996 // +-------------+ 7997 // 7998 // The AND node may be safely removed for some combinations of inputs. In 7999 // particular we need to take into account the extension type of the Input, 8000 // the exact values of AddConstant, CompConstant, and CC, along with the nominal 8001 // width of the input (this can work for any width inputs, the above graph is 8002 // specific to 8 bits. 8003 // 8004 // The specific equations were worked out by generating output tables for each 8005 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The 8006 // problem was simplified by working with 4 bit inputs, which means we only 8007 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero 8008 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8 8009 // patterns present in both extensions (0,7). For every distinct set of 8010 // AddConstant and CompConstants bit patterns we can consider the masked and 8011 // unmasked versions to be equivalent if the result of this function is true for 8012 // all 16 distinct bit patterns of for the current extension type of Input (w0). 8013 // 8014 // sub w8, w0, w1 8015 // and w10, w8, #0x0f 8016 // cmp w8, w2 8017 // cset w9, AArch64CC 8018 // cmp w10, w2 8019 // cset w11, AArch64CC 8020 // cmp w9, w11 8021 // cset w0, eq 8022 // ret 8023 // 8024 // Since the above function shows when the outputs are equivalent it defines 8025 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and 8026 // would be expensive to run during compiles. The equations below were written 8027 // in a test harness that confirmed they gave equivalent outputs to the above 8028 // for all inputs function, so they can be used determine if the removal is 8029 // legal instead. 8030 // 8031 // isEquivalentMaskless() is the code for testing if the AND can be removed 8032 // factored out of the DAG recognition as the DAG can take several forms. 8033 8034 static 8035 bool isEquivalentMaskless(unsigned CC, unsigned width, 8036 ISD::LoadExtType ExtType, signed AddConstant, 8037 signed CompConstant) { 8038 // By being careful about our equations and only writing the in term 8039 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can 8040 // make them generally applicable to all bit widths. 8041 signed MaxUInt = (1 << width); 8042 8043 // For the purposes of these comparisons sign extending the type is 8044 // equivalent to zero extending the add and displacing it by half the integer 8045 // width. Provided we are careful and make sure our equations are valid over 8046 // the whole range we can just adjust the input and avoid writing equations 8047 // for sign extended inputs. 8048 if (ExtType == ISD::SEXTLOAD) 8049 AddConstant -= (1 << (width-1)); 8050 8051 switch(CC) { 8052 case AArch64CC::LE: 8053 case AArch64CC::GT: { 8054 if ((AddConstant == 0) || 8055 (CompConstant == MaxUInt - 1 && AddConstant < 0) || 8056 (AddConstant >= 0 && CompConstant < 0) || 8057 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant)) 8058 return true; 8059 } break; 8060 case AArch64CC::LT: 8061 case AArch64CC::GE: { 8062 if ((AddConstant == 0) || 8063 (AddConstant >= 0 && CompConstant <= 0) || 8064 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant)) 8065 return true; 8066 } break; 8067 case AArch64CC::HI: 8068 case AArch64CC::LS: { 8069 if ((AddConstant >= 0 && CompConstant < 0) || 8070 (AddConstant <= 0 && CompConstant >= -1 && 8071 CompConstant < AddConstant + MaxUInt)) 8072 return true; 8073 } break; 8074 case AArch64CC::PL: 8075 case AArch64CC::MI: { 8076 if ((AddConstant == 0) || 8077 (AddConstant > 0 && CompConstant <= 0) || 8078 (AddConstant < 0 && CompConstant <= AddConstant)) 8079 return true; 8080 } break; 8081 case AArch64CC::LO: 8082 case AArch64CC::HS: { 8083 if ((AddConstant >= 0 && CompConstant <= 0) || 8084 (AddConstant <= 0 && CompConstant >= 0 && 8085 CompConstant <= AddConstant + MaxUInt)) 8086 return true; 8087 } break; 8088 case AArch64CC::EQ: 8089 case AArch64CC::NE: { 8090 if ((AddConstant > 0 && CompConstant < 0) || 8091 (AddConstant < 0 && CompConstant >= 0 && 8092 CompConstant < AddConstant + MaxUInt) || 8093 (AddConstant >= 0 && CompConstant >= 0 && 8094 CompConstant >= AddConstant) || 8095 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant)) 8096 8097 return true; 8098 } break; 8099 case AArch64CC::VS: 8100 case AArch64CC::VC: 8101 case AArch64CC::AL: 8102 case AArch64CC::NV: 8103 return true; 8104 case AArch64CC::Invalid: 8105 break; 8106 } 8107 8108 return false; 8109 } 8110 8111 static 8112 SDValue performCONDCombine(SDNode *N, 8113 TargetLowering::DAGCombinerInfo &DCI, 8114 SelectionDAG &DAG, unsigned CCIndex, 8115 unsigned CmpIndex) { 8116 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue(); 8117 SDNode *SubsNode = N->getOperand(CmpIndex).getNode(); 8118 unsigned CondOpcode = SubsNode->getOpcode(); 8119 8120 if (CondOpcode != AArch64ISD::SUBS) 8121 return SDValue(); 8122 8123 // There is a SUBS feeding this condition. Is it fed by a mask we can 8124 // use? 8125 8126 SDNode *AndNode = SubsNode->getOperand(0).getNode(); 8127 unsigned MaskBits = 0; 8128 8129 if (AndNode->getOpcode() != ISD::AND) 8130 return SDValue(); 8131 8132 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) { 8133 uint32_t CNV = CN->getZExtValue(); 8134 if (CNV == 255) 8135 MaskBits = 8; 8136 else if (CNV == 65535) 8137 MaskBits = 16; 8138 } 8139 8140 if (!MaskBits) 8141 return SDValue(); 8142 8143 SDValue AddValue = AndNode->getOperand(0); 8144 8145 if (AddValue.getOpcode() != ISD::ADD) 8146 return SDValue(); 8147 8148 // The basic dag structure is correct, grab the inputs and validate them. 8149 8150 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0); 8151 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1); 8152 SDValue SubsInputValue = SubsNode->getOperand(1); 8153 8154 // The mask is present and the provenance of all the values is a smaller type, 8155 // lets see if the mask is superfluous. 8156 8157 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) || 8158 !isa<ConstantSDNode>(SubsInputValue.getNode())) 8159 return SDValue(); 8160 8161 ISD::LoadExtType ExtType; 8162 8163 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) || 8164 !checkValueWidth(AddInputValue2, MaskBits, ExtType) || 8165 !checkValueWidth(AddInputValue1, MaskBits, ExtType) ) 8166 return SDValue(); 8167 8168 if(!isEquivalentMaskless(CC, MaskBits, ExtType, 8169 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(), 8170 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue())) 8171 return SDValue(); 8172 8173 // The AND is not necessary, remove it. 8174 8175 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0), 8176 SubsNode->getValueType(1)); 8177 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) }; 8178 8179 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops); 8180 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode()); 8181 8182 return SDValue(N, 0); 8183 } 8184 8185 // Optimize compare with zero and branch. 8186 static SDValue performBRCONDCombine(SDNode *N, 8187 TargetLowering::DAGCombinerInfo &DCI, 8188 SelectionDAG &DAG) { 8189 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3); 8190 if (NV.getNode()) 8191 N = NV.getNode(); 8192 SDValue Chain = N->getOperand(0); 8193 SDValue Dest = N->getOperand(1); 8194 SDValue CCVal = N->getOperand(2); 8195 SDValue Cmp = N->getOperand(3); 8196 8197 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!"); 8198 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue(); 8199 if (CC != AArch64CC::EQ && CC != AArch64CC::NE) 8200 return SDValue(); 8201 8202 unsigned CmpOpc = Cmp.getOpcode(); 8203 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS) 8204 return SDValue(); 8205 8206 // Only attempt folding if there is only one use of the flag and no use of the 8207 // value. 8208 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1)) 8209 return SDValue(); 8210 8211 SDValue LHS = Cmp.getOperand(0); 8212 SDValue RHS = Cmp.getOperand(1); 8213 8214 assert(LHS.getValueType() == RHS.getValueType() && 8215 "Expected the value type to be the same for both operands!"); 8216 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64) 8217 return SDValue(); 8218 8219 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue()) 8220 std::swap(LHS, RHS); 8221 8222 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue()) 8223 return SDValue(); 8224 8225 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA || 8226 LHS.getOpcode() == ISD::SRL) 8227 return SDValue(); 8228 8229 // Fold the compare into the branch instruction. 8230 SDValue BR; 8231 if (CC == AArch64CC::EQ) 8232 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); 8233 else 8234 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); 8235 8236 // Do not add new nodes to DAG combiner worklist. 8237 DCI.CombineTo(N, BR, false); 8238 8239 return SDValue(); 8240 } 8241 8242 // vselect (v1i1 setcc) -> 8243 // vselect (v1iXX setcc) (XX is the size of the compared operand type) 8244 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as 8245 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine 8246 // such VSELECT. 8247 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) { 8248 SDValue N0 = N->getOperand(0); 8249 EVT CCVT = N0.getValueType(); 8250 8251 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 || 8252 CCVT.getVectorElementType() != MVT::i1) 8253 return SDValue(); 8254 8255 EVT ResVT = N->getValueType(0); 8256 EVT CmpVT = N0.getOperand(0).getValueType(); 8257 // Only combine when the result type is of the same size as the compared 8258 // operands. 8259 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) 8260 return SDValue(); 8261 8262 SDValue IfTrue = N->getOperand(1); 8263 SDValue IfFalse = N->getOperand(2); 8264 SDValue SetCC = 8265 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(), 8266 N0.getOperand(0), N0.getOperand(1), 8267 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8268 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, 8269 IfTrue, IfFalse); 8270 } 8271 8272 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with 8273 /// the compare-mask instructions rather than going via NZCV, even if LHS and 8274 /// RHS are really scalar. This replaces any scalar setcc in the above pattern 8275 /// with a vector one followed by a DUP shuffle on the result. 8276 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) { 8277 SDValue N0 = N->getOperand(0); 8278 EVT ResVT = N->getValueType(0); 8279 8280 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1) 8281 return SDValue(); 8282 8283 // If NumMaskElts == 0, the comparison is larger than select result. The 8284 // largest real NEON comparison is 64-bits per lane, which means the result is 8285 // at most 32-bits and an illegal vector. Just bail out for now. 8286 EVT SrcVT = N0.getOperand(0).getValueType(); 8287 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits(); 8288 if (!ResVT.isVector() || NumMaskElts == 0) 8289 return SDValue(); 8290 8291 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts); 8292 EVT CCVT = SrcVT.changeVectorElementTypeToInteger(); 8293 8294 // First perform a vector comparison, where lane 0 is the one we're interested 8295 // in. 8296 SDLoc DL(N0); 8297 SDValue LHS = 8298 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0)); 8299 SDValue RHS = 8300 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1)); 8301 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); 8302 8303 // Now duplicate the comparison mask we want across all other lanes. 8304 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0); 8305 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data()); 8306 Mask = DAG.getNode(ISD::BITCAST, DL, 8307 ResVT.changeVectorElementTypeToInteger(), Mask); 8308 8309 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2)); 8310 } 8311 8312 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, 8313 DAGCombinerInfo &DCI) const { 8314 SelectionDAG &DAG = DCI.DAG; 8315 switch (N->getOpcode()) { 8316 default: 8317 break; 8318 case ISD::ADD: 8319 case ISD::SUB: 8320 return performAddSubLongCombine(N, DCI, DAG); 8321 case ISD::XOR: 8322 return performXorCombine(N, DAG, DCI, Subtarget); 8323 case ISD::MUL: 8324 return performMulCombine(N, DAG, DCI, Subtarget); 8325 case ISD::SINT_TO_FP: 8326 case ISD::UINT_TO_FP: 8327 return performIntToFpCombine(N, DAG); 8328 case ISD::OR: 8329 return performORCombine(N, DCI, Subtarget); 8330 case ISD::INTRINSIC_WO_CHAIN: 8331 return performIntrinsicCombine(N, DCI, Subtarget); 8332 case ISD::ANY_EXTEND: 8333 case ISD::ZERO_EXTEND: 8334 case ISD::SIGN_EXTEND: 8335 return performExtendCombine(N, DCI, DAG); 8336 case ISD::BITCAST: 8337 return performBitcastCombine(N, DCI, DAG); 8338 case ISD::CONCAT_VECTORS: 8339 return performConcatVectorsCombine(N, DCI, DAG); 8340 case ISD::SELECT: 8341 return performSelectCombine(N, DAG); 8342 case ISD::VSELECT: 8343 return performVSelectCombine(N, DCI.DAG); 8344 case ISD::STORE: 8345 return performSTORECombine(N, DCI, DAG, Subtarget); 8346 case AArch64ISD::BRCOND: 8347 return performBRCONDCombine(N, DCI, DAG); 8348 case AArch64ISD::CSEL: 8349 return performCONDCombine(N, DCI, DAG, 2, 3); 8350 case AArch64ISD::DUP: 8351 return performPostLD1Combine(N, DCI, false); 8352 case ISD::INSERT_VECTOR_ELT: 8353 return performPostLD1Combine(N, DCI, true); 8354 case ISD::INTRINSIC_VOID: 8355 case ISD::INTRINSIC_W_CHAIN: 8356 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 8357 case Intrinsic::aarch64_neon_ld2: 8358 case Intrinsic::aarch64_neon_ld3: 8359 case Intrinsic::aarch64_neon_ld4: 8360 case Intrinsic::aarch64_neon_ld1x2: 8361 case Intrinsic::aarch64_neon_ld1x3: 8362 case Intrinsic::aarch64_neon_ld1x4: 8363 case Intrinsic::aarch64_neon_ld2lane: 8364 case Intrinsic::aarch64_neon_ld3lane: 8365 case Intrinsic::aarch64_neon_ld4lane: 8366 case Intrinsic::aarch64_neon_ld2r: 8367 case Intrinsic::aarch64_neon_ld3r: 8368 case Intrinsic::aarch64_neon_ld4r: 8369 case Intrinsic::aarch64_neon_st2: 8370 case Intrinsic::aarch64_neon_st3: 8371 case Intrinsic::aarch64_neon_st4: 8372 case Intrinsic::aarch64_neon_st1x2: 8373 case Intrinsic::aarch64_neon_st1x3: 8374 case Intrinsic::aarch64_neon_st1x4: 8375 case Intrinsic::aarch64_neon_st2lane: 8376 case Intrinsic::aarch64_neon_st3lane: 8377 case Intrinsic::aarch64_neon_st4lane: 8378 return performNEONPostLDSTCombine(N, DCI, DAG); 8379 default: 8380 break; 8381 } 8382 } 8383 return SDValue(); 8384 } 8385 8386 // Check if the return value is used as only a return value, as otherwise 8387 // we can't perform a tail-call. In particular, we need to check for 8388 // target ISD nodes that are returns and any other "odd" constructs 8389 // that the generic analysis code won't necessarily catch. 8390 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N, 8391 SDValue &Chain) const { 8392 if (N->getNumValues() != 1) 8393 return false; 8394 if (!N->hasNUsesOfValue(1, 0)) 8395 return false; 8396 8397 SDValue TCChain = Chain; 8398 SDNode *Copy = *N->use_begin(); 8399 if (Copy->getOpcode() == ISD::CopyToReg) { 8400 // If the copy has a glue operand, we conservatively assume it isn't safe to 8401 // perform a tail call. 8402 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() == 8403 MVT::Glue) 8404 return false; 8405 TCChain = Copy->getOperand(0); 8406 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 8407 return false; 8408 8409 bool HasRet = false; 8410 for (SDNode *Node : Copy->uses()) { 8411 if (Node->getOpcode() != AArch64ISD::RET_FLAG) 8412 return false; 8413 HasRet = true; 8414 } 8415 8416 if (!HasRet) 8417 return false; 8418 8419 Chain = TCChain; 8420 return true; 8421 } 8422 8423 // Return whether the an instruction can potentially be optimized to a tail 8424 // call. This will cause the optimizers to attempt to move, or duplicate, 8425 // return instructions to help enable tail call optimizations for this 8426 // instruction. 8427 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 8428 if (!CI->isTailCall()) 8429 return false; 8430 8431 return true; 8432 } 8433 8434 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base, 8435 SDValue &Offset, 8436 ISD::MemIndexedMode &AM, 8437 bool &IsInc, 8438 SelectionDAG &DAG) const { 8439 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) 8440 return false; 8441 8442 Base = Op->getOperand(0); 8443 // All of the indexed addressing mode instructions take a signed 8444 // 9 bit immediate offset. 8445 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 8446 int64_t RHSC = (int64_t)RHS->getZExtValue(); 8447 if (RHSC >= 256 || RHSC <= -256) 8448 return false; 8449 IsInc = (Op->getOpcode() == ISD::ADD); 8450 Offset = Op->getOperand(1); 8451 return true; 8452 } 8453 return false; 8454 } 8455 8456 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 8457 SDValue &Offset, 8458 ISD::MemIndexedMode &AM, 8459 SelectionDAG &DAG) const { 8460 EVT VT; 8461 SDValue Ptr; 8462 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8463 VT = LD->getMemoryVT(); 8464 Ptr = LD->getBasePtr(); 8465 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8466 VT = ST->getMemoryVT(); 8467 Ptr = ST->getBasePtr(); 8468 } else 8469 return false; 8470 8471 bool IsInc; 8472 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG)) 8473 return false; 8474 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC; 8475 return true; 8476 } 8477 8478 bool AArch64TargetLowering::getPostIndexedAddressParts( 8479 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, 8480 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const { 8481 EVT VT; 8482 SDValue Ptr; 8483 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8484 VT = LD->getMemoryVT(); 8485 Ptr = LD->getBasePtr(); 8486 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8487 VT = ST->getMemoryVT(); 8488 Ptr = ST->getBasePtr(); 8489 } else 8490 return false; 8491 8492 bool IsInc; 8493 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG)) 8494 return false; 8495 // Post-indexing updates the base, so it's not a valid transform 8496 // if that's not the same as the load's pointer. 8497 if (Ptr != Base) 8498 return false; 8499 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC; 8500 return true; 8501 } 8502 8503 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 8504 SelectionDAG &DAG) { 8505 if (N->getValueType(0) != MVT::i16) 8506 return; 8507 8508 SDLoc DL(N); 8509 SDValue Op = N->getOperand(0); 8510 assert(Op.getValueType() == MVT::f16 && 8511 "Inconsistent bitcast? Only 16-bit types should be i16 or f16"); 8512 Op = SDValue( 8513 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32, 8514 DAG.getUNDEF(MVT::i32), Op, 8515 DAG.getTargetConstant(AArch64::hsub, MVT::i32)), 8516 0); 8517 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op); 8518 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op)); 8519 } 8520 8521 void AArch64TargetLowering::ReplaceNodeResults( 8522 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const { 8523 switch (N->getOpcode()) { 8524 default: 8525 llvm_unreachable("Don't know how to custom expand this"); 8526 case ISD::BITCAST: 8527 ReplaceBITCASTResults(N, Results, DAG); 8528 return; 8529 case ISD::FP_TO_UINT: 8530 case ISD::FP_TO_SINT: 8531 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion"); 8532 // Let normal code take care of it by not adding anything to Results. 8533 return; 8534 } 8535 } 8536 8537 bool AArch64TargetLowering::useLoadStackGuardNode() const { 8538 return true; 8539 } 8540 8541 TargetLoweringBase::LegalizeTypeAction 8542 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const { 8543 MVT SVT = VT.getSimpleVT(); 8544 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8, 8545 // v4i16, v2i32 instead of to promote. 8546 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 8547 || SVT == MVT::v1f32) 8548 return TypeWidenVector; 8549 8550 return TargetLoweringBase::getPreferredVectorAction(VT); 8551 } 8552 8553 // Loads and stores less than 128-bits are already atomic; ones above that 8554 // are doomed anyway, so defer to the default libcall and blame the OS when 8555 // things go wrong. 8556 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { 8557 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits(); 8558 return Size == 128; 8559 } 8560 8561 // Loads and stores less than 128-bits are already atomic; ones above that 8562 // are doomed anyway, so defer to the default libcall and blame the OS when 8563 // things go wrong. 8564 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const { 8565 unsigned Size = LI->getType()->getPrimitiveSizeInBits(); 8566 return Size == 128; 8567 } 8568 8569 // For the real atomic operations, we have ldxr/stxr up to 128 bits, 8570 bool AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { 8571 unsigned Size = AI->getType()->getPrimitiveSizeInBits(); 8572 return Size <= 128; 8573 } 8574 8575 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const { 8576 return true; 8577 } 8578 8579 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 8580 AtomicOrdering Ord) const { 8581 Module *M = Builder.GetInsertBlock()->getParent()->getParent(); 8582 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType(); 8583 bool IsAcquire = isAtLeastAcquire(Ord); 8584 8585 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd 8586 // intrinsic must return {i64, i64} and we have to recombine them into a 8587 // single i128 here. 8588 if (ValTy->getPrimitiveSizeInBits() == 128) { 8589 Intrinsic::ID Int = 8590 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp; 8591 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int); 8592 8593 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext())); 8594 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi"); 8595 8596 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo"); 8597 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi"); 8598 Lo = Builder.CreateZExt(Lo, ValTy, "lo64"); 8599 Hi = Builder.CreateZExt(Hi, ValTy, "hi64"); 8600 return Builder.CreateOr( 8601 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64"); 8602 } 8603 8604 Type *Tys[] = { Addr->getType() }; 8605 Intrinsic::ID Int = 8606 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr; 8607 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys); 8608 8609 return Builder.CreateTruncOrBitCast( 8610 Builder.CreateCall(Ldxr, Addr), 8611 cast<PointerType>(Addr->getType())->getElementType()); 8612 } 8613 8614 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder, 8615 Value *Val, Value *Addr, 8616 AtomicOrdering Ord) const { 8617 Module *M = Builder.GetInsertBlock()->getParent()->getParent(); 8618 bool IsRelease = isAtLeastRelease(Ord); 8619 8620 // Since the intrinsics must have legal type, the i128 intrinsics take two 8621 // parameters: "i64, i64". We must marshal Val into the appropriate form 8622 // before the call. 8623 if (Val->getType()->getPrimitiveSizeInBits() == 128) { 8624 Intrinsic::ID Int = 8625 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp; 8626 Function *Stxr = Intrinsic::getDeclaration(M, Int); 8627 Type *Int64Ty = Type::getInt64Ty(M->getContext()); 8628 8629 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo"); 8630 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi"); 8631 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext())); 8632 return Builder.CreateCall3(Stxr, Lo, Hi, Addr); 8633 } 8634 8635 Intrinsic::ID Int = 8636 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr; 8637 Type *Tys[] = { Addr->getType() }; 8638 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys); 8639 8640 return Builder.CreateCall2( 8641 Stxr, Builder.CreateZExtOrBitCast( 8642 Val, Stxr->getFunctionType()->getParamType(0)), 8643 Addr); 8644 } 8645