1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation  ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64TargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64ISelLowering.h"
14 #include "AArch64CallingConvention.h"
15 #include "AArch64ExpandImm.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64RegisterInfo.h"
19 #include "AArch64Subtarget.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/APInt.h"
24 #include "llvm/ADT/ArrayRef.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/ADT/Twine.h"
32 #include "llvm/Analysis/ObjCARCUtil.h"
33 #include "llvm/Analysis/VectorUtils.h"
34 #include "llvm/CodeGen/Analysis.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstr.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineMemOperand.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/RuntimeLibcalls.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/CodeGen/SelectionDAGNodes.h"
46 #include "llvm/CodeGen/TargetCallingConv.h"
47 #include "llvm/CodeGen/TargetInstrInfo.h"
48 #include "llvm/CodeGen/ValueTypes.h"
49 #include "llvm/IR/Attributes.h"
50 #include "llvm/IR/Constants.h"
51 #include "llvm/IR/DataLayout.h"
52 #include "llvm/IR/DebugLoc.h"
53 #include "llvm/IR/DerivedTypes.h"
54 #include "llvm/IR/Function.h"
55 #include "llvm/IR/GetElementPtrTypeIterator.h"
56 #include "llvm/IR/GlobalValue.h"
57 #include "llvm/IR/IRBuilder.h"
58 #include "llvm/IR/Instruction.h"
59 #include "llvm/IR/Instructions.h"
60 #include "llvm/IR/IntrinsicInst.h"
61 #include "llvm/IR/Intrinsics.h"
62 #include "llvm/IR/IntrinsicsAArch64.h"
63 #include "llvm/IR/Module.h"
64 #include "llvm/IR/OperandTraits.h"
65 #include "llvm/IR/PatternMatch.h"
66 #include "llvm/IR/Type.h"
67 #include "llvm/IR/Use.h"
68 #include "llvm/IR/Value.h"
69 #include "llvm/MC/MCRegisterInfo.h"
70 #include "llvm/Support/Casting.h"
71 #include "llvm/Support/CodeGen.h"
72 #include "llvm/Support/CommandLine.h"
73 #include "llvm/Support/Compiler.h"
74 #include "llvm/Support/Debug.h"
75 #include "llvm/Support/ErrorHandling.h"
76 #include "llvm/Support/KnownBits.h"
77 #include "llvm/Support/MachineValueType.h"
78 #include "llvm/Support/MathExtras.h"
79 #include "llvm/Support/raw_ostream.h"
80 #include "llvm/Target/TargetMachine.h"
81 #include "llvm/Target/TargetOptions.h"
82 #include <algorithm>
83 #include <bitset>
84 #include <cassert>
85 #include <cctype>
86 #include <cstdint>
87 #include <cstdlib>
88 #include <iterator>
89 #include <limits>
90 #include <tuple>
91 #include <utility>
92 #include <vector>
93 
94 using namespace llvm;
95 using namespace llvm::PatternMatch;
96 
97 #define DEBUG_TYPE "aarch64-lower"
98 
99 STATISTIC(NumTailCalls, "Number of tail calls");
100 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
101 STATISTIC(NumOptimizedImms, "Number of times immediates were optimized");
102 
103 // FIXME: The necessary dtprel relocations don't seem to be supported
104 // well in the GNU bfd and gold linkers at the moment. Therefore, by
105 // default, for now, fall back to GeneralDynamic code generation.
106 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
107     "aarch64-elf-ldtls-generation", cl::Hidden,
108     cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
109     cl::init(false));
110 
111 static cl::opt<bool>
112 EnableOptimizeLogicalImm("aarch64-enable-logical-imm", cl::Hidden,
113                          cl::desc("Enable AArch64 logical imm instruction "
114                                   "optimization"),
115                          cl::init(true));
116 
117 // Temporary option added for the purpose of testing functionality added
118 // to DAGCombiner.cpp in D92230. It is expected that this can be removed
119 // in future when both implementations will be based off MGATHER rather
120 // than the GLD1 nodes added for the SVE gather load intrinsics.
121 static cl::opt<bool>
122 EnableCombineMGatherIntrinsics("aarch64-enable-mgather-combine", cl::Hidden,
123                                 cl::desc("Combine extends of AArch64 masked "
124                                          "gather intrinsics"),
125                                 cl::init(true));
126 
127 /// Value type used for condition codes.
128 static const MVT MVT_CC = MVT::i32;
129 
130 static inline EVT getPackedSVEVectorVT(EVT VT) {
131   switch (VT.getSimpleVT().SimpleTy) {
132   default:
133     llvm_unreachable("unexpected element type for vector");
134   case MVT::i8:
135     return MVT::nxv16i8;
136   case MVT::i16:
137     return MVT::nxv8i16;
138   case MVT::i32:
139     return MVT::nxv4i32;
140   case MVT::i64:
141     return MVT::nxv2i64;
142   case MVT::f16:
143     return MVT::nxv8f16;
144   case MVT::f32:
145     return MVT::nxv4f32;
146   case MVT::f64:
147     return MVT::nxv2f64;
148   case MVT::bf16:
149     return MVT::nxv8bf16;
150   }
151 }
152 
153 // NOTE: Currently there's only a need to return integer vector types. If this
154 // changes then just add an extra "type" parameter.
155 static inline EVT getPackedSVEVectorVT(ElementCount EC) {
156   switch (EC.getKnownMinValue()) {
157   default:
158     llvm_unreachable("unexpected element count for vector");
159   case 16:
160     return MVT::nxv16i8;
161   case 8:
162     return MVT::nxv8i16;
163   case 4:
164     return MVT::nxv4i32;
165   case 2:
166     return MVT::nxv2i64;
167   }
168 }
169 
170 static inline EVT getPromotedVTForPredicate(EVT VT) {
171   assert(VT.isScalableVector() && (VT.getVectorElementType() == MVT::i1) &&
172          "Expected scalable predicate vector type!");
173   switch (VT.getVectorMinNumElements()) {
174   default:
175     llvm_unreachable("unexpected element count for vector");
176   case 2:
177     return MVT::nxv2i64;
178   case 4:
179     return MVT::nxv4i32;
180   case 8:
181     return MVT::nxv8i16;
182   case 16:
183     return MVT::nxv16i8;
184   }
185 }
186 
187 /// Returns true if VT's elements occupy the lowest bit positions of its
188 /// associated register class without any intervening space.
189 ///
190 /// For example, nxv2f16, nxv4f16 and nxv8f16 are legal types that belong to the
191 /// same register class, but only nxv8f16 can be treated as a packed vector.
192 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) {
193   assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
194          "Expected legal vector type!");
195   return VT.isFixedLengthVector() ||
196          VT.getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock;
197 }
198 
199 // Returns true for ####_MERGE_PASSTHRU opcodes, whose operands have a leading
200 // predicate and end with a passthru value matching the result type.
201 static bool isMergePassthruOpcode(unsigned Opc) {
202   switch (Opc) {
203   default:
204     return false;
205   case AArch64ISD::BITREVERSE_MERGE_PASSTHRU:
206   case AArch64ISD::BSWAP_MERGE_PASSTHRU:
207   case AArch64ISD::CTLZ_MERGE_PASSTHRU:
208   case AArch64ISD::CTPOP_MERGE_PASSTHRU:
209   case AArch64ISD::DUP_MERGE_PASSTHRU:
210   case AArch64ISD::ABS_MERGE_PASSTHRU:
211   case AArch64ISD::NEG_MERGE_PASSTHRU:
212   case AArch64ISD::FNEG_MERGE_PASSTHRU:
213   case AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU:
214   case AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU:
215   case AArch64ISD::FCEIL_MERGE_PASSTHRU:
216   case AArch64ISD::FFLOOR_MERGE_PASSTHRU:
217   case AArch64ISD::FNEARBYINT_MERGE_PASSTHRU:
218   case AArch64ISD::FRINT_MERGE_PASSTHRU:
219   case AArch64ISD::FROUND_MERGE_PASSTHRU:
220   case AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU:
221   case AArch64ISD::FTRUNC_MERGE_PASSTHRU:
222   case AArch64ISD::FP_ROUND_MERGE_PASSTHRU:
223   case AArch64ISD::FP_EXTEND_MERGE_PASSTHRU:
224   case AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU:
225   case AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU:
226   case AArch64ISD::FCVTZU_MERGE_PASSTHRU:
227   case AArch64ISD::FCVTZS_MERGE_PASSTHRU:
228   case AArch64ISD::FSQRT_MERGE_PASSTHRU:
229   case AArch64ISD::FRECPX_MERGE_PASSTHRU:
230   case AArch64ISD::FABS_MERGE_PASSTHRU:
231     return true;
232   }
233 }
234 
235 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
236                                              const AArch64Subtarget &STI)
237     : TargetLowering(TM), Subtarget(&STI) {
238   // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
239   // we have to make something up. Arbitrarily, choose ZeroOrOne.
240   setBooleanContents(ZeroOrOneBooleanContent);
241   // When comparing vectors the result sets the different elements in the
242   // vector to all-one or all-zero.
243   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
244 
245   // Set up the register classes.
246   addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
247   addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
248 
249   if (Subtarget->hasFPARMv8()) {
250     addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
251     addRegisterClass(MVT::bf16, &AArch64::FPR16RegClass);
252     addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
253     addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
254     addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
255   }
256 
257   if (Subtarget->hasNEON()) {
258     addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
259     addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
260     // Someone set us up the NEON.
261     addDRTypeForNEON(MVT::v2f32);
262     addDRTypeForNEON(MVT::v8i8);
263     addDRTypeForNEON(MVT::v4i16);
264     addDRTypeForNEON(MVT::v2i32);
265     addDRTypeForNEON(MVT::v1i64);
266     addDRTypeForNEON(MVT::v1f64);
267     addDRTypeForNEON(MVT::v4f16);
268     if (Subtarget->hasBF16())
269       addDRTypeForNEON(MVT::v4bf16);
270 
271     addQRTypeForNEON(MVT::v4f32);
272     addQRTypeForNEON(MVT::v2f64);
273     addQRTypeForNEON(MVT::v16i8);
274     addQRTypeForNEON(MVT::v8i16);
275     addQRTypeForNEON(MVT::v4i32);
276     addQRTypeForNEON(MVT::v2i64);
277     addQRTypeForNEON(MVT::v8f16);
278     if (Subtarget->hasBF16())
279       addQRTypeForNEON(MVT::v8bf16);
280   }
281 
282   if (Subtarget->hasSVE()) {
283     // Add legal sve predicate types
284     addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass);
285     addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass);
286     addRegisterClass(MVT::nxv8i1, &AArch64::PPRRegClass);
287     addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass);
288 
289     // Add legal sve data types
290     addRegisterClass(MVT::nxv16i8, &AArch64::ZPRRegClass);
291     addRegisterClass(MVT::nxv8i16, &AArch64::ZPRRegClass);
292     addRegisterClass(MVT::nxv4i32, &AArch64::ZPRRegClass);
293     addRegisterClass(MVT::nxv2i64, &AArch64::ZPRRegClass);
294 
295     addRegisterClass(MVT::nxv2f16, &AArch64::ZPRRegClass);
296     addRegisterClass(MVT::nxv4f16, &AArch64::ZPRRegClass);
297     addRegisterClass(MVT::nxv8f16, &AArch64::ZPRRegClass);
298     addRegisterClass(MVT::nxv2f32, &AArch64::ZPRRegClass);
299     addRegisterClass(MVT::nxv4f32, &AArch64::ZPRRegClass);
300     addRegisterClass(MVT::nxv2f64, &AArch64::ZPRRegClass);
301 
302     if (Subtarget->hasBF16()) {
303       addRegisterClass(MVT::nxv2bf16, &AArch64::ZPRRegClass);
304       addRegisterClass(MVT::nxv4bf16, &AArch64::ZPRRegClass);
305       addRegisterClass(MVT::nxv8bf16, &AArch64::ZPRRegClass);
306     }
307 
308     if (Subtarget->useSVEForFixedLengthVectors()) {
309       for (MVT VT : MVT::integer_fixedlen_vector_valuetypes())
310         if (useSVEForFixedLengthVectorVT(VT))
311           addRegisterClass(VT, &AArch64::ZPRRegClass);
312 
313       for (MVT VT : MVT::fp_fixedlen_vector_valuetypes())
314         if (useSVEForFixedLengthVectorVT(VT))
315           addRegisterClass(VT, &AArch64::ZPRRegClass);
316     }
317 
318     for (auto VT : { MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64 }) {
319       setOperationAction(ISD::SADDSAT, VT, Legal);
320       setOperationAction(ISD::UADDSAT, VT, Legal);
321       setOperationAction(ISD::SSUBSAT, VT, Legal);
322       setOperationAction(ISD::USUBSAT, VT, Legal);
323       setOperationAction(ISD::UREM, VT, Expand);
324       setOperationAction(ISD::SREM, VT, Expand);
325       setOperationAction(ISD::SDIVREM, VT, Expand);
326       setOperationAction(ISD::UDIVREM, VT, Expand);
327     }
328 
329     for (auto VT :
330          { MVT::nxv2i8, MVT::nxv2i16, MVT::nxv2i32, MVT::nxv2i64, MVT::nxv4i8,
331            MVT::nxv4i16, MVT::nxv4i32, MVT::nxv8i8, MVT::nxv8i16 })
332       setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Legal);
333 
334     for (auto VT :
335          { MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32, MVT::nxv4f32,
336            MVT::nxv2f64 }) {
337       setCondCodeAction(ISD::SETO, VT, Expand);
338       setCondCodeAction(ISD::SETOLT, VT, Expand);
339       setCondCodeAction(ISD::SETLT, VT, Expand);
340       setCondCodeAction(ISD::SETOLE, VT, Expand);
341       setCondCodeAction(ISD::SETLE, VT, Expand);
342       setCondCodeAction(ISD::SETULT, VT, Expand);
343       setCondCodeAction(ISD::SETULE, VT, Expand);
344       setCondCodeAction(ISD::SETUGE, VT, Expand);
345       setCondCodeAction(ISD::SETUGT, VT, Expand);
346       setCondCodeAction(ISD::SETUEQ, VT, Expand);
347       setCondCodeAction(ISD::SETUNE, VT, Expand);
348 
349       setOperationAction(ISD::FREM, VT, Expand);
350       setOperationAction(ISD::FPOW, VT, Expand);
351       setOperationAction(ISD::FPOWI, VT, Expand);
352       setOperationAction(ISD::FCOS, VT, Expand);
353       setOperationAction(ISD::FSIN, VT, Expand);
354       setOperationAction(ISD::FSINCOS, VT, Expand);
355       setOperationAction(ISD::FEXP, VT, Expand);
356       setOperationAction(ISD::FEXP2, VT, Expand);
357       setOperationAction(ISD::FLOG, VT, Expand);
358       setOperationAction(ISD::FLOG2, VT, Expand);
359       setOperationAction(ISD::FLOG10, VT, Expand);
360     }
361   }
362 
363   // Compute derived properties from the register classes
364   computeRegisterProperties(Subtarget->getRegisterInfo());
365 
366   // Provide all sorts of operation actions
367   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
368   setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
369   setOperationAction(ISD::SETCC, MVT::i32, Custom);
370   setOperationAction(ISD::SETCC, MVT::i64, Custom);
371   setOperationAction(ISD::SETCC, MVT::f16, Custom);
372   setOperationAction(ISD::SETCC, MVT::f32, Custom);
373   setOperationAction(ISD::SETCC, MVT::f64, Custom);
374   setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
375   setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
376   setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
377   setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
378   setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
379   setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
380   setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
381   setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
382   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
383   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
384   setOperationAction(ISD::BR_CC, MVT::i64, Custom);
385   setOperationAction(ISD::BR_CC, MVT::f16, Custom);
386   setOperationAction(ISD::BR_CC, MVT::f32, Custom);
387   setOperationAction(ISD::BR_CC, MVT::f64, Custom);
388   setOperationAction(ISD::SELECT, MVT::i32, Custom);
389   setOperationAction(ISD::SELECT, MVT::i64, Custom);
390   setOperationAction(ISD::SELECT, MVT::f16, Custom);
391   setOperationAction(ISD::SELECT, MVT::f32, Custom);
392   setOperationAction(ISD::SELECT, MVT::f64, Custom);
393   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
394   setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
395   setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
396   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
397   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
398   setOperationAction(ISD::BR_JT, MVT::Other, Custom);
399   setOperationAction(ISD::JumpTable, MVT::i64, Custom);
400 
401   setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
402   setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
403   setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
404 
405   setOperationAction(ISD::FREM, MVT::f32, Expand);
406   setOperationAction(ISD::FREM, MVT::f64, Expand);
407   setOperationAction(ISD::FREM, MVT::f80, Expand);
408 
409   setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
410 
411   // Custom lowering hooks are needed for XOR
412   // to fold it into CSINC/CSINV.
413   setOperationAction(ISD::XOR, MVT::i32, Custom);
414   setOperationAction(ISD::XOR, MVT::i64, Custom);
415 
416   // Virtually no operation on f128 is legal, but LLVM can't expand them when
417   // there's a valid register class, so we need custom operations in most cases.
418   setOperationAction(ISD::FABS, MVT::f128, Expand);
419   setOperationAction(ISD::FADD, MVT::f128, LibCall);
420   setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
421   setOperationAction(ISD::FCOS, MVT::f128, Expand);
422   setOperationAction(ISD::FDIV, MVT::f128, LibCall);
423   setOperationAction(ISD::FMA, MVT::f128, Expand);
424   setOperationAction(ISD::FMUL, MVT::f128, LibCall);
425   setOperationAction(ISD::FNEG, MVT::f128, Expand);
426   setOperationAction(ISD::FPOW, MVT::f128, Expand);
427   setOperationAction(ISD::FREM, MVT::f128, Expand);
428   setOperationAction(ISD::FRINT, MVT::f128, Expand);
429   setOperationAction(ISD::FSIN, MVT::f128, Expand);
430   setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
431   setOperationAction(ISD::FSQRT, MVT::f128, Expand);
432   setOperationAction(ISD::FSUB, MVT::f128, LibCall);
433   setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
434   setOperationAction(ISD::SETCC, MVT::f128, Custom);
435   setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom);
436   setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom);
437   setOperationAction(ISD::BR_CC, MVT::f128, Custom);
438   setOperationAction(ISD::SELECT, MVT::f128, Custom);
439   setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
440   setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
441 
442   // Lowering for many of the conversions is actually specified by the non-f128
443   // type. The LowerXXX function will be trivial when f128 isn't involved.
444   setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
445   setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
446   setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
447   setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
448   setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
449   setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i128, Custom);
450   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
451   setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
452   setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
453   setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
454   setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
455   setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i128, Custom);
456   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
457   setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
458   setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
459   setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
460   setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
461   setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i128, Custom);
462   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
463   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
464   setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
465   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
466   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
467   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
468   setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
469   setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
470   setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
471   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
472   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
473   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
474 
475   setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
476   setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
477   setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
478   setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
479 
480   // Variable arguments.
481   setOperationAction(ISD::VASTART, MVT::Other, Custom);
482   setOperationAction(ISD::VAARG, MVT::Other, Custom);
483   setOperationAction(ISD::VACOPY, MVT::Other, Custom);
484   setOperationAction(ISD::VAEND, MVT::Other, Expand);
485 
486   // Variable-sized objects.
487   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
488   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
489 
490   if (Subtarget->isTargetWindows())
491     setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
492   else
493     setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
494 
495   // Constant pool entries
496   setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
497 
498   // BlockAddress
499   setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
500 
501   // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
502   setOperationAction(ISD::ADDC, MVT::i32, Custom);
503   setOperationAction(ISD::ADDE, MVT::i32, Custom);
504   setOperationAction(ISD::SUBC, MVT::i32, Custom);
505   setOperationAction(ISD::SUBE, MVT::i32, Custom);
506   setOperationAction(ISD::ADDC, MVT::i64, Custom);
507   setOperationAction(ISD::ADDE, MVT::i64, Custom);
508   setOperationAction(ISD::SUBC, MVT::i64, Custom);
509   setOperationAction(ISD::SUBE, MVT::i64, Custom);
510 
511   // AArch64 lacks both left-rotate and popcount instructions.
512   setOperationAction(ISD::ROTL, MVT::i32, Expand);
513   setOperationAction(ISD::ROTL, MVT::i64, Expand);
514   for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
515     setOperationAction(ISD::ROTL, VT, Expand);
516     setOperationAction(ISD::ROTR, VT, Expand);
517   }
518 
519   // AArch64 doesn't have i32 MULH{S|U}.
520   setOperationAction(ISD::MULHU, MVT::i32, Expand);
521   setOperationAction(ISD::MULHS, MVT::i32, Expand);
522 
523   // AArch64 doesn't have {U|S}MUL_LOHI.
524   setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
525   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
526 
527   setOperationAction(ISD::CTPOP, MVT::i32, Custom);
528   setOperationAction(ISD::CTPOP, MVT::i64, Custom);
529   setOperationAction(ISD::CTPOP, MVT::i128, Custom);
530 
531   setOperationAction(ISD::ABS, MVT::i32, Custom);
532   setOperationAction(ISD::ABS, MVT::i64, Custom);
533 
534   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
535   setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
536   for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
537     setOperationAction(ISD::SDIVREM, VT, Expand);
538     setOperationAction(ISD::UDIVREM, VT, Expand);
539   }
540   setOperationAction(ISD::SREM, MVT::i32, Expand);
541   setOperationAction(ISD::SREM, MVT::i64, Expand);
542   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
543   setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
544   setOperationAction(ISD::UREM, MVT::i32, Expand);
545   setOperationAction(ISD::UREM, MVT::i64, Expand);
546 
547   // Custom lower Add/Sub/Mul with overflow.
548   setOperationAction(ISD::SADDO, MVT::i32, Custom);
549   setOperationAction(ISD::SADDO, MVT::i64, Custom);
550   setOperationAction(ISD::UADDO, MVT::i32, Custom);
551   setOperationAction(ISD::UADDO, MVT::i64, Custom);
552   setOperationAction(ISD::SSUBO, MVT::i32, Custom);
553   setOperationAction(ISD::SSUBO, MVT::i64, Custom);
554   setOperationAction(ISD::USUBO, MVT::i32, Custom);
555   setOperationAction(ISD::USUBO, MVT::i64, Custom);
556   setOperationAction(ISD::SMULO, MVT::i32, Custom);
557   setOperationAction(ISD::SMULO, MVT::i64, Custom);
558   setOperationAction(ISD::UMULO, MVT::i32, Custom);
559   setOperationAction(ISD::UMULO, MVT::i64, Custom);
560 
561   setOperationAction(ISD::FSIN, MVT::f32, Expand);
562   setOperationAction(ISD::FSIN, MVT::f64, Expand);
563   setOperationAction(ISD::FCOS, MVT::f32, Expand);
564   setOperationAction(ISD::FCOS, MVT::f64, Expand);
565   setOperationAction(ISD::FPOW, MVT::f32, Expand);
566   setOperationAction(ISD::FPOW, MVT::f64, Expand);
567   setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
568   setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
569   if (Subtarget->hasFullFP16())
570     setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
571   else
572     setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
573 
574   setOperationAction(ISD::FREM,    MVT::f16,   Promote);
575   setOperationAction(ISD::FREM,    MVT::v4f16, Expand);
576   setOperationAction(ISD::FREM,    MVT::v8f16, Expand);
577   setOperationAction(ISD::FPOW,    MVT::f16,   Promote);
578   setOperationAction(ISD::FPOW,    MVT::v4f16, Expand);
579   setOperationAction(ISD::FPOW,    MVT::v8f16, Expand);
580   setOperationAction(ISD::FPOWI,   MVT::f16,   Promote);
581   setOperationAction(ISD::FPOWI,   MVT::v4f16, Expand);
582   setOperationAction(ISD::FPOWI,   MVT::v8f16, Expand);
583   setOperationAction(ISD::FCOS,    MVT::f16,   Promote);
584   setOperationAction(ISD::FCOS,    MVT::v4f16, Expand);
585   setOperationAction(ISD::FCOS,    MVT::v8f16, Expand);
586   setOperationAction(ISD::FSIN,    MVT::f16,   Promote);
587   setOperationAction(ISD::FSIN,    MVT::v4f16, Expand);
588   setOperationAction(ISD::FSIN,    MVT::v8f16, Expand);
589   setOperationAction(ISD::FSINCOS, MVT::f16,   Promote);
590   setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
591   setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
592   setOperationAction(ISD::FEXP,    MVT::f16,   Promote);
593   setOperationAction(ISD::FEXP,    MVT::v4f16, Expand);
594   setOperationAction(ISD::FEXP,    MVT::v8f16, Expand);
595   setOperationAction(ISD::FEXP2,   MVT::f16,   Promote);
596   setOperationAction(ISD::FEXP2,   MVT::v4f16, Expand);
597   setOperationAction(ISD::FEXP2,   MVT::v8f16, Expand);
598   setOperationAction(ISD::FLOG,    MVT::f16,   Promote);
599   setOperationAction(ISD::FLOG,    MVT::v4f16, Expand);
600   setOperationAction(ISD::FLOG,    MVT::v8f16, Expand);
601   setOperationAction(ISD::FLOG2,   MVT::f16,   Promote);
602   setOperationAction(ISD::FLOG2,   MVT::v4f16, Expand);
603   setOperationAction(ISD::FLOG2,   MVT::v8f16, Expand);
604   setOperationAction(ISD::FLOG10,  MVT::f16,   Promote);
605   setOperationAction(ISD::FLOG10,  MVT::v4f16, Expand);
606   setOperationAction(ISD::FLOG10,  MVT::v8f16, Expand);
607 
608   if (!Subtarget->hasFullFP16()) {
609     setOperationAction(ISD::SELECT,      MVT::f16,  Promote);
610     setOperationAction(ISD::SELECT_CC,   MVT::f16,  Promote);
611     setOperationAction(ISD::SETCC,       MVT::f16,  Promote);
612     setOperationAction(ISD::BR_CC,       MVT::f16,  Promote);
613     setOperationAction(ISD::FADD,        MVT::f16,  Promote);
614     setOperationAction(ISD::FSUB,        MVT::f16,  Promote);
615     setOperationAction(ISD::FMUL,        MVT::f16,  Promote);
616     setOperationAction(ISD::FDIV,        MVT::f16,  Promote);
617     setOperationAction(ISD::FMA,         MVT::f16,  Promote);
618     setOperationAction(ISD::FNEG,        MVT::f16,  Promote);
619     setOperationAction(ISD::FABS,        MVT::f16,  Promote);
620     setOperationAction(ISD::FCEIL,       MVT::f16,  Promote);
621     setOperationAction(ISD::FSQRT,       MVT::f16,  Promote);
622     setOperationAction(ISD::FFLOOR,      MVT::f16,  Promote);
623     setOperationAction(ISD::FNEARBYINT,  MVT::f16,  Promote);
624     setOperationAction(ISD::FRINT,       MVT::f16,  Promote);
625     setOperationAction(ISD::FROUND,      MVT::f16,  Promote);
626     setOperationAction(ISD::FROUNDEVEN,  MVT::f16,  Promote);
627     setOperationAction(ISD::FTRUNC,      MVT::f16,  Promote);
628     setOperationAction(ISD::FMINNUM,     MVT::f16,  Promote);
629     setOperationAction(ISD::FMAXNUM,     MVT::f16,  Promote);
630     setOperationAction(ISD::FMINIMUM,    MVT::f16,  Promote);
631     setOperationAction(ISD::FMAXIMUM,    MVT::f16,  Promote);
632 
633     // promote v4f16 to v4f32 when that is known to be safe.
634     setOperationAction(ISD::FADD,        MVT::v4f16, Promote);
635     setOperationAction(ISD::FSUB,        MVT::v4f16, Promote);
636     setOperationAction(ISD::FMUL,        MVT::v4f16, Promote);
637     setOperationAction(ISD::FDIV,        MVT::v4f16, Promote);
638     AddPromotedToType(ISD::FADD,         MVT::v4f16, MVT::v4f32);
639     AddPromotedToType(ISD::FSUB,         MVT::v4f16, MVT::v4f32);
640     AddPromotedToType(ISD::FMUL,         MVT::v4f16, MVT::v4f32);
641     AddPromotedToType(ISD::FDIV,         MVT::v4f16, MVT::v4f32);
642 
643     setOperationAction(ISD::FABS,        MVT::v4f16, Expand);
644     setOperationAction(ISD::FNEG,        MVT::v4f16, Expand);
645     setOperationAction(ISD::FROUND,      MVT::v4f16, Expand);
646     setOperationAction(ISD::FROUNDEVEN,  MVT::v4f16, Expand);
647     setOperationAction(ISD::FMA,         MVT::v4f16, Expand);
648     setOperationAction(ISD::SETCC,       MVT::v4f16, Expand);
649     setOperationAction(ISD::BR_CC,       MVT::v4f16, Expand);
650     setOperationAction(ISD::SELECT,      MVT::v4f16, Expand);
651     setOperationAction(ISD::SELECT_CC,   MVT::v4f16, Expand);
652     setOperationAction(ISD::FTRUNC,      MVT::v4f16, Expand);
653     setOperationAction(ISD::FCOPYSIGN,   MVT::v4f16, Expand);
654     setOperationAction(ISD::FFLOOR,      MVT::v4f16, Expand);
655     setOperationAction(ISD::FCEIL,       MVT::v4f16, Expand);
656     setOperationAction(ISD::FRINT,       MVT::v4f16, Expand);
657     setOperationAction(ISD::FNEARBYINT,  MVT::v4f16, Expand);
658     setOperationAction(ISD::FSQRT,       MVT::v4f16, Expand);
659 
660     setOperationAction(ISD::FABS,        MVT::v8f16, Expand);
661     setOperationAction(ISD::FADD,        MVT::v8f16, Expand);
662     setOperationAction(ISD::FCEIL,       MVT::v8f16, Expand);
663     setOperationAction(ISD::FCOPYSIGN,   MVT::v8f16, Expand);
664     setOperationAction(ISD::FDIV,        MVT::v8f16, Expand);
665     setOperationAction(ISD::FFLOOR,      MVT::v8f16, Expand);
666     setOperationAction(ISD::FMA,         MVT::v8f16, Expand);
667     setOperationAction(ISD::FMUL,        MVT::v8f16, Expand);
668     setOperationAction(ISD::FNEARBYINT,  MVT::v8f16, Expand);
669     setOperationAction(ISD::FNEG,        MVT::v8f16, Expand);
670     setOperationAction(ISD::FROUND,      MVT::v8f16, Expand);
671     setOperationAction(ISD::FROUNDEVEN,  MVT::v8f16, Expand);
672     setOperationAction(ISD::FRINT,       MVT::v8f16, Expand);
673     setOperationAction(ISD::FSQRT,       MVT::v8f16, Expand);
674     setOperationAction(ISD::FSUB,        MVT::v8f16, Expand);
675     setOperationAction(ISD::FTRUNC,      MVT::v8f16, Expand);
676     setOperationAction(ISD::SETCC,       MVT::v8f16, Expand);
677     setOperationAction(ISD::BR_CC,       MVT::v8f16, Expand);
678     setOperationAction(ISD::SELECT,      MVT::v8f16, Expand);
679     setOperationAction(ISD::SELECT_CC,   MVT::v8f16, Expand);
680     setOperationAction(ISD::FP_EXTEND,   MVT::v8f16, Expand);
681   }
682 
683   // AArch64 has implementations of a lot of rounding-like FP operations.
684   for (MVT Ty : {MVT::f32, MVT::f64}) {
685     setOperationAction(ISD::FFLOOR, Ty, Legal);
686     setOperationAction(ISD::FNEARBYINT, Ty, Legal);
687     setOperationAction(ISD::FCEIL, Ty, Legal);
688     setOperationAction(ISD::FRINT, Ty, Legal);
689     setOperationAction(ISD::FTRUNC, Ty, Legal);
690     setOperationAction(ISD::FROUND, Ty, Legal);
691     setOperationAction(ISD::FROUNDEVEN, Ty, Legal);
692     setOperationAction(ISD::FMINNUM, Ty, Legal);
693     setOperationAction(ISD::FMAXNUM, Ty, Legal);
694     setOperationAction(ISD::FMINIMUM, Ty, Legal);
695     setOperationAction(ISD::FMAXIMUM, Ty, Legal);
696     setOperationAction(ISD::LROUND, Ty, Legal);
697     setOperationAction(ISD::LLROUND, Ty, Legal);
698     setOperationAction(ISD::LRINT, Ty, Legal);
699     setOperationAction(ISD::LLRINT, Ty, Legal);
700   }
701 
702   if (Subtarget->hasFullFP16()) {
703     setOperationAction(ISD::FNEARBYINT, MVT::f16, Legal);
704     setOperationAction(ISD::FFLOOR,  MVT::f16, Legal);
705     setOperationAction(ISD::FCEIL,   MVT::f16, Legal);
706     setOperationAction(ISD::FRINT,   MVT::f16, Legal);
707     setOperationAction(ISD::FTRUNC,  MVT::f16, Legal);
708     setOperationAction(ISD::FROUND,  MVT::f16, Legal);
709     setOperationAction(ISD::FROUNDEVEN,  MVT::f16, Legal);
710     setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
711     setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
712     setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
713     setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
714   }
715 
716   setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
717 
718   setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
719   setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
720 
721   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
722   setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
723   setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
724   setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
725   setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
726 
727   // Generate outline atomics library calls only if LSE was not specified for
728   // subtarget
729   if (Subtarget->outlineAtomics() && !Subtarget->hasLSE()) {
730     setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, LibCall);
731     setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, LibCall);
732     setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, LibCall);
733     setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, LibCall);
734     setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, LibCall);
735     setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, LibCall);
736     setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, LibCall);
737     setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, LibCall);
738     setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, LibCall);
739     setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, LibCall);
740     setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, LibCall);
741     setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, LibCall);
742     setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, LibCall);
743     setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, LibCall);
744     setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, LibCall);
745     setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, LibCall);
746     setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, LibCall);
747     setOperationAction(ISD::ATOMIC_LOAD_CLR, MVT::i8, LibCall);
748     setOperationAction(ISD::ATOMIC_LOAD_CLR, MVT::i16, LibCall);
749     setOperationAction(ISD::ATOMIC_LOAD_CLR, MVT::i32, LibCall);
750     setOperationAction(ISD::ATOMIC_LOAD_CLR, MVT::i64, LibCall);
751     setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, LibCall);
752     setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, LibCall);
753     setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, LibCall);
754     setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, LibCall);
755 #define LCALLNAMES(A, B, N)                                                    \
756   setLibcallName(A##N##_RELAX, #B #N "_relax");                                \
757   setLibcallName(A##N##_ACQ, #B #N "_acq");                                    \
758   setLibcallName(A##N##_REL, #B #N "_rel");                                    \
759   setLibcallName(A##N##_ACQ_REL, #B #N "_acq_rel");
760 #define LCALLNAME4(A, B)                                                       \
761   LCALLNAMES(A, B, 1)                                                          \
762   LCALLNAMES(A, B, 2) LCALLNAMES(A, B, 4) LCALLNAMES(A, B, 8)
763 #define LCALLNAME5(A, B)                                                       \
764   LCALLNAMES(A, B, 1)                                                          \
765   LCALLNAMES(A, B, 2)                                                          \
766   LCALLNAMES(A, B, 4) LCALLNAMES(A, B, 8) LCALLNAMES(A, B, 16)
767     LCALLNAME5(RTLIB::OUTLINE_ATOMIC_CAS, __aarch64_cas)
768     LCALLNAME4(RTLIB::OUTLINE_ATOMIC_SWP, __aarch64_swp)
769     LCALLNAME4(RTLIB::OUTLINE_ATOMIC_LDADD, __aarch64_ldadd)
770     LCALLNAME4(RTLIB::OUTLINE_ATOMIC_LDSET, __aarch64_ldset)
771     LCALLNAME4(RTLIB::OUTLINE_ATOMIC_LDCLR, __aarch64_ldclr)
772     LCALLNAME4(RTLIB::OUTLINE_ATOMIC_LDEOR, __aarch64_ldeor)
773 #undef LCALLNAMES
774 #undef LCALLNAME4
775 #undef LCALLNAME5
776   }
777 
778   // 128-bit loads and stores can be done without expanding
779   setOperationAction(ISD::LOAD, MVT::i128, Custom);
780   setOperationAction(ISD::STORE, MVT::i128, Custom);
781 
782   // 256 bit non-temporal stores can be lowered to STNP. Do this as part of the
783   // custom lowering, as there are no un-paired non-temporal stores and
784   // legalization will break up 256 bit inputs.
785   setOperationAction(ISD::STORE, MVT::v32i8, Custom);
786   setOperationAction(ISD::STORE, MVT::v16i16, Custom);
787   setOperationAction(ISD::STORE, MVT::v16f16, Custom);
788   setOperationAction(ISD::STORE, MVT::v8i32, Custom);
789   setOperationAction(ISD::STORE, MVT::v8f32, Custom);
790   setOperationAction(ISD::STORE, MVT::v4f64, Custom);
791   setOperationAction(ISD::STORE, MVT::v4i64, Custom);
792 
793   // Lower READCYCLECOUNTER using an mrs from PMCCNTR_EL0.
794   // This requires the Performance Monitors extension.
795   if (Subtarget->hasPerfMon())
796     setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
797 
798   if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
799       getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
800     // Issue __sincos_stret if available.
801     setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
802     setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
803   } else {
804     setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
805     setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
806   }
807 
808   if (Subtarget->getTargetTriple().isOSMSVCRT()) {
809     // MSVCRT doesn't have powi; fall back to pow
810     setLibcallName(RTLIB::POWI_F32, nullptr);
811     setLibcallName(RTLIB::POWI_F64, nullptr);
812   }
813 
814   // Make floating-point constants legal for the large code model, so they don't
815   // become loads from the constant pool.
816   if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
817     setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
818     setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
819   }
820 
821   // AArch64 does not have floating-point extending loads, i1 sign-extending
822   // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
823   for (MVT VT : MVT::fp_valuetypes()) {
824     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
825     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
826     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
827     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
828   }
829   for (MVT VT : MVT::integer_valuetypes())
830     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
831 
832   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
833   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
834   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
835   setTruncStoreAction(MVT::f128, MVT::f80, Expand);
836   setTruncStoreAction(MVT::f128, MVT::f64, Expand);
837   setTruncStoreAction(MVT::f128, MVT::f32, Expand);
838   setTruncStoreAction(MVT::f128, MVT::f16, Expand);
839 
840   setOperationAction(ISD::BITCAST, MVT::i16, Custom);
841   setOperationAction(ISD::BITCAST, MVT::f16, Custom);
842   setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
843 
844   // Indexed loads and stores are supported.
845   for (unsigned im = (unsigned)ISD::PRE_INC;
846        im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
847     setIndexedLoadAction(im, MVT::i8, Legal);
848     setIndexedLoadAction(im, MVT::i16, Legal);
849     setIndexedLoadAction(im, MVT::i32, Legal);
850     setIndexedLoadAction(im, MVT::i64, Legal);
851     setIndexedLoadAction(im, MVT::f64, Legal);
852     setIndexedLoadAction(im, MVT::f32, Legal);
853     setIndexedLoadAction(im, MVT::f16, Legal);
854     setIndexedLoadAction(im, MVT::bf16, Legal);
855     setIndexedStoreAction(im, MVT::i8, Legal);
856     setIndexedStoreAction(im, MVT::i16, Legal);
857     setIndexedStoreAction(im, MVT::i32, Legal);
858     setIndexedStoreAction(im, MVT::i64, Legal);
859     setIndexedStoreAction(im, MVT::f64, Legal);
860     setIndexedStoreAction(im, MVT::f32, Legal);
861     setIndexedStoreAction(im, MVT::f16, Legal);
862     setIndexedStoreAction(im, MVT::bf16, Legal);
863   }
864 
865   // Trap.
866   setOperationAction(ISD::TRAP, MVT::Other, Legal);
867   setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
868   setOperationAction(ISD::UBSANTRAP, MVT::Other, Legal);
869 
870   // We combine OR nodes for bitfield operations.
871   setTargetDAGCombine(ISD::OR);
872   // Try to create BICs for vector ANDs.
873   setTargetDAGCombine(ISD::AND);
874 
875   // Vector add and sub nodes may conceal a high-half opportunity.
876   // Also, try to fold ADD into CSINC/CSINV..
877   setTargetDAGCombine(ISD::ADD);
878   setTargetDAGCombine(ISD::ABS);
879   setTargetDAGCombine(ISD::SUB);
880   setTargetDAGCombine(ISD::SRL);
881   setTargetDAGCombine(ISD::XOR);
882   setTargetDAGCombine(ISD::SINT_TO_FP);
883   setTargetDAGCombine(ISD::UINT_TO_FP);
884 
885   // TODO: Do the same for FP_TO_*INT_SAT.
886   setTargetDAGCombine(ISD::FP_TO_SINT);
887   setTargetDAGCombine(ISD::FP_TO_UINT);
888   setTargetDAGCombine(ISD::FDIV);
889 
890   // Try and combine setcc with csel
891   setTargetDAGCombine(ISD::SETCC);
892 
893   setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
894 
895   setTargetDAGCombine(ISD::ANY_EXTEND);
896   setTargetDAGCombine(ISD::ZERO_EXTEND);
897   setTargetDAGCombine(ISD::SIGN_EXTEND);
898   setTargetDAGCombine(ISD::VECTOR_SPLICE);
899   setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
900   setTargetDAGCombine(ISD::TRUNCATE);
901   setTargetDAGCombine(ISD::CONCAT_VECTORS);
902   setTargetDAGCombine(ISD::STORE);
903   if (Subtarget->supportsAddressTopByteIgnored())
904     setTargetDAGCombine(ISD::LOAD);
905 
906   setTargetDAGCombine(ISD::MUL);
907 
908   setTargetDAGCombine(ISD::SELECT);
909   setTargetDAGCombine(ISD::VSELECT);
910 
911   setTargetDAGCombine(ISD::INTRINSIC_VOID);
912   setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
913   setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
914   setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
915   setTargetDAGCombine(ISD::VECREDUCE_ADD);
916   setTargetDAGCombine(ISD::STEP_VECTOR);
917 
918   setTargetDAGCombine(ISD::GlobalAddress);
919 
920   // In case of strict alignment, avoid an excessive number of byte wide stores.
921   MaxStoresPerMemsetOptSize = 8;
922   MaxStoresPerMemset = Subtarget->requiresStrictAlign()
923                        ? MaxStoresPerMemsetOptSize : 32;
924 
925   MaxGluedStoresPerMemcpy = 4;
926   MaxStoresPerMemcpyOptSize = 4;
927   MaxStoresPerMemcpy = Subtarget->requiresStrictAlign()
928                        ? MaxStoresPerMemcpyOptSize : 16;
929 
930   MaxStoresPerMemmoveOptSize = MaxStoresPerMemmove = 4;
931 
932   MaxLoadsPerMemcmpOptSize = 4;
933   MaxLoadsPerMemcmp = Subtarget->requiresStrictAlign()
934                       ? MaxLoadsPerMemcmpOptSize : 8;
935 
936   setStackPointerRegisterToSaveRestore(AArch64::SP);
937 
938   setSchedulingPreference(Sched::Hybrid);
939 
940   EnableExtLdPromotion = true;
941 
942   // Set required alignment.
943   setMinFunctionAlignment(Align(4));
944   // Set preferred alignments.
945   setPrefLoopAlignment(Align(1ULL << STI.getPrefLoopLogAlignment()));
946   setPrefFunctionAlignment(Align(1ULL << STI.getPrefFunctionLogAlignment()));
947 
948   // Only change the limit for entries in a jump table if specified by
949   // the sub target, but not at the command line.
950   unsigned MaxJT = STI.getMaximumJumpTableSize();
951   if (MaxJT && getMaximumJumpTableSize() == UINT_MAX)
952     setMaximumJumpTableSize(MaxJT);
953 
954   setHasExtractBitsInsn(true);
955 
956   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
957 
958   if (Subtarget->hasNEON()) {
959     // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
960     // silliness like this:
961     setOperationAction(ISD::FABS, MVT::v1f64, Expand);
962     setOperationAction(ISD::FADD, MVT::v1f64, Expand);
963     setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
964     setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
965     setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
966     setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
967     setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
968     setOperationAction(ISD::FMA, MVT::v1f64, Expand);
969     setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
970     setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
971     setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
972     setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
973     setOperationAction(ISD::FREM, MVT::v1f64, Expand);
974     setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
975     setOperationAction(ISD::FROUNDEVEN, MVT::v1f64, Expand);
976     setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
977     setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
978     setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
979     setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
980     setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
981     setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
982     setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
983     setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
984     setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
985     setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
986     setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
987 
988     setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
989     setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
990     setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
991     setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
992     setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
993 
994     setOperationAction(ISD::MUL, MVT::v1i64, Expand);
995 
996     // AArch64 doesn't have a direct vector ->f32 conversion instructions for
997     // elements smaller than i32, so promote the input to i32 first.
998     setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32);
999     setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32);
1000     setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32);
1001     setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32);
1002     setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v16i8, MVT::v16i32);
1003     setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v16i8, MVT::v16i32);
1004 
1005     // Similarly, there is no direct i32 -> f64 vector conversion instruction.
1006     setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
1007     setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
1008     setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
1009     setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
1010     // Or, direct i32 -> f16 vector conversion.  Set it so custom, so the
1011     // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
1012     setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
1013     setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
1014 
1015     if (Subtarget->hasFullFP16()) {
1016       setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1017       setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1018       setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
1019       setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1020     } else {
1021       // when AArch64 doesn't have fullfp16 support, promote the input
1022       // to i32 first.
1023       setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i16, MVT::v4i32);
1024       setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i16, MVT::v4i32);
1025       setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i16, MVT::v8i32);
1026       setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i16, MVT::v8i32);
1027     }
1028 
1029     setOperationAction(ISD::CTLZ,       MVT::v1i64, Expand);
1030     setOperationAction(ISD::CTLZ,       MVT::v2i64, Expand);
1031     setOperationAction(ISD::BITREVERSE, MVT::v8i8, Legal);
1032     setOperationAction(ISD::BITREVERSE, MVT::v16i8, Legal);
1033     setOperationAction(ISD::BITREVERSE, MVT::v2i32, Custom);
1034     setOperationAction(ISD::BITREVERSE, MVT::v4i32, Custom);
1035     setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom);
1036     setOperationAction(ISD::BITREVERSE, MVT::v2i64, Custom);
1037 
1038     // AArch64 doesn't have MUL.2d:
1039     setOperationAction(ISD::MUL, MVT::v2i64, Expand);
1040     // Custom handling for some quad-vector types to detect MULL.
1041     setOperationAction(ISD::MUL, MVT::v8i16, Custom);
1042     setOperationAction(ISD::MUL, MVT::v4i32, Custom);
1043     setOperationAction(ISD::MUL, MVT::v2i64, Custom);
1044 
1045     // Saturates
1046     for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
1047                     MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1048       setOperationAction(ISD::SADDSAT, VT, Legal);
1049       setOperationAction(ISD::UADDSAT, VT, Legal);
1050       setOperationAction(ISD::SSUBSAT, VT, Legal);
1051       setOperationAction(ISD::USUBSAT, VT, Legal);
1052     }
1053 
1054     for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v16i8, MVT::v8i16,
1055                    MVT::v4i32}) {
1056       setOperationAction(ISD::ABDS, VT, Legal);
1057       setOperationAction(ISD::ABDU, VT, Legal);
1058     }
1059 
1060     // Vector reductions
1061     for (MVT VT : { MVT::v4f16, MVT::v2f32,
1062                     MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
1063       if (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()) {
1064         setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
1065         setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
1066 
1067         setOperationAction(ISD::VECREDUCE_FADD, VT, Legal);
1068       }
1069     }
1070     for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
1071                     MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
1072       setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
1073       setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
1074       setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
1075       setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
1076       setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
1077     }
1078     setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom);
1079 
1080     setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
1081     setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
1082     // Likewise, narrowing and extending vector loads/stores aren't handled
1083     // directly.
1084     for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1085       setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
1086 
1087       if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) {
1088         setOperationAction(ISD::MULHS, VT, Legal);
1089         setOperationAction(ISD::MULHU, VT, Legal);
1090       } else {
1091         setOperationAction(ISD::MULHS, VT, Expand);
1092         setOperationAction(ISD::MULHU, VT, Expand);
1093       }
1094       setOperationAction(ISD::SMUL_LOHI, VT, Expand);
1095       setOperationAction(ISD::UMUL_LOHI, VT, Expand);
1096 
1097       setOperationAction(ISD::BSWAP, VT, Expand);
1098       setOperationAction(ISD::CTTZ, VT, Expand);
1099 
1100       for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
1101         setTruncStoreAction(VT, InnerVT, Expand);
1102         setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
1103         setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
1104         setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
1105       }
1106     }
1107 
1108     // AArch64 has implementations of a lot of rounding-like FP operations.
1109     for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
1110       setOperationAction(ISD::FFLOOR, Ty, Legal);
1111       setOperationAction(ISD::FNEARBYINT, Ty, Legal);
1112       setOperationAction(ISD::FCEIL, Ty, Legal);
1113       setOperationAction(ISD::FRINT, Ty, Legal);
1114       setOperationAction(ISD::FTRUNC, Ty, Legal);
1115       setOperationAction(ISD::FROUND, Ty, Legal);
1116       setOperationAction(ISD::FROUNDEVEN, Ty, Legal);
1117     }
1118 
1119     if (Subtarget->hasFullFP16()) {
1120       for (MVT Ty : {MVT::v4f16, MVT::v8f16}) {
1121         setOperationAction(ISD::FFLOOR, Ty, Legal);
1122         setOperationAction(ISD::FNEARBYINT, Ty, Legal);
1123         setOperationAction(ISD::FCEIL, Ty, Legal);
1124         setOperationAction(ISD::FRINT, Ty, Legal);
1125         setOperationAction(ISD::FTRUNC, Ty, Legal);
1126         setOperationAction(ISD::FROUND, Ty, Legal);
1127         setOperationAction(ISD::FROUNDEVEN, Ty, Legal);
1128       }
1129     }
1130 
1131     if (Subtarget->hasSVE())
1132       setOperationAction(ISD::VSCALE, MVT::i32, Custom);
1133 
1134     setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom);
1135 
1136     setLoadExtAction(ISD::EXTLOAD,  MVT::v4i16, MVT::v4i8, Custom);
1137     setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Custom);
1138     setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Custom);
1139     setLoadExtAction(ISD::EXTLOAD,  MVT::v4i32, MVT::v4i8, Custom);
1140     setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Custom);
1141     setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Custom);
1142   }
1143 
1144   if (Subtarget->hasSVE()) {
1145     for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64}) {
1146       setOperationAction(ISD::BITREVERSE, VT, Custom);
1147       setOperationAction(ISD::BSWAP, VT, Custom);
1148       setOperationAction(ISD::CTLZ, VT, Custom);
1149       setOperationAction(ISD::CTPOP, VT, Custom);
1150       setOperationAction(ISD::CTTZ, VT, Custom);
1151       setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1152       setOperationAction(ISD::UINT_TO_FP, VT, Custom);
1153       setOperationAction(ISD::SINT_TO_FP, VT, Custom);
1154       setOperationAction(ISD::FP_TO_UINT, VT, Custom);
1155       setOperationAction(ISD::FP_TO_SINT, VT, Custom);
1156       setOperationAction(ISD::MGATHER, VT, Custom);
1157       setOperationAction(ISD::MSCATTER, VT, Custom);
1158       setOperationAction(ISD::MLOAD, VT, Custom);
1159       setOperationAction(ISD::MUL, VT, Custom);
1160       setOperationAction(ISD::MULHS, VT, Custom);
1161       setOperationAction(ISD::MULHU, VT, Custom);
1162       setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
1163       setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);
1164       setOperationAction(ISD::SELECT, VT, Custom);
1165       setOperationAction(ISD::SETCC, VT, Custom);
1166       setOperationAction(ISD::SDIV, VT, Custom);
1167       setOperationAction(ISD::UDIV, VT, Custom);
1168       setOperationAction(ISD::SMIN, VT, Custom);
1169       setOperationAction(ISD::UMIN, VT, Custom);
1170       setOperationAction(ISD::SMAX, VT, Custom);
1171       setOperationAction(ISD::UMAX, VT, Custom);
1172       setOperationAction(ISD::SHL, VT, Custom);
1173       setOperationAction(ISD::SRL, VT, Custom);
1174       setOperationAction(ISD::SRA, VT, Custom);
1175       setOperationAction(ISD::ABS, VT, Custom);
1176       setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
1177       setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
1178       setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
1179       setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
1180       setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
1181       setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
1182       setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
1183       setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
1184 
1185       setOperationAction(ISD::UMUL_LOHI, VT, Expand);
1186       setOperationAction(ISD::SMUL_LOHI, VT, Expand);
1187       setOperationAction(ISD::SELECT_CC, VT, Expand);
1188       setOperationAction(ISD::ROTL, VT, Expand);
1189       setOperationAction(ISD::ROTR, VT, Expand);
1190     }
1191 
1192     // Illegal unpacked integer vector types.
1193     for (auto VT : {MVT::nxv8i8, MVT::nxv4i16, MVT::nxv2i32}) {
1194       setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1195       setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1196     }
1197 
1198     // Legalize unpacked bitcasts to REINTERPRET_CAST.
1199     for (auto VT : {MVT::nxv2i16, MVT::nxv4i16, MVT::nxv2i32, MVT::nxv2bf16,
1200                     MVT::nxv2f16, MVT::nxv4f16, MVT::nxv2f32})
1201       setOperationAction(ISD::BITCAST, VT, Custom);
1202 
1203     for (auto VT : {MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1}) {
1204       setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1205       setOperationAction(ISD::SELECT, VT, Custom);
1206       setOperationAction(ISD::SETCC, VT, Custom);
1207       setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
1208       setOperationAction(ISD::TRUNCATE, VT, Custom);
1209       setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
1210       setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
1211       setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
1212 
1213       setOperationAction(ISD::SELECT_CC, VT, Expand);
1214       setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1215       setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1216 
1217       // There are no legal MVT::nxv16f## based types.
1218       if (VT != MVT::nxv16i1) {
1219         setOperationAction(ISD::SINT_TO_FP, VT, Custom);
1220         setOperationAction(ISD::UINT_TO_FP, VT, Custom);
1221       }
1222     }
1223 
1224     // NEON doesn't support masked loads/stores/gathers/scatters, but SVE does
1225     for (auto VT : {MVT::v4f16, MVT::v8f16, MVT::v2f32, MVT::v4f32, MVT::v1f64,
1226                     MVT::v2f64, MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
1227                     MVT::v2i32, MVT::v4i32, MVT::v1i64, MVT::v2i64}) {
1228       setOperationAction(ISD::MLOAD, VT, Custom);
1229       setOperationAction(ISD::MSTORE, VT, Custom);
1230       setOperationAction(ISD::MGATHER, VT, Custom);
1231       setOperationAction(ISD::MSCATTER, VT, Custom);
1232     }
1233 
1234     for (MVT VT : MVT::fp_scalable_vector_valuetypes()) {
1235       for (MVT InnerVT : MVT::fp_scalable_vector_valuetypes()) {
1236         // Avoid marking truncating FP stores as legal to prevent the
1237         // DAGCombiner from creating unsupported truncating stores.
1238         setTruncStoreAction(VT, InnerVT, Expand);
1239         // SVE does not have floating-point extending loads.
1240         setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
1241         setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
1242         setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
1243       }
1244     }
1245 
1246     // SVE supports truncating stores of 64 and 128-bit vectors
1247     setTruncStoreAction(MVT::v2i64, MVT::v2i8, Custom);
1248     setTruncStoreAction(MVT::v2i64, MVT::v2i16, Custom);
1249     setTruncStoreAction(MVT::v2i64, MVT::v2i32, Custom);
1250     setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
1251     setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
1252 
1253     for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32,
1254                     MVT::nxv4f32, MVT::nxv2f64}) {
1255       setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1256       setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1257       setOperationAction(ISD::MGATHER, VT, Custom);
1258       setOperationAction(ISD::MSCATTER, VT, Custom);
1259       setOperationAction(ISD::MLOAD, VT, Custom);
1260       setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
1261       setOperationAction(ISD::SELECT, VT, Custom);
1262       setOperationAction(ISD::FADD, VT, Custom);
1263       setOperationAction(ISD::FDIV, VT, Custom);
1264       setOperationAction(ISD::FMA, VT, Custom);
1265       setOperationAction(ISD::FMAXIMUM, VT, Custom);
1266       setOperationAction(ISD::FMAXNUM, VT, Custom);
1267       setOperationAction(ISD::FMINIMUM, VT, Custom);
1268       setOperationAction(ISD::FMINNUM, VT, Custom);
1269       setOperationAction(ISD::FMUL, VT, Custom);
1270       setOperationAction(ISD::FNEG, VT, Custom);
1271       setOperationAction(ISD::FSUB, VT, Custom);
1272       setOperationAction(ISD::FCEIL, VT, Custom);
1273       setOperationAction(ISD::FFLOOR, VT, Custom);
1274       setOperationAction(ISD::FNEARBYINT, VT, Custom);
1275       setOperationAction(ISD::FRINT, VT, Custom);
1276       setOperationAction(ISD::FROUND, VT, Custom);
1277       setOperationAction(ISD::FROUNDEVEN, VT, Custom);
1278       setOperationAction(ISD::FTRUNC, VT, Custom);
1279       setOperationAction(ISD::FSQRT, VT, Custom);
1280       setOperationAction(ISD::FABS, VT, Custom);
1281       setOperationAction(ISD::FP_EXTEND, VT, Custom);
1282       setOperationAction(ISD::FP_ROUND, VT, Custom);
1283       setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
1284       setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
1285       setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
1286       setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
1287       setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);
1288 
1289       setOperationAction(ISD::SELECT_CC, VT, Expand);
1290     }
1291 
1292     for (auto VT : {MVT::nxv2bf16, MVT::nxv4bf16, MVT::nxv8bf16}) {
1293       setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1294       setOperationAction(ISD::MGATHER, VT, Custom);
1295       setOperationAction(ISD::MSCATTER, VT, Custom);
1296       setOperationAction(ISD::MLOAD, VT, Custom);
1297     }
1298 
1299     setOperationAction(ISD::SPLAT_VECTOR, MVT::nxv8bf16, Custom);
1300 
1301     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i8, Custom);
1302     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
1303 
1304     // NOTE: Currently this has to happen after computeRegisterProperties rather
1305     // than the preferred option of combining it with the addRegisterClass call.
1306     if (Subtarget->useSVEForFixedLengthVectors()) {
1307       for (MVT VT : MVT::integer_fixedlen_vector_valuetypes())
1308         if (useSVEForFixedLengthVectorVT(VT))
1309           addTypeForFixedLengthSVE(VT);
1310       for (MVT VT : MVT::fp_fixedlen_vector_valuetypes())
1311         if (useSVEForFixedLengthVectorVT(VT))
1312           addTypeForFixedLengthSVE(VT);
1313 
1314       // 64bit results can mean a bigger than NEON input.
1315       for (auto VT : {MVT::v8i8, MVT::v4i16})
1316         setOperationAction(ISD::TRUNCATE, VT, Custom);
1317       setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom);
1318 
1319       // 128bit results imply a bigger than NEON input.
1320       for (auto VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
1321         setOperationAction(ISD::TRUNCATE, VT, Custom);
1322       for (auto VT : {MVT::v8f16, MVT::v4f32})
1323         setOperationAction(ISD::FP_ROUND, VT, Custom);
1324 
1325       // These operations are not supported on NEON but SVE can do them.
1326       setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom);
1327       setOperationAction(ISD::CTLZ, MVT::v1i64, Custom);
1328       setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1329       setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
1330       setOperationAction(ISD::MUL, MVT::v1i64, Custom);
1331       setOperationAction(ISD::MUL, MVT::v2i64, Custom);
1332       setOperationAction(ISD::MULHS, MVT::v1i64, Custom);
1333       setOperationAction(ISD::MULHS, MVT::v2i64, Custom);
1334       setOperationAction(ISD::MULHU, MVT::v1i64, Custom);
1335       setOperationAction(ISD::MULHU, MVT::v2i64, Custom);
1336       setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
1337       setOperationAction(ISD::SDIV, MVT::v16i8, Custom);
1338       setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
1339       setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1340       setOperationAction(ISD::SDIV, MVT::v2i32, Custom);
1341       setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1342       setOperationAction(ISD::SDIV, MVT::v1i64, Custom);
1343       setOperationAction(ISD::SDIV, MVT::v2i64, Custom);
1344       setOperationAction(ISD::SMAX, MVT::v1i64, Custom);
1345       setOperationAction(ISD::SMAX, MVT::v2i64, Custom);
1346       setOperationAction(ISD::SMIN, MVT::v1i64, Custom);
1347       setOperationAction(ISD::SMIN, MVT::v2i64, Custom);
1348       setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
1349       setOperationAction(ISD::UDIV, MVT::v16i8, Custom);
1350       setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
1351       setOperationAction(ISD::UDIV, MVT::v8i16, Custom);
1352       setOperationAction(ISD::UDIV, MVT::v2i32, Custom);
1353       setOperationAction(ISD::UDIV, MVT::v4i32, Custom);
1354       setOperationAction(ISD::UDIV, MVT::v1i64, Custom);
1355       setOperationAction(ISD::UDIV, MVT::v2i64, Custom);
1356       setOperationAction(ISD::UMAX, MVT::v1i64, Custom);
1357       setOperationAction(ISD::UMAX, MVT::v2i64, Custom);
1358       setOperationAction(ISD::UMIN, MVT::v1i64, Custom);
1359       setOperationAction(ISD::UMIN, MVT::v2i64, Custom);
1360       setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom);
1361       setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
1362       setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
1363       setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
1364 
1365       // Int operations with no NEON support.
1366       for (auto VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
1367                       MVT::v2i32, MVT::v4i32, MVT::v2i64}) {
1368         setOperationAction(ISD::BITREVERSE, VT, Custom);
1369         setOperationAction(ISD::CTTZ, VT, Custom);
1370         setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
1371         setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
1372         setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
1373       }
1374 
1375       // FP operations with no NEON support.
1376       for (auto VT : {MVT::v4f16, MVT::v8f16, MVT::v2f32, MVT::v4f32,
1377                       MVT::v1f64, MVT::v2f64})
1378         setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
1379 
1380       // Use SVE for vectors with more than 2 elements.
1381       for (auto VT : {MVT::v4f16, MVT::v8f16, MVT::v4f32})
1382         setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
1383     }
1384 
1385     setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv2i1, MVT::nxv2i64);
1386     setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv4i1, MVT::nxv4i32);
1387     setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv8i1, MVT::nxv8i16);
1388     setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv16i1, MVT::nxv16i8);
1389   }
1390 
1391   PredictableSelectIsExpensive = Subtarget->predictableSelectIsExpensive();
1392 }
1393 
1394 void AArch64TargetLowering::addTypeForNEON(MVT VT) {
1395   assert(VT.isVector() && "VT should be a vector type");
1396 
1397   if (VT.isFloatingPoint()) {
1398     MVT PromoteTo = EVT(VT).changeVectorElementTypeToInteger().getSimpleVT();
1399     setOperationPromotedToType(ISD::LOAD, VT, PromoteTo);
1400     setOperationPromotedToType(ISD::STORE, VT, PromoteTo);
1401   }
1402 
1403   // Mark vector float intrinsics as expand.
1404   if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
1405     setOperationAction(ISD::FSIN, VT, Expand);
1406     setOperationAction(ISD::FCOS, VT, Expand);
1407     setOperationAction(ISD::FPOW, VT, Expand);
1408     setOperationAction(ISD::FLOG, VT, Expand);
1409     setOperationAction(ISD::FLOG2, VT, Expand);
1410     setOperationAction(ISD::FLOG10, VT, Expand);
1411     setOperationAction(ISD::FEXP, VT, Expand);
1412     setOperationAction(ISD::FEXP2, VT, Expand);
1413   }
1414 
1415   // But we do support custom-lowering for FCOPYSIGN.
1416   if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
1417       ((VT == MVT::v4f16 || VT == MVT::v8f16) && Subtarget->hasFullFP16()))
1418     setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1419 
1420   setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1421   setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1422   setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1423   setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1424   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1425   setOperationAction(ISD::SRA, VT, Custom);
1426   setOperationAction(ISD::SRL, VT, Custom);
1427   setOperationAction(ISD::SHL, VT, Custom);
1428   setOperationAction(ISD::OR, VT, Custom);
1429   setOperationAction(ISD::SETCC, VT, Custom);
1430   setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
1431 
1432   setOperationAction(ISD::SELECT, VT, Expand);
1433   setOperationAction(ISD::SELECT_CC, VT, Expand);
1434   setOperationAction(ISD::VSELECT, VT, Expand);
1435   for (MVT InnerVT : MVT::all_valuetypes())
1436     setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
1437 
1438   // CNT supports only B element sizes, then use UADDLP to widen.
1439   if (VT != MVT::v8i8 && VT != MVT::v16i8)
1440     setOperationAction(ISD::CTPOP, VT, Custom);
1441 
1442   setOperationAction(ISD::UDIV, VT, Expand);
1443   setOperationAction(ISD::SDIV, VT, Expand);
1444   setOperationAction(ISD::UREM, VT, Expand);
1445   setOperationAction(ISD::SREM, VT, Expand);
1446   setOperationAction(ISD::FREM, VT, Expand);
1447 
1448   setOperationAction(ISD::FP_TO_SINT, VT, Custom);
1449   setOperationAction(ISD::FP_TO_UINT, VT, Custom);
1450 
1451   if (!VT.isFloatingPoint())
1452     setOperationAction(ISD::ABS, VT, Legal);
1453 
1454   // [SU][MIN|MAX] are available for all NEON types apart from i64.
1455   if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64)
1456     for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
1457       setOperationAction(Opcode, VT, Legal);
1458 
1459   // F[MIN|MAX][NUM|NAN] are available for all FP NEON types.
1460   if (VT.isFloatingPoint() &&
1461       VT.getVectorElementType() != MVT::bf16 &&
1462       (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
1463     for (unsigned Opcode :
1464          {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})
1465       setOperationAction(Opcode, VT, Legal);
1466 
1467   if (Subtarget->isLittleEndian()) {
1468     for (unsigned im = (unsigned)ISD::PRE_INC;
1469          im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1470       setIndexedLoadAction(im, VT, Legal);
1471       setIndexedStoreAction(im, VT, Legal);
1472     }
1473   }
1474 }
1475 
1476 void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
1477   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
1478 
1479   // By default everything must be expanded.
1480   for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op)
1481     setOperationAction(Op, VT, Expand);
1482 
1483   // We use EXTRACT_SUBVECTOR to "cast" a scalable vector to a fixed length one.
1484   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1485 
1486   if (VT.isFloatingPoint()) {
1487     setCondCodeAction(ISD::SETO, VT, Expand);
1488     setCondCodeAction(ISD::SETOLT, VT, Expand);
1489     setCondCodeAction(ISD::SETLT, VT, Expand);
1490     setCondCodeAction(ISD::SETOLE, VT, Expand);
1491     setCondCodeAction(ISD::SETLE, VT, Expand);
1492     setCondCodeAction(ISD::SETULT, VT, Expand);
1493     setCondCodeAction(ISD::SETULE, VT, Expand);
1494     setCondCodeAction(ISD::SETUGE, VT, Expand);
1495     setCondCodeAction(ISD::SETUGT, VT, Expand);
1496     setCondCodeAction(ISD::SETUEQ, VT, Expand);
1497     setCondCodeAction(ISD::SETUNE, VT, Expand);
1498   }
1499 
1500   // Mark integer truncating stores as having custom lowering
1501   if (VT.isInteger()) {
1502     MVT InnerVT = VT.changeVectorElementType(MVT::i8);
1503     while (InnerVT != VT) {
1504       setTruncStoreAction(VT, InnerVT, Custom);
1505       InnerVT = InnerVT.changeVectorElementType(
1506           MVT::getIntegerVT(2 * InnerVT.getScalarSizeInBits()));
1507     }
1508   }
1509 
1510   // Lower fixed length vector operations to scalable equivalents.
1511   setOperationAction(ISD::ABS, VT, Custom);
1512   setOperationAction(ISD::ADD, VT, Custom);
1513   setOperationAction(ISD::AND, VT, Custom);
1514   setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1515   setOperationAction(ISD::BITCAST, VT, Custom);
1516   setOperationAction(ISD::BITREVERSE, VT, Custom);
1517   setOperationAction(ISD::BSWAP, VT, Custom);
1518   setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1519   setOperationAction(ISD::CTLZ, VT, Custom);
1520   setOperationAction(ISD::CTPOP, VT, Custom);
1521   setOperationAction(ISD::CTTZ, VT, Custom);
1522   setOperationAction(ISD::FABS, VT, Custom);
1523   setOperationAction(ISD::FADD, VT, Custom);
1524   setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1525   setOperationAction(ISD::FCEIL, VT, Custom);
1526   setOperationAction(ISD::FDIV, VT, Custom);
1527   setOperationAction(ISD::FFLOOR, VT, Custom);
1528   setOperationAction(ISD::FMA, VT, Custom);
1529   setOperationAction(ISD::FMAXIMUM, VT, Custom);
1530   setOperationAction(ISD::FMAXNUM, VT, Custom);
1531   setOperationAction(ISD::FMINIMUM, VT, Custom);
1532   setOperationAction(ISD::FMINNUM, VT, Custom);
1533   setOperationAction(ISD::FMUL, VT, Custom);
1534   setOperationAction(ISD::FNEARBYINT, VT, Custom);
1535   setOperationAction(ISD::FNEG, VT, Custom);
1536   setOperationAction(ISD::FP_EXTEND, VT, Custom);
1537   setOperationAction(ISD::FP_ROUND, VT, Custom);
1538   setOperationAction(ISD::FP_TO_SINT, VT, Custom);
1539   setOperationAction(ISD::FP_TO_UINT, VT, Custom);
1540   setOperationAction(ISD::FRINT, VT, Custom);
1541   setOperationAction(ISD::FROUND, VT, Custom);
1542   setOperationAction(ISD::FROUNDEVEN, VT, Custom);
1543   setOperationAction(ISD::FSQRT, VT, Custom);
1544   setOperationAction(ISD::FSUB, VT, Custom);
1545   setOperationAction(ISD::FTRUNC, VT, Custom);
1546   setOperationAction(ISD::LOAD, VT, Custom);
1547   setOperationAction(ISD::MGATHER, VT, Custom);
1548   setOperationAction(ISD::MLOAD, VT, Custom);
1549   setOperationAction(ISD::MSCATTER, VT, Custom);
1550   setOperationAction(ISD::MSTORE, VT, Custom);
1551   setOperationAction(ISD::MUL, VT, Custom);
1552   setOperationAction(ISD::MULHS, VT, Custom);
1553   setOperationAction(ISD::MULHU, VT, Custom);
1554   setOperationAction(ISD::OR, VT, Custom);
1555   setOperationAction(ISD::SDIV, VT, Custom);
1556   setOperationAction(ISD::SELECT, VT, Custom);
1557   setOperationAction(ISD::SETCC, VT, Custom);
1558   setOperationAction(ISD::SHL, VT, Custom);
1559   setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1560   setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
1561   setOperationAction(ISD::SINT_TO_FP, VT, Custom);
1562   setOperationAction(ISD::SMAX, VT, Custom);
1563   setOperationAction(ISD::SMIN, VT, Custom);
1564   setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
1565   setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);
1566   setOperationAction(ISD::SRA, VT, Custom);
1567   setOperationAction(ISD::SRL, VT, Custom);
1568   setOperationAction(ISD::STORE, VT, Custom);
1569   setOperationAction(ISD::SUB, VT, Custom);
1570   setOperationAction(ISD::TRUNCATE, VT, Custom);
1571   setOperationAction(ISD::UDIV, VT, Custom);
1572   setOperationAction(ISD::UINT_TO_FP, VT, Custom);
1573   setOperationAction(ISD::UMAX, VT, Custom);
1574   setOperationAction(ISD::UMIN, VT, Custom);
1575   setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
1576   setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
1577   setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
1578   setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
1579   setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
1580   setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
1581   setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
1582   setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1583   setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
1584   setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
1585   setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
1586   setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
1587   setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
1588   setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1589   setOperationAction(ISD::VSELECT, VT, Custom);
1590   setOperationAction(ISD::XOR, VT, Custom);
1591   setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1592 }
1593 
1594 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
1595   addRegisterClass(VT, &AArch64::FPR64RegClass);
1596   addTypeForNEON(VT);
1597 }
1598 
1599 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
1600   addRegisterClass(VT, &AArch64::FPR128RegClass);
1601   addTypeForNEON(VT);
1602 }
1603 
1604 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &,
1605                                               LLVMContext &C, EVT VT) const {
1606   if (!VT.isVector())
1607     return MVT::i32;
1608   if (VT.isScalableVector())
1609     return EVT::getVectorVT(C, MVT::i1, VT.getVectorElementCount());
1610   return VT.changeVectorElementTypeToInteger();
1611 }
1612 
1613 static bool optimizeLogicalImm(SDValue Op, unsigned Size, uint64_t Imm,
1614                                const APInt &Demanded,
1615                                TargetLowering::TargetLoweringOpt &TLO,
1616                                unsigned NewOpc) {
1617   uint64_t OldImm = Imm, NewImm, Enc;
1618   uint64_t Mask = ((uint64_t)(-1LL) >> (64 - Size)), OrigMask = Mask;
1619 
1620   // Return if the immediate is already all zeros, all ones, a bimm32 or a
1621   // bimm64.
1622   if (Imm == 0 || Imm == Mask ||
1623       AArch64_AM::isLogicalImmediate(Imm & Mask, Size))
1624     return false;
1625 
1626   unsigned EltSize = Size;
1627   uint64_t DemandedBits = Demanded.getZExtValue();
1628 
1629   // Clear bits that are not demanded.
1630   Imm &= DemandedBits;
1631 
1632   while (true) {
1633     // The goal here is to set the non-demanded bits in a way that minimizes
1634     // the number of switching between 0 and 1. In order to achieve this goal,
1635     // we set the non-demanded bits to the value of the preceding demanded bits.
1636     // For example, if we have an immediate 0bx10xx0x1 ('x' indicates a
1637     // non-demanded bit), we copy bit0 (1) to the least significant 'x',
1638     // bit2 (0) to 'xx', and bit6 (1) to the most significant 'x'.
1639     // The final result is 0b11000011.
1640     uint64_t NonDemandedBits = ~DemandedBits;
1641     uint64_t InvertedImm = ~Imm & DemandedBits;
1642     uint64_t RotatedImm =
1643         ((InvertedImm << 1) | (InvertedImm >> (EltSize - 1) & 1)) &
1644         NonDemandedBits;
1645     uint64_t Sum = RotatedImm + NonDemandedBits;
1646     bool Carry = NonDemandedBits & ~Sum & (1ULL << (EltSize - 1));
1647     uint64_t Ones = (Sum + Carry) & NonDemandedBits;
1648     NewImm = (Imm | Ones) & Mask;
1649 
1650     // If NewImm or its bitwise NOT is a shifted mask, it is a bitmask immediate
1651     // or all-ones or all-zeros, in which case we can stop searching. Otherwise,
1652     // we halve the element size and continue the search.
1653     if (isShiftedMask_64(NewImm) || isShiftedMask_64(~(NewImm | ~Mask)))
1654       break;
1655 
1656     // We cannot shrink the element size any further if it is 2-bits.
1657     if (EltSize == 2)
1658       return false;
1659 
1660     EltSize /= 2;
1661     Mask >>= EltSize;
1662     uint64_t Hi = Imm >> EltSize, DemandedBitsHi = DemandedBits >> EltSize;
1663 
1664     // Return if there is mismatch in any of the demanded bits of Imm and Hi.
1665     if (((Imm ^ Hi) & (DemandedBits & DemandedBitsHi) & Mask) != 0)
1666       return false;
1667 
1668     // Merge the upper and lower halves of Imm and DemandedBits.
1669     Imm |= Hi;
1670     DemandedBits |= DemandedBitsHi;
1671   }
1672 
1673   ++NumOptimizedImms;
1674 
1675   // Replicate the element across the register width.
1676   while (EltSize < Size) {
1677     NewImm |= NewImm << EltSize;
1678     EltSize *= 2;
1679   }
1680 
1681   (void)OldImm;
1682   assert(((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 &&
1683          "demanded bits should never be altered");
1684   assert(OldImm != NewImm && "the new imm shouldn't be equal to the old imm");
1685 
1686   // Create the new constant immediate node.
1687   EVT VT = Op.getValueType();
1688   SDLoc DL(Op);
1689   SDValue New;
1690 
1691   // If the new constant immediate is all-zeros or all-ones, let the target
1692   // independent DAG combine optimize this node.
1693   if (NewImm == 0 || NewImm == OrigMask) {
1694     New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
1695                           TLO.DAG.getConstant(NewImm, DL, VT));
1696   // Otherwise, create a machine node so that target independent DAG combine
1697   // doesn't undo this optimization.
1698   } else {
1699     Enc = AArch64_AM::encodeLogicalImmediate(NewImm, Size);
1700     SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT);
1701     New = SDValue(
1702         TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0);
1703   }
1704 
1705   return TLO.CombineTo(Op, New);
1706 }
1707 
1708 bool AArch64TargetLowering::targetShrinkDemandedConstant(
1709     SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1710     TargetLoweringOpt &TLO) const {
1711   // Delay this optimization to as late as possible.
1712   if (!TLO.LegalOps)
1713     return false;
1714 
1715   if (!EnableOptimizeLogicalImm)
1716     return false;
1717 
1718   EVT VT = Op.getValueType();
1719   if (VT.isVector())
1720     return false;
1721 
1722   unsigned Size = VT.getSizeInBits();
1723   assert((Size == 32 || Size == 64) &&
1724          "i32 or i64 is expected after legalization.");
1725 
1726   // Exit early if we demand all bits.
1727   if (DemandedBits.countPopulation() == Size)
1728     return false;
1729 
1730   unsigned NewOpc;
1731   switch (Op.getOpcode()) {
1732   default:
1733     return false;
1734   case ISD::AND:
1735     NewOpc = Size == 32 ? AArch64::ANDWri : AArch64::ANDXri;
1736     break;
1737   case ISD::OR:
1738     NewOpc = Size == 32 ? AArch64::ORRWri : AArch64::ORRXri;
1739     break;
1740   case ISD::XOR:
1741     NewOpc = Size == 32 ? AArch64::EORWri : AArch64::EORXri;
1742     break;
1743   }
1744   ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1745   if (!C)
1746     return false;
1747   uint64_t Imm = C->getZExtValue();
1748   return optimizeLogicalImm(Op, Size, Imm, DemandedBits, TLO, NewOpc);
1749 }
1750 
1751 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
1752 /// Mask are known to be either zero or one and return them Known.
1753 void AArch64TargetLowering::computeKnownBitsForTargetNode(
1754     const SDValue Op, KnownBits &Known,
1755     const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
1756   switch (Op.getOpcode()) {
1757   default:
1758     break;
1759   case AArch64ISD::CSEL: {
1760     KnownBits Known2;
1761     Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1762     Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1763     Known = KnownBits::commonBits(Known, Known2);
1764     break;
1765   }
1766   case AArch64ISD::LOADgot:
1767   case AArch64ISD::ADDlow: {
1768     if (!Subtarget->isTargetILP32())
1769       break;
1770     // In ILP32 mode all valid pointers are in the low 4GB of the address-space.
1771     Known.Zero = APInt::getHighBitsSet(64, 32);
1772     break;
1773   }
1774   case ISD::INTRINSIC_W_CHAIN: {
1775     ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
1776     Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
1777     switch (IntID) {
1778     default: return;
1779     case Intrinsic::aarch64_ldaxr:
1780     case Intrinsic::aarch64_ldxr: {
1781       unsigned BitWidth = Known.getBitWidth();
1782       EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
1783       unsigned MemBits = VT.getScalarSizeInBits();
1784       Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
1785       return;
1786     }
1787     }
1788     break;
1789   }
1790   case ISD::INTRINSIC_WO_CHAIN:
1791   case ISD::INTRINSIC_VOID: {
1792     unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1793     switch (IntNo) {
1794     default:
1795       break;
1796     case Intrinsic::aarch64_neon_umaxv:
1797     case Intrinsic::aarch64_neon_uminv: {
1798       // Figure out the datatype of the vector operand. The UMINV instruction
1799       // will zero extend the result, so we can mark as known zero all the
1800       // bits larger than the element datatype. 32-bit or larget doesn't need
1801       // this as those are legal types and will be handled by isel directly.
1802       MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
1803       unsigned BitWidth = Known.getBitWidth();
1804       if (VT == MVT::v8i8 || VT == MVT::v16i8) {
1805         assert(BitWidth >= 8 && "Unexpected width!");
1806         APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
1807         Known.Zero |= Mask;
1808       } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
1809         assert(BitWidth >= 16 && "Unexpected width!");
1810         APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
1811         Known.Zero |= Mask;
1812       }
1813       break;
1814     } break;
1815     }
1816   }
1817   }
1818 }
1819 
1820 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
1821                                                   EVT) const {
1822   return MVT::i64;
1823 }
1824 
1825 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(
1826     EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
1827     bool *Fast) const {
1828   if (Subtarget->requiresStrictAlign())
1829     return false;
1830 
1831   if (Fast) {
1832     // Some CPUs are fine with unaligned stores except for 128-bit ones.
1833     *Fast = !Subtarget->isMisaligned128StoreSlow() || VT.getStoreSize() != 16 ||
1834             // See comments in performSTORECombine() for more details about
1835             // these conditions.
1836 
1837             // Code that uses clang vector extensions can mark that it
1838             // wants unaligned accesses to be treated as fast by
1839             // underspecifying alignment to be 1 or 2.
1840             Alignment <= 2 ||
1841 
1842             // Disregard v2i64. Memcpy lowering produces those and splitting
1843             // them regresses performance on micro-benchmarks and olden/bh.
1844             VT == MVT::v2i64;
1845   }
1846   return true;
1847 }
1848 
1849 // Same as above but handling LLTs instead.
1850 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(
1851     LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
1852     bool *Fast) const {
1853   if (Subtarget->requiresStrictAlign())
1854     return false;
1855 
1856   if (Fast) {
1857     // Some CPUs are fine with unaligned stores except for 128-bit ones.
1858     *Fast = !Subtarget->isMisaligned128StoreSlow() ||
1859             Ty.getSizeInBytes() != 16 ||
1860             // See comments in performSTORECombine() for more details about
1861             // these conditions.
1862 
1863             // Code that uses clang vector extensions can mark that it
1864             // wants unaligned accesses to be treated as fast by
1865             // underspecifying alignment to be 1 or 2.
1866             Alignment <= 2 ||
1867 
1868             // Disregard v2i64. Memcpy lowering produces those and splitting
1869             // them regresses performance on micro-benchmarks and olden/bh.
1870             Ty == LLT::fixed_vector(2, 64);
1871   }
1872   return true;
1873 }
1874 
1875 FastISel *
1876 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1877                                       const TargetLibraryInfo *libInfo) const {
1878   return AArch64::createFastISel(funcInfo, libInfo);
1879 }
1880 
1881 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
1882 #define MAKE_CASE(V)                                                           \
1883   case V:                                                                      \
1884     return #V;
1885   switch ((AArch64ISD::NodeType)Opcode) {
1886   case AArch64ISD::FIRST_NUMBER:
1887     break;
1888     MAKE_CASE(AArch64ISD::CALL)
1889     MAKE_CASE(AArch64ISD::ADRP)
1890     MAKE_CASE(AArch64ISD::ADR)
1891     MAKE_CASE(AArch64ISD::ADDlow)
1892     MAKE_CASE(AArch64ISD::LOADgot)
1893     MAKE_CASE(AArch64ISD::RET_FLAG)
1894     MAKE_CASE(AArch64ISD::BRCOND)
1895     MAKE_CASE(AArch64ISD::CSEL)
1896     MAKE_CASE(AArch64ISD::CSINV)
1897     MAKE_CASE(AArch64ISD::CSNEG)
1898     MAKE_CASE(AArch64ISD::CSINC)
1899     MAKE_CASE(AArch64ISD::THREAD_POINTER)
1900     MAKE_CASE(AArch64ISD::TLSDESC_CALLSEQ)
1901     MAKE_CASE(AArch64ISD::ADD_PRED)
1902     MAKE_CASE(AArch64ISD::MUL_PRED)
1903     MAKE_CASE(AArch64ISD::MULHS_PRED)
1904     MAKE_CASE(AArch64ISD::MULHU_PRED)
1905     MAKE_CASE(AArch64ISD::SDIV_PRED)
1906     MAKE_CASE(AArch64ISD::SHL_PRED)
1907     MAKE_CASE(AArch64ISD::SMAX_PRED)
1908     MAKE_CASE(AArch64ISD::SMIN_PRED)
1909     MAKE_CASE(AArch64ISD::SRA_PRED)
1910     MAKE_CASE(AArch64ISD::SRL_PRED)
1911     MAKE_CASE(AArch64ISD::SUB_PRED)
1912     MAKE_CASE(AArch64ISD::UDIV_PRED)
1913     MAKE_CASE(AArch64ISD::UMAX_PRED)
1914     MAKE_CASE(AArch64ISD::UMIN_PRED)
1915     MAKE_CASE(AArch64ISD::FNEG_MERGE_PASSTHRU)
1916     MAKE_CASE(AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU)
1917     MAKE_CASE(AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU)
1918     MAKE_CASE(AArch64ISD::FCEIL_MERGE_PASSTHRU)
1919     MAKE_CASE(AArch64ISD::FFLOOR_MERGE_PASSTHRU)
1920     MAKE_CASE(AArch64ISD::FNEARBYINT_MERGE_PASSTHRU)
1921     MAKE_CASE(AArch64ISD::FRINT_MERGE_PASSTHRU)
1922     MAKE_CASE(AArch64ISD::FROUND_MERGE_PASSTHRU)
1923     MAKE_CASE(AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU)
1924     MAKE_CASE(AArch64ISD::FTRUNC_MERGE_PASSTHRU)
1925     MAKE_CASE(AArch64ISD::FP_ROUND_MERGE_PASSTHRU)
1926     MAKE_CASE(AArch64ISD::FP_EXTEND_MERGE_PASSTHRU)
1927     MAKE_CASE(AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU)
1928     MAKE_CASE(AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU)
1929     MAKE_CASE(AArch64ISD::FCVTZU_MERGE_PASSTHRU)
1930     MAKE_CASE(AArch64ISD::FCVTZS_MERGE_PASSTHRU)
1931     MAKE_CASE(AArch64ISD::FSQRT_MERGE_PASSTHRU)
1932     MAKE_CASE(AArch64ISD::FRECPX_MERGE_PASSTHRU)
1933     MAKE_CASE(AArch64ISD::FABS_MERGE_PASSTHRU)
1934     MAKE_CASE(AArch64ISD::ABS_MERGE_PASSTHRU)
1935     MAKE_CASE(AArch64ISD::NEG_MERGE_PASSTHRU)
1936     MAKE_CASE(AArch64ISD::SETCC_MERGE_ZERO)
1937     MAKE_CASE(AArch64ISD::ADC)
1938     MAKE_CASE(AArch64ISD::SBC)
1939     MAKE_CASE(AArch64ISD::ADDS)
1940     MAKE_CASE(AArch64ISD::SUBS)
1941     MAKE_CASE(AArch64ISD::ADCS)
1942     MAKE_CASE(AArch64ISD::SBCS)
1943     MAKE_CASE(AArch64ISD::ANDS)
1944     MAKE_CASE(AArch64ISD::CCMP)
1945     MAKE_CASE(AArch64ISD::CCMN)
1946     MAKE_CASE(AArch64ISD::FCCMP)
1947     MAKE_CASE(AArch64ISD::FCMP)
1948     MAKE_CASE(AArch64ISD::STRICT_FCMP)
1949     MAKE_CASE(AArch64ISD::STRICT_FCMPE)
1950     MAKE_CASE(AArch64ISD::DUP)
1951     MAKE_CASE(AArch64ISD::DUPLANE8)
1952     MAKE_CASE(AArch64ISD::DUPLANE16)
1953     MAKE_CASE(AArch64ISD::DUPLANE32)
1954     MAKE_CASE(AArch64ISD::DUPLANE64)
1955     MAKE_CASE(AArch64ISD::MOVI)
1956     MAKE_CASE(AArch64ISD::MOVIshift)
1957     MAKE_CASE(AArch64ISD::MOVIedit)
1958     MAKE_CASE(AArch64ISD::MOVImsl)
1959     MAKE_CASE(AArch64ISD::FMOV)
1960     MAKE_CASE(AArch64ISD::MVNIshift)
1961     MAKE_CASE(AArch64ISD::MVNImsl)
1962     MAKE_CASE(AArch64ISD::BICi)
1963     MAKE_CASE(AArch64ISD::ORRi)
1964     MAKE_CASE(AArch64ISD::BSP)
1965     MAKE_CASE(AArch64ISD::EXTR)
1966     MAKE_CASE(AArch64ISD::ZIP1)
1967     MAKE_CASE(AArch64ISD::ZIP2)
1968     MAKE_CASE(AArch64ISD::UZP1)
1969     MAKE_CASE(AArch64ISD::UZP2)
1970     MAKE_CASE(AArch64ISD::TRN1)
1971     MAKE_CASE(AArch64ISD::TRN2)
1972     MAKE_CASE(AArch64ISD::REV16)
1973     MAKE_CASE(AArch64ISD::REV32)
1974     MAKE_CASE(AArch64ISD::REV64)
1975     MAKE_CASE(AArch64ISD::EXT)
1976     MAKE_CASE(AArch64ISD::SPLICE)
1977     MAKE_CASE(AArch64ISD::VSHL)
1978     MAKE_CASE(AArch64ISD::VLSHR)
1979     MAKE_CASE(AArch64ISD::VASHR)
1980     MAKE_CASE(AArch64ISD::VSLI)
1981     MAKE_CASE(AArch64ISD::VSRI)
1982     MAKE_CASE(AArch64ISD::CMEQ)
1983     MAKE_CASE(AArch64ISD::CMGE)
1984     MAKE_CASE(AArch64ISD::CMGT)
1985     MAKE_CASE(AArch64ISD::CMHI)
1986     MAKE_CASE(AArch64ISD::CMHS)
1987     MAKE_CASE(AArch64ISD::FCMEQ)
1988     MAKE_CASE(AArch64ISD::FCMGE)
1989     MAKE_CASE(AArch64ISD::FCMGT)
1990     MAKE_CASE(AArch64ISD::CMEQz)
1991     MAKE_CASE(AArch64ISD::CMGEz)
1992     MAKE_CASE(AArch64ISD::CMGTz)
1993     MAKE_CASE(AArch64ISD::CMLEz)
1994     MAKE_CASE(AArch64ISD::CMLTz)
1995     MAKE_CASE(AArch64ISD::FCMEQz)
1996     MAKE_CASE(AArch64ISD::FCMGEz)
1997     MAKE_CASE(AArch64ISD::FCMGTz)
1998     MAKE_CASE(AArch64ISD::FCMLEz)
1999     MAKE_CASE(AArch64ISD::FCMLTz)
2000     MAKE_CASE(AArch64ISD::SADDV)
2001     MAKE_CASE(AArch64ISD::UADDV)
2002     MAKE_CASE(AArch64ISD::SRHADD)
2003     MAKE_CASE(AArch64ISD::URHADD)
2004     MAKE_CASE(AArch64ISD::SHADD)
2005     MAKE_CASE(AArch64ISD::UHADD)
2006     MAKE_CASE(AArch64ISD::SDOT)
2007     MAKE_CASE(AArch64ISD::UDOT)
2008     MAKE_CASE(AArch64ISD::SMINV)
2009     MAKE_CASE(AArch64ISD::UMINV)
2010     MAKE_CASE(AArch64ISD::SMAXV)
2011     MAKE_CASE(AArch64ISD::UMAXV)
2012     MAKE_CASE(AArch64ISD::SADDV_PRED)
2013     MAKE_CASE(AArch64ISD::UADDV_PRED)
2014     MAKE_CASE(AArch64ISD::SMAXV_PRED)
2015     MAKE_CASE(AArch64ISD::UMAXV_PRED)
2016     MAKE_CASE(AArch64ISD::SMINV_PRED)
2017     MAKE_CASE(AArch64ISD::UMINV_PRED)
2018     MAKE_CASE(AArch64ISD::ORV_PRED)
2019     MAKE_CASE(AArch64ISD::EORV_PRED)
2020     MAKE_CASE(AArch64ISD::ANDV_PRED)
2021     MAKE_CASE(AArch64ISD::CLASTA_N)
2022     MAKE_CASE(AArch64ISD::CLASTB_N)
2023     MAKE_CASE(AArch64ISD::LASTA)
2024     MAKE_CASE(AArch64ISD::LASTB)
2025     MAKE_CASE(AArch64ISD::REINTERPRET_CAST)
2026     MAKE_CASE(AArch64ISD::TBL)
2027     MAKE_CASE(AArch64ISD::FADD_PRED)
2028     MAKE_CASE(AArch64ISD::FADDA_PRED)
2029     MAKE_CASE(AArch64ISD::FADDV_PRED)
2030     MAKE_CASE(AArch64ISD::FDIV_PRED)
2031     MAKE_CASE(AArch64ISD::FMA_PRED)
2032     MAKE_CASE(AArch64ISD::FMAX_PRED)
2033     MAKE_CASE(AArch64ISD::FMAXV_PRED)
2034     MAKE_CASE(AArch64ISD::FMAXNM_PRED)
2035     MAKE_CASE(AArch64ISD::FMAXNMV_PRED)
2036     MAKE_CASE(AArch64ISD::FMIN_PRED)
2037     MAKE_CASE(AArch64ISD::FMINV_PRED)
2038     MAKE_CASE(AArch64ISD::FMINNM_PRED)
2039     MAKE_CASE(AArch64ISD::FMINNMV_PRED)
2040     MAKE_CASE(AArch64ISD::FMUL_PRED)
2041     MAKE_CASE(AArch64ISD::FSUB_PRED)
2042     MAKE_CASE(AArch64ISD::BIC)
2043     MAKE_CASE(AArch64ISD::BIT)
2044     MAKE_CASE(AArch64ISD::CBZ)
2045     MAKE_CASE(AArch64ISD::CBNZ)
2046     MAKE_CASE(AArch64ISD::TBZ)
2047     MAKE_CASE(AArch64ISD::TBNZ)
2048     MAKE_CASE(AArch64ISD::TC_RETURN)
2049     MAKE_CASE(AArch64ISD::PREFETCH)
2050     MAKE_CASE(AArch64ISD::SITOF)
2051     MAKE_CASE(AArch64ISD::UITOF)
2052     MAKE_CASE(AArch64ISD::NVCAST)
2053     MAKE_CASE(AArch64ISD::MRS)
2054     MAKE_CASE(AArch64ISD::SQSHL_I)
2055     MAKE_CASE(AArch64ISD::UQSHL_I)
2056     MAKE_CASE(AArch64ISD::SRSHR_I)
2057     MAKE_CASE(AArch64ISD::URSHR_I)
2058     MAKE_CASE(AArch64ISD::SQSHLU_I)
2059     MAKE_CASE(AArch64ISD::WrapperLarge)
2060     MAKE_CASE(AArch64ISD::LD2post)
2061     MAKE_CASE(AArch64ISD::LD3post)
2062     MAKE_CASE(AArch64ISD::LD4post)
2063     MAKE_CASE(AArch64ISD::ST2post)
2064     MAKE_CASE(AArch64ISD::ST3post)
2065     MAKE_CASE(AArch64ISD::ST4post)
2066     MAKE_CASE(AArch64ISD::LD1x2post)
2067     MAKE_CASE(AArch64ISD::LD1x3post)
2068     MAKE_CASE(AArch64ISD::LD1x4post)
2069     MAKE_CASE(AArch64ISD::ST1x2post)
2070     MAKE_CASE(AArch64ISD::ST1x3post)
2071     MAKE_CASE(AArch64ISD::ST1x4post)
2072     MAKE_CASE(AArch64ISD::LD1DUPpost)
2073     MAKE_CASE(AArch64ISD::LD2DUPpost)
2074     MAKE_CASE(AArch64ISD::LD3DUPpost)
2075     MAKE_CASE(AArch64ISD::LD4DUPpost)
2076     MAKE_CASE(AArch64ISD::LD1LANEpost)
2077     MAKE_CASE(AArch64ISD::LD2LANEpost)
2078     MAKE_CASE(AArch64ISD::LD3LANEpost)
2079     MAKE_CASE(AArch64ISD::LD4LANEpost)
2080     MAKE_CASE(AArch64ISD::ST2LANEpost)
2081     MAKE_CASE(AArch64ISD::ST3LANEpost)
2082     MAKE_CASE(AArch64ISD::ST4LANEpost)
2083     MAKE_CASE(AArch64ISD::SMULL)
2084     MAKE_CASE(AArch64ISD::UMULL)
2085     MAKE_CASE(AArch64ISD::FRECPE)
2086     MAKE_CASE(AArch64ISD::FRECPS)
2087     MAKE_CASE(AArch64ISD::FRSQRTE)
2088     MAKE_CASE(AArch64ISD::FRSQRTS)
2089     MAKE_CASE(AArch64ISD::STG)
2090     MAKE_CASE(AArch64ISD::STZG)
2091     MAKE_CASE(AArch64ISD::ST2G)
2092     MAKE_CASE(AArch64ISD::STZ2G)
2093     MAKE_CASE(AArch64ISD::SUNPKHI)
2094     MAKE_CASE(AArch64ISD::SUNPKLO)
2095     MAKE_CASE(AArch64ISD::UUNPKHI)
2096     MAKE_CASE(AArch64ISD::UUNPKLO)
2097     MAKE_CASE(AArch64ISD::INSR)
2098     MAKE_CASE(AArch64ISD::PTEST)
2099     MAKE_CASE(AArch64ISD::PTRUE)
2100     MAKE_CASE(AArch64ISD::LD1_MERGE_ZERO)
2101     MAKE_CASE(AArch64ISD::LD1S_MERGE_ZERO)
2102     MAKE_CASE(AArch64ISD::LDNF1_MERGE_ZERO)
2103     MAKE_CASE(AArch64ISD::LDNF1S_MERGE_ZERO)
2104     MAKE_CASE(AArch64ISD::LDFF1_MERGE_ZERO)
2105     MAKE_CASE(AArch64ISD::LDFF1S_MERGE_ZERO)
2106     MAKE_CASE(AArch64ISD::LD1RQ_MERGE_ZERO)
2107     MAKE_CASE(AArch64ISD::LD1RO_MERGE_ZERO)
2108     MAKE_CASE(AArch64ISD::SVE_LD2_MERGE_ZERO)
2109     MAKE_CASE(AArch64ISD::SVE_LD3_MERGE_ZERO)
2110     MAKE_CASE(AArch64ISD::SVE_LD4_MERGE_ZERO)
2111     MAKE_CASE(AArch64ISD::GLD1_MERGE_ZERO)
2112     MAKE_CASE(AArch64ISD::GLD1_SCALED_MERGE_ZERO)
2113     MAKE_CASE(AArch64ISD::GLD1_SXTW_MERGE_ZERO)
2114     MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO)
2115     MAKE_CASE(AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO)
2116     MAKE_CASE(AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO)
2117     MAKE_CASE(AArch64ISD::GLD1_IMM_MERGE_ZERO)
2118     MAKE_CASE(AArch64ISD::GLD1S_MERGE_ZERO)
2119     MAKE_CASE(AArch64ISD::GLD1S_SCALED_MERGE_ZERO)
2120     MAKE_CASE(AArch64ISD::GLD1S_SXTW_MERGE_ZERO)
2121     MAKE_CASE(AArch64ISD::GLD1S_UXTW_MERGE_ZERO)
2122     MAKE_CASE(AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO)
2123     MAKE_CASE(AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO)
2124     MAKE_CASE(AArch64ISD::GLD1S_IMM_MERGE_ZERO)
2125     MAKE_CASE(AArch64ISD::GLDFF1_MERGE_ZERO)
2126     MAKE_CASE(AArch64ISD::GLDFF1_SCALED_MERGE_ZERO)
2127     MAKE_CASE(AArch64ISD::GLDFF1_SXTW_MERGE_ZERO)
2128     MAKE_CASE(AArch64ISD::GLDFF1_UXTW_MERGE_ZERO)
2129     MAKE_CASE(AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO)
2130     MAKE_CASE(AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO)
2131     MAKE_CASE(AArch64ISD::GLDFF1_IMM_MERGE_ZERO)
2132     MAKE_CASE(AArch64ISD::GLDFF1S_MERGE_ZERO)
2133     MAKE_CASE(AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO)
2134     MAKE_CASE(AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO)
2135     MAKE_CASE(AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO)
2136     MAKE_CASE(AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO)
2137     MAKE_CASE(AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO)
2138     MAKE_CASE(AArch64ISD::GLDFF1S_IMM_MERGE_ZERO)
2139     MAKE_CASE(AArch64ISD::GLDNT1_MERGE_ZERO)
2140     MAKE_CASE(AArch64ISD::GLDNT1_INDEX_MERGE_ZERO)
2141     MAKE_CASE(AArch64ISD::GLDNT1S_MERGE_ZERO)
2142     MAKE_CASE(AArch64ISD::ST1_PRED)
2143     MAKE_CASE(AArch64ISD::SST1_PRED)
2144     MAKE_CASE(AArch64ISD::SST1_SCALED_PRED)
2145     MAKE_CASE(AArch64ISD::SST1_SXTW_PRED)
2146     MAKE_CASE(AArch64ISD::SST1_UXTW_PRED)
2147     MAKE_CASE(AArch64ISD::SST1_SXTW_SCALED_PRED)
2148     MAKE_CASE(AArch64ISD::SST1_UXTW_SCALED_PRED)
2149     MAKE_CASE(AArch64ISD::SST1_IMM_PRED)
2150     MAKE_CASE(AArch64ISD::SSTNT1_PRED)
2151     MAKE_CASE(AArch64ISD::SSTNT1_INDEX_PRED)
2152     MAKE_CASE(AArch64ISD::LDP)
2153     MAKE_CASE(AArch64ISD::STP)
2154     MAKE_CASE(AArch64ISD::STNP)
2155     MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU)
2156     MAKE_CASE(AArch64ISD::BSWAP_MERGE_PASSTHRU)
2157     MAKE_CASE(AArch64ISD::CTLZ_MERGE_PASSTHRU)
2158     MAKE_CASE(AArch64ISD::CTPOP_MERGE_PASSTHRU)
2159     MAKE_CASE(AArch64ISD::DUP_MERGE_PASSTHRU)
2160     MAKE_CASE(AArch64ISD::INDEX_VECTOR)
2161     MAKE_CASE(AArch64ISD::UADDLP)
2162     MAKE_CASE(AArch64ISD::CALL_RVMARKER)
2163   }
2164 #undef MAKE_CASE
2165   return nullptr;
2166 }
2167 
2168 MachineBasicBlock *
2169 AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
2170                                     MachineBasicBlock *MBB) const {
2171   // We materialise the F128CSEL pseudo-instruction as some control flow and a
2172   // phi node:
2173 
2174   // OrigBB:
2175   //     [... previous instrs leading to comparison ...]
2176   //     b.ne TrueBB
2177   //     b EndBB
2178   // TrueBB:
2179   //     ; Fallthrough
2180   // EndBB:
2181   //     Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
2182 
2183   MachineFunction *MF = MBB->getParent();
2184   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2185   const BasicBlock *LLVM_BB = MBB->getBasicBlock();
2186   DebugLoc DL = MI.getDebugLoc();
2187   MachineFunction::iterator It = ++MBB->getIterator();
2188 
2189   Register DestReg = MI.getOperand(0).getReg();
2190   Register IfTrueReg = MI.getOperand(1).getReg();
2191   Register IfFalseReg = MI.getOperand(2).getReg();
2192   unsigned CondCode = MI.getOperand(3).getImm();
2193   bool NZCVKilled = MI.getOperand(4).isKill();
2194 
2195   MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
2196   MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
2197   MF->insert(It, TrueBB);
2198   MF->insert(It, EndBB);
2199 
2200   // Transfer rest of current basic-block to EndBB
2201   EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
2202                 MBB->end());
2203   EndBB->transferSuccessorsAndUpdatePHIs(MBB);
2204 
2205   BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
2206   BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
2207   MBB->addSuccessor(TrueBB);
2208   MBB->addSuccessor(EndBB);
2209 
2210   // TrueBB falls through to the end.
2211   TrueBB->addSuccessor(EndBB);
2212 
2213   if (!NZCVKilled) {
2214     TrueBB->addLiveIn(AArch64::NZCV);
2215     EndBB->addLiveIn(AArch64::NZCV);
2216   }
2217 
2218   BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
2219       .addReg(IfTrueReg)
2220       .addMBB(TrueBB)
2221       .addReg(IfFalseReg)
2222       .addMBB(MBB);
2223 
2224   MI.eraseFromParent();
2225   return EndBB;
2226 }
2227 
2228 MachineBasicBlock *AArch64TargetLowering::EmitLoweredCatchRet(
2229        MachineInstr &MI, MachineBasicBlock *BB) const {
2230   assert(!isAsynchronousEHPersonality(classifyEHPersonality(
2231              BB->getParent()->getFunction().getPersonalityFn())) &&
2232          "SEH does not use catchret!");
2233   return BB;
2234 }
2235 
2236 MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
2237     MachineInstr &MI, MachineBasicBlock *BB) const {
2238   switch (MI.getOpcode()) {
2239   default:
2240 #ifndef NDEBUG
2241     MI.dump();
2242 #endif
2243     llvm_unreachable("Unexpected instruction for custom inserter!");
2244 
2245   case AArch64::F128CSEL:
2246     return EmitF128CSEL(MI, BB);
2247 
2248   case TargetOpcode::STACKMAP:
2249   case TargetOpcode::PATCHPOINT:
2250   case TargetOpcode::STATEPOINT:
2251     return emitPatchPoint(MI, BB);
2252 
2253   case AArch64::CATCHRET:
2254     return EmitLoweredCatchRet(MI, BB);
2255   }
2256 }
2257 
2258 //===----------------------------------------------------------------------===//
2259 // AArch64 Lowering private implementation.
2260 //===----------------------------------------------------------------------===//
2261 
2262 //===----------------------------------------------------------------------===//
2263 // Lowering Code
2264 //===----------------------------------------------------------------------===//
2265 
2266 // Forward declarations of SVE fixed length lowering helpers
2267 static EVT getContainerForFixedLengthVector(SelectionDAG &DAG, EVT VT);
2268 static SDValue convertToScalableVector(SelectionDAG &DAG, EVT VT, SDValue V);
2269 static SDValue convertFromScalableVector(SelectionDAG &DAG, EVT VT, SDValue V);
2270 static SDValue convertFixedMaskToScalableVector(SDValue Mask,
2271                                                 SelectionDAG &DAG);
2272 
2273 /// isZerosVector - Check whether SDNode N is a zero-filled vector.
2274 static bool isZerosVector(const SDNode *N) {
2275   // Look through a bit convert.
2276   while (N->getOpcode() == ISD::BITCAST)
2277     N = N->getOperand(0).getNode();
2278 
2279   if (ISD::isConstantSplatVectorAllZeros(N))
2280     return true;
2281 
2282   if (N->getOpcode() != AArch64ISD::DUP)
2283     return false;
2284 
2285   auto Opnd0 = N->getOperand(0);
2286   auto *CINT = dyn_cast<ConstantSDNode>(Opnd0);
2287   auto *CFP = dyn_cast<ConstantFPSDNode>(Opnd0);
2288   return (CINT && CINT->isNullValue()) || (CFP && CFP->isZero());
2289 }
2290 
2291 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
2292 /// CC
2293 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
2294   switch (CC) {
2295   default:
2296     llvm_unreachable("Unknown condition code!");
2297   case ISD::SETNE:
2298     return AArch64CC::NE;
2299   case ISD::SETEQ:
2300     return AArch64CC::EQ;
2301   case ISD::SETGT:
2302     return AArch64CC::GT;
2303   case ISD::SETGE:
2304     return AArch64CC::GE;
2305   case ISD::SETLT:
2306     return AArch64CC::LT;
2307   case ISD::SETLE:
2308     return AArch64CC::LE;
2309   case ISD::SETUGT:
2310     return AArch64CC::HI;
2311   case ISD::SETUGE:
2312     return AArch64CC::HS;
2313   case ISD::SETULT:
2314     return AArch64CC::LO;
2315   case ISD::SETULE:
2316     return AArch64CC::LS;
2317   }
2318 }
2319 
2320 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
2321 static void changeFPCCToAArch64CC(ISD::CondCode CC,
2322                                   AArch64CC::CondCode &CondCode,
2323                                   AArch64CC::CondCode &CondCode2) {
2324   CondCode2 = AArch64CC::AL;
2325   switch (CC) {
2326   default:
2327     llvm_unreachable("Unknown FP condition!");
2328   case ISD::SETEQ:
2329   case ISD::SETOEQ:
2330     CondCode = AArch64CC::EQ;
2331     break;
2332   case ISD::SETGT:
2333   case ISD::SETOGT:
2334     CondCode = AArch64CC::GT;
2335     break;
2336   case ISD::SETGE:
2337   case ISD::SETOGE:
2338     CondCode = AArch64CC::GE;
2339     break;
2340   case ISD::SETOLT:
2341     CondCode = AArch64CC::MI;
2342     break;
2343   case ISD::SETOLE:
2344     CondCode = AArch64CC::LS;
2345     break;
2346   case ISD::SETONE:
2347     CondCode = AArch64CC::MI;
2348     CondCode2 = AArch64CC::GT;
2349     break;
2350   case ISD::SETO:
2351     CondCode = AArch64CC::VC;
2352     break;
2353   case ISD::SETUO:
2354     CondCode = AArch64CC::VS;
2355     break;
2356   case ISD::SETUEQ:
2357     CondCode = AArch64CC::EQ;
2358     CondCode2 = AArch64CC::VS;
2359     break;
2360   case ISD::SETUGT:
2361     CondCode = AArch64CC::HI;
2362     break;
2363   case ISD::SETUGE:
2364     CondCode = AArch64CC::PL;
2365     break;
2366   case ISD::SETLT:
2367   case ISD::SETULT:
2368     CondCode = AArch64CC::LT;
2369     break;
2370   case ISD::SETLE:
2371   case ISD::SETULE:
2372     CondCode = AArch64CC::LE;
2373     break;
2374   case ISD::SETNE:
2375   case ISD::SETUNE:
2376     CondCode = AArch64CC::NE;
2377     break;
2378   }
2379 }
2380 
2381 /// Convert a DAG fp condition code to an AArch64 CC.
2382 /// This differs from changeFPCCToAArch64CC in that it returns cond codes that
2383 /// should be AND'ed instead of OR'ed.
2384 static void changeFPCCToANDAArch64CC(ISD::CondCode CC,
2385                                      AArch64CC::CondCode &CondCode,
2386                                      AArch64CC::CondCode &CondCode2) {
2387   CondCode2 = AArch64CC::AL;
2388   switch (CC) {
2389   default:
2390     changeFPCCToAArch64CC(CC, CondCode, CondCode2);
2391     assert(CondCode2 == AArch64CC::AL);
2392     break;
2393   case ISD::SETONE:
2394     // (a one b)
2395     // == ((a olt b) || (a ogt b))
2396     // == ((a ord b) && (a une b))
2397     CondCode = AArch64CC::VC;
2398     CondCode2 = AArch64CC::NE;
2399     break;
2400   case ISD::SETUEQ:
2401     // (a ueq b)
2402     // == ((a uno b) || (a oeq b))
2403     // == ((a ule b) && (a uge b))
2404     CondCode = AArch64CC::PL;
2405     CondCode2 = AArch64CC::LE;
2406     break;
2407   }
2408 }
2409 
2410 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
2411 /// CC usable with the vector instructions. Fewer operations are available
2412 /// without a real NZCV register, so we have to use less efficient combinations
2413 /// to get the same effect.
2414 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
2415                                         AArch64CC::CondCode &CondCode,
2416                                         AArch64CC::CondCode &CondCode2,
2417                                         bool &Invert) {
2418   Invert = false;
2419   switch (CC) {
2420   default:
2421     // Mostly the scalar mappings work fine.
2422     changeFPCCToAArch64CC(CC, CondCode, CondCode2);
2423     break;
2424   case ISD::SETUO:
2425     Invert = true;
2426     LLVM_FALLTHROUGH;
2427   case ISD::SETO:
2428     CondCode = AArch64CC::MI;
2429     CondCode2 = AArch64CC::GE;
2430     break;
2431   case ISD::SETUEQ:
2432   case ISD::SETULT:
2433   case ISD::SETULE:
2434   case ISD::SETUGT:
2435   case ISD::SETUGE:
2436     // All of the compare-mask comparisons are ordered, but we can switch
2437     // between the two by a double inversion. E.g. ULE == !OGT.
2438     Invert = true;
2439     changeFPCCToAArch64CC(getSetCCInverse(CC, /* FP inverse */ MVT::f32),
2440                           CondCode, CondCode2);
2441     break;
2442   }
2443 }
2444 
2445 static bool isLegalArithImmed(uint64_t C) {
2446   // Matches AArch64DAGToDAGISel::SelectArithImmed().
2447   bool IsLegal = (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
2448   LLVM_DEBUG(dbgs() << "Is imm " << C
2449                     << " legal: " << (IsLegal ? "yes\n" : "no\n"));
2450   return IsLegal;
2451 }
2452 
2453 // Can a (CMP op1, (sub 0, op2) be turned into a CMN instruction on
2454 // the grounds that "op1 - (-op2) == op1 + op2" ? Not always, the C and V flags
2455 // can be set differently by this operation. It comes down to whether
2456 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
2457 // everything is fine. If not then the optimization is wrong. Thus general
2458 // comparisons are only valid if op2 != 0.
2459 //
2460 // So, finally, the only LLVM-native comparisons that don't mention C and V
2461 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
2462 // the absence of information about op2.
2463 static bool isCMN(SDValue Op, ISD::CondCode CC) {
2464   return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0)) &&
2465          (CC == ISD::SETEQ || CC == ISD::SETNE);
2466 }
2467 
2468 static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl,
2469                                       SelectionDAG &DAG, SDValue Chain,
2470                                       bool IsSignaling) {
2471   EVT VT = LHS.getValueType();
2472   assert(VT != MVT::f128);
2473   assert(VT != MVT::f16 && "Lowering of strict fp16 not yet implemented");
2474   unsigned Opcode =
2475       IsSignaling ? AArch64ISD::STRICT_FCMPE : AArch64ISD::STRICT_FCMP;
2476   return DAG.getNode(Opcode, dl, {VT, MVT::Other}, {Chain, LHS, RHS});
2477 }
2478 
2479 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2480                               const SDLoc &dl, SelectionDAG &DAG) {
2481   EVT VT = LHS.getValueType();
2482   const bool FullFP16 =
2483     static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
2484 
2485   if (VT.isFloatingPoint()) {
2486     assert(VT != MVT::f128);
2487     if (VT == MVT::f16 && !FullFP16) {
2488       LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
2489       RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
2490       VT = MVT::f32;
2491     }
2492     return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
2493   }
2494 
2495   // The CMP instruction is just an alias for SUBS, and representing it as
2496   // SUBS means that it's possible to get CSE with subtract operations.
2497   // A later phase can perform the optimization of setting the destination
2498   // register to WZR/XZR if it ends up being unused.
2499   unsigned Opcode = AArch64ISD::SUBS;
2500 
2501   if (isCMN(RHS, CC)) {
2502     // Can we combine a (CMP op1, (sub 0, op2) into a CMN instruction ?
2503     Opcode = AArch64ISD::ADDS;
2504     RHS = RHS.getOperand(1);
2505   } else if (isCMN(LHS, CC)) {
2506     // As we are looking for EQ/NE compares, the operands can be commuted ; can
2507     // we combine a (CMP (sub 0, op1), op2) into a CMN instruction ?
2508     Opcode = AArch64ISD::ADDS;
2509     LHS = LHS.getOperand(1);
2510   } else if (isNullConstant(RHS) && !isUnsignedIntSetCC(CC)) {
2511     if (LHS.getOpcode() == ISD::AND) {
2512       // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
2513       // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
2514       // of the signed comparisons.
2515       const SDValue ANDSNode = DAG.getNode(AArch64ISD::ANDS, dl,
2516                                            DAG.getVTList(VT, MVT_CC),
2517                                            LHS.getOperand(0),
2518                                            LHS.getOperand(1));
2519       // Replace all users of (and X, Y) with newly generated (ands X, Y)
2520       DAG.ReplaceAllUsesWith(LHS, ANDSNode);
2521       return ANDSNode.getValue(1);
2522     } else if (LHS.getOpcode() == AArch64ISD::ANDS) {
2523       // Use result of ANDS
2524       return LHS.getValue(1);
2525     }
2526   }
2527 
2528   return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
2529       .getValue(1);
2530 }
2531 
2532 /// \defgroup AArch64CCMP CMP;CCMP matching
2533 ///
2534 /// These functions deal with the formation of CMP;CCMP;... sequences.
2535 /// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
2536 /// a comparison. They set the NZCV flags to a predefined value if their
2537 /// predicate is false. This allows to express arbitrary conjunctions, for
2538 /// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B)))"
2539 /// expressed as:
2540 ///   cmp A
2541 ///   ccmp B, inv(CB), CA
2542 ///   check for CB flags
2543 ///
2544 /// This naturally lets us implement chains of AND operations with SETCC
2545 /// operands. And we can even implement some other situations by transforming
2546 /// them:
2547 ///   - We can implement (NEG SETCC) i.e. negating a single comparison by
2548 ///     negating the flags used in a CCMP/FCCMP operations.
2549 ///   - We can negate the result of a whole chain of CMP/CCMP/FCCMP operations
2550 ///     by negating the flags we test for afterwards. i.e.
2551 ///     NEG (CMP CCMP CCCMP ...) can be implemented.
2552 ///   - Note that we can only ever negate all previously processed results.
2553 ///     What we can not implement by flipping the flags to test is a negation
2554 ///     of two sub-trees (because the negation affects all sub-trees emitted so
2555 ///     far, so the 2nd sub-tree we emit would also affect the first).
2556 /// With those tools we can implement some OR operations:
2557 ///   - (OR (SETCC A) (SETCC B)) can be implemented via:
2558 ///     NEG (AND (NEG (SETCC A)) (NEG (SETCC B)))
2559 ///   - After transforming OR to NEG/AND combinations we may be able to use NEG
2560 ///     elimination rules from earlier to implement the whole thing as a
2561 ///     CCMP/FCCMP chain.
2562 ///
2563 /// As complete example:
2564 ///     or (or (setCA (cmp A)) (setCB (cmp B)))
2565 ///        (and (setCC (cmp C)) (setCD (cmp D)))"
2566 /// can be reassociated to:
2567 ///     or (and (setCC (cmp C)) setCD (cmp D))
2568 //         (or (setCA (cmp A)) (setCB (cmp B)))
2569 /// can be transformed to:
2570 ///     not (and (not (and (setCC (cmp C)) (setCD (cmp D))))
2571 ///              (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
2572 /// which can be implemented as:
2573 ///   cmp C
2574 ///   ccmp D, inv(CD), CC
2575 ///   ccmp A, CA, inv(CD)
2576 ///   ccmp B, CB, inv(CA)
2577 ///   check for CB flags
2578 ///
2579 /// A counterexample is "or (and A B) (and C D)" which translates to
2580 /// not (and (not (and (not A) (not B))) (not (and (not C) (not D)))), we
2581 /// can only implement 1 of the inner (not) operations, but not both!
2582 /// @{
2583 
2584 /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
2585 static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
2586                                          ISD::CondCode CC, SDValue CCOp,
2587                                          AArch64CC::CondCode Predicate,
2588                                          AArch64CC::CondCode OutCC,
2589                                          const SDLoc &DL, SelectionDAG &DAG) {
2590   unsigned Opcode = 0;
2591   const bool FullFP16 =
2592     static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
2593 
2594   if (LHS.getValueType().isFloatingPoint()) {
2595     assert(LHS.getValueType() != MVT::f128);
2596     if (LHS.getValueType() == MVT::f16 && !FullFP16) {
2597       LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
2598       RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
2599     }
2600     Opcode = AArch64ISD::FCCMP;
2601   } else if (RHS.getOpcode() == ISD::SUB) {
2602     SDValue SubOp0 = RHS.getOperand(0);
2603     if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2604       // See emitComparison() on why we can only do this for SETEQ and SETNE.
2605       Opcode = AArch64ISD::CCMN;
2606       RHS = RHS.getOperand(1);
2607     }
2608   }
2609   if (Opcode == 0)
2610     Opcode = AArch64ISD::CCMP;
2611 
2612   SDValue Condition = DAG.getConstant(Predicate, DL, MVT_CC);
2613   AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
2614   unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
2615   SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
2616   return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
2617 }
2618 
2619 /// Returns true if @p Val is a tree of AND/OR/SETCC operations that can be
2620 /// expressed as a conjunction. See \ref AArch64CCMP.
2621 /// \param CanNegate    Set to true if we can negate the whole sub-tree just by
2622 ///                     changing the conditions on the SETCC tests.
2623 ///                     (this means we can call emitConjunctionRec() with
2624 ///                      Negate==true on this sub-tree)
2625 /// \param MustBeFirst  Set to true if this subtree needs to be negated and we
2626 ///                     cannot do the negation naturally. We are required to
2627 ///                     emit the subtree first in this case.
2628 /// \param WillNegate   Is true if are called when the result of this
2629 ///                     subexpression must be negated. This happens when the
2630 ///                     outer expression is an OR. We can use this fact to know
2631 ///                     that we have a double negation (or (or ...) ...) that
2632 ///                     can be implemented for free.
2633 static bool canEmitConjunction(const SDValue Val, bool &CanNegate,
2634                                bool &MustBeFirst, bool WillNegate,
2635                                unsigned Depth = 0) {
2636   if (!Val.hasOneUse())
2637     return false;
2638   unsigned Opcode = Val->getOpcode();
2639   if (Opcode == ISD::SETCC) {
2640     if (Val->getOperand(0).getValueType() == MVT::f128)
2641       return false;
2642     CanNegate = true;
2643     MustBeFirst = false;
2644     return true;
2645   }
2646   // Protect against exponential runtime and stack overflow.
2647   if (Depth > 6)
2648     return false;
2649   if (Opcode == ISD::AND || Opcode == ISD::OR) {
2650     bool IsOR = Opcode == ISD::OR;
2651     SDValue O0 = Val->getOperand(0);
2652     SDValue O1 = Val->getOperand(1);
2653     bool CanNegateL;
2654     bool MustBeFirstL;
2655     if (!canEmitConjunction(O0, CanNegateL, MustBeFirstL, IsOR, Depth+1))
2656       return false;
2657     bool CanNegateR;
2658     bool MustBeFirstR;
2659     if (!canEmitConjunction(O1, CanNegateR, MustBeFirstR, IsOR, Depth+1))
2660       return false;
2661 
2662     if (MustBeFirstL && MustBeFirstR)
2663       return false;
2664 
2665     if (IsOR) {
2666       // For an OR expression we need to be able to naturally negate at least
2667       // one side or we cannot do the transformation at all.
2668       if (!CanNegateL && !CanNegateR)
2669         return false;
2670       // If we the result of the OR will be negated and we can naturally negate
2671       // the leafs, then this sub-tree as a whole negates naturally.
2672       CanNegate = WillNegate && CanNegateL && CanNegateR;
2673       // If we cannot naturally negate the whole sub-tree, then this must be
2674       // emitted first.
2675       MustBeFirst = !CanNegate;
2676     } else {
2677       assert(Opcode == ISD::AND && "Must be OR or AND");
2678       // We cannot naturally negate an AND operation.
2679       CanNegate = false;
2680       MustBeFirst = MustBeFirstL || MustBeFirstR;
2681     }
2682     return true;
2683   }
2684   return false;
2685 }
2686 
2687 /// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
2688 /// of CCMP/CFCMP ops. See @ref AArch64CCMP.
2689 /// Tries to transform the given i1 producing node @p Val to a series compare
2690 /// and conditional compare operations. @returns an NZCV flags producing node
2691 /// and sets @p OutCC to the flags that should be tested or returns SDValue() if
2692 /// transformation was not possible.
2693 /// \p Negate is true if we want this sub-tree being negated just by changing
2694 /// SETCC conditions.
2695 static SDValue emitConjunctionRec(SelectionDAG &DAG, SDValue Val,
2696     AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp,
2697     AArch64CC::CondCode Predicate) {
2698   // We're at a tree leaf, produce a conditional comparison operation.
2699   unsigned Opcode = Val->getOpcode();
2700   if (Opcode == ISD::SETCC) {
2701     SDValue LHS = Val->getOperand(0);
2702     SDValue RHS = Val->getOperand(1);
2703     ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
2704     bool isInteger = LHS.getValueType().isInteger();
2705     if (Negate)
2706       CC = getSetCCInverse(CC, LHS.getValueType());
2707     SDLoc DL(Val);
2708     // Determine OutCC and handle FP special case.
2709     if (isInteger) {
2710       OutCC = changeIntCCToAArch64CC(CC);
2711     } else {
2712       assert(LHS.getValueType().isFloatingPoint());
2713       AArch64CC::CondCode ExtraCC;
2714       changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);
2715       // Some floating point conditions can't be tested with a single condition
2716       // code. Construct an additional comparison in this case.
2717       if (ExtraCC != AArch64CC::AL) {
2718         SDValue ExtraCmp;
2719         if (!CCOp.getNode())
2720           ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
2721         else
2722           ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate,
2723                                                ExtraCC, DL, DAG);
2724         CCOp = ExtraCmp;
2725         Predicate = ExtraCC;
2726       }
2727     }
2728 
2729     // Produce a normal comparison if we are first in the chain
2730     if (!CCOp)
2731       return emitComparison(LHS, RHS, CC, DL, DAG);
2732     // Otherwise produce a ccmp.
2733     return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL,
2734                                      DAG);
2735   }
2736   assert(Val->hasOneUse() && "Valid conjunction/disjunction tree");
2737 
2738   bool IsOR = Opcode == ISD::OR;
2739 
2740   SDValue LHS = Val->getOperand(0);
2741   bool CanNegateL;
2742   bool MustBeFirstL;
2743   bool ValidL = canEmitConjunction(LHS, CanNegateL, MustBeFirstL, IsOR);
2744   assert(ValidL && "Valid conjunction/disjunction tree");
2745   (void)ValidL;
2746 
2747   SDValue RHS = Val->getOperand(1);
2748   bool CanNegateR;
2749   bool MustBeFirstR;
2750   bool ValidR = canEmitConjunction(RHS, CanNegateR, MustBeFirstR, IsOR);
2751   assert(ValidR && "Valid conjunction/disjunction tree");
2752   (void)ValidR;
2753 
2754   // Swap sub-tree that must come first to the right side.
2755   if (MustBeFirstL) {
2756     assert(!MustBeFirstR && "Valid conjunction/disjunction tree");
2757     std::swap(LHS, RHS);
2758     std::swap(CanNegateL, CanNegateR);
2759     std::swap(MustBeFirstL, MustBeFirstR);
2760   }
2761 
2762   bool NegateR;
2763   bool NegateAfterR;
2764   bool NegateL;
2765   bool NegateAfterAll;
2766   if (Opcode == ISD::OR) {
2767     // Swap the sub-tree that we can negate naturally to the left.
2768     if (!CanNegateL) {
2769       assert(CanNegateR && "at least one side must be negatable");
2770       assert(!MustBeFirstR && "invalid conjunction/disjunction tree");
2771       assert(!Negate);
2772       std::swap(LHS, RHS);
2773       NegateR = false;
2774       NegateAfterR = true;
2775     } else {
2776       // Negate the left sub-tree if possible, otherwise negate the result.
2777       NegateR = CanNegateR;
2778       NegateAfterR = !CanNegateR;
2779     }
2780     NegateL = true;
2781     NegateAfterAll = !Negate;
2782   } else {
2783     assert(Opcode == ISD::AND && "Valid conjunction/disjunction tree");
2784     assert(!Negate && "Valid conjunction/disjunction tree");
2785 
2786     NegateL = false;
2787     NegateR = false;
2788     NegateAfterR = false;
2789     NegateAfterAll = false;
2790   }
2791 
2792   // Emit sub-trees.
2793   AArch64CC::CondCode RHSCC;
2794   SDValue CmpR = emitConjunctionRec(DAG, RHS, RHSCC, NegateR, CCOp, Predicate);
2795   if (NegateAfterR)
2796     RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
2797   SDValue CmpL = emitConjunctionRec(DAG, LHS, OutCC, NegateL, CmpR, RHSCC);
2798   if (NegateAfterAll)
2799     OutCC = AArch64CC::getInvertedCondCode(OutCC);
2800   return CmpL;
2801 }
2802 
2803 /// Emit expression as a conjunction (a series of CCMP/CFCMP ops).
2804 /// In some cases this is even possible with OR operations in the expression.
2805 /// See \ref AArch64CCMP.
2806 /// \see emitConjunctionRec().
2807 static SDValue emitConjunction(SelectionDAG &DAG, SDValue Val,
2808                                AArch64CC::CondCode &OutCC) {
2809   bool DummyCanNegate;
2810   bool DummyMustBeFirst;
2811   if (!canEmitConjunction(Val, DummyCanNegate, DummyMustBeFirst, false))
2812     return SDValue();
2813 
2814   return emitConjunctionRec(DAG, Val, OutCC, false, SDValue(), AArch64CC::AL);
2815 }
2816 
2817 /// @}
2818 
2819 /// Returns how profitable it is to fold a comparison's operand's shift and/or
2820 /// extension operations.
2821 static unsigned getCmpOperandFoldingProfit(SDValue Op) {
2822   auto isSupportedExtend = [&](SDValue V) {
2823     if (V.getOpcode() == ISD::SIGN_EXTEND_INREG)
2824       return true;
2825 
2826     if (V.getOpcode() == ISD::AND)
2827       if (ConstantSDNode *MaskCst = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
2828         uint64_t Mask = MaskCst->getZExtValue();
2829         return (Mask == 0xFF || Mask == 0xFFFF || Mask == 0xFFFFFFFF);
2830       }
2831 
2832     return false;
2833   };
2834 
2835   if (!Op.hasOneUse())
2836     return 0;
2837 
2838   if (isSupportedExtend(Op))
2839     return 1;
2840 
2841   unsigned Opc = Op.getOpcode();
2842   if (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA)
2843     if (ConstantSDNode *ShiftCst = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2844       uint64_t Shift = ShiftCst->getZExtValue();
2845       if (isSupportedExtend(Op.getOperand(0)))
2846         return (Shift <= 4) ? 2 : 1;
2847       EVT VT = Op.getValueType();
2848       if ((VT == MVT::i32 && Shift <= 31) || (VT == MVT::i64 && Shift <= 63))
2849         return 1;
2850     }
2851 
2852   return 0;
2853 }
2854 
2855 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2856                              SDValue &AArch64cc, SelectionDAG &DAG,
2857                              const SDLoc &dl) {
2858   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2859     EVT VT = RHS.getValueType();
2860     uint64_t C = RHSC->getZExtValue();
2861     if (!isLegalArithImmed(C)) {
2862       // Constant does not fit, try adjusting it by one?
2863       switch (CC) {
2864       default:
2865         break;
2866       case ISD::SETLT:
2867       case ISD::SETGE:
2868         if ((VT == MVT::i32 && C != 0x80000000 &&
2869              isLegalArithImmed((uint32_t)(C - 1))) ||
2870             (VT == MVT::i64 && C != 0x80000000ULL &&
2871              isLegalArithImmed(C - 1ULL))) {
2872           CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2873           C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
2874           RHS = DAG.getConstant(C, dl, VT);
2875         }
2876         break;
2877       case ISD::SETULT:
2878       case ISD::SETUGE:
2879         if ((VT == MVT::i32 && C != 0 &&
2880              isLegalArithImmed((uint32_t)(C - 1))) ||
2881             (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
2882           CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2883           C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
2884           RHS = DAG.getConstant(C, dl, VT);
2885         }
2886         break;
2887       case ISD::SETLE:
2888       case ISD::SETGT:
2889         if ((VT == MVT::i32 && C != INT32_MAX &&
2890              isLegalArithImmed((uint32_t)(C + 1))) ||
2891             (VT == MVT::i64 && C != INT64_MAX &&
2892              isLegalArithImmed(C + 1ULL))) {
2893           CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2894           C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
2895           RHS = DAG.getConstant(C, dl, VT);
2896         }
2897         break;
2898       case ISD::SETULE:
2899       case ISD::SETUGT:
2900         if ((VT == MVT::i32 && C != UINT32_MAX &&
2901              isLegalArithImmed((uint32_t)(C + 1))) ||
2902             (VT == MVT::i64 && C != UINT64_MAX &&
2903              isLegalArithImmed(C + 1ULL))) {
2904           CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2905           C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
2906           RHS = DAG.getConstant(C, dl, VT);
2907         }
2908         break;
2909       }
2910     }
2911   }
2912 
2913   // Comparisons are canonicalized so that the RHS operand is simpler than the
2914   // LHS one, the extreme case being when RHS is an immediate. However, AArch64
2915   // can fold some shift+extend operations on the RHS operand, so swap the
2916   // operands if that can be done.
2917   //
2918   // For example:
2919   //    lsl     w13, w11, #1
2920   //    cmp     w13, w12
2921   // can be turned into:
2922   //    cmp     w12, w11, lsl #1
2923   if (!isa<ConstantSDNode>(RHS) ||
2924       !isLegalArithImmed(cast<ConstantSDNode>(RHS)->getZExtValue())) {
2925     SDValue TheLHS = isCMN(LHS, CC) ? LHS.getOperand(1) : LHS;
2926 
2927     if (getCmpOperandFoldingProfit(TheLHS) > getCmpOperandFoldingProfit(RHS)) {
2928       std::swap(LHS, RHS);
2929       CC = ISD::getSetCCSwappedOperands(CC);
2930     }
2931   }
2932 
2933   SDValue Cmp;
2934   AArch64CC::CondCode AArch64CC;
2935   if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
2936     const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
2937 
2938     // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
2939     // For the i8 operand, the largest immediate is 255, so this can be easily
2940     // encoded in the compare instruction. For the i16 operand, however, the
2941     // largest immediate cannot be encoded in the compare.
2942     // Therefore, use a sign extending load and cmn to avoid materializing the
2943     // -1 constant. For example,
2944     // movz w1, #65535
2945     // ldrh w0, [x0, #0]
2946     // cmp w0, w1
2947     // >
2948     // ldrsh w0, [x0, #0]
2949     // cmn w0, #1
2950     // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
2951     // if and only if (sext LHS) == (sext RHS). The checks are in place to
2952     // ensure both the LHS and RHS are truly zero extended and to make sure the
2953     // transformation is profitable.
2954     if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
2955         cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
2956         cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
2957         LHS.getNode()->hasNUsesOfValue(1, 0)) {
2958       int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
2959       if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
2960         SDValue SExt =
2961             DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
2962                         DAG.getValueType(MVT::i16));
2963         Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
2964                                                    RHS.getValueType()),
2965                              CC, dl, DAG);
2966         AArch64CC = changeIntCCToAArch64CC(CC);
2967       }
2968     }
2969 
2970     if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
2971       if ((Cmp = emitConjunction(DAG, LHS, AArch64CC))) {
2972         if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
2973           AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
2974       }
2975     }
2976   }
2977 
2978   if (!Cmp) {
2979     Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2980     AArch64CC = changeIntCCToAArch64CC(CC);
2981   }
2982   AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
2983   return Cmp;
2984 }
2985 
2986 static std::pair<SDValue, SDValue>
2987 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
2988   assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
2989          "Unsupported value type");
2990   SDValue Value, Overflow;
2991   SDLoc DL(Op);
2992   SDValue LHS = Op.getOperand(0);
2993   SDValue RHS = Op.getOperand(1);
2994   unsigned Opc = 0;
2995   switch (Op.getOpcode()) {
2996   default:
2997     llvm_unreachable("Unknown overflow instruction!");
2998   case ISD::SADDO:
2999     Opc = AArch64ISD::ADDS;
3000     CC = AArch64CC::VS;
3001     break;
3002   case ISD::UADDO:
3003     Opc = AArch64ISD::ADDS;
3004     CC = AArch64CC::HS;
3005     break;
3006   case ISD::SSUBO:
3007     Opc = AArch64ISD::SUBS;
3008     CC = AArch64CC::VS;
3009     break;
3010   case ISD::USUBO:
3011     Opc = AArch64ISD::SUBS;
3012     CC = AArch64CC::LO;
3013     break;
3014   // Multiply needs a little bit extra work.
3015   case ISD::SMULO:
3016   case ISD::UMULO: {
3017     CC = AArch64CC::NE;
3018     bool IsSigned = Op.getOpcode() == ISD::SMULO;
3019     if (Op.getValueType() == MVT::i32) {
3020       // Extend to 64-bits, then perform a 64-bit multiply.
3021       unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3022       LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
3023       RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
3024       SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
3025       Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
3026 
3027       // Check that the result fits into a 32-bit integer.
3028       SDVTList VTs = DAG.getVTList(MVT::i64, MVT_CC);
3029       if (IsSigned) {
3030         // cmp xreg, wreg, sxtw
3031         SDValue SExtMul = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Value);
3032         Overflow =
3033             DAG.getNode(AArch64ISD::SUBS, DL, VTs, Mul, SExtMul).getValue(1);
3034       } else {
3035         // tst xreg, #0xffffffff00000000
3036         SDValue UpperBits = DAG.getConstant(0xFFFFFFFF00000000, DL, MVT::i64);
3037         Overflow =
3038             DAG.getNode(AArch64ISD::ANDS, DL, VTs, Mul, UpperBits).getValue(1);
3039       }
3040       break;
3041     }
3042     assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
3043     // For the 64 bit multiply
3044     Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
3045     if (IsSigned) {
3046       SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
3047       SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
3048                                       DAG.getConstant(63, DL, MVT::i64));
3049       // It is important that LowerBits is last, otherwise the arithmetic
3050       // shift will not be folded into the compare (SUBS).
3051       SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
3052       Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
3053                      .getValue(1);
3054     } else {
3055       SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
3056       SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
3057       Overflow =
3058           DAG.getNode(AArch64ISD::SUBS, DL, VTs,
3059                       DAG.getConstant(0, DL, MVT::i64),
3060                       UpperBits).getValue(1);
3061     }
3062     break;
3063   }
3064   } // switch (...)
3065 
3066   if (Opc) {
3067     SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
3068 
3069     // Emit the AArch64 operation with overflow check.
3070     Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
3071     Overflow = Value.getValue(1);
3072   }
3073   return std::make_pair(Value, Overflow);
3074 }
3075 
3076 SDValue AArch64TargetLowering::LowerXOR(SDValue Op, SelectionDAG &DAG) const {
3077   if (useSVEForFixedLengthVectorVT(Op.getValueType()))
3078     return LowerToScalableOp(Op, DAG);
3079 
3080   SDValue Sel = Op.getOperand(0);
3081   SDValue Other = Op.getOperand(1);
3082   SDLoc dl(Sel);
3083 
3084   // If the operand is an overflow checking operation, invert the condition
3085   // code and kill the Not operation. I.e., transform:
3086   // (xor (overflow_op_bool, 1))
3087   //   -->
3088   // (csel 1, 0, invert(cc), overflow_op_bool)
3089   // ... which later gets transformed to just a cset instruction with an
3090   // inverted condition code, rather than a cset + eor sequence.
3091   if (isOneConstant(Other) && ISD::isOverflowIntrOpRes(Sel)) {
3092     // Only lower legal XALUO ops.
3093     if (!DAG.getTargetLoweringInfo().isTypeLegal(Sel->getValueType(0)))
3094       return SDValue();
3095 
3096     SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
3097     SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
3098     AArch64CC::CondCode CC;
3099     SDValue Value, Overflow;
3100     std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Sel.getValue(0), DAG);
3101     SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
3102     return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,
3103                        CCVal, Overflow);
3104   }
3105   // If neither operand is a SELECT_CC, give up.
3106   if (Sel.getOpcode() != ISD::SELECT_CC)
3107     std::swap(Sel, Other);
3108   if (Sel.getOpcode() != ISD::SELECT_CC)
3109     return Op;
3110 
3111   // The folding we want to perform is:
3112   // (xor x, (select_cc a, b, cc, 0, -1) )
3113   //   -->
3114   // (csel x, (xor x, -1), cc ...)
3115   //
3116   // The latter will get matched to a CSINV instruction.
3117 
3118   ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
3119   SDValue LHS = Sel.getOperand(0);
3120   SDValue RHS = Sel.getOperand(1);
3121   SDValue TVal = Sel.getOperand(2);
3122   SDValue FVal = Sel.getOperand(3);
3123 
3124   // FIXME: This could be generalized to non-integer comparisons.
3125   if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
3126     return Op;
3127 
3128   ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3129   ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3130 
3131   // The values aren't constants, this isn't the pattern we're looking for.
3132   if (!CFVal || !CTVal)
3133     return Op;
3134 
3135   // We can commute the SELECT_CC by inverting the condition.  This
3136   // might be needed to make this fit into a CSINV pattern.
3137   if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3138     std::swap(TVal, FVal);
3139     std::swap(CTVal, CFVal);
3140     CC = ISD::getSetCCInverse(CC, LHS.getValueType());
3141   }
3142 
3143   // If the constants line up, perform the transform!
3144   if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
3145     SDValue CCVal;
3146     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3147 
3148     FVal = Other;
3149     TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
3150                        DAG.getConstant(-1ULL, dl, Other.getValueType()));
3151 
3152     return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
3153                        CCVal, Cmp);
3154   }
3155 
3156   return Op;
3157 }
3158 
3159 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
3160   EVT VT = Op.getValueType();
3161 
3162   // Let legalize expand this if it isn't a legal type yet.
3163   if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
3164     return SDValue();
3165 
3166   SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3167 
3168   unsigned Opc;
3169   bool ExtraOp = false;
3170   switch (Op.getOpcode()) {
3171   default:
3172     llvm_unreachable("Invalid code");
3173   case ISD::ADDC:
3174     Opc = AArch64ISD::ADDS;
3175     break;
3176   case ISD::SUBC:
3177     Opc = AArch64ISD::SUBS;
3178     break;
3179   case ISD::ADDE:
3180     Opc = AArch64ISD::ADCS;
3181     ExtraOp = true;
3182     break;
3183   case ISD::SUBE:
3184     Opc = AArch64ISD::SBCS;
3185     ExtraOp = true;
3186     break;
3187   }
3188 
3189   if (!ExtraOp)
3190     return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
3191   return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
3192                      Op.getOperand(2));
3193 }
3194 
3195 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
3196   // Let legalize expand this if it isn't a legal type yet.
3197   if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3198     return SDValue();
3199 
3200   SDLoc dl(Op);
3201   AArch64CC::CondCode CC;
3202   // The actual operation that sets the overflow or carry flag.
3203   SDValue Value, Overflow;
3204   std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
3205 
3206   // We use 0 and 1 as false and true values.
3207   SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
3208   SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
3209 
3210   // We use an inverted condition, because the conditional select is inverted
3211   // too. This will allow it to be selected to a single instruction:
3212   // CSINC Wd, WZR, WZR, invert(cond).
3213   SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
3214   Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
3215                          CCVal, Overflow);
3216 
3217   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3218   return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
3219 }
3220 
3221 // Prefetch operands are:
3222 // 1: Address to prefetch
3223 // 2: bool isWrite
3224 // 3: int locality (0 = no locality ... 3 = extreme locality)
3225 // 4: bool isDataCache
3226 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
3227   SDLoc DL(Op);
3228   unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3229   unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
3230   unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3231 
3232   bool IsStream = !Locality;
3233   // When the locality number is set
3234   if (Locality) {
3235     // The front-end should have filtered out the out-of-range values
3236     assert(Locality <= 3 && "Prefetch locality out-of-range");
3237     // The locality degree is the opposite of the cache speed.
3238     // Put the number the other way around.
3239     // The encoding starts at 0 for level 1
3240     Locality = 3 - Locality;
3241   }
3242 
3243   // built the mask value encoding the expected behavior.
3244   unsigned PrfOp = (IsWrite << 4) |     // Load/Store bit
3245                    (!IsData << 3) |     // IsDataCache bit
3246                    (Locality << 1) |    // Cache level bits
3247                    (unsigned)IsStream;  // Stream bit
3248   return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
3249                      DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
3250 }
3251 
3252 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
3253                                               SelectionDAG &DAG) const {
3254   EVT VT = Op.getValueType();
3255   if (VT.isScalableVector())
3256     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FP_EXTEND_MERGE_PASSTHRU);
3257 
3258   if (useSVEForFixedLengthVectorVT(VT))
3259     return LowerFixedLengthFPExtendToSVE(Op, DAG);
3260 
3261   assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
3262   return SDValue();
3263 }
3264 
3265 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
3266                                              SelectionDAG &DAG) const {
3267   if (Op.getValueType().isScalableVector())
3268     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FP_ROUND_MERGE_PASSTHRU);
3269 
3270   bool IsStrict = Op->isStrictFPOpcode();
3271   SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
3272   EVT SrcVT = SrcVal.getValueType();
3273 
3274   if (useSVEForFixedLengthVectorVT(SrcVT))
3275     return LowerFixedLengthFPRoundToSVE(Op, DAG);
3276 
3277   if (SrcVT != MVT::f128) {
3278     // Expand cases where the input is a vector bigger than NEON.
3279     if (useSVEForFixedLengthVectorVT(SrcVT))
3280       return SDValue();
3281 
3282     // It's legal except when f128 is involved
3283     return Op;
3284   }
3285 
3286   return SDValue();
3287 }
3288 
3289 SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op,
3290                                                     SelectionDAG &DAG) const {
3291   // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
3292   // Any additional optimization in this function should be recorded
3293   // in the cost tables.
3294   EVT InVT = Op.getOperand(0).getValueType();
3295   EVT VT = Op.getValueType();
3296 
3297   if (VT.isScalableVector()) {
3298     unsigned Opcode = Op.getOpcode() == ISD::FP_TO_UINT
3299                           ? AArch64ISD::FCVTZU_MERGE_PASSTHRU
3300                           : AArch64ISD::FCVTZS_MERGE_PASSTHRU;
3301     return LowerToPredicatedOp(Op, DAG, Opcode);
3302   }
3303 
3304   if (useSVEForFixedLengthVectorVT(VT) || useSVEForFixedLengthVectorVT(InVT))
3305     return LowerFixedLengthFPToIntToSVE(Op, DAG);
3306 
3307   unsigned NumElts = InVT.getVectorNumElements();
3308 
3309   // f16 conversions are promoted to f32 when full fp16 is not supported.
3310   if (InVT.getVectorElementType() == MVT::f16 &&
3311       !Subtarget->hasFullFP16()) {
3312     MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts);
3313     SDLoc dl(Op);
3314     return DAG.getNode(
3315         Op.getOpcode(), dl, Op.getValueType(),
3316         DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)));
3317   }
3318 
3319   uint64_t VTSize = VT.getFixedSizeInBits();
3320   uint64_t InVTSize = InVT.getFixedSizeInBits();
3321   if (VTSize < InVTSize) {
3322     SDLoc dl(Op);
3323     SDValue Cv =
3324         DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
3325                     Op.getOperand(0));
3326     return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
3327   }
3328 
3329   if (VTSize > InVTSize) {
3330     SDLoc dl(Op);
3331     MVT ExtVT =
3332         MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
3333                          VT.getVectorNumElements());
3334     SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
3335     return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
3336   }
3337 
3338   // Type changing conversions are illegal.
3339   return Op;
3340 }
3341 
3342 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
3343                                               SelectionDAG &DAG) const {
3344   bool IsStrict = Op->isStrictFPOpcode();
3345   SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
3346 
3347   if (SrcVal.getValueType().isVector())
3348     return LowerVectorFP_TO_INT(Op, DAG);
3349 
3350   // f16 conversions are promoted to f32 when full fp16 is not supported.
3351   if (SrcVal.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {
3352     assert(!IsStrict && "Lowering of strict fp16 not yet implemented");
3353     SDLoc dl(Op);
3354     return DAG.getNode(
3355         Op.getOpcode(), dl, Op.getValueType(),
3356         DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, SrcVal));
3357   }
3358 
3359   if (SrcVal.getValueType() != MVT::f128) {
3360     // It's legal except when f128 is involved
3361     return Op;
3362   }
3363 
3364   return SDValue();
3365 }
3366 
3367 SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
3368                                                   SelectionDAG &DAG) const {
3369   // AArch64 FP-to-int conversions saturate to the destination register size, so
3370   // we can lower common saturating conversions to simple instructions.
3371   SDValue SrcVal = Op.getOperand(0);
3372 
3373   EVT SrcVT = SrcVal.getValueType();
3374   EVT DstVT = Op.getValueType();
3375 
3376   EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
3377   uint64_t SatWidth = SatVT.getScalarSizeInBits();
3378   uint64_t DstWidth = DstVT.getScalarSizeInBits();
3379   assert(SatWidth <= DstWidth && "Saturation width cannot exceed result width");
3380 
3381   // TODO: Support lowering of NEON and SVE conversions.
3382   if (SrcVT.isVector())
3383     return SDValue();
3384 
3385   // TODO: Saturate to SatWidth explicitly.
3386   if (SatWidth != DstWidth)
3387     return SDValue();
3388 
3389   // In the absence of FP16 support, promote f32 to f16, like LowerFP_TO_INT().
3390   if (SrcVT == MVT::f16 && !Subtarget->hasFullFP16())
3391     return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
3392                        DAG.getNode(ISD::FP_EXTEND, SDLoc(Op), MVT::f32, SrcVal),
3393                        Op.getOperand(1));
3394 
3395   // Cases that we can emit directly.
3396   if ((SrcVT == MVT::f64 || SrcVT == MVT::f32 ||
3397        (SrcVT == MVT::f16 && Subtarget->hasFullFP16())) &&
3398       (DstVT == MVT::i64 || DstVT == MVT::i32))
3399     return Op;
3400 
3401   // For all other cases, fall back on the expanded form.
3402   return SDValue();
3403 }
3404 
3405 SDValue AArch64TargetLowering::LowerVectorINT_TO_FP(SDValue Op,
3406                                                     SelectionDAG &DAG) const {
3407   // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
3408   // Any additional optimization in this function should be recorded
3409   // in the cost tables.
3410   EVT VT = Op.getValueType();
3411   SDLoc dl(Op);
3412   SDValue In = Op.getOperand(0);
3413   EVT InVT = In.getValueType();
3414   unsigned Opc = Op.getOpcode();
3415   bool IsSigned = Opc == ISD::SINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP;
3416 
3417   if (VT.isScalableVector()) {
3418     if (InVT.getVectorElementType() == MVT::i1) {
3419       // We can't directly extend an SVE predicate; extend it first.
3420       unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3421       EVT CastVT = getPromotedVTForPredicate(InVT);
3422       In = DAG.getNode(CastOpc, dl, CastVT, In);
3423       return DAG.getNode(Opc, dl, VT, In);
3424     }
3425 
3426     unsigned Opcode = IsSigned ? AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU
3427                                : AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU;
3428     return LowerToPredicatedOp(Op, DAG, Opcode);
3429   }
3430 
3431   if (useSVEForFixedLengthVectorVT(VT) || useSVEForFixedLengthVectorVT(InVT))
3432     return LowerFixedLengthIntToFPToSVE(Op, DAG);
3433 
3434   uint64_t VTSize = VT.getFixedSizeInBits();
3435   uint64_t InVTSize = InVT.getFixedSizeInBits();
3436   if (VTSize < InVTSize) {
3437     MVT CastVT =
3438         MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
3439                          InVT.getVectorNumElements());
3440     In = DAG.getNode(Opc, dl, CastVT, In);
3441     return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
3442   }
3443 
3444   if (VTSize > InVTSize) {
3445     unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3446     EVT CastVT = VT.changeVectorElementTypeToInteger();
3447     In = DAG.getNode(CastOpc, dl, CastVT, In);
3448     return DAG.getNode(Opc, dl, VT, In);
3449   }
3450 
3451   return Op;
3452 }
3453 
3454 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
3455                                             SelectionDAG &DAG) const {
3456   if (Op.getValueType().isVector())
3457     return LowerVectorINT_TO_FP(Op, DAG);
3458 
3459   bool IsStrict = Op->isStrictFPOpcode();
3460   SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
3461 
3462   // f16 conversions are promoted to f32 when full fp16 is not supported.
3463   if (Op.getValueType() == MVT::f16 &&
3464       !Subtarget->hasFullFP16()) {
3465     assert(!IsStrict && "Lowering of strict fp16 not yet implemented");
3466     SDLoc dl(Op);
3467     return DAG.getNode(
3468         ISD::FP_ROUND, dl, MVT::f16,
3469         DAG.getNode(Op.getOpcode(), dl, MVT::f32, SrcVal),
3470         DAG.getIntPtrConstant(0, dl));
3471   }
3472 
3473   // i128 conversions are libcalls.
3474   if (SrcVal.getValueType() == MVT::i128)
3475     return SDValue();
3476 
3477   // Other conversions are legal, unless it's to the completely software-based
3478   // fp128.
3479   if (Op.getValueType() != MVT::f128)
3480     return Op;
3481   return SDValue();
3482 }
3483 
3484 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
3485                                             SelectionDAG &DAG) const {
3486   // For iOS, we want to call an alternative entry point: __sincos_stret,
3487   // which returns the values in two S / D registers.
3488   SDLoc dl(Op);
3489   SDValue Arg = Op.getOperand(0);
3490   EVT ArgVT = Arg.getValueType();
3491   Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
3492 
3493   ArgListTy Args;
3494   ArgListEntry Entry;
3495 
3496   Entry.Node = Arg;
3497   Entry.Ty = ArgTy;
3498   Entry.IsSExt = false;
3499   Entry.IsZExt = false;
3500   Args.push_back(Entry);
3501 
3502   RTLIB::Libcall LC = ArgVT == MVT::f64 ? RTLIB::SINCOS_STRET_F64
3503                                         : RTLIB::SINCOS_STRET_F32;
3504   const char *LibcallName = getLibcallName(LC);
3505   SDValue Callee =
3506       DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout()));
3507 
3508   StructType *RetTy = StructType::get(ArgTy, ArgTy);
3509   TargetLowering::CallLoweringInfo CLI(DAG);
3510   CLI.setDebugLoc(dl)
3511       .setChain(DAG.getEntryNode())
3512       .setLibCallee(CallingConv::Fast, RetTy, Callee, std::move(Args));
3513 
3514   std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3515   return CallResult.first;
3516 }
3517 
3518 static MVT getSVEContainerType(EVT ContentTy);
3519 
3520 SDValue AArch64TargetLowering::LowerBITCAST(SDValue Op,
3521                                             SelectionDAG &DAG) const {
3522   EVT OpVT = Op.getValueType();
3523   EVT ArgVT = Op.getOperand(0).getValueType();
3524 
3525   if (useSVEForFixedLengthVectorVT(OpVT))
3526     return LowerFixedLengthBitcastToSVE(Op, DAG);
3527 
3528   if (OpVT.isScalableVector()) {
3529     if (isTypeLegal(OpVT) && !isTypeLegal(ArgVT)) {
3530       assert(OpVT.isFloatingPoint() && !ArgVT.isFloatingPoint() &&
3531              "Expected int->fp bitcast!");
3532       SDValue ExtResult =
3533           DAG.getNode(ISD::ANY_EXTEND, SDLoc(Op), getSVEContainerType(ArgVT),
3534                       Op.getOperand(0));
3535       return getSVESafeBitCast(OpVT, ExtResult, DAG);
3536     }
3537     return getSVESafeBitCast(OpVT, Op.getOperand(0), DAG);
3538   }
3539 
3540   if (OpVT != MVT::f16 && OpVT != MVT::bf16)
3541     return SDValue();
3542 
3543   assert(ArgVT == MVT::i16);
3544   SDLoc DL(Op);
3545 
3546   Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
3547   Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
3548   return SDValue(
3549       DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, OpVT, Op,
3550                          DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
3551       0);
3552 }
3553 
3554 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
3555   if (OrigVT.getSizeInBits() >= 64)
3556     return OrigVT;
3557 
3558   assert(OrigVT.isSimple() && "Expecting a simple value type");
3559 
3560   MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
3561   switch (OrigSimpleTy) {
3562   default: llvm_unreachable("Unexpected Vector Type");
3563   case MVT::v2i8:
3564   case MVT::v2i16:
3565      return MVT::v2i32;
3566   case MVT::v4i8:
3567     return  MVT::v4i16;
3568   }
3569 }
3570 
3571 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
3572                                                  const EVT &OrigTy,
3573                                                  const EVT &ExtTy,
3574                                                  unsigned ExtOpcode) {
3575   // The vector originally had a size of OrigTy. It was then extended to ExtTy.
3576   // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
3577   // 64-bits we need to insert a new extension so that it will be 64-bits.
3578   assert(ExtTy.is128BitVector() && "Unexpected extension size");
3579   if (OrigTy.getSizeInBits() >= 64)
3580     return N;
3581 
3582   // Must extend size to at least 64 bits to be used as an operand for VMULL.
3583   EVT NewVT = getExtensionTo64Bits(OrigTy);
3584 
3585   return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
3586 }
3587 
3588 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
3589                                    bool isSigned) {
3590   EVT VT = N->getValueType(0);
3591 
3592   if (N->getOpcode() != ISD::BUILD_VECTOR)
3593     return false;
3594 
3595   for (const SDValue &Elt : N->op_values()) {
3596     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
3597       unsigned EltSize = VT.getScalarSizeInBits();
3598       unsigned HalfSize = EltSize / 2;
3599       if (isSigned) {
3600         if (!isIntN(HalfSize, C->getSExtValue()))
3601           return false;
3602       } else {
3603         if (!isUIntN(HalfSize, C->getZExtValue()))
3604           return false;
3605       }
3606       continue;
3607     }
3608     return false;
3609   }
3610 
3611   return true;
3612 }
3613 
3614 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
3615   if (N->getOpcode() == ISD::SIGN_EXTEND ||
3616       N->getOpcode() == ISD::ZERO_EXTEND || N->getOpcode() == ISD::ANY_EXTEND)
3617     return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
3618                                              N->getOperand(0)->getValueType(0),
3619                                              N->getValueType(0),
3620                                              N->getOpcode());
3621 
3622   assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
3623   EVT VT = N->getValueType(0);
3624   SDLoc dl(N);
3625   unsigned EltSize = VT.getScalarSizeInBits() / 2;
3626   unsigned NumElts = VT.getVectorNumElements();
3627   MVT TruncVT = MVT::getIntegerVT(EltSize);
3628   SmallVector<SDValue, 8> Ops;
3629   for (unsigned i = 0; i != NumElts; ++i) {
3630     ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
3631     const APInt &CInt = C->getAPIntValue();
3632     // Element types smaller than 32 bits are not legal, so use i32 elements.
3633     // The values are implicitly truncated so sext vs. zext doesn't matter.
3634     Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
3635   }
3636   return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops);
3637 }
3638 
3639 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
3640   return N->getOpcode() == ISD::SIGN_EXTEND ||
3641          N->getOpcode() == ISD::ANY_EXTEND ||
3642          isExtendedBUILD_VECTOR(N, DAG, true);
3643 }
3644 
3645 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
3646   return N->getOpcode() == ISD::ZERO_EXTEND ||
3647          N->getOpcode() == ISD::ANY_EXTEND ||
3648          isExtendedBUILD_VECTOR(N, DAG, false);
3649 }
3650 
3651 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
3652   unsigned Opcode = N->getOpcode();
3653   if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
3654     SDNode *N0 = N->getOperand(0).getNode();
3655     SDNode *N1 = N->getOperand(1).getNode();
3656     return N0->hasOneUse() && N1->hasOneUse() &&
3657       isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
3658   }
3659   return false;
3660 }
3661 
3662 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
3663   unsigned Opcode = N->getOpcode();
3664   if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
3665     SDNode *N0 = N->getOperand(0).getNode();
3666     SDNode *N1 = N->getOperand(1).getNode();
3667     return N0->hasOneUse() && N1->hasOneUse() &&
3668       isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
3669   }
3670   return false;
3671 }
3672 
3673 SDValue AArch64TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3674                                                 SelectionDAG &DAG) const {
3675   // The rounding mode is in bits 23:22 of the FPSCR.
3676   // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3677   // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3678   // so that the shift + and get folded into a bitfield extract.
3679   SDLoc dl(Op);
3680 
3681   SDValue Chain = Op.getOperand(0);
3682   SDValue FPCR_64 = DAG.getNode(
3683       ISD::INTRINSIC_W_CHAIN, dl, {MVT::i64, MVT::Other},
3684       {Chain, DAG.getConstant(Intrinsic::aarch64_get_fpcr, dl, MVT::i64)});
3685   Chain = FPCR_64.getValue(1);
3686   SDValue FPCR_32 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, FPCR_64);
3687   SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPCR_32,
3688                                   DAG.getConstant(1U << 22, dl, MVT::i32));
3689   SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3690                               DAG.getConstant(22, dl, MVT::i32));
3691   SDValue AND = DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3692                             DAG.getConstant(3, dl, MVT::i32));
3693   return DAG.getMergeValues({AND, Chain}, dl);
3694 }
3695 
3696 SDValue AArch64TargetLowering::LowerSET_ROUNDING(SDValue Op,
3697                                                  SelectionDAG &DAG) const {
3698   SDLoc DL(Op);
3699   SDValue Chain = Op->getOperand(0);
3700   SDValue RMValue = Op->getOperand(1);
3701 
3702   // The rounding mode is in bits 23:22 of the FPCR.
3703   // The llvm.set.rounding argument value to the rounding mode in FPCR mapping
3704   // is 0->3, 1->0, 2->1, 3->2. The formula we use to implement this is
3705   // ((arg - 1) & 3) << 22).
3706   //
3707   // The argument of llvm.set.rounding must be within the segment [0, 3], so
3708   // NearestTiesToAway (4) is not handled here. It is responsibility of the code
3709   // generated llvm.set.rounding to ensure this condition.
3710 
3711   // Calculate new value of FPCR[23:22].
3712   RMValue = DAG.getNode(ISD::SUB, DL, MVT::i32, RMValue,
3713                         DAG.getConstant(1, DL, MVT::i32));
3714   RMValue = DAG.getNode(ISD::AND, DL, MVT::i32, RMValue,
3715                         DAG.getConstant(0x3, DL, MVT::i32));
3716   RMValue =
3717       DAG.getNode(ISD::SHL, DL, MVT::i32, RMValue,
3718                   DAG.getConstant(AArch64::RoundingBitsPos, DL, MVT::i32));
3719   RMValue = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, RMValue);
3720 
3721   // Get current value of FPCR.
3722   SDValue Ops[] = {
3723       Chain, DAG.getTargetConstant(Intrinsic::aarch64_get_fpcr, DL, MVT::i64)};
3724   SDValue FPCR =
3725       DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, {MVT::i64, MVT::Other}, Ops);
3726   Chain = FPCR.getValue(1);
3727   FPCR = FPCR.getValue(0);
3728 
3729   // Put new rounding mode into FPSCR[23:22].
3730   const int RMMask = ~(AArch64::Rounding::rmMask << AArch64::RoundingBitsPos);
3731   FPCR = DAG.getNode(ISD::AND, DL, MVT::i64, FPCR,
3732                      DAG.getConstant(RMMask, DL, MVT::i64));
3733   FPCR = DAG.getNode(ISD::OR, DL, MVT::i64, FPCR, RMValue);
3734   SDValue Ops2[] = {
3735       Chain, DAG.getTargetConstant(Intrinsic::aarch64_set_fpcr, DL, MVT::i64),
3736       FPCR};
3737   return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2);
3738 }
3739 
3740 SDValue AArch64TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
3741   EVT VT = Op.getValueType();
3742 
3743   // If SVE is available then i64 vector multiplications can also be made legal.
3744   bool OverrideNEON = VT == MVT::v2i64 || VT == MVT::v1i64;
3745 
3746   if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT, OverrideNEON))
3747     return LowerToPredicatedOp(Op, DAG, AArch64ISD::MUL_PRED, OverrideNEON);
3748 
3749   // Multiplications are only custom-lowered for 128-bit vectors so that
3750   // VMULL can be detected.  Otherwise v2i64 multiplications are not legal.
3751   assert(VT.is128BitVector() && VT.isInteger() &&
3752          "unexpected type for custom-lowering ISD::MUL");
3753   SDNode *N0 = Op.getOperand(0).getNode();
3754   SDNode *N1 = Op.getOperand(1).getNode();
3755   unsigned NewOpc = 0;
3756   bool isMLA = false;
3757   bool isN0SExt = isSignExtended(N0, DAG);
3758   bool isN1SExt = isSignExtended(N1, DAG);
3759   if (isN0SExt && isN1SExt)
3760     NewOpc = AArch64ISD::SMULL;
3761   else {
3762     bool isN0ZExt = isZeroExtended(N0, DAG);
3763     bool isN1ZExt = isZeroExtended(N1, DAG);
3764     if (isN0ZExt && isN1ZExt)
3765       NewOpc = AArch64ISD::UMULL;
3766     else if (isN1SExt || isN1ZExt) {
3767       // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
3768       // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
3769       if (isN1SExt && isAddSubSExt(N0, DAG)) {
3770         NewOpc = AArch64ISD::SMULL;
3771         isMLA = true;
3772       } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
3773         NewOpc =  AArch64ISD::UMULL;
3774         isMLA = true;
3775       } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
3776         std::swap(N0, N1);
3777         NewOpc =  AArch64ISD::UMULL;
3778         isMLA = true;
3779       }
3780     }
3781 
3782     if (!NewOpc) {
3783       if (VT == MVT::v2i64)
3784         // Fall through to expand this.  It is not legal.
3785         return SDValue();
3786       else
3787         // Other vector multiplications are legal.
3788         return Op;
3789     }
3790   }
3791 
3792   // Legalize to a S/UMULL instruction
3793   SDLoc DL(Op);
3794   SDValue Op0;
3795   SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
3796   if (!isMLA) {
3797     Op0 = skipExtensionForVectorMULL(N0, DAG);
3798     assert(Op0.getValueType().is64BitVector() &&
3799            Op1.getValueType().is64BitVector() &&
3800            "unexpected types for extended operands to VMULL");
3801     return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3802   }
3803   // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
3804   // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
3805   // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
3806   SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
3807   SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
3808   EVT Op1VT = Op1.getValueType();
3809   return DAG.getNode(N0->getOpcode(), DL, VT,
3810                      DAG.getNode(NewOpc, DL, VT,
3811                                DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
3812                      DAG.getNode(NewOpc, DL, VT,
3813                                DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
3814 }
3815 
3816 static inline SDValue getPTrue(SelectionDAG &DAG, SDLoc DL, EVT VT,
3817                                int Pattern) {
3818   return DAG.getNode(AArch64ISD::PTRUE, DL, VT,
3819                      DAG.getTargetConstant(Pattern, DL, MVT::i32));
3820 }
3821 
3822 static SDValue lowerConvertToSVBool(SDValue Op, SelectionDAG &DAG) {
3823   SDLoc DL(Op);
3824   EVT OutVT = Op.getValueType();
3825   SDValue InOp = Op.getOperand(1);
3826   EVT InVT = InOp.getValueType();
3827 
3828   // Return the operand if the cast isn't changing type,
3829   // i.e. <n x 16 x i1> -> <n x 16 x i1>
3830   if (InVT == OutVT)
3831     return InOp;
3832 
3833   SDValue Reinterpret =
3834       DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, OutVT, InOp);
3835 
3836   // If the argument converted to an svbool is a ptrue or a comparison, the
3837   // lanes introduced by the widening are zero by construction.
3838   switch (InOp.getOpcode()) {
3839   case AArch64ISD::SETCC_MERGE_ZERO:
3840     return Reinterpret;
3841   case ISD::INTRINSIC_WO_CHAIN:
3842     if (InOp.getConstantOperandVal(0) == Intrinsic::aarch64_sve_ptrue)
3843       return Reinterpret;
3844   }
3845 
3846   // Otherwise, zero the newly introduced lanes.
3847   SDValue Mask = getPTrue(DAG, DL, InVT, AArch64SVEPredPattern::all);
3848   SDValue MaskReinterpret =
3849       DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, OutVT, Mask);
3850   return DAG.getNode(ISD::AND, DL, OutVT, Reinterpret, MaskReinterpret);
3851 }
3852 
3853 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3854                                                      SelectionDAG &DAG) const {
3855   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3856   SDLoc dl(Op);
3857   switch (IntNo) {
3858   default: return SDValue();    // Don't custom lower most intrinsics.
3859   case Intrinsic::thread_pointer: {
3860     EVT PtrVT = getPointerTy(DAG.getDataLayout());
3861     return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT);
3862   }
3863   case Intrinsic::aarch64_neon_abs: {
3864     EVT Ty = Op.getValueType();
3865     if (Ty == MVT::i64) {
3866       SDValue Result = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64,
3867                                    Op.getOperand(1));
3868       Result = DAG.getNode(ISD::ABS, dl, MVT::v1i64, Result);
3869       return DAG.getNode(ISD::BITCAST, dl, MVT::i64, Result);
3870     } else if (Ty.isVector() && Ty.isInteger() && isTypeLegal(Ty)) {
3871       return DAG.getNode(ISD::ABS, dl, Ty, Op.getOperand(1));
3872     } else {
3873       report_fatal_error("Unexpected type for AArch64 NEON intrinic");
3874     }
3875   }
3876   case Intrinsic::aarch64_neon_smax:
3877     return DAG.getNode(ISD::SMAX, dl, Op.getValueType(),
3878                        Op.getOperand(1), Op.getOperand(2));
3879   case Intrinsic::aarch64_neon_umax:
3880     return DAG.getNode(ISD::UMAX, dl, Op.getValueType(),
3881                        Op.getOperand(1), Op.getOperand(2));
3882   case Intrinsic::aarch64_neon_smin:
3883     return DAG.getNode(ISD::SMIN, dl, Op.getValueType(),
3884                        Op.getOperand(1), Op.getOperand(2));
3885   case Intrinsic::aarch64_neon_umin:
3886     return DAG.getNode(ISD::UMIN, dl, Op.getValueType(),
3887                        Op.getOperand(1), Op.getOperand(2));
3888 
3889   case Intrinsic::aarch64_sve_sunpkhi:
3890     return DAG.getNode(AArch64ISD::SUNPKHI, dl, Op.getValueType(),
3891                        Op.getOperand(1));
3892   case Intrinsic::aarch64_sve_sunpklo:
3893     return DAG.getNode(AArch64ISD::SUNPKLO, dl, Op.getValueType(),
3894                        Op.getOperand(1));
3895   case Intrinsic::aarch64_sve_uunpkhi:
3896     return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(),
3897                        Op.getOperand(1));
3898   case Intrinsic::aarch64_sve_uunpklo:
3899     return DAG.getNode(AArch64ISD::UUNPKLO, dl, Op.getValueType(),
3900                        Op.getOperand(1));
3901   case Intrinsic::aarch64_sve_clasta_n:
3902     return DAG.getNode(AArch64ISD::CLASTA_N, dl, Op.getValueType(),
3903                        Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3904   case Intrinsic::aarch64_sve_clastb_n:
3905     return DAG.getNode(AArch64ISD::CLASTB_N, dl, Op.getValueType(),
3906                        Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3907   case Intrinsic::aarch64_sve_lasta:
3908     return DAG.getNode(AArch64ISD::LASTA, dl, Op.getValueType(),
3909                        Op.getOperand(1), Op.getOperand(2));
3910   case Intrinsic::aarch64_sve_lastb:
3911     return DAG.getNode(AArch64ISD::LASTB, dl, Op.getValueType(),
3912                        Op.getOperand(1), Op.getOperand(2));
3913   case Intrinsic::aarch64_sve_rev:
3914     return DAG.getNode(ISD::VECTOR_REVERSE, dl, Op.getValueType(),
3915                        Op.getOperand(1));
3916   case Intrinsic::aarch64_sve_tbl:
3917     return DAG.getNode(AArch64ISD::TBL, dl, Op.getValueType(),
3918                        Op.getOperand(1), Op.getOperand(2));
3919   case Intrinsic::aarch64_sve_trn1:
3920     return DAG.getNode(AArch64ISD::TRN1, dl, Op.getValueType(),
3921                        Op.getOperand(1), Op.getOperand(2));
3922   case Intrinsic::aarch64_sve_trn2:
3923     return DAG.getNode(AArch64ISD::TRN2, dl, Op.getValueType(),
3924                        Op.getOperand(1), Op.getOperand(2));
3925   case Intrinsic::aarch64_sve_uzp1:
3926     return DAG.getNode(AArch64ISD::UZP1, dl, Op.getValueType(),
3927                        Op.getOperand(1), Op.getOperand(2));
3928   case Intrinsic::aarch64_sve_uzp2:
3929     return DAG.getNode(AArch64ISD::UZP2, dl, Op.getValueType(),
3930                        Op.getOperand(1), Op.getOperand(2));
3931   case Intrinsic::aarch64_sve_zip1:
3932     return DAG.getNode(AArch64ISD::ZIP1, dl, Op.getValueType(),
3933                        Op.getOperand(1), Op.getOperand(2));
3934   case Intrinsic::aarch64_sve_zip2:
3935     return DAG.getNode(AArch64ISD::ZIP2, dl, Op.getValueType(),
3936                        Op.getOperand(1), Op.getOperand(2));
3937   case Intrinsic::aarch64_sve_splice:
3938     return DAG.getNode(AArch64ISD::SPLICE, dl, Op.getValueType(),
3939                        Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3940   case Intrinsic::aarch64_sve_ptrue:
3941     return DAG.getNode(AArch64ISD::PTRUE, dl, Op.getValueType(),
3942                        Op.getOperand(1));
3943   case Intrinsic::aarch64_sve_clz:
3944     return DAG.getNode(AArch64ISD::CTLZ_MERGE_PASSTHRU, dl, Op.getValueType(),
3945                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3946   case Intrinsic::aarch64_sve_cnt: {
3947     SDValue Data = Op.getOperand(3);
3948     // CTPOP only supports integer operands.
3949     if (Data.getValueType().isFloatingPoint())
3950       Data = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Data);
3951     return DAG.getNode(AArch64ISD::CTPOP_MERGE_PASSTHRU, dl, Op.getValueType(),
3952                        Op.getOperand(2), Data, Op.getOperand(1));
3953   }
3954   case Intrinsic::aarch64_sve_dupq_lane:
3955     return LowerDUPQLane(Op, DAG);
3956   case Intrinsic::aarch64_sve_convert_from_svbool:
3957     return DAG.getNode(AArch64ISD::REINTERPRET_CAST, dl, Op.getValueType(),
3958                        Op.getOperand(1));
3959   case Intrinsic::aarch64_sve_convert_to_svbool:
3960     return lowerConvertToSVBool(Op, DAG);
3961   case Intrinsic::aarch64_sve_fneg:
3962     return DAG.getNode(AArch64ISD::FNEG_MERGE_PASSTHRU, dl, Op.getValueType(),
3963                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3964   case Intrinsic::aarch64_sve_frintp:
3965     return DAG.getNode(AArch64ISD::FCEIL_MERGE_PASSTHRU, dl, Op.getValueType(),
3966                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3967   case Intrinsic::aarch64_sve_frintm:
3968     return DAG.getNode(AArch64ISD::FFLOOR_MERGE_PASSTHRU, dl, Op.getValueType(),
3969                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3970   case Intrinsic::aarch64_sve_frinti:
3971     return DAG.getNode(AArch64ISD::FNEARBYINT_MERGE_PASSTHRU, dl, Op.getValueType(),
3972                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3973   case Intrinsic::aarch64_sve_frintx:
3974     return DAG.getNode(AArch64ISD::FRINT_MERGE_PASSTHRU, dl, Op.getValueType(),
3975                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3976   case Intrinsic::aarch64_sve_frinta:
3977     return DAG.getNode(AArch64ISD::FROUND_MERGE_PASSTHRU, dl, Op.getValueType(),
3978                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3979   case Intrinsic::aarch64_sve_frintn:
3980     return DAG.getNode(AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU, dl, Op.getValueType(),
3981                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3982   case Intrinsic::aarch64_sve_frintz:
3983     return DAG.getNode(AArch64ISD::FTRUNC_MERGE_PASSTHRU, dl, Op.getValueType(),
3984                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
3985   case Intrinsic::aarch64_sve_ucvtf:
3986     return DAG.getNode(AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU, dl,
3987                        Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
3988                        Op.getOperand(1));
3989   case Intrinsic::aarch64_sve_scvtf:
3990     return DAG.getNode(AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU, dl,
3991                        Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
3992                        Op.getOperand(1));
3993   case Intrinsic::aarch64_sve_fcvtzu:
3994     return DAG.getNode(AArch64ISD::FCVTZU_MERGE_PASSTHRU, dl,
3995                        Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
3996                        Op.getOperand(1));
3997   case Intrinsic::aarch64_sve_fcvtzs:
3998     return DAG.getNode(AArch64ISD::FCVTZS_MERGE_PASSTHRU, dl,
3999                        Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
4000                        Op.getOperand(1));
4001   case Intrinsic::aarch64_sve_fsqrt:
4002     return DAG.getNode(AArch64ISD::FSQRT_MERGE_PASSTHRU, dl, Op.getValueType(),
4003                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
4004   case Intrinsic::aarch64_sve_frecpx:
4005     return DAG.getNode(AArch64ISD::FRECPX_MERGE_PASSTHRU, dl, Op.getValueType(),
4006                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
4007   case Intrinsic::aarch64_sve_fabs:
4008     return DAG.getNode(AArch64ISD::FABS_MERGE_PASSTHRU, dl, Op.getValueType(),
4009                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
4010   case Intrinsic::aarch64_sve_abs:
4011     return DAG.getNode(AArch64ISD::ABS_MERGE_PASSTHRU, dl, Op.getValueType(),
4012                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
4013   case Intrinsic::aarch64_sve_neg:
4014     return DAG.getNode(AArch64ISD::NEG_MERGE_PASSTHRU, dl, Op.getValueType(),
4015                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
4016   case Intrinsic::aarch64_sve_insr: {
4017     SDValue Scalar = Op.getOperand(2);
4018     EVT ScalarTy = Scalar.getValueType();
4019     if ((ScalarTy == MVT::i8) || (ScalarTy == MVT::i16))
4020       Scalar = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Scalar);
4021 
4022     return DAG.getNode(AArch64ISD::INSR, dl, Op.getValueType(),
4023                        Op.getOperand(1), Scalar);
4024   }
4025   case Intrinsic::aarch64_sve_rbit:
4026     return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl,
4027                        Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
4028                        Op.getOperand(1));
4029   case Intrinsic::aarch64_sve_revb:
4030     return DAG.getNode(AArch64ISD::BSWAP_MERGE_PASSTHRU, dl, Op.getValueType(),
4031                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
4032   case Intrinsic::aarch64_sve_sxtb:
4033     return DAG.getNode(
4034         AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, dl, Op.getValueType(),
4035         Op.getOperand(2), Op.getOperand(3),
4036         DAG.getValueType(Op.getValueType().changeVectorElementType(MVT::i8)),
4037         Op.getOperand(1));
4038   case Intrinsic::aarch64_sve_sxth:
4039     return DAG.getNode(
4040         AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, dl, Op.getValueType(),
4041         Op.getOperand(2), Op.getOperand(3),
4042         DAG.getValueType(Op.getValueType().changeVectorElementType(MVT::i16)),
4043         Op.getOperand(1));
4044   case Intrinsic::aarch64_sve_sxtw:
4045     return DAG.getNode(
4046         AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, dl, Op.getValueType(),
4047         Op.getOperand(2), Op.getOperand(3),
4048         DAG.getValueType(Op.getValueType().changeVectorElementType(MVT::i32)),
4049         Op.getOperand(1));
4050   case Intrinsic::aarch64_sve_uxtb:
4051     return DAG.getNode(
4052         AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU, dl, Op.getValueType(),
4053         Op.getOperand(2), Op.getOperand(3),
4054         DAG.getValueType(Op.getValueType().changeVectorElementType(MVT::i8)),
4055         Op.getOperand(1));
4056   case Intrinsic::aarch64_sve_uxth:
4057     return DAG.getNode(
4058         AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU, dl, Op.getValueType(),
4059         Op.getOperand(2), Op.getOperand(3),
4060         DAG.getValueType(Op.getValueType().changeVectorElementType(MVT::i16)),
4061         Op.getOperand(1));
4062   case Intrinsic::aarch64_sve_uxtw:
4063     return DAG.getNode(
4064         AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU, dl, Op.getValueType(),
4065         Op.getOperand(2), Op.getOperand(3),
4066         DAG.getValueType(Op.getValueType().changeVectorElementType(MVT::i32)),
4067         Op.getOperand(1));
4068 
4069   case Intrinsic::localaddress: {
4070     const auto &MF = DAG.getMachineFunction();
4071     const auto *RegInfo = Subtarget->getRegisterInfo();
4072     unsigned Reg = RegInfo->getLocalAddressRegister(MF);
4073     return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg,
4074                               Op.getSimpleValueType());
4075   }
4076 
4077   case Intrinsic::eh_recoverfp: {
4078     // FIXME: This needs to be implemented to correctly handle highly aligned
4079     // stack objects. For now we simply return the incoming FP. Refer D53541
4080     // for more details.
4081     SDValue FnOp = Op.getOperand(1);
4082     SDValue IncomingFPOp = Op.getOperand(2);
4083     GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
4084     auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
4085     if (!Fn)
4086       report_fatal_error(
4087           "llvm.eh.recoverfp must take a function as the first argument");
4088     return IncomingFPOp;
4089   }
4090 
4091   case Intrinsic::aarch64_neon_vsri:
4092   case Intrinsic::aarch64_neon_vsli: {
4093     EVT Ty = Op.getValueType();
4094 
4095     if (!Ty.isVector())
4096       report_fatal_error("Unexpected type for aarch64_neon_vsli");
4097 
4098     assert(Op.getConstantOperandVal(3) <= Ty.getScalarSizeInBits());
4099 
4100     bool IsShiftRight = IntNo == Intrinsic::aarch64_neon_vsri;
4101     unsigned Opcode = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI;
4102     return DAG.getNode(Opcode, dl, Ty, Op.getOperand(1), Op.getOperand(2),
4103                        Op.getOperand(3));
4104   }
4105 
4106   case Intrinsic::aarch64_neon_srhadd:
4107   case Intrinsic::aarch64_neon_urhadd:
4108   case Intrinsic::aarch64_neon_shadd:
4109   case Intrinsic::aarch64_neon_uhadd: {
4110     bool IsSignedAdd = (IntNo == Intrinsic::aarch64_neon_srhadd ||
4111                         IntNo == Intrinsic::aarch64_neon_shadd);
4112     bool IsRoundingAdd = (IntNo == Intrinsic::aarch64_neon_srhadd ||
4113                           IntNo == Intrinsic::aarch64_neon_urhadd);
4114     unsigned Opcode =
4115         IsSignedAdd ? (IsRoundingAdd ? AArch64ISD::SRHADD : AArch64ISD::SHADD)
4116                     : (IsRoundingAdd ? AArch64ISD::URHADD : AArch64ISD::UHADD);
4117     return DAG.getNode(Opcode, dl, Op.getValueType(), Op.getOperand(1),
4118                        Op.getOperand(2));
4119   }
4120   case Intrinsic::aarch64_neon_sabd:
4121   case Intrinsic::aarch64_neon_uabd: {
4122     unsigned Opcode = IntNo == Intrinsic::aarch64_neon_uabd ? ISD::ABDU
4123                                                             : ISD::ABDS;
4124     return DAG.getNode(Opcode, dl, Op.getValueType(), Op.getOperand(1),
4125                        Op.getOperand(2));
4126   }
4127   case Intrinsic::aarch64_neon_uaddlp: {
4128     unsigned Opcode = AArch64ISD::UADDLP;
4129     return DAG.getNode(Opcode, dl, Op.getValueType(), Op.getOperand(1));
4130   }
4131   case Intrinsic::aarch64_neon_sdot:
4132   case Intrinsic::aarch64_neon_udot:
4133   case Intrinsic::aarch64_sve_sdot:
4134   case Intrinsic::aarch64_sve_udot: {
4135     unsigned Opcode = (IntNo == Intrinsic::aarch64_neon_udot ||
4136                        IntNo == Intrinsic::aarch64_sve_udot)
4137                           ? AArch64ISD::UDOT
4138                           : AArch64ISD::SDOT;
4139     return DAG.getNode(Opcode, dl, Op.getValueType(), Op.getOperand(1),
4140                        Op.getOperand(2), Op.getOperand(3));
4141   }
4142   }
4143 }
4144 
4145 bool AArch64TargetLowering::shouldExtendGSIndex(EVT VT, EVT &EltTy) const {
4146   if (VT.getVectorElementType() == MVT::i8 ||
4147       VT.getVectorElementType() == MVT::i16) {
4148     EltTy = MVT::i32;
4149     return true;
4150   }
4151   return false;
4152 }
4153 
4154 bool AArch64TargetLowering::shouldRemoveExtendFromGSIndex(EVT VT) const {
4155   if (VT.getVectorElementType() == MVT::i32 &&
4156       VT.getVectorElementCount().getKnownMinValue() >= 4)
4157     return true;
4158 
4159   return false;
4160 }
4161 
4162 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
4163   return ExtVal.getValueType().isScalableVector();
4164 }
4165 
4166 unsigned getGatherVecOpcode(bool IsScaled, bool IsSigned, bool NeedsExtend) {
4167   std::map<std::tuple<bool, bool, bool>, unsigned> AddrModes = {
4168       {std::make_tuple(/*Scaled*/ false, /*Signed*/ false, /*Extend*/ false),
4169        AArch64ISD::GLD1_MERGE_ZERO},
4170       {std::make_tuple(/*Scaled*/ false, /*Signed*/ false, /*Extend*/ true),
4171        AArch64ISD::GLD1_UXTW_MERGE_ZERO},
4172       {std::make_tuple(/*Scaled*/ false, /*Signed*/ true, /*Extend*/ false),
4173        AArch64ISD::GLD1_MERGE_ZERO},
4174       {std::make_tuple(/*Scaled*/ false, /*Signed*/ true, /*Extend*/ true),
4175        AArch64ISD::GLD1_SXTW_MERGE_ZERO},
4176       {std::make_tuple(/*Scaled*/ true, /*Signed*/ false, /*Extend*/ false),
4177        AArch64ISD::GLD1_SCALED_MERGE_ZERO},
4178       {std::make_tuple(/*Scaled*/ true, /*Signed*/ false, /*Extend*/ true),
4179        AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO},
4180       {std::make_tuple(/*Scaled*/ true, /*Signed*/ true, /*Extend*/ false),
4181        AArch64ISD::GLD1_SCALED_MERGE_ZERO},
4182       {std::make_tuple(/*Scaled*/ true, /*Signed*/ true, /*Extend*/ true),
4183        AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO},
4184   };
4185   auto Key = std::make_tuple(IsScaled, IsSigned, NeedsExtend);
4186   return AddrModes.find(Key)->second;
4187 }
4188 
4189 unsigned getScatterVecOpcode(bool IsScaled, bool IsSigned, bool NeedsExtend) {
4190   std::map<std::tuple<bool, bool, bool>, unsigned> AddrModes = {
4191       {std::make_tuple(/*Scaled*/ false, /*Signed*/ false, /*Extend*/ false),
4192        AArch64ISD::SST1_PRED},
4193       {std::make_tuple(/*Scaled*/ false, /*Signed*/ false, /*Extend*/ true),
4194        AArch64ISD::SST1_UXTW_PRED},
4195       {std::make_tuple(/*Scaled*/ false, /*Signed*/ true, /*Extend*/ false),
4196        AArch64ISD::SST1_PRED},
4197       {std::make_tuple(/*Scaled*/ false, /*Signed*/ true, /*Extend*/ true),
4198        AArch64ISD::SST1_SXTW_PRED},
4199       {std::make_tuple(/*Scaled*/ true, /*Signed*/ false, /*Extend*/ false),
4200        AArch64ISD::SST1_SCALED_PRED},
4201       {std::make_tuple(/*Scaled*/ true, /*Signed*/ false, /*Extend*/ true),
4202        AArch64ISD::SST1_UXTW_SCALED_PRED},
4203       {std::make_tuple(/*Scaled*/ true, /*Signed*/ true, /*Extend*/ false),
4204        AArch64ISD::SST1_SCALED_PRED},
4205       {std::make_tuple(/*Scaled*/ true, /*Signed*/ true, /*Extend*/ true),
4206        AArch64ISD::SST1_SXTW_SCALED_PRED},
4207   };
4208   auto Key = std::make_tuple(IsScaled, IsSigned, NeedsExtend);
4209   return AddrModes.find(Key)->second;
4210 }
4211 
4212 unsigned getSignExtendedGatherOpcode(unsigned Opcode) {
4213   switch (Opcode) {
4214   default:
4215     llvm_unreachable("unimplemented opcode");
4216     return Opcode;
4217   case AArch64ISD::GLD1_MERGE_ZERO:
4218     return AArch64ISD::GLD1S_MERGE_ZERO;
4219   case AArch64ISD::GLD1_IMM_MERGE_ZERO:
4220     return AArch64ISD::GLD1S_IMM_MERGE_ZERO;
4221   case AArch64ISD::GLD1_UXTW_MERGE_ZERO:
4222     return AArch64ISD::GLD1S_UXTW_MERGE_ZERO;
4223   case AArch64ISD::GLD1_SXTW_MERGE_ZERO:
4224     return AArch64ISD::GLD1S_SXTW_MERGE_ZERO;
4225   case AArch64ISD::GLD1_SCALED_MERGE_ZERO:
4226     return AArch64ISD::GLD1S_SCALED_MERGE_ZERO;
4227   case AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO:
4228     return AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO;
4229   case AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO:
4230     return AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO;
4231   }
4232 }
4233 
4234 bool getGatherScatterIndexIsExtended(SDValue Index) {
4235   unsigned Opcode = Index.getOpcode();
4236   if (Opcode == ISD::SIGN_EXTEND_INREG)
4237     return true;
4238 
4239   if (Opcode == ISD::AND) {
4240     SDValue Splat = Index.getOperand(1);
4241     if (Splat.getOpcode() != ISD::SPLAT_VECTOR)
4242       return false;
4243     ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Splat.getOperand(0));
4244     if (!Mask || Mask->getZExtValue() != 0xFFFFFFFF)
4245       return false;
4246     return true;
4247   }
4248 
4249   return false;
4250 }
4251 
4252 // If the base pointer of a masked gather or scatter is null, we
4253 // may be able to swap BasePtr & Index and use the vector + register
4254 // or vector + immediate addressing mode, e.g.
4255 // VECTOR + REGISTER:
4256 //    getelementptr nullptr, <vscale x N x T> (splat(%offset)) + %indices)
4257 // -> getelementptr %offset, <vscale x N x T> %indices
4258 // VECTOR + IMMEDIATE:
4259 //    getelementptr nullptr, <vscale x N x T> (splat(#x)) + %indices)
4260 // -> getelementptr #x, <vscale x N x T> %indices
4261 void selectGatherScatterAddrMode(SDValue &BasePtr, SDValue &Index, EVT MemVT,
4262                                  unsigned &Opcode, bool IsGather,
4263                                  SelectionDAG &DAG) {
4264   if (!isNullConstant(BasePtr))
4265     return;
4266 
4267   // FIXME: This will not match for fixed vector type codegen as the nodes in
4268   // question will have fixed<->scalable conversions around them. This should be
4269   // moved to a DAG combine or complex pattern so that is executes after all of
4270   // the fixed vector insert and extracts have been removed. This deficiency
4271   // will result in a sub-optimal addressing mode being used, i.e. an ADD not
4272   // being folded into the scatter/gather.
4273   ConstantSDNode *Offset = nullptr;
4274   if (Index.getOpcode() == ISD::ADD)
4275     if (auto SplatVal = DAG.getSplatValue(Index.getOperand(1))) {
4276       if (isa<ConstantSDNode>(SplatVal))
4277         Offset = cast<ConstantSDNode>(SplatVal);
4278       else {
4279         BasePtr = SplatVal;
4280         Index = Index->getOperand(0);
4281         return;
4282       }
4283     }
4284 
4285   unsigned NewOp =
4286       IsGather ? AArch64ISD::GLD1_IMM_MERGE_ZERO : AArch64ISD::SST1_IMM_PRED;
4287 
4288   if (!Offset) {
4289     std::swap(BasePtr, Index);
4290     Opcode = NewOp;
4291     return;
4292   }
4293 
4294   uint64_t OffsetVal = Offset->getZExtValue();
4295   unsigned ScalarSizeInBytes = MemVT.getScalarSizeInBits() / 8;
4296   auto ConstOffset = DAG.getConstant(OffsetVal, SDLoc(Index), MVT::i64);
4297 
4298   if (OffsetVal % ScalarSizeInBytes || OffsetVal / ScalarSizeInBytes > 31) {
4299     // Index is out of range for the immediate addressing mode
4300     BasePtr = ConstOffset;
4301     Index = Index->getOperand(0);
4302     return;
4303   }
4304 
4305   // Immediate is in range
4306   Opcode = NewOp;
4307   BasePtr = Index->getOperand(0);
4308   Index = ConstOffset;
4309 }
4310 
4311 SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,
4312                                             SelectionDAG &DAG) const {
4313   SDLoc DL(Op);
4314   MaskedGatherSDNode *MGT = cast<MaskedGatherSDNode>(Op);
4315   assert(MGT && "Can only custom lower gather load nodes");
4316 
4317   bool IsFixedLength = MGT->getMemoryVT().isFixedLengthVector();
4318 
4319   SDValue Index = MGT->getIndex();
4320   SDValue Chain = MGT->getChain();
4321   SDValue PassThru = MGT->getPassThru();
4322   SDValue Mask = MGT->getMask();
4323   SDValue BasePtr = MGT->getBasePtr();
4324   ISD::LoadExtType ExtTy = MGT->getExtensionType();
4325 
4326   ISD::MemIndexType IndexType = MGT->getIndexType();
4327   bool IsScaled =
4328       IndexType == ISD::SIGNED_SCALED || IndexType == ISD::UNSIGNED_SCALED;
4329   bool IsSigned =
4330       IndexType == ISD::SIGNED_SCALED || IndexType == ISD::SIGNED_UNSCALED;
4331   bool IdxNeedsExtend =
4332       getGatherScatterIndexIsExtended(Index) ||
4333       Index.getSimpleValueType().getVectorElementType() == MVT::i32;
4334   bool ResNeedsSignExtend = ExtTy == ISD::EXTLOAD || ExtTy == ISD::SEXTLOAD;
4335 
4336   EVT VT = PassThru.getSimpleValueType();
4337   EVT IndexVT = Index.getSimpleValueType();
4338   EVT MemVT = MGT->getMemoryVT();
4339   SDValue InputVT = DAG.getValueType(MemVT);
4340 
4341   if (VT.getVectorElementType() == MVT::bf16 &&
4342       !static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasBF16())
4343     return SDValue();
4344 
4345   if (IsFixedLength) {
4346     assert(Subtarget->useSVEForFixedLengthVectors() &&
4347            "Cannot lower when not using SVE for fixed vectors");
4348     IndexVT = getContainerForFixedLengthVector(DAG, IndexVT);
4349     MemVT = IndexVT.changeVectorElementType(MemVT.getVectorElementType());
4350     InputVT = DAG.getValueType(MemVT.changeTypeToInteger());
4351   }
4352 
4353   if (PassThru->isUndef() || isZerosVector(PassThru.getNode()))
4354     PassThru = SDValue();
4355 
4356   if (VT.isFloatingPoint() && !IsFixedLength) {
4357     // Handle FP data by using an integer gather and casting the result.
4358     if (PassThru) {
4359       EVT PassThruVT = getPackedSVEVectorVT(VT.getVectorElementCount());
4360       PassThru = getSVESafeBitCast(PassThruVT, PassThru, DAG);
4361     }
4362     InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger());
4363   }
4364 
4365   SDVTList VTs = DAG.getVTList(IndexVT, MVT::Other);
4366 
4367   if (getGatherScatterIndexIsExtended(Index))
4368     Index = Index.getOperand(0);
4369 
4370   unsigned Opcode = getGatherVecOpcode(IsScaled, IsSigned, IdxNeedsExtend);
4371   selectGatherScatterAddrMode(BasePtr, Index, MemVT, Opcode,
4372                               /*isGather=*/true, DAG);
4373 
4374   if (ResNeedsSignExtend)
4375     Opcode = getSignExtendedGatherOpcode(Opcode);
4376 
4377   if (IsFixedLength) {
4378     if (Index.getSimpleValueType().isFixedLengthVector())
4379       Index = convertToScalableVector(DAG, IndexVT, Index);
4380     if (BasePtr.getSimpleValueType().isFixedLengthVector())
4381       BasePtr = convertToScalableVector(DAG, IndexVT, BasePtr);
4382     Mask = convertFixedMaskToScalableVector(Mask, DAG);
4383   }
4384 
4385   SDValue Ops[] = {Chain, Mask, BasePtr, Index, InputVT};
4386   SDValue Result = DAG.getNode(Opcode, DL, VTs, Ops);
4387   Chain = Result.getValue(1);
4388 
4389   if (IsFixedLength) {
4390     Result = convertFromScalableVector(
4391         DAG, VT.changeVectorElementType(IndexVT.getVectorElementType()),
4392         Result);
4393     Result = DAG.getNode(ISD::TRUNCATE, DL, VT.changeTypeToInteger(), Result);
4394     Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
4395 
4396     if (PassThru)
4397       Result = DAG.getSelect(DL, VT, MGT->getMask(), Result, PassThru);
4398   } else {
4399     if (PassThru)
4400       Result = DAG.getSelect(DL, IndexVT, Mask, Result, PassThru);
4401 
4402     if (VT.isFloatingPoint())
4403       Result = getSVESafeBitCast(VT, Result, DAG);
4404   }
4405 
4406   return DAG.getMergeValues({Result, Chain}, DL);
4407 }
4408 
4409 SDValue AArch64TargetLowering::LowerMSCATTER(SDValue Op,
4410                                              SelectionDAG &DAG) const {
4411   SDLoc DL(Op);
4412   MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(Op);
4413   assert(MSC && "Can only custom lower scatter store nodes");
4414 
4415   bool IsFixedLength = MSC->getMemoryVT().isFixedLengthVector();
4416 
4417   SDValue Index = MSC->getIndex();
4418   SDValue Chain = MSC->getChain();
4419   SDValue StoreVal = MSC->getValue();
4420   SDValue Mask = MSC->getMask();
4421   SDValue BasePtr = MSC->getBasePtr();
4422 
4423   ISD::MemIndexType IndexType = MSC->getIndexType();
4424   bool IsScaled =
4425       IndexType == ISD::SIGNED_SCALED || IndexType == ISD::UNSIGNED_SCALED;
4426   bool IsSigned =
4427       IndexType == ISD::SIGNED_SCALED || IndexType == ISD::SIGNED_UNSCALED;
4428   bool NeedsExtend =
4429       getGatherScatterIndexIsExtended(Index) ||
4430       Index.getSimpleValueType().getVectorElementType() == MVT::i32;
4431 
4432   EVT VT = StoreVal.getSimpleValueType();
4433   EVT IndexVT = Index.getSimpleValueType();
4434   SDVTList VTs = DAG.getVTList(MVT::Other);
4435   EVT MemVT = MSC->getMemoryVT();
4436   SDValue InputVT = DAG.getValueType(MemVT);
4437 
4438   if (VT.getVectorElementType() == MVT::bf16 &&
4439       !static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasBF16())
4440     return SDValue();
4441 
4442   if (IsFixedLength) {
4443     assert(Subtarget->useSVEForFixedLengthVectors() &&
4444            "Cannot lower when not using SVE for fixed vectors");
4445     IndexVT = getContainerForFixedLengthVector(DAG, IndexVT);
4446     MemVT = IndexVT.changeVectorElementType(MemVT.getVectorElementType());
4447     InputVT = DAG.getValueType(MemVT.changeTypeToInteger());
4448 
4449     StoreVal =
4450         DAG.getNode(ISD::BITCAST, DL, VT.changeTypeToInteger(), StoreVal);
4451     StoreVal = DAG.getNode(
4452         ISD::ANY_EXTEND, DL,
4453         VT.changeVectorElementType(IndexVT.getVectorElementType()), StoreVal);
4454     StoreVal = convertToScalableVector(DAG, IndexVT, StoreVal);
4455   } else if (VT.isFloatingPoint()) {
4456     // Handle FP data by casting the data so an integer scatter can be used.
4457     EVT StoreValVT = getPackedSVEVectorVT(VT.getVectorElementCount());
4458     StoreVal = getSVESafeBitCast(StoreValVT, StoreVal, DAG);
4459     InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger());
4460   }
4461 
4462   if (getGatherScatterIndexIsExtended(Index))
4463     Index = Index.getOperand(0);
4464 
4465   unsigned Opcode = getScatterVecOpcode(IsScaled, IsSigned, NeedsExtend);
4466   selectGatherScatterAddrMode(BasePtr, Index, MemVT, Opcode,
4467                               /*isGather=*/false, DAG);
4468 
4469   if (IsFixedLength) {
4470     if (Index.getSimpleValueType().isFixedLengthVector())
4471       Index = convertToScalableVector(DAG, IndexVT, Index);
4472     if (BasePtr.getSimpleValueType().isFixedLengthVector())
4473       BasePtr = convertToScalableVector(DAG, IndexVT, BasePtr);
4474     Mask = convertFixedMaskToScalableVector(Mask, DAG);
4475   }
4476 
4477   SDValue Ops[] = {Chain, StoreVal, Mask, BasePtr, Index, InputVT};
4478   return DAG.getNode(Opcode, DL, VTs, Ops);
4479 }
4480 
4481 SDValue AArch64TargetLowering::LowerMLOAD(SDValue Op, SelectionDAG &DAG) const {
4482   SDLoc DL(Op);
4483   MaskedLoadSDNode *LoadNode = cast<MaskedLoadSDNode>(Op);
4484   assert(LoadNode && "Expected custom lowering of a masked load node");
4485   EVT VT = Op->getValueType(0);
4486 
4487   if (useSVEForFixedLengthVectorVT(VT, true))
4488     return LowerFixedLengthVectorMLoadToSVE(Op, DAG);
4489 
4490   SDValue PassThru = LoadNode->getPassThru();
4491   SDValue Mask = LoadNode->getMask();
4492 
4493   if (PassThru->isUndef() || isZerosVector(PassThru.getNode()))
4494     return Op;
4495 
4496   SDValue Load = DAG.getMaskedLoad(
4497       VT, DL, LoadNode->getChain(), LoadNode->getBasePtr(),
4498       LoadNode->getOffset(), Mask, DAG.getUNDEF(VT), LoadNode->getMemoryVT(),
4499       LoadNode->getMemOperand(), LoadNode->getAddressingMode(),
4500       LoadNode->getExtensionType());
4501 
4502   SDValue Result = DAG.getSelect(DL, VT, Mask, Load, PassThru);
4503 
4504   return DAG.getMergeValues({Result, Load.getValue(1)}, DL);
4505 }
4506 
4507 // Custom lower trunc store for v4i8 vectors, since it is promoted to v4i16.
4508 static SDValue LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST,
4509                                         EVT VT, EVT MemVT,
4510                                         SelectionDAG &DAG) {
4511   assert(VT.isVector() && "VT should be a vector type");
4512   assert(MemVT == MVT::v4i8 && VT == MVT::v4i16);
4513 
4514   SDValue Value = ST->getValue();
4515 
4516   // It first extend the promoted v4i16 to v8i16, truncate to v8i8, and extract
4517   // the word lane which represent the v4i8 subvector.  It optimizes the store
4518   // to:
4519   //
4520   //   xtn  v0.8b, v0.8h
4521   //   str  s0, [x0]
4522 
4523   SDValue Undef = DAG.getUNDEF(MVT::i16);
4524   SDValue UndefVec = DAG.getBuildVector(MVT::v4i16, DL,
4525                                         {Undef, Undef, Undef, Undef});
4526 
4527   SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16,
4528                                  Value, UndefVec);
4529   SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i8, TruncExt);
4530 
4531   Trunc = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Trunc);
4532   SDValue ExtractTrunc = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
4533                                      Trunc, DAG.getConstant(0, DL, MVT::i64));
4534 
4535   return DAG.getStore(ST->getChain(), DL, ExtractTrunc,
4536                       ST->getBasePtr(), ST->getMemOperand());
4537 }
4538 
4539 // Custom lowering for any store, vector or scalar and/or default or with
4540 // a truncate operations.  Currently only custom lower truncate operation
4541 // from vector v4i16 to v4i8 or volatile stores of i128.
4542 SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
4543                                           SelectionDAG &DAG) const {
4544   SDLoc Dl(Op);
4545   StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
4546   assert (StoreNode && "Can only custom lower store nodes");
4547 
4548   SDValue Value = StoreNode->getValue();
4549 
4550   EVT VT = Value.getValueType();
4551   EVT MemVT = StoreNode->getMemoryVT();
4552 
4553   if (VT.isVector()) {
4554     if (useSVEForFixedLengthVectorVT(VT, true))
4555       return LowerFixedLengthVectorStoreToSVE(Op, DAG);
4556 
4557     unsigned AS = StoreNode->getAddressSpace();
4558     Align Alignment = StoreNode->getAlign();
4559     if (Alignment < MemVT.getStoreSize() &&
4560         !allowsMisalignedMemoryAccesses(MemVT, AS, Alignment,
4561                                         StoreNode->getMemOperand()->getFlags(),
4562                                         nullptr)) {
4563       return scalarizeVectorStore(StoreNode, DAG);
4564     }
4565 
4566     if (StoreNode->isTruncatingStore() && VT == MVT::v4i16 &&
4567         MemVT == MVT::v4i8) {
4568       return LowerTruncateVectorStore(Dl, StoreNode, VT, MemVT, DAG);
4569     }
4570     // 256 bit non-temporal stores can be lowered to STNP. Do this as part of
4571     // the custom lowering, as there are no un-paired non-temporal stores and
4572     // legalization will break up 256 bit inputs.
4573     ElementCount EC = MemVT.getVectorElementCount();
4574     if (StoreNode->isNonTemporal() && MemVT.getSizeInBits() == 256u &&
4575         EC.isKnownEven() &&
4576         ((MemVT.getScalarSizeInBits() == 8u ||
4577           MemVT.getScalarSizeInBits() == 16u ||
4578           MemVT.getScalarSizeInBits() == 32u ||
4579           MemVT.getScalarSizeInBits() == 64u))) {
4580       SDValue Lo =
4581           DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl,
4582                       MemVT.getHalfNumVectorElementsVT(*DAG.getContext()),
4583                       StoreNode->getValue(), DAG.getConstant(0, Dl, MVT::i64));
4584       SDValue Hi =
4585           DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl,
4586                       MemVT.getHalfNumVectorElementsVT(*DAG.getContext()),
4587                       StoreNode->getValue(),
4588                       DAG.getConstant(EC.getKnownMinValue() / 2, Dl, MVT::i64));
4589       SDValue Result = DAG.getMemIntrinsicNode(
4590           AArch64ISD::STNP, Dl, DAG.getVTList(MVT::Other),
4591           {StoreNode->getChain(), Lo, Hi, StoreNode->getBasePtr()},
4592           StoreNode->getMemoryVT(), StoreNode->getMemOperand());
4593       return Result;
4594     }
4595   } else if (MemVT == MVT::i128 && StoreNode->isVolatile()) {
4596     assert(StoreNode->getValue()->getValueType(0) == MVT::i128);
4597     SDValue Lo =
4598         DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i64, StoreNode->getValue(),
4599                     DAG.getConstant(0, Dl, MVT::i64));
4600     SDValue Hi =
4601         DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i64, StoreNode->getValue(),
4602                     DAG.getConstant(1, Dl, MVT::i64));
4603     SDValue Result = DAG.getMemIntrinsicNode(
4604         AArch64ISD::STP, Dl, DAG.getVTList(MVT::Other),
4605         {StoreNode->getChain(), Lo, Hi, StoreNode->getBasePtr()},
4606         StoreNode->getMemoryVT(), StoreNode->getMemOperand());
4607     return Result;
4608   }
4609 
4610   return SDValue();
4611 }
4612 
4613 // Custom lowering for extending v4i8 vector loads.
4614 SDValue AArch64TargetLowering::LowerLOAD(SDValue Op,
4615                                          SelectionDAG &DAG) const {
4616   SDLoc DL(Op);
4617   LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
4618   assert(LoadNode && "Expected custom lowering of a load node");
4619   EVT VT = Op->getValueType(0);
4620   assert((VT == MVT::v4i16 || VT == MVT::v4i32) && "Expected v4i16 or v4i32");
4621 
4622   if (LoadNode->getMemoryVT() != MVT::v4i8)
4623     return SDValue();
4624 
4625   unsigned ExtType;
4626   if (LoadNode->getExtensionType() == ISD::SEXTLOAD)
4627     ExtType = ISD::SIGN_EXTEND;
4628   else if (LoadNode->getExtensionType() == ISD::ZEXTLOAD ||
4629            LoadNode->getExtensionType() == ISD::EXTLOAD)
4630     ExtType = ISD::ZERO_EXTEND;
4631   else
4632     return SDValue();
4633 
4634   SDValue Load = DAG.getLoad(MVT::f32, DL, LoadNode->getChain(),
4635                              LoadNode->getBasePtr(), MachinePointerInfo());
4636   SDValue Chain = Load.getValue(1);
4637   SDValue Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f32, Load);
4638   SDValue BC = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Vec);
4639   SDValue Ext = DAG.getNode(ExtType, DL, MVT::v8i16, BC);
4640   Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Ext,
4641                     DAG.getConstant(0, DL, MVT::i64));
4642   if (VT == MVT::v4i32)
4643     Ext = DAG.getNode(ExtType, DL, MVT::v4i32, Ext);
4644   return DAG.getMergeValues({Ext, Chain}, DL);
4645 }
4646 
4647 // Generate SUBS and CSEL for integer abs.
4648 SDValue AArch64TargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
4649   MVT VT = Op.getSimpleValueType();
4650 
4651   if (VT.isVector())
4652     return LowerToPredicatedOp(Op, DAG, AArch64ISD::ABS_MERGE_PASSTHRU);
4653 
4654   SDLoc DL(Op);
4655   SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
4656                             Op.getOperand(0));
4657   // Generate SUBS & CSEL.
4658   SDValue Cmp =
4659       DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
4660                   Op.getOperand(0), DAG.getConstant(0, DL, VT));
4661   return DAG.getNode(AArch64ISD::CSEL, DL, VT, Op.getOperand(0), Neg,
4662                      DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
4663                      Cmp.getValue(1));
4664 }
4665 
4666 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
4667                                               SelectionDAG &DAG) const {
4668   LLVM_DEBUG(dbgs() << "Custom lowering: ");
4669   LLVM_DEBUG(Op.dump());
4670 
4671   switch (Op.getOpcode()) {
4672   default:
4673     llvm_unreachable("unimplemented operand");
4674     return SDValue();
4675   case ISD::BITCAST:
4676     return LowerBITCAST(Op, DAG);
4677   case ISD::GlobalAddress:
4678     return LowerGlobalAddress(Op, DAG);
4679   case ISD::GlobalTLSAddress:
4680     return LowerGlobalTLSAddress(Op, DAG);
4681   case ISD::SETCC:
4682   case ISD::STRICT_FSETCC:
4683   case ISD::STRICT_FSETCCS:
4684     return LowerSETCC(Op, DAG);
4685   case ISD::BR_CC:
4686     return LowerBR_CC(Op, DAG);
4687   case ISD::SELECT:
4688     return LowerSELECT(Op, DAG);
4689   case ISD::SELECT_CC:
4690     return LowerSELECT_CC(Op, DAG);
4691   case ISD::JumpTable:
4692     return LowerJumpTable(Op, DAG);
4693   case ISD::BR_JT:
4694     return LowerBR_JT(Op, DAG);
4695   case ISD::ConstantPool:
4696     return LowerConstantPool(Op, DAG);
4697   case ISD::BlockAddress:
4698     return LowerBlockAddress(Op, DAG);
4699   case ISD::VASTART:
4700     return LowerVASTART(Op, DAG);
4701   case ISD::VACOPY:
4702     return LowerVACOPY(Op, DAG);
4703   case ISD::VAARG:
4704     return LowerVAARG(Op, DAG);
4705   case ISD::ADDC:
4706   case ISD::ADDE:
4707   case ISD::SUBC:
4708   case ISD::SUBE:
4709     return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
4710   case ISD::SADDO:
4711   case ISD::UADDO:
4712   case ISD::SSUBO:
4713   case ISD::USUBO:
4714   case ISD::SMULO:
4715   case ISD::UMULO:
4716     return LowerXALUO(Op, DAG);
4717   case ISD::FADD:
4718     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FADD_PRED);
4719   case ISD::FSUB:
4720     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FSUB_PRED);
4721   case ISD::FMUL:
4722     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMUL_PRED);
4723   case ISD::FMA:
4724     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED);
4725   case ISD::FDIV:
4726     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FDIV_PRED);
4727   case ISD::FNEG:
4728     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FNEG_MERGE_PASSTHRU);
4729   case ISD::FCEIL:
4730     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FCEIL_MERGE_PASSTHRU);
4731   case ISD::FFLOOR:
4732     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FFLOOR_MERGE_PASSTHRU);
4733   case ISD::FNEARBYINT:
4734     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FNEARBYINT_MERGE_PASSTHRU);
4735   case ISD::FRINT:
4736     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FRINT_MERGE_PASSTHRU);
4737   case ISD::FROUND:
4738     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FROUND_MERGE_PASSTHRU);
4739   case ISD::FROUNDEVEN:
4740     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU);
4741   case ISD::FTRUNC:
4742     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FTRUNC_MERGE_PASSTHRU);
4743   case ISD::FSQRT:
4744     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FSQRT_MERGE_PASSTHRU);
4745   case ISD::FABS:
4746     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FABS_MERGE_PASSTHRU);
4747   case ISD::FP_ROUND:
4748   case ISD::STRICT_FP_ROUND:
4749     return LowerFP_ROUND(Op, DAG);
4750   case ISD::FP_EXTEND:
4751     return LowerFP_EXTEND(Op, DAG);
4752   case ISD::FRAMEADDR:
4753     return LowerFRAMEADDR(Op, DAG);
4754   case ISD::SPONENTRY:
4755     return LowerSPONENTRY(Op, DAG);
4756   case ISD::RETURNADDR:
4757     return LowerRETURNADDR(Op, DAG);
4758   case ISD::ADDROFRETURNADDR:
4759     return LowerADDROFRETURNADDR(Op, DAG);
4760   case ISD::CONCAT_VECTORS:
4761     return LowerCONCAT_VECTORS(Op, DAG);
4762   case ISD::INSERT_VECTOR_ELT:
4763     return LowerINSERT_VECTOR_ELT(Op, DAG);
4764   case ISD::EXTRACT_VECTOR_ELT:
4765     return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4766   case ISD::BUILD_VECTOR:
4767     return LowerBUILD_VECTOR(Op, DAG);
4768   case ISD::VECTOR_SHUFFLE:
4769     return LowerVECTOR_SHUFFLE(Op, DAG);
4770   case ISD::SPLAT_VECTOR:
4771     return LowerSPLAT_VECTOR(Op, DAG);
4772   case ISD::EXTRACT_SUBVECTOR:
4773     return LowerEXTRACT_SUBVECTOR(Op, DAG);
4774   case ISD::INSERT_SUBVECTOR:
4775     return LowerINSERT_SUBVECTOR(Op, DAG);
4776   case ISD::SDIV:
4777   case ISD::UDIV:
4778     return LowerDIV(Op, DAG);
4779   case ISD::SMIN:
4780     return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED,
4781                                /*OverrideNEON=*/true);
4782   case ISD::UMIN:
4783     return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED,
4784                                /*OverrideNEON=*/true);
4785   case ISD::SMAX:
4786     return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED,
4787                                /*OverrideNEON=*/true);
4788   case ISD::UMAX:
4789     return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED,
4790                                /*OverrideNEON=*/true);
4791   case ISD::SRA:
4792   case ISD::SRL:
4793   case ISD::SHL:
4794     return LowerVectorSRA_SRL_SHL(Op, DAG);
4795   case ISD::SHL_PARTS:
4796   case ISD::SRL_PARTS:
4797   case ISD::SRA_PARTS:
4798     return LowerShiftParts(Op, DAG);
4799   case ISD::CTPOP:
4800     return LowerCTPOP(Op, DAG);
4801   case ISD::FCOPYSIGN:
4802     return LowerFCOPYSIGN(Op, DAG);
4803   case ISD::OR:
4804     return LowerVectorOR(Op, DAG);
4805   case ISD::XOR:
4806     return LowerXOR(Op, DAG);
4807   case ISD::PREFETCH:
4808     return LowerPREFETCH(Op, DAG);
4809   case ISD::SINT_TO_FP:
4810   case ISD::UINT_TO_FP:
4811   case ISD::STRICT_SINT_TO_FP:
4812   case ISD::STRICT_UINT_TO_FP:
4813     return LowerINT_TO_FP(Op, DAG);
4814   case ISD::FP_TO_SINT:
4815   case ISD::FP_TO_UINT:
4816   case ISD::STRICT_FP_TO_SINT:
4817   case ISD::STRICT_FP_TO_UINT:
4818     return LowerFP_TO_INT(Op, DAG);
4819   case ISD::FP_TO_SINT_SAT:
4820   case ISD::FP_TO_UINT_SAT:
4821     return LowerFP_TO_INT_SAT(Op, DAG);
4822   case ISD::FSINCOS:
4823     return LowerFSINCOS(Op, DAG);
4824   case ISD::FLT_ROUNDS_:
4825     return LowerFLT_ROUNDS_(Op, DAG);
4826   case ISD::SET_ROUNDING:
4827     return LowerSET_ROUNDING(Op, DAG);
4828   case ISD::MUL:
4829     return LowerMUL(Op, DAG);
4830   case ISD::MULHS:
4831     return LowerToPredicatedOp(Op, DAG, AArch64ISD::MULHS_PRED,
4832                                /*OverrideNEON=*/true);
4833   case ISD::MULHU:
4834     return LowerToPredicatedOp(Op, DAG, AArch64ISD::MULHU_PRED,
4835                                /*OverrideNEON=*/true);
4836   case ISD::INTRINSIC_WO_CHAIN:
4837     return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4838   case ISD::STORE:
4839     return LowerSTORE(Op, DAG);
4840   case ISD::MSTORE:
4841     return LowerFixedLengthVectorMStoreToSVE(Op, DAG);
4842   case ISD::MGATHER:
4843     return LowerMGATHER(Op, DAG);
4844   case ISD::MSCATTER:
4845     return LowerMSCATTER(Op, DAG);
4846   case ISD::VECREDUCE_SEQ_FADD:
4847     return LowerVECREDUCE_SEQ_FADD(Op, DAG);
4848   case ISD::VECREDUCE_ADD:
4849   case ISD::VECREDUCE_AND:
4850   case ISD::VECREDUCE_OR:
4851   case ISD::VECREDUCE_XOR:
4852   case ISD::VECREDUCE_SMAX:
4853   case ISD::VECREDUCE_SMIN:
4854   case ISD::VECREDUCE_UMAX:
4855   case ISD::VECREDUCE_UMIN:
4856   case ISD::VECREDUCE_FADD:
4857   case ISD::VECREDUCE_FMAX:
4858   case ISD::VECREDUCE_FMIN:
4859     return LowerVECREDUCE(Op, DAG);
4860   case ISD::ATOMIC_LOAD_SUB:
4861     return LowerATOMIC_LOAD_SUB(Op, DAG);
4862   case ISD::ATOMIC_LOAD_AND:
4863     return LowerATOMIC_LOAD_AND(Op, DAG);
4864   case ISD::DYNAMIC_STACKALLOC:
4865     return LowerDYNAMIC_STACKALLOC(Op, DAG);
4866   case ISD::VSCALE:
4867     return LowerVSCALE(Op, DAG);
4868   case ISD::ANY_EXTEND:
4869   case ISD::SIGN_EXTEND:
4870   case ISD::ZERO_EXTEND:
4871     return LowerFixedLengthVectorIntExtendToSVE(Op, DAG);
4872   case ISD::SIGN_EXTEND_INREG: {
4873     // Only custom lower when ExtraVT has a legal byte based element type.
4874     EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
4875     EVT ExtraEltVT = ExtraVT.getVectorElementType();
4876     if ((ExtraEltVT != MVT::i8) && (ExtraEltVT != MVT::i16) &&
4877         (ExtraEltVT != MVT::i32) && (ExtraEltVT != MVT::i64))
4878       return SDValue();
4879 
4880     return LowerToPredicatedOp(Op, DAG,
4881                                AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU);
4882   }
4883   case ISD::TRUNCATE:
4884     return LowerTRUNCATE(Op, DAG);
4885   case ISD::MLOAD:
4886     return LowerMLOAD(Op, DAG);
4887   case ISD::LOAD:
4888     if (useSVEForFixedLengthVectorVT(Op.getValueType()))
4889       return LowerFixedLengthVectorLoadToSVE(Op, DAG);
4890     return LowerLOAD(Op, DAG);
4891   case ISD::ADD:
4892     return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED);
4893   case ISD::AND:
4894     return LowerToScalableOp(Op, DAG);
4895   case ISD::SUB:
4896     return LowerToPredicatedOp(Op, DAG, AArch64ISD::SUB_PRED);
4897   case ISD::FMAXIMUM:
4898     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMAX_PRED);
4899   case ISD::FMAXNUM:
4900     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMAXNM_PRED);
4901   case ISD::FMINIMUM:
4902     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMIN_PRED);
4903   case ISD::FMINNUM:
4904     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMINNM_PRED);
4905   case ISD::VSELECT:
4906     return LowerFixedLengthVectorSelectToSVE(Op, DAG);
4907   case ISD::ABS:
4908     return LowerABS(Op, DAG);
4909   case ISD::BITREVERSE:
4910     return LowerBitreverse(Op, DAG);
4911   case ISD::BSWAP:
4912     return LowerToPredicatedOp(Op, DAG, AArch64ISD::BSWAP_MERGE_PASSTHRU);
4913   case ISD::CTLZ:
4914     return LowerToPredicatedOp(Op, DAG, AArch64ISD::CTLZ_MERGE_PASSTHRU,
4915                                /*OverrideNEON=*/true);
4916   case ISD::CTTZ:
4917     return LowerCTTZ(Op, DAG);
4918   case ISD::VECTOR_SPLICE:
4919     return LowerVECTOR_SPLICE(Op, DAG);
4920   }
4921 }
4922 
4923 bool AArch64TargetLowering::mergeStoresAfterLegalization(EVT VT) const {
4924   return !Subtarget->useSVEForFixedLengthVectors();
4925 }
4926 
4927 bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(
4928     EVT VT, bool OverrideNEON) const {
4929   if (!Subtarget->useSVEForFixedLengthVectors())
4930     return false;
4931 
4932   if (!VT.isFixedLengthVector())
4933     return false;
4934 
4935   // Don't use SVE for vectors we cannot scalarize if required.
4936   switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
4937   // Fixed length predicates should be promoted to i8.
4938   // NOTE: This is consistent with how NEON (and thus 64/128bit vectors) work.
4939   case MVT::i1:
4940   default:
4941     return false;
4942   case MVT::i8:
4943   case MVT::i16:
4944   case MVT::i32:
4945   case MVT::i64:
4946   case MVT::f16:
4947   case MVT::f32:
4948   case MVT::f64:
4949     break;
4950   }
4951 
4952   // All SVE implementations support NEON sized vectors.
4953   if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector()))
4954     return true;
4955 
4956   // Ensure NEON MVTs only belong to a single register class.
4957   if (VT.getFixedSizeInBits() <= 128)
4958     return false;
4959 
4960   // Don't use SVE for types that don't fit.
4961   if (VT.getFixedSizeInBits() > Subtarget->getMinSVEVectorSizeInBits())
4962     return false;
4963 
4964   // TODO: Perhaps an artificial restriction, but worth having whilst getting
4965   // the base fixed length SVE support in place.
4966   if (!VT.isPow2VectorType())
4967     return false;
4968 
4969   return true;
4970 }
4971 
4972 //===----------------------------------------------------------------------===//
4973 //                      Calling Convention Implementation
4974 //===----------------------------------------------------------------------===//
4975 
4976 /// Selects the correct CCAssignFn for a given CallingConvention value.
4977 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
4978                                                      bool IsVarArg) const {
4979   switch (CC) {
4980   default:
4981     report_fatal_error("Unsupported calling convention.");
4982   case CallingConv::WebKit_JS:
4983     return CC_AArch64_WebKit_JS;
4984   case CallingConv::GHC:
4985     return CC_AArch64_GHC;
4986   case CallingConv::C:
4987   case CallingConv::Fast:
4988   case CallingConv::PreserveMost:
4989   case CallingConv::CXX_FAST_TLS:
4990   case CallingConv::Swift:
4991   case CallingConv::SwiftTail:
4992   case CallingConv::Tail:
4993     if (Subtarget->isTargetWindows() && IsVarArg)
4994       return CC_AArch64_Win64_VarArg;
4995     if (!Subtarget->isTargetDarwin())
4996       return CC_AArch64_AAPCS;
4997     if (!IsVarArg)
4998       return CC_AArch64_DarwinPCS;
4999     return Subtarget->isTargetILP32() ? CC_AArch64_DarwinPCS_ILP32_VarArg
5000                                       : CC_AArch64_DarwinPCS_VarArg;
5001    case CallingConv::Win64:
5002     return IsVarArg ? CC_AArch64_Win64_VarArg : CC_AArch64_AAPCS;
5003    case CallingConv::CFGuard_Check:
5004      return CC_AArch64_Win64_CFGuard_Check;
5005    case CallingConv::AArch64_VectorCall:
5006    case CallingConv::AArch64_SVE_VectorCall:
5007      return CC_AArch64_AAPCS;
5008   }
5009 }
5010 
5011 CCAssignFn *
5012 AArch64TargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
5013   return CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
5014                                       : RetCC_AArch64_AAPCS;
5015 }
5016 
5017 SDValue AArch64TargetLowering::LowerFormalArguments(
5018     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
5019     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
5020     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5021   MachineFunction &MF = DAG.getMachineFunction();
5022   MachineFrameInfo &MFI = MF.getFrameInfo();
5023   bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv());
5024 
5025   // Assign locations to all of the incoming arguments.
5026   SmallVector<CCValAssign, 16> ArgLocs;
5027   DenseMap<unsigned, SDValue> CopiedRegs;
5028   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
5029                  *DAG.getContext());
5030 
5031   // At this point, Ins[].VT may already be promoted to i32. To correctly
5032   // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
5033   // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
5034   // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
5035   // we use a special version of AnalyzeFormalArguments to pass in ValVT and
5036   // LocVT.
5037   unsigned NumArgs = Ins.size();
5038   Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
5039   unsigned CurArgIdx = 0;
5040   for (unsigned i = 0; i != NumArgs; ++i) {
5041     MVT ValVT = Ins[i].VT;
5042     if (Ins[i].isOrigArg()) {
5043       std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
5044       CurArgIdx = Ins[i].getOrigArgIndex();
5045 
5046       // Get type of the original argument.
5047       EVT ActualVT = getValueType(DAG.getDataLayout(), CurOrigArg->getType(),
5048                                   /*AllowUnknown*/ true);
5049       MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
5050       // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
5051       if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
5052         ValVT = MVT::i8;
5053       else if (ActualMVT == MVT::i16)
5054         ValVT = MVT::i16;
5055     }
5056     bool UseVarArgCC = false;
5057     if (IsWin64)
5058       UseVarArgCC = isVarArg;
5059     CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, UseVarArgCC);
5060     bool Res =
5061         AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
5062     assert(!Res && "Call operand has unhandled type");
5063     (void)Res;
5064   }
5065   SmallVector<SDValue, 16> ArgValues;
5066   unsigned ExtraArgLocs = 0;
5067   for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5068     CCValAssign &VA = ArgLocs[i - ExtraArgLocs];
5069 
5070     if (Ins[i].Flags.isByVal()) {
5071       // Byval is used for HFAs in the PCS, but the system should work in a
5072       // non-compliant manner for larger structs.
5073       EVT PtrVT = getPointerTy(DAG.getDataLayout());
5074       int Size = Ins[i].Flags.getByValSize();
5075       unsigned NumRegs = (Size + 7) / 8;
5076 
5077       // FIXME: This works on big-endian for composite byvals, which are the common
5078       // case. It should also work for fundamental types too.
5079       unsigned FrameIdx =
5080         MFI.CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
5081       SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrVT);
5082       InVals.push_back(FrameIdxN);
5083 
5084       continue;
5085     }
5086 
5087     if (Ins[i].Flags.isSwiftAsync())
5088       MF.getInfo<AArch64FunctionInfo>()->setHasSwiftAsyncContext(true);
5089 
5090     SDValue ArgValue;
5091     if (VA.isRegLoc()) {
5092       // Arguments stored in registers.
5093       EVT RegVT = VA.getLocVT();
5094       const TargetRegisterClass *RC;
5095 
5096       if (RegVT == MVT::i32)
5097         RC = &AArch64::GPR32RegClass;
5098       else if (RegVT == MVT::i64)
5099         RC = &AArch64::GPR64RegClass;
5100       else if (RegVT == MVT::f16 || RegVT == MVT::bf16)
5101         RC = &AArch64::FPR16RegClass;
5102       else if (RegVT == MVT::f32)
5103         RC = &AArch64::FPR32RegClass;
5104       else if (RegVT == MVT::f64 || RegVT.is64BitVector())
5105         RC = &AArch64::FPR64RegClass;
5106       else if (RegVT == MVT::f128 || RegVT.is128BitVector())
5107         RC = &AArch64::FPR128RegClass;
5108       else if (RegVT.isScalableVector() &&
5109                RegVT.getVectorElementType() == MVT::i1)
5110         RC = &AArch64::PPRRegClass;
5111       else if (RegVT.isScalableVector())
5112         RC = &AArch64::ZPRRegClass;
5113       else
5114         llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
5115 
5116       // Transform the arguments in physical registers into virtual ones.
5117       unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
5118       ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
5119 
5120       // If this is an 8, 16 or 32-bit value, it is really passed promoted
5121       // to 64 bits.  Insert an assert[sz]ext to capture this, then
5122       // truncate to the right size.
5123       switch (VA.getLocInfo()) {
5124       default:
5125         llvm_unreachable("Unknown loc info!");
5126       case CCValAssign::Full:
5127         break;
5128       case CCValAssign::Indirect:
5129         assert(VA.getValVT().isScalableVector() &&
5130                "Only scalable vectors can be passed indirectly");
5131         break;
5132       case CCValAssign::BCvt:
5133         ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
5134         break;
5135       case CCValAssign::AExt:
5136       case CCValAssign::SExt:
5137       case CCValAssign::ZExt:
5138         break;
5139       case CCValAssign::AExtUpper:
5140         ArgValue = DAG.getNode(ISD::SRL, DL, RegVT, ArgValue,
5141                                DAG.getConstant(32, DL, RegVT));
5142         ArgValue = DAG.getZExtOrTrunc(ArgValue, DL, VA.getValVT());
5143         break;
5144       }
5145     } else { // VA.isRegLoc()
5146       assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
5147       unsigned ArgOffset = VA.getLocMemOffset();
5148       unsigned ArgSize = (VA.getLocInfo() == CCValAssign::Indirect
5149                               ? VA.getLocVT().getSizeInBits()
5150                               : VA.getValVT().getSizeInBits()) / 8;
5151 
5152       uint32_t BEAlign = 0;
5153       if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
5154           !Ins[i].Flags.isInConsecutiveRegs())
5155         BEAlign = 8 - ArgSize;
5156 
5157       int FI = MFI.CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
5158 
5159       // Create load nodes to retrieve arguments from the stack.
5160       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
5161 
5162       // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
5163       ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5164       MVT MemVT = VA.getValVT();
5165 
5166       switch (VA.getLocInfo()) {
5167       default:
5168         break;
5169       case CCValAssign::Trunc:
5170       case CCValAssign::BCvt:
5171         MemVT = VA.getLocVT();
5172         break;
5173       case CCValAssign::Indirect:
5174         assert(VA.getValVT().isScalableVector() &&
5175                "Only scalable vectors can be passed indirectly");
5176         MemVT = VA.getLocVT();
5177         break;
5178       case CCValAssign::SExt:
5179         ExtType = ISD::SEXTLOAD;
5180         break;
5181       case CCValAssign::ZExt:
5182         ExtType = ISD::ZEXTLOAD;
5183         break;
5184       case CCValAssign::AExt:
5185         ExtType = ISD::EXTLOAD;
5186         break;
5187       }
5188 
5189       ArgValue = DAG.getExtLoad(
5190           ExtType, DL, VA.getLocVT(), Chain, FIN,
5191           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
5192           MemVT);
5193     }
5194 
5195     if (VA.getLocInfo() == CCValAssign::Indirect) {
5196       assert(VA.getValVT().isScalableVector() &&
5197            "Only scalable vectors can be passed indirectly");
5198 
5199       uint64_t PartSize = VA.getValVT().getStoreSize().getKnownMinSize();
5200       unsigned NumParts = 1;
5201       if (Ins[i].Flags.isInConsecutiveRegs()) {
5202         assert(!Ins[i].Flags.isInConsecutiveRegsLast());
5203         while (!Ins[i + NumParts - 1].Flags.isInConsecutiveRegsLast())
5204           ++NumParts;
5205       }
5206 
5207       MVT PartLoad = VA.getValVT();
5208       SDValue Ptr = ArgValue;
5209 
5210       // Ensure we generate all loads for each tuple part, whilst updating the
5211       // pointer after each load correctly using vscale.
5212       while (NumParts > 0) {
5213         ArgValue = DAG.getLoad(PartLoad, DL, Chain, Ptr, MachinePointerInfo());
5214         InVals.push_back(ArgValue);
5215         NumParts--;
5216         if (NumParts > 0) {
5217           SDValue BytesIncrement = DAG.getVScale(
5218               DL, Ptr.getValueType(),
5219               APInt(Ptr.getValueSizeInBits().getFixedSize(), PartSize));
5220           SDNodeFlags Flags;
5221           Flags.setNoUnsignedWrap(true);
5222           Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5223                             BytesIncrement, Flags);
5224           ExtraArgLocs++;
5225           i++;
5226         }
5227       }
5228     } else {
5229       if (Subtarget->isTargetILP32() && Ins[i].Flags.isPointer())
5230         ArgValue = DAG.getNode(ISD::AssertZext, DL, ArgValue.getValueType(),
5231                                ArgValue, DAG.getValueType(MVT::i32));
5232       InVals.push_back(ArgValue);
5233     }
5234   }
5235   assert((ArgLocs.size() + ExtraArgLocs) == Ins.size());
5236 
5237   // varargs
5238   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
5239   if (isVarArg) {
5240     if (!Subtarget->isTargetDarwin() || IsWin64) {
5241       // The AAPCS variadic function ABI is identical to the non-variadic
5242       // one. As a result there may be more arguments in registers and we should
5243       // save them for future reference.
5244       // Win64 variadic functions also pass arguments in registers, but all float
5245       // arguments are passed in integer registers.
5246       saveVarArgRegisters(CCInfo, DAG, DL, Chain);
5247     }
5248 
5249     // This will point to the next argument passed via stack.
5250     unsigned StackOffset = CCInfo.getNextStackOffset();
5251     // We currently pass all varargs at 8-byte alignment, or 4 for ILP32
5252     StackOffset = alignTo(StackOffset, Subtarget->isTargetILP32() ? 4 : 8);
5253     FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
5254 
5255     if (MFI.hasMustTailInVarArgFunc()) {
5256       SmallVector<MVT, 2> RegParmTypes;
5257       RegParmTypes.push_back(MVT::i64);
5258       RegParmTypes.push_back(MVT::f128);
5259       // Compute the set of forwarded registers. The rest are scratch.
5260       SmallVectorImpl<ForwardedRegister> &Forwards =
5261                                        FuncInfo->getForwardedMustTailRegParms();
5262       CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes,
5263                                                CC_AArch64_AAPCS);
5264 
5265       // Conservatively forward X8, since it might be used for aggregate return.
5266       if (!CCInfo.isAllocated(AArch64::X8)) {
5267         unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
5268         Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
5269       }
5270     }
5271   }
5272 
5273   // On Windows, InReg pointers must be returned, so record the pointer in a
5274   // virtual register at the start of the function so it can be returned in the
5275   // epilogue.
5276   if (IsWin64) {
5277     for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
5278       if (Ins[I].Flags.isInReg()) {
5279         assert(!FuncInfo->getSRetReturnReg());
5280 
5281         MVT PtrTy = getPointerTy(DAG.getDataLayout());
5282         Register Reg =
5283             MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
5284         FuncInfo->setSRetReturnReg(Reg);
5285 
5286         SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[I]);
5287         Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
5288         break;
5289       }
5290     }
5291   }
5292 
5293   unsigned StackArgSize = CCInfo.getNextStackOffset();
5294   bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
5295   if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
5296     // This is a non-standard ABI so by fiat I say we're allowed to make full
5297     // use of the stack area to be popped, which must be aligned to 16 bytes in
5298     // any case:
5299     StackArgSize = alignTo(StackArgSize, 16);
5300 
5301     // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
5302     // a multiple of 16.
5303     FuncInfo->setArgumentStackToRestore(StackArgSize);
5304 
5305     // This realignment carries over to the available bytes below. Our own
5306     // callers will guarantee the space is free by giving an aligned value to
5307     // CALLSEQ_START.
5308   }
5309   // Even if we're not expected to free up the space, it's useful to know how
5310   // much is there while considering tail calls (because we can reuse it).
5311   FuncInfo->setBytesInStackArgArea(StackArgSize);
5312 
5313   if (Subtarget->hasCustomCallingConv())
5314     Subtarget->getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
5315 
5316   return Chain;
5317 }
5318 
5319 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
5320                                                 SelectionDAG &DAG,
5321                                                 const SDLoc &DL,
5322                                                 SDValue &Chain) const {
5323   MachineFunction &MF = DAG.getMachineFunction();
5324   MachineFrameInfo &MFI = MF.getFrameInfo();
5325   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
5326   auto PtrVT = getPointerTy(DAG.getDataLayout());
5327   bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv());
5328 
5329   SmallVector<SDValue, 8> MemOps;
5330 
5331   static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
5332                                           AArch64::X3, AArch64::X4, AArch64::X5,
5333                                           AArch64::X6, AArch64::X7 };
5334   static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
5335   unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
5336 
5337   unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
5338   int GPRIdx = 0;
5339   if (GPRSaveSize != 0) {
5340     if (IsWin64) {
5341       GPRIdx = MFI.CreateFixedObject(GPRSaveSize, -(int)GPRSaveSize, false);
5342       if (GPRSaveSize & 15)
5343         // The extra size here, if triggered, will always be 8.
5344         MFI.CreateFixedObject(16 - (GPRSaveSize & 15), -(int)alignTo(GPRSaveSize, 16), false);
5345     } else
5346       GPRIdx = MFI.CreateStackObject(GPRSaveSize, Align(8), false);
5347 
5348     SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
5349 
5350     for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
5351       unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
5352       SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
5353       SDValue Store = DAG.getStore(
5354           Val.getValue(1), DL, Val, FIN,
5355           IsWin64
5356               ? MachinePointerInfo::getFixedStack(DAG.getMachineFunction(),
5357                                                   GPRIdx,
5358                                                   (i - FirstVariadicGPR) * 8)
5359               : MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 8));
5360       MemOps.push_back(Store);
5361       FIN =
5362           DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
5363     }
5364   }
5365   FuncInfo->setVarArgsGPRIndex(GPRIdx);
5366   FuncInfo->setVarArgsGPRSize(GPRSaveSize);
5367 
5368   if (Subtarget->hasFPARMv8() && !IsWin64) {
5369     static const MCPhysReg FPRArgRegs[] = {
5370         AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
5371         AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
5372     static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
5373     unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
5374 
5375     unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
5376     int FPRIdx = 0;
5377     if (FPRSaveSize != 0) {
5378       FPRIdx = MFI.CreateStackObject(FPRSaveSize, Align(16), false);
5379 
5380       SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);
5381 
5382       for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
5383         unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
5384         SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
5385 
5386         SDValue Store = DAG.getStore(
5387             Val.getValue(1), DL, Val, FIN,
5388             MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 16));
5389         MemOps.push_back(Store);
5390         FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
5391                           DAG.getConstant(16, DL, PtrVT));
5392       }
5393     }
5394     FuncInfo->setVarArgsFPRIndex(FPRIdx);
5395     FuncInfo->setVarArgsFPRSize(FPRSaveSize);
5396   }
5397 
5398   if (!MemOps.empty()) {
5399     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
5400   }
5401 }
5402 
5403 /// LowerCallResult - Lower the result values of a call into the
5404 /// appropriate copies out of appropriate physical registers.
5405 SDValue AArch64TargetLowering::LowerCallResult(
5406     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
5407     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
5408     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
5409     SDValue ThisVal) const {
5410   CCAssignFn *RetCC = CCAssignFnForReturn(CallConv);
5411   // Assign locations to each value returned by this call.
5412   SmallVector<CCValAssign, 16> RVLocs;
5413   DenseMap<unsigned, SDValue> CopiedRegs;
5414   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5415                  *DAG.getContext());
5416   CCInfo.AnalyzeCallResult(Ins, RetCC);
5417 
5418   // Copy all of the result registers out of their specified physreg.
5419   for (unsigned i = 0; i != RVLocs.size(); ++i) {
5420     CCValAssign VA = RVLocs[i];
5421 
5422     // Pass 'this' value directly from the argument to return value, to avoid
5423     // reg unit interference
5424     if (i == 0 && isThisReturn) {
5425       assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
5426              "unexpected return calling convention register assignment");
5427       InVals.push_back(ThisVal);
5428       continue;
5429     }
5430 
5431     // Avoid copying a physreg twice since RegAllocFast is incompetent and only
5432     // allows one use of a physreg per block.
5433     SDValue Val = CopiedRegs.lookup(VA.getLocReg());
5434     if (!Val) {
5435       Val =
5436           DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
5437       Chain = Val.getValue(1);
5438       InFlag = Val.getValue(2);
5439       CopiedRegs[VA.getLocReg()] = Val;
5440     }
5441 
5442     switch (VA.getLocInfo()) {
5443     default:
5444       llvm_unreachable("Unknown loc info!");
5445     case CCValAssign::Full:
5446       break;
5447     case CCValAssign::BCvt:
5448       Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
5449       break;
5450     case CCValAssign::AExtUpper:
5451       Val = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Val,
5452                         DAG.getConstant(32, DL, VA.getLocVT()));
5453       LLVM_FALLTHROUGH;
5454     case CCValAssign::AExt:
5455       LLVM_FALLTHROUGH;
5456     case CCValAssign::ZExt:
5457       Val = DAG.getZExtOrTrunc(Val, DL, VA.getValVT());
5458       break;
5459     }
5460 
5461     InVals.push_back(Val);
5462   }
5463 
5464   return Chain;
5465 }
5466 
5467 /// Return true if the calling convention is one that we can guarantee TCO for.
5468 static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
5469   return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
5470          CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
5471 }
5472 
5473 /// Return true if we might ever do TCO for calls with this calling convention.
5474 static bool mayTailCallThisCC(CallingConv::ID CC) {
5475   switch (CC) {
5476   case CallingConv::C:
5477   case CallingConv::AArch64_SVE_VectorCall:
5478   case CallingConv::PreserveMost:
5479   case CallingConv::Swift:
5480   case CallingConv::SwiftTail:
5481   case CallingConv::Tail:
5482   case CallingConv::Fast:
5483     return true;
5484   default:
5485     return false;
5486   }
5487 }
5488 
5489 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
5490     SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
5491     const SmallVectorImpl<ISD::OutputArg> &Outs,
5492     const SmallVectorImpl<SDValue> &OutVals,
5493     const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
5494   if (!mayTailCallThisCC(CalleeCC))
5495     return false;
5496 
5497   MachineFunction &MF = DAG.getMachineFunction();
5498   const Function &CallerF = MF.getFunction();
5499   CallingConv::ID CallerCC = CallerF.getCallingConv();
5500 
5501   // Functions using the C or Fast calling convention that have an SVE signature
5502   // preserve more registers and should assume the SVE_VectorCall CC.
5503   // The check for matching callee-saved regs will determine whether it is
5504   // eligible for TCO.
5505   if ((CallerCC == CallingConv::C || CallerCC == CallingConv::Fast) &&
5506       AArch64RegisterInfo::hasSVEArgsOrReturn(&MF))
5507     CallerCC = CallingConv::AArch64_SVE_VectorCall;
5508 
5509   bool CCMatch = CallerCC == CalleeCC;
5510 
5511   // When using the Windows calling convention on a non-windows OS, we want
5512   // to back up and restore X18 in such functions; we can't do a tail call
5513   // from those functions.
5514   if (CallerCC == CallingConv::Win64 && !Subtarget->isTargetWindows() &&
5515       CalleeCC != CallingConv::Win64)
5516     return false;
5517 
5518   // Byval parameters hand the function a pointer directly into the stack area
5519   // we want to reuse during a tail call. Working around this *is* possible (see
5520   // X86) but less efficient and uglier in LowerCall.
5521   for (Function::const_arg_iterator i = CallerF.arg_begin(),
5522                                     e = CallerF.arg_end();
5523        i != e; ++i) {
5524     if (i->hasByValAttr())
5525       return false;
5526 
5527     // On Windows, "inreg" attributes signify non-aggregate indirect returns.
5528     // In this case, it is necessary to save/restore X0 in the callee. Tail
5529     // call opt interferes with this. So we disable tail call opt when the
5530     // caller has an argument with "inreg" attribute.
5531 
5532     // FIXME: Check whether the callee also has an "inreg" argument.
5533     if (i->hasInRegAttr())
5534       return false;
5535   }
5536 
5537   if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
5538     return CCMatch;
5539 
5540   // Externally-defined functions with weak linkage should not be
5541   // tail-called on AArch64 when the OS does not support dynamic
5542   // pre-emption of symbols, as the AAELF spec requires normal calls
5543   // to undefined weak functions to be replaced with a NOP or jump to the
5544   // next instruction. The behaviour of branch instructions in this
5545   // situation (as used for tail calls) is implementation-defined, so we
5546   // cannot rely on the linker replacing the tail call with a return.
5547   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
5548     const GlobalValue *GV = G->getGlobal();
5549     const Triple &TT = getTargetMachine().getTargetTriple();
5550     if (GV->hasExternalWeakLinkage() &&
5551         (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
5552       return false;
5553   }
5554 
5555   // Now we search for cases where we can use a tail call without changing the
5556   // ABI. Sibcall is used in some places (particularly gcc) to refer to this
5557   // concept.
5558 
5559   // I want anyone implementing a new calling convention to think long and hard
5560   // about this assert.
5561   assert((!isVarArg || CalleeCC == CallingConv::C) &&
5562          "Unexpected variadic calling convention");
5563 
5564   LLVMContext &C = *DAG.getContext();
5565   if (isVarArg && !Outs.empty()) {
5566     // At least two cases here: if caller is fastcc then we can't have any
5567     // memory arguments (we'd be expected to clean up the stack afterwards). If
5568     // caller is C then we could potentially use its argument area.
5569 
5570     // FIXME: for now we take the most conservative of these in both cases:
5571     // disallow all variadic memory operands.
5572     SmallVector<CCValAssign, 16> ArgLocs;
5573     CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
5574 
5575     CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
5576     for (const CCValAssign &ArgLoc : ArgLocs)
5577       if (!ArgLoc.isRegLoc())
5578         return false;
5579   }
5580 
5581   // Check that the call results are passed in the same way.
5582   if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
5583                                   CCAssignFnForCall(CalleeCC, isVarArg),
5584                                   CCAssignFnForCall(CallerCC, isVarArg)))
5585     return false;
5586   // The callee has to preserve all registers the caller needs to preserve.
5587   const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
5588   const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
5589   if (!CCMatch) {
5590     const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
5591     if (Subtarget->hasCustomCallingConv()) {
5592       TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
5593       TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
5594     }
5595     if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
5596       return false;
5597   }
5598 
5599   // Nothing more to check if the callee is taking no arguments
5600   if (Outs.empty())
5601     return true;
5602 
5603   SmallVector<CCValAssign, 16> ArgLocs;
5604   CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
5605 
5606   CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
5607 
5608   const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
5609 
5610   // If any of the arguments is passed indirectly, it must be SVE, so the
5611   // 'getBytesInStackArgArea' is not sufficient to determine whether we need to
5612   // allocate space on the stack. That is why we determine this explicitly here
5613   // the call cannot be a tailcall.
5614   if (llvm::any_of(ArgLocs, [](CCValAssign &A) {
5615         assert((A.getLocInfo() != CCValAssign::Indirect ||
5616                 A.getValVT().isScalableVector()) &&
5617                "Expected value to be scalable");
5618         return A.getLocInfo() == CCValAssign::Indirect;
5619       }))
5620     return false;
5621 
5622   // If the stack arguments for this call do not fit into our own save area then
5623   // the call cannot be made tail.
5624   if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
5625     return false;
5626 
5627   const MachineRegisterInfo &MRI = MF.getRegInfo();
5628   if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
5629     return false;
5630 
5631   return true;
5632 }
5633 
5634 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
5635                                                    SelectionDAG &DAG,
5636                                                    MachineFrameInfo &MFI,
5637                                                    int ClobberedFI) const {
5638   SmallVector<SDValue, 8> ArgChains;
5639   int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
5640   int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
5641 
5642   // Include the original chain at the beginning of the list. When this is
5643   // used by target LowerCall hooks, this helps legalize find the
5644   // CALLSEQ_BEGIN node.
5645   ArgChains.push_back(Chain);
5646 
5647   // Add a chain value for each stack argument corresponding
5648   for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
5649                             UE = DAG.getEntryNode().getNode()->use_end();
5650        U != UE; ++U)
5651     if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
5652       if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
5653         if (FI->getIndex() < 0) {
5654           int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
5655           int64_t InLastByte = InFirstByte;
5656           InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
5657 
5658           if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
5659               (FirstByte <= InFirstByte && InFirstByte <= LastByte))
5660             ArgChains.push_back(SDValue(L, 1));
5661         }
5662 
5663   // Build a tokenfactor for all the chains.
5664   return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
5665 }
5666 
5667 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
5668                                                    bool TailCallOpt) const {
5669   return (CallCC == CallingConv::Fast && TailCallOpt) ||
5670          CallCC == CallingConv::Tail || CallCC == CallingConv::SwiftTail;
5671 }
5672 
5673 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
5674 /// and add input and output parameter nodes.
5675 SDValue
5676 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
5677                                  SmallVectorImpl<SDValue> &InVals) const {
5678   SelectionDAG &DAG = CLI.DAG;
5679   SDLoc &DL = CLI.DL;
5680   SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
5681   SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
5682   SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
5683   SDValue Chain = CLI.Chain;
5684   SDValue Callee = CLI.Callee;
5685   bool &IsTailCall = CLI.IsTailCall;
5686   CallingConv::ID CallConv = CLI.CallConv;
5687   bool IsVarArg = CLI.IsVarArg;
5688 
5689   MachineFunction &MF = DAG.getMachineFunction();
5690   MachineFunction::CallSiteInfo CSInfo;
5691   bool IsThisReturn = false;
5692 
5693   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
5694   bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
5695   bool IsSibCall = false;
5696   bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CallConv);
5697 
5698   // Check callee args/returns for SVE registers and set calling convention
5699   // accordingly.
5700   if (CallConv == CallingConv::C || CallConv == CallingConv::Fast) {
5701     bool CalleeOutSVE = any_of(Outs, [](ISD::OutputArg &Out){
5702       return Out.VT.isScalableVector();
5703     });
5704     bool CalleeInSVE = any_of(Ins, [](ISD::InputArg &In){
5705       return In.VT.isScalableVector();
5706     });
5707 
5708     if (CalleeInSVE || CalleeOutSVE)
5709       CallConv = CallingConv::AArch64_SVE_VectorCall;
5710   }
5711 
5712   if (IsTailCall) {
5713     // Check if it's really possible to do a tail call.
5714     IsTailCall = isEligibleForTailCallOptimization(
5715         Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
5716 
5717     // A sibling call is one where we're under the usual C ABI and not planning
5718     // to change that but can still do a tail call:
5719     if (!TailCallOpt && IsTailCall && CallConv != CallingConv::Tail &&
5720         CallConv != CallingConv::SwiftTail)
5721       IsSibCall = true;
5722 
5723     if (IsTailCall)
5724       ++NumTailCalls;
5725   }
5726 
5727   if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall())
5728     report_fatal_error("failed to perform tail call elimination on a call "
5729                        "site marked musttail");
5730 
5731   // Analyze operands of the call, assigning locations to each operand.
5732   SmallVector<CCValAssign, 16> ArgLocs;
5733   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
5734                  *DAG.getContext());
5735 
5736   if (IsVarArg) {
5737     // Handle fixed and variable vector arguments differently.
5738     // Variable vector arguments always go into memory.
5739     unsigned NumArgs = Outs.size();
5740 
5741     for (unsigned i = 0; i != NumArgs; ++i) {
5742       MVT ArgVT = Outs[i].VT;
5743       if (!Outs[i].IsFixed && ArgVT.isScalableVector())
5744         report_fatal_error("Passing SVE types to variadic functions is "
5745                            "currently not supported");
5746 
5747       ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5748       bool UseVarArgCC = !Outs[i].IsFixed;
5749       // On Windows, the fixed arguments in a vararg call are passed in GPRs
5750       // too, so use the vararg CC to force them to integer registers.
5751       if (IsCalleeWin64)
5752         UseVarArgCC = true;
5753       CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, UseVarArgCC);
5754       bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
5755       assert(!Res && "Call operand has unhandled type");
5756       (void)Res;
5757     }
5758   } else {
5759     // At this point, Outs[].VT may already be promoted to i32. To correctly
5760     // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
5761     // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
5762     // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
5763     // we use a special version of AnalyzeCallOperands to pass in ValVT and
5764     // LocVT.
5765     unsigned NumArgs = Outs.size();
5766     for (unsigned i = 0; i != NumArgs; ++i) {
5767       MVT ValVT = Outs[i].VT;
5768       // Get type of the original argument.
5769       EVT ActualVT = getValueType(DAG.getDataLayout(),
5770                                   CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
5771                                   /*AllowUnknown*/ true);
5772       MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
5773       ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5774       // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
5775       if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
5776         ValVT = MVT::i8;
5777       else if (ActualMVT == MVT::i16)
5778         ValVT = MVT::i16;
5779 
5780       CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
5781       bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
5782       assert(!Res && "Call operand has unhandled type");
5783       (void)Res;
5784     }
5785   }
5786 
5787   // Get a count of how many bytes are to be pushed on the stack.
5788   unsigned NumBytes = CCInfo.getNextStackOffset();
5789 
5790   if (IsSibCall) {
5791     // Since we're not changing the ABI to make this a tail call, the memory
5792     // operands are already available in the caller's incoming argument space.
5793     NumBytes = 0;
5794   }
5795 
5796   // FPDiff is the byte offset of the call's argument area from the callee's.
5797   // Stores to callee stack arguments will be placed in FixedStackSlots offset
5798   // by this amount for a tail call. In a sibling call it must be 0 because the
5799   // caller will deallocate the entire stack and the callee still expects its
5800   // arguments to begin at SP+0. Completely unused for non-tail calls.
5801   int FPDiff = 0;
5802 
5803   if (IsTailCall && !IsSibCall) {
5804     unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
5805 
5806     // Since callee will pop argument stack as a tail call, we must keep the
5807     // popped size 16-byte aligned.
5808     NumBytes = alignTo(NumBytes, 16);
5809 
5810     // FPDiff will be negative if this tail call requires more space than we
5811     // would automatically have in our incoming argument space. Positive if we
5812     // can actually shrink the stack.
5813     FPDiff = NumReusableBytes - NumBytes;
5814 
5815     // Update the required reserved area if this is the tail call requiring the
5816     // most argument stack space.
5817     if (FPDiff < 0 && FuncInfo->getTailCallReservedStack() < (unsigned)-FPDiff)
5818       FuncInfo->setTailCallReservedStack(-FPDiff);
5819 
5820     // The stack pointer must be 16-byte aligned at all times it's used for a
5821     // memory operation, which in practice means at *all* times and in
5822     // particular across call boundaries. Therefore our own arguments started at
5823     // a 16-byte aligned SP and the delta applied for the tail call should
5824     // satisfy the same constraint.
5825     assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
5826   }
5827 
5828   // Adjust the stack pointer for the new arguments...
5829   // These operations are automatically eliminated by the prolog/epilog pass
5830   if (!IsSibCall)
5831     Chain = DAG.getCALLSEQ_START(Chain, IsTailCall ? 0 : NumBytes, 0, DL);
5832 
5833   SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
5834                                         getPointerTy(DAG.getDataLayout()));
5835 
5836   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5837   SmallSet<unsigned, 8> RegsUsed;
5838   SmallVector<SDValue, 8> MemOpChains;
5839   auto PtrVT = getPointerTy(DAG.getDataLayout());
5840 
5841   if (IsVarArg && CLI.CB && CLI.CB->isMustTailCall()) {
5842     const auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
5843     for (const auto &F : Forwards) {
5844       SDValue Val = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
5845        RegsToPass.emplace_back(F.PReg, Val);
5846     }
5847   }
5848 
5849   // Walk the register/memloc assignments, inserting copies/loads.
5850   unsigned ExtraArgLocs = 0;
5851   for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
5852     CCValAssign &VA = ArgLocs[i - ExtraArgLocs];
5853     SDValue Arg = OutVals[i];
5854     ISD::ArgFlagsTy Flags = Outs[i].Flags;
5855 
5856     // Promote the value if needed.
5857     switch (VA.getLocInfo()) {
5858     default:
5859       llvm_unreachable("Unknown loc info!");
5860     case CCValAssign::Full:
5861       break;
5862     case CCValAssign::SExt:
5863       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
5864       break;
5865     case CCValAssign::ZExt:
5866       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
5867       break;
5868     case CCValAssign::AExt:
5869       if (Outs[i].ArgVT == MVT::i1) {
5870         // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
5871         Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
5872         Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
5873       }
5874       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
5875       break;
5876     case CCValAssign::AExtUpper:
5877       assert(VA.getValVT() == MVT::i32 && "only expect 32 -> 64 upper bits");
5878       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
5879       Arg = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Arg,
5880                         DAG.getConstant(32, DL, VA.getLocVT()));
5881       break;
5882     case CCValAssign::BCvt:
5883       Arg = DAG.getBitcast(VA.getLocVT(), Arg);
5884       break;
5885     case CCValAssign::Trunc:
5886       Arg = DAG.getZExtOrTrunc(Arg, DL, VA.getLocVT());
5887       break;
5888     case CCValAssign::FPExt:
5889       Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
5890       break;
5891     case CCValAssign::Indirect:
5892       assert(VA.getValVT().isScalableVector() &&
5893              "Only scalable vectors can be passed indirectly");
5894 
5895       uint64_t StoreSize = VA.getValVT().getStoreSize().getKnownMinSize();
5896       uint64_t PartSize = StoreSize;
5897       unsigned NumParts = 1;
5898       if (Outs[i].Flags.isInConsecutiveRegs()) {
5899         assert(!Outs[i].Flags.isInConsecutiveRegsLast());
5900         while (!Outs[i + NumParts - 1].Flags.isInConsecutiveRegsLast())
5901           ++NumParts;
5902         StoreSize *= NumParts;
5903       }
5904 
5905       MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
5906       Type *Ty = EVT(VA.getValVT()).getTypeForEVT(*DAG.getContext());
5907       Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
5908       int FI = MFI.CreateStackObject(StoreSize, Alignment, false);
5909       MFI.setStackID(FI, TargetStackID::ScalableVector);
5910 
5911       MachinePointerInfo MPI =
5912           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
5913       SDValue Ptr = DAG.getFrameIndex(
5914           FI, DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()));
5915       SDValue SpillSlot = Ptr;
5916 
5917       // Ensure we generate all stores for each tuple part, whilst updating the
5918       // pointer after each store correctly using vscale.
5919       while (NumParts) {
5920         Chain = DAG.getStore(Chain, DL, OutVals[i], Ptr, MPI);
5921         NumParts--;
5922         if (NumParts > 0) {
5923           SDValue BytesIncrement = DAG.getVScale(
5924               DL, Ptr.getValueType(),
5925               APInt(Ptr.getValueSizeInBits().getFixedSize(), PartSize));
5926           SDNodeFlags Flags;
5927           Flags.setNoUnsignedWrap(true);
5928 
5929           MPI = MachinePointerInfo(MPI.getAddrSpace());
5930           Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5931                             BytesIncrement, Flags);
5932           ExtraArgLocs++;
5933           i++;
5934         }
5935       }
5936 
5937       Arg = SpillSlot;
5938       break;
5939     }
5940 
5941     if (VA.isRegLoc()) {
5942       if (i == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
5943           Outs[0].VT == MVT::i64) {
5944         assert(VA.getLocVT() == MVT::i64 &&
5945                "unexpected calling convention register assignment");
5946         assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
5947                "unexpected use of 'returned'");
5948         IsThisReturn = true;
5949       }
5950       if (RegsUsed.count(VA.getLocReg())) {
5951         // If this register has already been used then we're trying to pack
5952         // parts of an [N x i32] into an X-register. The extension type will
5953         // take care of putting the two halves in the right place but we have to
5954         // combine them.
5955         SDValue &Bits =
5956             llvm::find_if(RegsToPass,
5957                           [=](const std::pair<unsigned, SDValue> &Elt) {
5958                             return Elt.first == VA.getLocReg();
5959                           })
5960                 ->second;
5961         Bits = DAG.getNode(ISD::OR, DL, Bits.getValueType(), Bits, Arg);
5962         // Call site info is used for function's parameter entry value
5963         // tracking. For now we track only simple cases when parameter
5964         // is transferred through whole register.
5965         llvm::erase_if(CSInfo, [&VA](MachineFunction::ArgRegPair ArgReg) {
5966           return ArgReg.Reg == VA.getLocReg();
5967         });
5968       } else {
5969         RegsToPass.emplace_back(VA.getLocReg(), Arg);
5970         RegsUsed.insert(VA.getLocReg());
5971         const TargetOptions &Options = DAG.getTarget().Options;
5972         if (Options.EmitCallSiteInfo)
5973           CSInfo.emplace_back(VA.getLocReg(), i);
5974       }
5975     } else {
5976       assert(VA.isMemLoc());
5977 
5978       SDValue DstAddr;
5979       MachinePointerInfo DstInfo;
5980 
5981       // FIXME: This works on big-endian for composite byvals, which are the
5982       // common case. It should also work for fundamental types too.
5983       uint32_t BEAlign = 0;
5984       unsigned OpSize;
5985       if (VA.getLocInfo() == CCValAssign::Indirect ||
5986           VA.getLocInfo() == CCValAssign::Trunc)
5987         OpSize = VA.getLocVT().getFixedSizeInBits();
5988       else
5989         OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
5990                                  : VA.getValVT().getSizeInBits();
5991       OpSize = (OpSize + 7) / 8;
5992       if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
5993           !Flags.isInConsecutiveRegs()) {
5994         if (OpSize < 8)
5995           BEAlign = 8 - OpSize;
5996       }
5997       unsigned LocMemOffset = VA.getLocMemOffset();
5998       int32_t Offset = LocMemOffset + BEAlign;
5999       SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
6000       PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
6001 
6002       if (IsTailCall) {
6003         Offset = Offset + FPDiff;
6004         int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
6005 
6006         DstAddr = DAG.getFrameIndex(FI, PtrVT);
6007         DstInfo =
6008             MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6009 
6010         // Make sure any stack arguments overlapping with where we're storing
6011         // are loaded before this eventual operation. Otherwise they'll be
6012         // clobbered.
6013         Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
6014       } else {
6015         SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
6016 
6017         DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
6018         DstInfo = MachinePointerInfo::getStack(DAG.getMachineFunction(),
6019                                                LocMemOffset);
6020       }
6021 
6022       if (Outs[i].Flags.isByVal()) {
6023         SDValue SizeNode =
6024             DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
6025         SDValue Cpy = DAG.getMemcpy(
6026             Chain, DL, DstAddr, Arg, SizeNode,
6027             Outs[i].Flags.getNonZeroByValAlign(),
6028             /*isVol = */ false, /*AlwaysInline = */ false,
6029             /*isTailCall = */ false, DstInfo, MachinePointerInfo());
6030 
6031         MemOpChains.push_back(Cpy);
6032       } else {
6033         // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
6034         // promoted to a legal register type i32, we should truncate Arg back to
6035         // i1/i8/i16.
6036         if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
6037             VA.getValVT() == MVT::i16)
6038           Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
6039 
6040         SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo);
6041         MemOpChains.push_back(Store);
6042       }
6043     }
6044   }
6045 
6046   if (!MemOpChains.empty())
6047     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
6048 
6049   // Build a sequence of copy-to-reg nodes chained together with token chain
6050   // and flag operands which copy the outgoing args into the appropriate regs.
6051   SDValue InFlag;
6052   for (auto &RegToPass : RegsToPass) {
6053     Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
6054                              RegToPass.second, InFlag);
6055     InFlag = Chain.getValue(1);
6056   }
6057 
6058   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
6059   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
6060   // node so that legalize doesn't hack it.
6061   if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
6062     auto GV = G->getGlobal();
6063     unsigned OpFlags =
6064         Subtarget->classifyGlobalFunctionReference(GV, getTargetMachine());
6065     if (OpFlags & AArch64II::MO_GOT) {
6066       Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
6067       Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
6068     } else {
6069       const GlobalValue *GV = G->getGlobal();
6070       Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
6071     }
6072   } else if (auto *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
6073     if (getTargetMachine().getCodeModel() == CodeModel::Large &&
6074         Subtarget->isTargetMachO()) {
6075       const char *Sym = S->getSymbol();
6076       Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
6077       Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
6078     } else {
6079       const char *Sym = S->getSymbol();
6080       Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
6081     }
6082   }
6083 
6084   // We don't usually want to end the call-sequence here because we would tidy
6085   // the frame up *after* the call, however in the ABI-changing tail-call case
6086   // we've carefully laid out the parameters so that when sp is reset they'll be
6087   // in the correct location.
6088   if (IsTailCall && !IsSibCall) {
6089     Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
6090                                DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
6091     InFlag = Chain.getValue(1);
6092   }
6093 
6094   std::vector<SDValue> Ops;
6095   Ops.push_back(Chain);
6096   Ops.push_back(Callee);
6097 
6098   if (IsTailCall) {
6099     // Each tail call may have to adjust the stack by a different amount, so
6100     // this information must travel along with the operation for eventual
6101     // consumption by emitEpilogue.
6102     Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
6103   }
6104 
6105   // Add argument registers to the end of the list so that they are known live
6106   // into the call.
6107   for (auto &RegToPass : RegsToPass)
6108     Ops.push_back(DAG.getRegister(RegToPass.first,
6109                                   RegToPass.second.getValueType()));
6110 
6111   // Add a register mask operand representing the call-preserved registers.
6112   const uint32_t *Mask;
6113   const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
6114   if (IsThisReturn) {
6115     // For 'this' returns, use the X0-preserving mask if applicable
6116     Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
6117     if (!Mask) {
6118       IsThisReturn = false;
6119       Mask = TRI->getCallPreservedMask(MF, CallConv);
6120     }
6121   } else
6122     Mask = TRI->getCallPreservedMask(MF, CallConv);
6123 
6124   if (Subtarget->hasCustomCallingConv())
6125     TRI->UpdateCustomCallPreservedMask(MF, &Mask);
6126 
6127   if (TRI->isAnyArgRegReserved(MF))
6128     TRI->emitReservedArgRegCallError(MF);
6129 
6130   assert(Mask && "Missing call preserved mask for calling convention");
6131   Ops.push_back(DAG.getRegisterMask(Mask));
6132 
6133   if (InFlag.getNode())
6134     Ops.push_back(InFlag);
6135 
6136   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6137 
6138   // If we're doing a tall call, use a TC_RETURN here rather than an
6139   // actual call instruction.
6140   if (IsTailCall) {
6141     MF.getFrameInfo().setHasTailCall();
6142     SDValue Ret = DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
6143     DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
6144     return Ret;
6145   }
6146 
6147   unsigned CallOpc = AArch64ISD::CALL;
6148   // Calls with operand bundle "clang.arc.attachedcall" are special. They should
6149   // be expanded to the call, directly followed by a special marker sequence.
6150   // Use the CALL_RVMARKER to do that.
6151   if (CLI.CB && objcarc::hasAttachedCallOpBundle(CLI.CB)) {
6152     assert(!IsTailCall &&
6153            "tail calls cannot be marked with clang.arc.attachedcall");
6154     CallOpc = AArch64ISD::CALL_RVMARKER;
6155   }
6156 
6157   // Returns a chain and a flag for retval copy to use.
6158   Chain = DAG.getNode(CallOpc, DL, NodeTys, Ops);
6159   DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
6160   InFlag = Chain.getValue(1);
6161   DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
6162 
6163   uint64_t CalleePopBytes =
6164       DoesCalleeRestoreStack(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : 0;
6165 
6166   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
6167                              DAG.getIntPtrConstant(CalleePopBytes, DL, true),
6168                              InFlag, DL);
6169   if (!Ins.empty())
6170     InFlag = Chain.getValue(1);
6171 
6172   // Handle result values, copying them out of physregs into vregs that we
6173   // return.
6174   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
6175                          InVals, IsThisReturn,
6176                          IsThisReturn ? OutVals[0] : SDValue());
6177 }
6178 
6179 bool AArch64TargetLowering::CanLowerReturn(
6180     CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
6181     const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
6182   CCAssignFn *RetCC = CCAssignFnForReturn(CallConv);
6183   SmallVector<CCValAssign, 16> RVLocs;
6184   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
6185   return CCInfo.CheckReturn(Outs, RetCC);
6186 }
6187 
6188 SDValue
6189 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
6190                                    bool isVarArg,
6191                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
6192                                    const SmallVectorImpl<SDValue> &OutVals,
6193                                    const SDLoc &DL, SelectionDAG &DAG) const {
6194   auto &MF = DAG.getMachineFunction();
6195   auto *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
6196 
6197   CCAssignFn *RetCC = CCAssignFnForReturn(CallConv);
6198   SmallVector<CCValAssign, 16> RVLocs;
6199   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
6200                  *DAG.getContext());
6201   CCInfo.AnalyzeReturn(Outs, RetCC);
6202 
6203   // Copy the result values into the output registers.
6204   SDValue Flag;
6205   SmallVector<std::pair<unsigned, SDValue>, 4> RetVals;
6206   SmallSet<unsigned, 4> RegsUsed;
6207   for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
6208        ++i, ++realRVLocIdx) {
6209     CCValAssign &VA = RVLocs[i];
6210     assert(VA.isRegLoc() && "Can only return in registers!");
6211     SDValue Arg = OutVals[realRVLocIdx];
6212 
6213     switch (VA.getLocInfo()) {
6214     default:
6215       llvm_unreachable("Unknown loc info!");
6216     case CCValAssign::Full:
6217       if (Outs[i].ArgVT == MVT::i1) {
6218         // AAPCS requires i1 to be zero-extended to i8 by the producer of the
6219         // value. This is strictly redundant on Darwin (which uses "zeroext
6220         // i1"), but will be optimised out before ISel.
6221         Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
6222         Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
6223       }
6224       break;
6225     case CCValAssign::BCvt:
6226       Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
6227       break;
6228     case CCValAssign::AExt:
6229     case CCValAssign::ZExt:
6230       Arg = DAG.getZExtOrTrunc(Arg, DL, VA.getLocVT());
6231       break;
6232     case CCValAssign::AExtUpper:
6233       assert(VA.getValVT() == MVT::i32 && "only expect 32 -> 64 upper bits");
6234       Arg = DAG.getZExtOrTrunc(Arg, DL, VA.getLocVT());
6235       Arg = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Arg,
6236                         DAG.getConstant(32, DL, VA.getLocVT()));
6237       break;
6238     }
6239 
6240     if (RegsUsed.count(VA.getLocReg())) {
6241       SDValue &Bits =
6242           llvm::find_if(RetVals, [=](const std::pair<unsigned, SDValue> &Elt) {
6243             return Elt.first == VA.getLocReg();
6244           })->second;
6245       Bits = DAG.getNode(ISD::OR, DL, Bits.getValueType(), Bits, Arg);
6246     } else {
6247       RetVals.emplace_back(VA.getLocReg(), Arg);
6248       RegsUsed.insert(VA.getLocReg());
6249     }
6250   }
6251 
6252   SmallVector<SDValue, 4> RetOps(1, Chain);
6253   for (auto &RetVal : RetVals) {
6254     Chain = DAG.getCopyToReg(Chain, DL, RetVal.first, RetVal.second, Flag);
6255     Flag = Chain.getValue(1);
6256     RetOps.push_back(
6257         DAG.getRegister(RetVal.first, RetVal.second.getValueType()));
6258   }
6259 
6260   // Windows AArch64 ABIs require that for returning structs by value we copy
6261   // the sret argument into X0 for the return.
6262   // We saved the argument into a virtual register in the entry block,
6263   // so now we copy the value out and into X0.
6264   if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
6265     SDValue Val = DAG.getCopyFromReg(RetOps[0], DL, SRetReg,
6266                                      getPointerTy(MF.getDataLayout()));
6267 
6268     unsigned RetValReg = AArch64::X0;
6269     Chain = DAG.getCopyToReg(Chain, DL, RetValReg, Val, Flag);
6270     Flag = Chain.getValue(1);
6271 
6272     RetOps.push_back(
6273       DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
6274   }
6275 
6276   const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
6277   const MCPhysReg *I =
6278       TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
6279   if (I) {
6280     for (; *I; ++I) {
6281       if (AArch64::GPR64RegClass.contains(*I))
6282         RetOps.push_back(DAG.getRegister(*I, MVT::i64));
6283       else if (AArch64::FPR64RegClass.contains(*I))
6284         RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
6285       else
6286         llvm_unreachable("Unexpected register class in CSRsViaCopy!");
6287     }
6288   }
6289 
6290   RetOps[0] = Chain; // Update chain.
6291 
6292   // Add the flag if we have it.
6293   if (Flag.getNode())
6294     RetOps.push_back(Flag);
6295 
6296   return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
6297 }
6298 
6299 //===----------------------------------------------------------------------===//
6300 //  Other Lowering Code
6301 //===----------------------------------------------------------------------===//
6302 
6303 SDValue AArch64TargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
6304                                              SelectionDAG &DAG,
6305                                              unsigned Flag) const {
6306   return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty,
6307                                     N->getOffset(), Flag);
6308 }
6309 
6310 SDValue AArch64TargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
6311                                              SelectionDAG &DAG,
6312                                              unsigned Flag) const {
6313   return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
6314 }
6315 
6316 SDValue AArch64TargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
6317                                              SelectionDAG &DAG,
6318                                              unsigned Flag) const {
6319   return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
6320                                    N->getOffset(), Flag);
6321 }
6322 
6323 SDValue AArch64TargetLowering::getTargetNode(BlockAddressSDNode* N, EVT Ty,
6324                                              SelectionDAG &DAG,
6325                                              unsigned Flag) const {
6326   return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
6327 }
6328 
6329 // (loadGOT sym)
6330 template <class NodeTy>
6331 SDValue AArch64TargetLowering::getGOT(NodeTy *N, SelectionDAG &DAG,
6332                                       unsigned Flags) const {
6333   LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getGOT\n");
6334   SDLoc DL(N);
6335   EVT Ty = getPointerTy(DAG.getDataLayout());
6336   SDValue GotAddr = getTargetNode(N, Ty, DAG, AArch64II::MO_GOT | Flags);
6337   // FIXME: Once remat is capable of dealing with instructions with register
6338   // operands, expand this into two nodes instead of using a wrapper node.
6339   return DAG.getNode(AArch64ISD::LOADgot, DL, Ty, GotAddr);
6340 }
6341 
6342 // (wrapper %highest(sym), %higher(sym), %hi(sym), %lo(sym))
6343 template <class NodeTy>
6344 SDValue AArch64TargetLowering::getAddrLarge(NodeTy *N, SelectionDAG &DAG,
6345                                             unsigned Flags) const {
6346   LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddrLarge\n");
6347   SDLoc DL(N);
6348   EVT Ty = getPointerTy(DAG.getDataLayout());
6349   const unsigned char MO_NC = AArch64II::MO_NC;
6350   return DAG.getNode(
6351       AArch64ISD::WrapperLarge, DL, Ty,
6352       getTargetNode(N, Ty, DAG, AArch64II::MO_G3 | Flags),
6353       getTargetNode(N, Ty, DAG, AArch64II::MO_G2 | MO_NC | Flags),
6354       getTargetNode(N, Ty, DAG, AArch64II::MO_G1 | MO_NC | Flags),
6355       getTargetNode(N, Ty, DAG, AArch64II::MO_G0 | MO_NC | Flags));
6356 }
6357 
6358 // (addlow (adrp %hi(sym)) %lo(sym))
6359 template <class NodeTy>
6360 SDValue AArch64TargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
6361                                        unsigned Flags) const {
6362   LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddr\n");
6363   SDLoc DL(N);
6364   EVT Ty = getPointerTy(DAG.getDataLayout());
6365   SDValue Hi = getTargetNode(N, Ty, DAG, AArch64II::MO_PAGE | Flags);
6366   SDValue Lo = getTargetNode(N, Ty, DAG,
6367                              AArch64II::MO_PAGEOFF | AArch64II::MO_NC | Flags);
6368   SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, Ty, Hi);
6369   return DAG.getNode(AArch64ISD::ADDlow, DL, Ty, ADRP, Lo);
6370 }
6371 
6372 // (adr sym)
6373 template <class NodeTy>
6374 SDValue AArch64TargetLowering::getAddrTiny(NodeTy *N, SelectionDAG &DAG,
6375                                            unsigned Flags) const {
6376   LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddrTiny\n");
6377   SDLoc DL(N);
6378   EVT Ty = getPointerTy(DAG.getDataLayout());
6379   SDValue Sym = getTargetNode(N, Ty, DAG, Flags);
6380   return DAG.getNode(AArch64ISD::ADR, DL, Ty, Sym);
6381 }
6382 
6383 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
6384                                                   SelectionDAG &DAG) const {
6385   GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
6386   const GlobalValue *GV = GN->getGlobal();
6387   unsigned OpFlags = Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
6388 
6389   if (OpFlags != AArch64II::MO_NO_FLAG)
6390     assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
6391            "unexpected offset in global node");
6392 
6393   // This also catches the large code model case for Darwin, and tiny code
6394   // model with got relocations.
6395   if ((OpFlags & AArch64II::MO_GOT) != 0) {
6396     return getGOT(GN, DAG, OpFlags);
6397   }
6398 
6399   SDValue Result;
6400   if (getTargetMachine().getCodeModel() == CodeModel::Large) {
6401     Result = getAddrLarge(GN, DAG, OpFlags);
6402   } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) {
6403     Result = getAddrTiny(GN, DAG, OpFlags);
6404   } else {
6405     Result = getAddr(GN, DAG, OpFlags);
6406   }
6407   EVT PtrVT = getPointerTy(DAG.getDataLayout());
6408   SDLoc DL(GN);
6409   if (OpFlags & (AArch64II::MO_DLLIMPORT | AArch64II::MO_COFFSTUB))
6410     Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
6411                          MachinePointerInfo::getGOT(DAG.getMachineFunction()));
6412   return Result;
6413 }
6414 
6415 /// Convert a TLS address reference into the correct sequence of loads
6416 /// and calls to compute the variable's address (for Darwin, currently) and
6417 /// return an SDValue containing the final node.
6418 
6419 /// Darwin only has one TLS scheme which must be capable of dealing with the
6420 /// fully general situation, in the worst case. This means:
6421 ///     + "extern __thread" declaration.
6422 ///     + Defined in a possibly unknown dynamic library.
6423 ///
6424 /// The general system is that each __thread variable has a [3 x i64] descriptor
6425 /// which contains information used by the runtime to calculate the address. The
6426 /// only part of this the compiler needs to know about is the first xword, which
6427 /// contains a function pointer that must be called with the address of the
6428 /// entire descriptor in "x0".
6429 ///
6430 /// Since this descriptor may be in a different unit, in general even the
6431 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
6432 /// is:
6433 ///     adrp x0, _var@TLVPPAGE
6434 ///     ldr x0, [x0, _var@TLVPPAGEOFF]   ; x0 now contains address of descriptor
6435 ///     ldr x1, [x0]                     ; x1 contains 1st entry of descriptor,
6436 ///                                      ; the function pointer
6437 ///     blr x1                           ; Uses descriptor address in x0
6438 ///     ; Address of _var is now in x0.
6439 ///
6440 /// If the address of _var's descriptor *is* known to the linker, then it can
6441 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
6442 /// a slight efficiency gain.
6443 SDValue
6444 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
6445                                                    SelectionDAG &DAG) const {
6446   assert(Subtarget->isTargetDarwin() &&
6447          "This function expects a Darwin target");
6448 
6449   SDLoc DL(Op);
6450   MVT PtrVT = getPointerTy(DAG.getDataLayout());
6451   MVT PtrMemVT = getPointerMemTy(DAG.getDataLayout());
6452   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6453 
6454   SDValue TLVPAddr =
6455       DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
6456   SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
6457 
6458   // The first entry in the descriptor is a function pointer that we must call
6459   // to obtain the address of the variable.
6460   SDValue Chain = DAG.getEntryNode();
6461   SDValue FuncTLVGet = DAG.getLoad(
6462       PtrMemVT, DL, Chain, DescAddr,
6463       MachinePointerInfo::getGOT(DAG.getMachineFunction()),
6464       Align(PtrMemVT.getSizeInBits() / 8),
6465       MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable);
6466   Chain = FuncTLVGet.getValue(1);
6467 
6468   // Extend loaded pointer if necessary (i.e. if ILP32) to DAG pointer.
6469   FuncTLVGet = DAG.getZExtOrTrunc(FuncTLVGet, DL, PtrVT);
6470 
6471   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
6472   MFI.setAdjustsStack(true);
6473 
6474   // TLS calls preserve all registers except those that absolutely must be
6475   // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
6476   // silly).
6477   const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
6478   const uint32_t *Mask = TRI->getTLSCallPreservedMask();
6479   if (Subtarget->hasCustomCallingConv())
6480     TRI->UpdateCustomCallPreservedMask(DAG.getMachineFunction(), &Mask);
6481 
6482   // Finally, we can make the call. This is just a degenerate version of a
6483   // normal AArch64 call node: x0 takes the address of the descriptor, and
6484   // returns the address of the variable in this thread.
6485   Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
6486   Chain =
6487       DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
6488                   Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
6489                   DAG.getRegisterMask(Mask), Chain.getValue(1));
6490   return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
6491 }
6492 
6493 /// Convert a thread-local variable reference into a sequence of instructions to
6494 /// compute the variable's address for the local exec TLS model of ELF targets.
6495 /// The sequence depends on the maximum TLS area size.
6496 SDValue AArch64TargetLowering::LowerELFTLSLocalExec(const GlobalValue *GV,
6497                                                     SDValue ThreadBase,
6498                                                     const SDLoc &DL,
6499                                                     SelectionDAG &DAG) const {
6500   EVT PtrVT = getPointerTy(DAG.getDataLayout());
6501   SDValue TPOff, Addr;
6502 
6503   switch (DAG.getTarget().Options.TLSSize) {
6504   default:
6505     llvm_unreachable("Unexpected TLS size");
6506 
6507   case 12: {
6508     // mrs   x0, TPIDR_EL0
6509     // add   x0, x0, :tprel_lo12:a
6510     SDValue Var = DAG.getTargetGlobalAddress(
6511         GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
6512     return SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
6513                                       Var,
6514                                       DAG.getTargetConstant(0, DL, MVT::i32)),
6515                    0);
6516   }
6517 
6518   case 24: {
6519     // mrs   x0, TPIDR_EL0
6520     // add   x0, x0, :tprel_hi12:a
6521     // add   x0, x0, :tprel_lo12_nc:a
6522     SDValue HiVar = DAG.getTargetGlobalAddress(
6523         GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
6524     SDValue LoVar = DAG.getTargetGlobalAddress(
6525         GV, DL, PtrVT, 0,
6526         AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
6527     Addr = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
6528                                       HiVar,
6529                                       DAG.getTargetConstant(0, DL, MVT::i32)),
6530                    0);
6531     return SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, Addr,
6532                                       LoVar,
6533                                       DAG.getTargetConstant(0, DL, MVT::i32)),
6534                    0);
6535   }
6536 
6537   case 32: {
6538     // mrs   x1, TPIDR_EL0
6539     // movz  x0, #:tprel_g1:a
6540     // movk  x0, #:tprel_g0_nc:a
6541     // add   x0, x1, x0
6542     SDValue HiVar = DAG.getTargetGlobalAddress(
6543         GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
6544     SDValue LoVar = DAG.getTargetGlobalAddress(
6545         GV, DL, PtrVT, 0,
6546         AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
6547     TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
6548                                        DAG.getTargetConstant(16, DL, MVT::i32)),
6549                     0);
6550     TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
6551                                        DAG.getTargetConstant(0, DL, MVT::i32)),
6552                     0);
6553     return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
6554   }
6555 
6556   case 48: {
6557     // mrs   x1, TPIDR_EL0
6558     // movz  x0, #:tprel_g2:a
6559     // movk  x0, #:tprel_g1_nc:a
6560     // movk  x0, #:tprel_g0_nc:a
6561     // add   x0, x1, x0
6562     SDValue HiVar = DAG.getTargetGlobalAddress(
6563         GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G2);
6564     SDValue MiVar = DAG.getTargetGlobalAddress(
6565         GV, DL, PtrVT, 0,
6566         AArch64II::MO_TLS | AArch64II::MO_G1 | AArch64II::MO_NC);
6567     SDValue LoVar = DAG.getTargetGlobalAddress(
6568         GV, DL, PtrVT, 0,
6569         AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
6570     TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
6571                                        DAG.getTargetConstant(32, DL, MVT::i32)),
6572                     0);
6573     TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, MiVar,
6574                                        DAG.getTargetConstant(16, DL, MVT::i32)),
6575                     0);
6576     TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
6577                                        DAG.getTargetConstant(0, DL, MVT::i32)),
6578                     0);
6579     return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
6580   }
6581   }
6582 }
6583 
6584 /// When accessing thread-local variables under either the general-dynamic or
6585 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
6586 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
6587 /// is a function pointer to carry out the resolution.
6588 ///
6589 /// The sequence is:
6590 ///    adrp  x0, :tlsdesc:var
6591 ///    ldr   x1, [x0, #:tlsdesc_lo12:var]
6592 ///    add   x0, x0, #:tlsdesc_lo12:var
6593 ///    .tlsdesccall var
6594 ///    blr   x1
6595 ///    (TPIDR_EL0 offset now in x0)
6596 ///
6597 ///  The above sequence must be produced unscheduled, to enable the linker to
6598 ///  optimize/relax this sequence.
6599 ///  Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
6600 ///  above sequence, and expanded really late in the compilation flow, to ensure
6601 ///  the sequence is produced as per above.
6602 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
6603                                                       const SDLoc &DL,
6604                                                       SelectionDAG &DAG) const {
6605   EVT PtrVT = getPointerTy(DAG.getDataLayout());
6606 
6607   SDValue Chain = DAG.getEntryNode();
6608   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6609 
6610   Chain =
6611       DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, {Chain, SymAddr});
6612   SDValue Glue = Chain.getValue(1);
6613 
6614   return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
6615 }
6616 
6617 SDValue
6618 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
6619                                                 SelectionDAG &DAG) const {
6620   assert(Subtarget->isTargetELF() && "This function expects an ELF target");
6621 
6622   const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6623 
6624   TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
6625 
6626   if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
6627     if (Model == TLSModel::LocalDynamic)
6628       Model = TLSModel::GeneralDynamic;
6629   }
6630 
6631   if (getTargetMachine().getCodeModel() == CodeModel::Large &&
6632       Model != TLSModel::LocalExec)
6633     report_fatal_error("ELF TLS only supported in small memory model or "
6634                        "in local exec TLS model");
6635   // Different choices can be made for the maximum size of the TLS area for a
6636   // module. For the small address model, the default TLS size is 16MiB and the
6637   // maximum TLS size is 4GiB.
6638   // FIXME: add tiny and large code model support for TLS access models other
6639   // than local exec. We currently generate the same code as small for tiny,
6640   // which may be larger than needed.
6641 
6642   SDValue TPOff;
6643   EVT PtrVT = getPointerTy(DAG.getDataLayout());
6644   SDLoc DL(Op);
6645   const GlobalValue *GV = GA->getGlobal();
6646 
6647   SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
6648 
6649   if (Model == TLSModel::LocalExec) {
6650     return LowerELFTLSLocalExec(GV, ThreadBase, DL, DAG);
6651   } else if (Model == TLSModel::InitialExec) {
6652     TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
6653     TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
6654   } else if (Model == TLSModel::LocalDynamic) {
6655     // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
6656     // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
6657     // the beginning of the module's TLS region, followed by a DTPREL offset
6658     // calculation.
6659 
6660     // These accesses will need deduplicating if there's more than one.
6661     AArch64FunctionInfo *MFI =
6662         DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
6663     MFI->incNumLocalDynamicTLSAccesses();
6664 
6665     // The call needs a relocation too for linker relaxation. It doesn't make
6666     // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
6667     // the address.
6668     SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
6669                                                   AArch64II::MO_TLS);
6670 
6671     // Now we can calculate the offset from TPIDR_EL0 to this module's
6672     // thread-local area.
6673     TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
6674 
6675     // Now use :dtprel_whatever: operations to calculate this variable's offset
6676     // in its thread-storage area.
6677     SDValue HiVar = DAG.getTargetGlobalAddress(
6678         GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
6679     SDValue LoVar = DAG.getTargetGlobalAddress(
6680         GV, DL, MVT::i64, 0,
6681         AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
6682 
6683     TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
6684                                        DAG.getTargetConstant(0, DL, MVT::i32)),
6685                     0);
6686     TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
6687                                        DAG.getTargetConstant(0, DL, MVT::i32)),
6688                     0);
6689   } else if (Model == TLSModel::GeneralDynamic) {
6690     // The call needs a relocation too for linker relaxation. It doesn't make
6691     // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
6692     // the address.
6693     SDValue SymAddr =
6694         DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
6695 
6696     // Finally we can make a call to calculate the offset from tpidr_el0.
6697     TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
6698   } else
6699     llvm_unreachable("Unsupported ELF TLS access model");
6700 
6701   return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
6702 }
6703 
6704 SDValue
6705 AArch64TargetLowering::LowerWindowsGlobalTLSAddress(SDValue Op,
6706                                                     SelectionDAG &DAG) const {
6707   assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering");
6708 
6709   SDValue Chain = DAG.getEntryNode();
6710   EVT PtrVT = getPointerTy(DAG.getDataLayout());
6711   SDLoc DL(Op);
6712 
6713   SDValue TEB = DAG.getRegister(AArch64::X18, MVT::i64);
6714 
6715   // Load the ThreadLocalStoragePointer from the TEB
6716   // A pointer to the TLS array is located at offset 0x58 from the TEB.
6717   SDValue TLSArray =
6718       DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x58, DL));
6719   TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
6720   Chain = TLSArray.getValue(1);
6721 
6722   // Load the TLS index from the C runtime;
6723   // This does the same as getAddr(), but without having a GlobalAddressSDNode.
6724   // This also does the same as LOADgot, but using a generic i32 load,
6725   // while LOADgot only loads i64.
6726   SDValue TLSIndexHi =
6727       DAG.getTargetExternalSymbol("_tls_index", PtrVT, AArch64II::MO_PAGE);
6728   SDValue TLSIndexLo = DAG.getTargetExternalSymbol(
6729       "_tls_index", PtrVT, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
6730   SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, TLSIndexHi);
6731   SDValue TLSIndex =
6732       DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, TLSIndexLo);
6733   TLSIndex = DAG.getLoad(MVT::i32, DL, Chain, TLSIndex, MachinePointerInfo());
6734   Chain = TLSIndex.getValue(1);
6735 
6736   // The pointer to the thread's TLS data area is at the TLS Index scaled by 8
6737   // offset into the TLSArray.
6738   TLSIndex = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TLSIndex);
6739   SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
6740                              DAG.getConstant(3, DL, PtrVT));
6741   SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
6742                             DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
6743                             MachinePointerInfo());
6744   Chain = TLS.getValue(1);
6745 
6746   const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6747   const GlobalValue *GV = GA->getGlobal();
6748   SDValue TGAHi = DAG.getTargetGlobalAddress(
6749       GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
6750   SDValue TGALo = DAG.getTargetGlobalAddress(
6751       GV, DL, PtrVT, 0,
6752       AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
6753 
6754   // Add the offset from the start of the .tls section (section base).
6755   SDValue Addr =
6756       SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TLS, TGAHi,
6757                                  DAG.getTargetConstant(0, DL, MVT::i32)),
6758               0);
6759   Addr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, Addr, TGALo);
6760   return Addr;
6761 }
6762 
6763 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
6764                                                      SelectionDAG &DAG) const {
6765   const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6766   if (DAG.getTarget().useEmulatedTLS())
6767     return LowerToTLSEmulatedModel(GA, DAG);
6768 
6769   if (Subtarget->isTargetDarwin())
6770     return LowerDarwinGlobalTLSAddress(Op, DAG);
6771   if (Subtarget->isTargetELF())
6772     return LowerELFGlobalTLSAddress(Op, DAG);
6773   if (Subtarget->isTargetWindows())
6774     return LowerWindowsGlobalTLSAddress(Op, DAG);
6775 
6776   llvm_unreachable("Unexpected platform trying to use TLS");
6777 }
6778 
6779 // Looks through \param Val to determine the bit that can be used to
6780 // check the sign of the value. It returns the unextended value and
6781 // the sign bit position.
6782 std::pair<SDValue, uint64_t> lookThroughSignExtension(SDValue Val) {
6783   if (Val.getOpcode() == ISD::SIGN_EXTEND_INREG)
6784     return {Val.getOperand(0),
6785             cast<VTSDNode>(Val.getOperand(1))->getVT().getFixedSizeInBits() -
6786                 1};
6787 
6788   if (Val.getOpcode() == ISD::SIGN_EXTEND)
6789     return {Val.getOperand(0),
6790             Val.getOperand(0)->getValueType(0).getFixedSizeInBits() - 1};
6791 
6792   return {Val, Val.getValueSizeInBits() - 1};
6793 }
6794 
6795 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
6796   SDValue Chain = Op.getOperand(0);
6797   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
6798   SDValue LHS = Op.getOperand(2);
6799   SDValue RHS = Op.getOperand(3);
6800   SDValue Dest = Op.getOperand(4);
6801   SDLoc dl(Op);
6802 
6803   MachineFunction &MF = DAG.getMachineFunction();
6804   // Speculation tracking/SLH assumes that optimized TB(N)Z/CB(N)Z instructions
6805   // will not be produced, as they are conditional branch instructions that do
6806   // not set flags.
6807   bool ProduceNonFlagSettingCondBr =
6808       !MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening);
6809 
6810   // Handle f128 first, since lowering it will result in comparing the return
6811   // value of a libcall against zero, which is just what the rest of LowerBR_CC
6812   // is expecting to deal with.
6813   if (LHS.getValueType() == MVT::f128) {
6814     softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl, LHS, RHS);
6815 
6816     // If softenSetCCOperands returned a scalar, we need to compare the result
6817     // against zero to select between true and false values.
6818     if (!RHS.getNode()) {
6819       RHS = DAG.getConstant(0, dl, LHS.getValueType());
6820       CC = ISD::SETNE;
6821     }
6822   }
6823 
6824   // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
6825   // instruction.
6826   if (ISD::isOverflowIntrOpRes(LHS) && isOneConstant(RHS) &&
6827       (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6828     // Only lower legal XALUO ops.
6829     if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
6830       return SDValue();
6831 
6832     // The actual operation with overflow check.
6833     AArch64CC::CondCode OFCC;
6834     SDValue Value, Overflow;
6835     std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
6836 
6837     if (CC == ISD::SETNE)
6838       OFCC = getInvertedCondCode(OFCC);
6839     SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
6840 
6841     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
6842                        Overflow);
6843   }
6844 
6845   if (LHS.getValueType().isInteger()) {
6846     assert((LHS.getValueType() == RHS.getValueType()) &&
6847            (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
6848 
6849     // If the RHS of the comparison is zero, we can potentially fold this
6850     // to a specialized branch.
6851     const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
6852     if (RHSC && RHSC->getZExtValue() == 0 && ProduceNonFlagSettingCondBr) {
6853       if (CC == ISD::SETEQ) {
6854         // See if we can use a TBZ to fold in an AND as well.
6855         // TBZ has a smaller branch displacement than CBZ.  If the offset is
6856         // out of bounds, a late MI-layer pass rewrites branches.
6857         // 403.gcc is an example that hits this case.
6858         if (LHS.getOpcode() == ISD::AND &&
6859             isa<ConstantSDNode>(LHS.getOperand(1)) &&
6860             isPowerOf2_64(LHS.getConstantOperandVal(1))) {
6861           SDValue Test = LHS.getOperand(0);
6862           uint64_t Mask = LHS.getConstantOperandVal(1);
6863           return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
6864                              DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
6865                              Dest);
6866         }
6867 
6868         return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
6869       } else if (CC == ISD::SETNE) {
6870         // See if we can use a TBZ to fold in an AND as well.
6871         // TBZ has a smaller branch displacement than CBZ.  If the offset is
6872         // out of bounds, a late MI-layer pass rewrites branches.
6873         // 403.gcc is an example that hits this case.
6874         if (LHS.getOpcode() == ISD::AND &&
6875             isa<ConstantSDNode>(LHS.getOperand(1)) &&
6876             isPowerOf2_64(LHS.getConstantOperandVal(1))) {
6877           SDValue Test = LHS.getOperand(0);
6878           uint64_t Mask = LHS.getConstantOperandVal(1);
6879           return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
6880                              DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
6881                              Dest);
6882         }
6883 
6884         return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
6885       } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
6886         // Don't combine AND since emitComparison converts the AND to an ANDS
6887         // (a.k.a. TST) and the test in the test bit and branch instruction
6888         // becomes redundant.  This would also increase register pressure.
6889         uint64_t SignBitPos;
6890         std::tie(LHS, SignBitPos) = lookThroughSignExtension(LHS);
6891         return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
6892                            DAG.getConstant(SignBitPos, dl, MVT::i64), Dest);
6893       }
6894     }
6895     if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
6896         LHS.getOpcode() != ISD::AND && ProduceNonFlagSettingCondBr) {
6897       // Don't combine AND since emitComparison converts the AND to an ANDS
6898       // (a.k.a. TST) and the test in the test bit and branch instruction
6899       // becomes redundant.  This would also increase register pressure.
6900       uint64_t SignBitPos;
6901       std::tie(LHS, SignBitPos) = lookThroughSignExtension(LHS);
6902       return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
6903                          DAG.getConstant(SignBitPos, dl, MVT::i64), Dest);
6904     }
6905 
6906     SDValue CCVal;
6907     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
6908     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
6909                        Cmp);
6910   }
6911 
6912   assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::bf16 ||
6913          LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
6914 
6915   // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6916   // clean.  Some of them require two branches to implement.
6917   SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
6918   AArch64CC::CondCode CC1, CC2;
6919   changeFPCCToAArch64CC(CC, CC1, CC2);
6920   SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
6921   SDValue BR1 =
6922       DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
6923   if (CC2 != AArch64CC::AL) {
6924     SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
6925     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
6926                        Cmp);
6927   }
6928 
6929   return BR1;
6930 }
6931 
6932 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
6933                                               SelectionDAG &DAG) const {
6934   EVT VT = Op.getValueType();
6935   SDLoc DL(Op);
6936 
6937   SDValue In1 = Op.getOperand(0);
6938   SDValue In2 = Op.getOperand(1);
6939   EVT SrcVT = In2.getValueType();
6940 
6941   if (SrcVT.bitsLT(VT))
6942     In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
6943   else if (SrcVT.bitsGT(VT))
6944     In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL));
6945 
6946   EVT VecVT;
6947   uint64_t EltMask;
6948   SDValue VecVal1, VecVal2;
6949 
6950   auto setVecVal = [&] (int Idx) {
6951     if (!VT.isVector()) {
6952       VecVal1 = DAG.getTargetInsertSubreg(Idx, DL, VecVT,
6953                                           DAG.getUNDEF(VecVT), In1);
6954       VecVal2 = DAG.getTargetInsertSubreg(Idx, DL, VecVT,
6955                                           DAG.getUNDEF(VecVT), In2);
6956     } else {
6957       VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
6958       VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
6959     }
6960   };
6961 
6962   if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
6963     VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
6964     EltMask = 0x80000000ULL;
6965     setVecVal(AArch64::ssub);
6966   } else if (VT == MVT::f64 || VT == MVT::v2f64) {
6967     VecVT = MVT::v2i64;
6968 
6969     // We want to materialize a mask with the high bit set, but the AdvSIMD
6970     // immediate moves cannot materialize that in a single instruction for
6971     // 64-bit elements. Instead, materialize zero and then negate it.
6972     EltMask = 0;
6973 
6974     setVecVal(AArch64::dsub);
6975   } else if (VT == MVT::f16 || VT == MVT::v4f16 || VT == MVT::v8f16) {
6976     VecVT = (VT == MVT::v4f16 ? MVT::v4i16 : MVT::v8i16);
6977     EltMask = 0x8000ULL;
6978     setVecVal(AArch64::hsub);
6979   } else {
6980     llvm_unreachable("Invalid type for copysign!");
6981   }
6982 
6983   SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
6984 
6985   // If we couldn't materialize the mask above, then the mask vector will be
6986   // the zero vector, and we need to negate it here.
6987   if (VT == MVT::f64 || VT == MVT::v2f64) {
6988     BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
6989     BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
6990     BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
6991   }
6992 
6993   SDValue Sel =
6994       DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
6995 
6996   if (VT == MVT::f16)
6997     return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, Sel);
6998   if (VT == MVT::f32)
6999     return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
7000   else if (VT == MVT::f64)
7001     return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
7002   else
7003     return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
7004 }
7005 
7006 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
7007   if (DAG.getMachineFunction().getFunction().hasFnAttribute(
7008           Attribute::NoImplicitFloat))
7009     return SDValue();
7010 
7011   if (!Subtarget->hasNEON())
7012     return SDValue();
7013 
7014   // While there is no integer popcount instruction, it can
7015   // be more efficiently lowered to the following sequence that uses
7016   // AdvSIMD registers/instructions as long as the copies to/from
7017   // the AdvSIMD registers are cheap.
7018   //  FMOV    D0, X0        // copy 64-bit int to vector, high bits zero'd
7019   //  CNT     V0.8B, V0.8B  // 8xbyte pop-counts
7020   //  ADDV    B0, V0.8B     // sum 8xbyte pop-counts
7021   //  UMOV    X0, V0.B[0]   // copy byte result back to integer reg
7022   SDValue Val = Op.getOperand(0);
7023   SDLoc DL(Op);
7024   EVT VT = Op.getValueType();
7025 
7026   if (VT == MVT::i32 || VT == MVT::i64) {
7027     if (VT == MVT::i32)
7028       Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
7029     Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
7030 
7031     SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
7032     SDValue UaddLV = DAG.getNode(
7033         ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
7034         DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
7035 
7036     if (VT == MVT::i64)
7037       UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
7038     return UaddLV;
7039   } else if (VT == MVT::i128) {
7040     Val = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Val);
7041 
7042     SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v16i8, Val);
7043     SDValue UaddLV = DAG.getNode(
7044         ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
7045         DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
7046 
7047     return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i128, UaddLV);
7048   }
7049 
7050   if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT))
7051     return LowerToPredicatedOp(Op, DAG, AArch64ISD::CTPOP_MERGE_PASSTHRU);
7052 
7053   assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
7054           VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
7055          "Unexpected type for custom ctpop lowering");
7056 
7057   EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
7058   Val = DAG.getBitcast(VT8Bit, Val);
7059   Val = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Val);
7060 
7061   // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds.
7062   unsigned EltSize = 8;
7063   unsigned NumElts = VT.is64BitVector() ? 8 : 16;
7064   while (EltSize != VT.getScalarSizeInBits()) {
7065     EltSize *= 2;
7066     NumElts /= 2;
7067     MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts);
7068     Val = DAG.getNode(
7069         ISD::INTRINSIC_WO_CHAIN, DL, WidenVT,
7070         DAG.getConstant(Intrinsic::aarch64_neon_uaddlp, DL, MVT::i32), Val);
7071   }
7072 
7073   return Val;
7074 }
7075 
7076 SDValue AArch64TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
7077   EVT VT = Op.getValueType();
7078   assert(VT.isScalableVector() ||
7079          useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true));
7080 
7081   SDLoc DL(Op);
7082   SDValue RBIT = DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(0));
7083   return DAG.getNode(ISD::CTLZ, DL, VT, RBIT);
7084 }
7085 
7086 SDValue AArch64TargetLowering::LowerBitreverse(SDValue Op,
7087                                                SelectionDAG &DAG) const {
7088   EVT VT = Op.getValueType();
7089 
7090   if (VT.isScalableVector() ||
7091       useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true))
7092     return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU,
7093                                true);
7094 
7095   SDLoc DL(Op);
7096   SDValue REVB;
7097   MVT VST;
7098 
7099   switch (VT.getSimpleVT().SimpleTy) {
7100   default:
7101     llvm_unreachable("Invalid type for bitreverse!");
7102 
7103   case MVT::v2i32: {
7104     VST = MVT::v8i8;
7105     REVB = DAG.getNode(AArch64ISD::REV32, DL, VST, Op.getOperand(0));
7106 
7107     break;
7108   }
7109 
7110   case MVT::v4i32: {
7111     VST = MVT::v16i8;
7112     REVB = DAG.getNode(AArch64ISD::REV32, DL, VST, Op.getOperand(0));
7113 
7114     break;
7115   }
7116 
7117   case MVT::v1i64: {
7118     VST = MVT::v8i8;
7119     REVB = DAG.getNode(AArch64ISD::REV64, DL, VST, Op.getOperand(0));
7120 
7121     break;
7122   }
7123 
7124   case MVT::v2i64: {
7125     VST = MVT::v16i8;
7126     REVB = DAG.getNode(AArch64ISD::REV64, DL, VST, Op.getOperand(0));
7127 
7128     break;
7129   }
7130   }
7131 
7132   return DAG.getNode(AArch64ISD::NVCAST, DL, VT,
7133                      DAG.getNode(ISD::BITREVERSE, DL, VST, REVB));
7134 }
7135 
7136 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7137 
7138   if (Op.getValueType().isVector())
7139     return LowerVSETCC(Op, DAG);
7140 
7141   bool IsStrict = Op->isStrictFPOpcode();
7142   bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS;
7143   unsigned OpNo = IsStrict ? 1 : 0;
7144   SDValue Chain;
7145   if (IsStrict)
7146     Chain = Op.getOperand(0);
7147   SDValue LHS = Op.getOperand(OpNo + 0);
7148   SDValue RHS = Op.getOperand(OpNo + 1);
7149   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(OpNo + 2))->get();
7150   SDLoc dl(Op);
7151 
7152   // We chose ZeroOrOneBooleanContents, so use zero and one.
7153   EVT VT = Op.getValueType();
7154   SDValue TVal = DAG.getConstant(1, dl, VT);
7155   SDValue FVal = DAG.getConstant(0, dl, VT);
7156 
7157   // Handle f128 first, since one possible outcome is a normal integer
7158   // comparison which gets picked up by the next if statement.
7159   if (LHS.getValueType() == MVT::f128) {
7160     softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl, LHS, RHS, Chain,
7161                         IsSignaling);
7162 
7163     // If softenSetCCOperands returned a scalar, use it.
7164     if (!RHS.getNode()) {
7165       assert(LHS.getValueType() == Op.getValueType() &&
7166              "Unexpected setcc expansion!");
7167       return IsStrict ? DAG.getMergeValues({LHS, Chain}, dl) : LHS;
7168     }
7169   }
7170 
7171   if (LHS.getValueType().isInteger()) {
7172     SDValue CCVal;
7173     SDValue Cmp = getAArch64Cmp(
7174         LHS, RHS, ISD::getSetCCInverse(CC, LHS.getValueType()), CCVal, DAG, dl);
7175 
7176     // Note that we inverted the condition above, so we reverse the order of
7177     // the true and false operands here.  This will allow the setcc to be
7178     // matched to a single CSINC instruction.
7179     SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
7180     return IsStrict ? DAG.getMergeValues({Res, Chain}, dl) : Res;
7181   }
7182 
7183   // Now we know we're dealing with FP values.
7184   assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
7185          LHS.getValueType() == MVT::f64);
7186 
7187   // If that fails, we'll need to perform an FCMP + CSEL sequence.  Go ahead
7188   // and do the comparison.
7189   SDValue Cmp;
7190   if (IsStrict)
7191     Cmp = emitStrictFPComparison(LHS, RHS, dl, DAG, Chain, IsSignaling);
7192   else
7193     Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
7194 
7195   AArch64CC::CondCode CC1, CC2;
7196   changeFPCCToAArch64CC(CC, CC1, CC2);
7197   SDValue Res;
7198   if (CC2 == AArch64CC::AL) {
7199     changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, LHS.getValueType()), CC1,
7200                           CC2);
7201     SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
7202 
7203     // Note that we inverted the condition above, so we reverse the order of
7204     // the true and false operands here.  This will allow the setcc to be
7205     // matched to a single CSINC instruction.
7206     Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
7207   } else {
7208     // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
7209     // totally clean.  Some of them require two CSELs to implement.  As is in
7210     // this case, we emit the first CSEL and then emit a second using the output
7211     // of the first as the RHS.  We're effectively OR'ing the two CC's together.
7212 
7213     // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
7214     SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
7215     SDValue CS1 =
7216         DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
7217 
7218     SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
7219     Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
7220   }
7221   return IsStrict ? DAG.getMergeValues({Res, Cmp.getValue(1)}, dl) : Res;
7222 }
7223 
7224 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
7225                                               SDValue RHS, SDValue TVal,
7226                                               SDValue FVal, const SDLoc &dl,
7227                                               SelectionDAG &DAG) const {
7228   // Handle f128 first, because it will result in a comparison of some RTLIB
7229   // call result against zero.
7230   if (LHS.getValueType() == MVT::f128) {
7231     softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl, LHS, RHS);
7232 
7233     // If softenSetCCOperands returned a scalar, we need to compare the result
7234     // against zero to select between true and false values.
7235     if (!RHS.getNode()) {
7236       RHS = DAG.getConstant(0, dl, LHS.getValueType());
7237       CC = ISD::SETNE;
7238     }
7239   }
7240 
7241   // Also handle f16, for which we need to do a f32 comparison.
7242   if (LHS.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {
7243     LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
7244     RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
7245   }
7246 
7247   // Next, handle integers.
7248   if (LHS.getValueType().isInteger()) {
7249     assert((LHS.getValueType() == RHS.getValueType()) &&
7250            (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
7251 
7252     ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
7253     ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
7254     ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
7255     // Check for sign pattern (SELECT_CC setgt, iN lhs, -1, 1, -1) and transform
7256     // into (OR (ASR lhs, N-1), 1), which requires less instructions for the
7257     // supported types.
7258     if (CC == ISD::SETGT && RHSC && RHSC->isAllOnesValue() && CTVal && CFVal &&
7259         CTVal->isOne() && CFVal->isAllOnesValue() &&
7260         LHS.getValueType() == TVal.getValueType()) {
7261       EVT VT = LHS.getValueType();
7262       SDValue Shift =
7263           DAG.getNode(ISD::SRA, dl, VT, LHS,
7264                       DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
7265       return DAG.getNode(ISD::OR, dl, VT, Shift, DAG.getConstant(1, dl, VT));
7266     }
7267 
7268     unsigned Opcode = AArch64ISD::CSEL;
7269 
7270     // If both the TVal and the FVal are constants, see if we can swap them in
7271     // order to for a CSINV or CSINC out of them.
7272     if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
7273       std::swap(TVal, FVal);
7274       std::swap(CTVal, CFVal);
7275       CC = ISD::getSetCCInverse(CC, LHS.getValueType());
7276     } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
7277       std::swap(TVal, FVal);
7278       std::swap(CTVal, CFVal);
7279       CC = ISD::getSetCCInverse(CC, LHS.getValueType());
7280     } else if (TVal.getOpcode() == ISD::XOR) {
7281       // If TVal is a NOT we want to swap TVal and FVal so that we can match
7282       // with a CSINV rather than a CSEL.
7283       if (isAllOnesConstant(TVal.getOperand(1))) {
7284         std::swap(TVal, FVal);
7285         std::swap(CTVal, CFVal);
7286         CC = ISD::getSetCCInverse(CC, LHS.getValueType());
7287       }
7288     } else if (TVal.getOpcode() == ISD::SUB) {
7289       // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
7290       // that we can match with a CSNEG rather than a CSEL.
7291       if (isNullConstant(TVal.getOperand(0))) {
7292         std::swap(TVal, FVal);
7293         std::swap(CTVal, CFVal);
7294         CC = ISD::getSetCCInverse(CC, LHS.getValueType());
7295       }
7296     } else if (CTVal && CFVal) {
7297       const int64_t TrueVal = CTVal->getSExtValue();
7298       const int64_t FalseVal = CFVal->getSExtValue();
7299       bool Swap = false;
7300 
7301       // If both TVal and FVal are constants, see if FVal is the
7302       // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
7303       // instead of a CSEL in that case.
7304       if (TrueVal == ~FalseVal) {
7305         Opcode = AArch64ISD::CSINV;
7306       } else if (FalseVal > std::numeric_limits<int64_t>::min() &&
7307                  TrueVal == -FalseVal) {
7308         Opcode = AArch64ISD::CSNEG;
7309       } else if (TVal.getValueType() == MVT::i32) {
7310         // If our operands are only 32-bit wide, make sure we use 32-bit
7311         // arithmetic for the check whether we can use CSINC. This ensures that
7312         // the addition in the check will wrap around properly in case there is
7313         // an overflow (which would not be the case if we do the check with
7314         // 64-bit arithmetic).
7315         const uint32_t TrueVal32 = CTVal->getZExtValue();
7316         const uint32_t FalseVal32 = CFVal->getZExtValue();
7317 
7318         if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
7319           Opcode = AArch64ISD::CSINC;
7320 
7321           if (TrueVal32 > FalseVal32) {
7322             Swap = true;
7323           }
7324         }
7325         // 64-bit check whether we can use CSINC.
7326       } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
7327         Opcode = AArch64ISD::CSINC;
7328 
7329         if (TrueVal > FalseVal) {
7330           Swap = true;
7331         }
7332       }
7333 
7334       // Swap TVal and FVal if necessary.
7335       if (Swap) {
7336         std::swap(TVal, FVal);
7337         std::swap(CTVal, CFVal);
7338         CC = ISD::getSetCCInverse(CC, LHS.getValueType());
7339       }
7340 
7341       if (Opcode != AArch64ISD::CSEL) {
7342         // Drop FVal since we can get its value by simply inverting/negating
7343         // TVal.
7344         FVal = TVal;
7345       }
7346     }
7347 
7348     // Avoid materializing a constant when possible by reusing a known value in
7349     // a register.  However, don't perform this optimization if the known value
7350     // is one, zero or negative one in the case of a CSEL.  We can always
7351     // materialize these values using CSINC, CSEL and CSINV with wzr/xzr as the
7352     // FVal, respectively.
7353     ConstantSDNode *RHSVal = dyn_cast<ConstantSDNode>(RHS);
7354     if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
7355         !RHSVal->isNullValue() && !RHSVal->isAllOnesValue()) {
7356       AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
7357       // Transform "a == C ? C : x" to "a == C ? a : x" and "a != C ? x : C" to
7358       // "a != C ? x : a" to avoid materializing C.
7359       if (CTVal && CTVal == RHSVal && AArch64CC == AArch64CC::EQ)
7360         TVal = LHS;
7361       else if (CFVal && CFVal == RHSVal && AArch64CC == AArch64CC::NE)
7362         FVal = LHS;
7363     } else if (Opcode == AArch64ISD::CSNEG && RHSVal && RHSVal->isOne()) {
7364       assert (CTVal && CFVal && "Expected constant operands for CSNEG.");
7365       // Use a CSINV to transform "a == C ? 1 : -1" to "a == C ? a : -1" to
7366       // avoid materializing C.
7367       AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
7368       if (CTVal == RHSVal && AArch64CC == AArch64CC::EQ) {
7369         Opcode = AArch64ISD::CSINV;
7370         TVal = LHS;
7371         FVal = DAG.getConstant(0, dl, FVal.getValueType());
7372       }
7373     }
7374 
7375     SDValue CCVal;
7376     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
7377     EVT VT = TVal.getValueType();
7378     return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
7379   }
7380 
7381   // Now we know we're dealing with FP values.
7382   assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
7383          LHS.getValueType() == MVT::f64);
7384   assert(LHS.getValueType() == RHS.getValueType());
7385   EVT VT = TVal.getValueType();
7386   SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
7387 
7388   // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
7389   // clean.  Some of them require two CSELs to implement.
7390   AArch64CC::CondCode CC1, CC2;
7391   changeFPCCToAArch64CC(CC, CC1, CC2);
7392 
7393   if (DAG.getTarget().Options.UnsafeFPMath) {
7394     // Transform "a == 0.0 ? 0.0 : x" to "a == 0.0 ? a : x" and
7395     // "a != 0.0 ? x : 0.0" to "a != 0.0 ? x : a" to avoid materializing 0.0.
7396     ConstantFPSDNode *RHSVal = dyn_cast<ConstantFPSDNode>(RHS);
7397     if (RHSVal && RHSVal->isZero()) {
7398       ConstantFPSDNode *CFVal = dyn_cast<ConstantFPSDNode>(FVal);
7399       ConstantFPSDNode *CTVal = dyn_cast<ConstantFPSDNode>(TVal);
7400 
7401       if ((CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETUEQ) &&
7402           CTVal && CTVal->isZero() && TVal.getValueType() == LHS.getValueType())
7403         TVal = LHS;
7404       else if ((CC == ISD::SETNE || CC == ISD::SETONE || CC == ISD::SETUNE) &&
7405                CFVal && CFVal->isZero() &&
7406                FVal.getValueType() == LHS.getValueType())
7407         FVal = LHS;
7408     }
7409   }
7410 
7411   // Emit first, and possibly only, CSEL.
7412   SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
7413   SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
7414 
7415   // If we need a second CSEL, emit it, using the output of the first as the
7416   // RHS.  We're effectively OR'ing the two CC's together.
7417   if (CC2 != AArch64CC::AL) {
7418     SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
7419     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
7420   }
7421 
7422   // Otherwise, return the output of the first CSEL.
7423   return CS1;
7424 }
7425 
7426 SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op,
7427                                                   SelectionDAG &DAG) const {
7428 
7429   EVT Ty = Op.getValueType();
7430   auto Idx = Op.getConstantOperandAPInt(2);
7431   if (Idx.sge(-1) && Idx.slt(Ty.getVectorMinNumElements()))
7432     return Op;
7433   return SDValue();
7434 }
7435 
7436 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
7437                                               SelectionDAG &DAG) const {
7438   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
7439   SDValue LHS = Op.getOperand(0);
7440   SDValue RHS = Op.getOperand(1);
7441   SDValue TVal = Op.getOperand(2);
7442   SDValue FVal = Op.getOperand(3);
7443   SDLoc DL(Op);
7444   return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
7445 }
7446 
7447 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
7448                                            SelectionDAG &DAG) const {
7449   SDValue CCVal = Op->getOperand(0);
7450   SDValue TVal = Op->getOperand(1);
7451   SDValue FVal = Op->getOperand(2);
7452   SDLoc DL(Op);
7453 
7454   EVT Ty = Op.getValueType();
7455   if (Ty.isScalableVector()) {
7456     SDValue TruncCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, CCVal);
7457     MVT PredVT = MVT::getVectorVT(MVT::i1, Ty.getVectorElementCount());
7458     SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, TruncCC);
7459     return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);
7460   }
7461 
7462   if (useSVEForFixedLengthVectorVT(Ty)) {
7463     // FIXME: Ideally this would be the same as above using i1 types, however
7464     // for the moment we can't deal with fixed i1 vector types properly, so
7465     // instead extend the predicate to a result type sized integer vector.
7466     MVT SplatValVT = MVT::getIntegerVT(Ty.getScalarSizeInBits());
7467     MVT PredVT = MVT::getVectorVT(SplatValVT, Ty.getVectorElementCount());
7468     SDValue SplatVal = DAG.getSExtOrTrunc(CCVal, DL, SplatValVT);
7469     SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, SplatVal);
7470     return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);
7471   }
7472 
7473   // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
7474   // instruction.
7475   if (ISD::isOverflowIntrOpRes(CCVal)) {
7476     // Only lower legal XALUO ops.
7477     if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
7478       return SDValue();
7479 
7480     AArch64CC::CondCode OFCC;
7481     SDValue Value, Overflow;
7482     std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
7483     SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
7484 
7485     return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
7486                        CCVal, Overflow);
7487   }
7488 
7489   // Lower it the same way as we would lower a SELECT_CC node.
7490   ISD::CondCode CC;
7491   SDValue LHS, RHS;
7492   if (CCVal.getOpcode() == ISD::SETCC) {
7493     LHS = CCVal.getOperand(0);
7494     RHS = CCVal.getOperand(1);
7495     CC = cast<CondCodeSDNode>(CCVal.getOperand(2))->get();
7496   } else {
7497     LHS = CCVal;
7498     RHS = DAG.getConstant(0, DL, CCVal.getValueType());
7499     CC = ISD::SETNE;
7500   }
7501   return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
7502 }
7503 
7504 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
7505                                               SelectionDAG &DAG) const {
7506   // Jump table entries as PC relative offsets. No additional tweaking
7507   // is necessary here. Just get the address of the jump table.
7508   JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7509 
7510   if (getTargetMachine().getCodeModel() == CodeModel::Large &&
7511       !Subtarget->isTargetMachO()) {
7512     return getAddrLarge(JT, DAG);
7513   } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) {
7514     return getAddrTiny(JT, DAG);
7515   }
7516   return getAddr(JT, DAG);
7517 }
7518 
7519 SDValue AArch64TargetLowering::LowerBR_JT(SDValue Op,
7520                                           SelectionDAG &DAG) const {
7521   // Jump table entries as PC relative offsets. No additional tweaking
7522   // is necessary here. Just get the address of the jump table.
7523   SDLoc DL(Op);
7524   SDValue JT = Op.getOperand(1);
7525   SDValue Entry = Op.getOperand(2);
7526   int JTI = cast<JumpTableSDNode>(JT.getNode())->getIndex();
7527 
7528   auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
7529   AFI->setJumpTableEntryInfo(JTI, 4, nullptr);
7530 
7531   SDNode *Dest =
7532       DAG.getMachineNode(AArch64::JumpTableDest32, DL, MVT::i64, MVT::i64, JT,
7533                          Entry, DAG.getTargetJumpTable(JTI, MVT::i32));
7534   return DAG.getNode(ISD::BRIND, DL, MVT::Other, Op.getOperand(0),
7535                      SDValue(Dest, 0));
7536 }
7537 
7538 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
7539                                                  SelectionDAG &DAG) const {
7540   ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7541 
7542   if (getTargetMachine().getCodeModel() == CodeModel::Large) {
7543     // Use the GOT for the large code model on iOS.
7544     if (Subtarget->isTargetMachO()) {
7545       return getGOT(CP, DAG);
7546     }
7547     return getAddrLarge(CP, DAG);
7548   } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) {
7549     return getAddrTiny(CP, DAG);
7550   } else {
7551     return getAddr(CP, DAG);
7552   }
7553 }
7554 
7555 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
7556                                                SelectionDAG &DAG) const {
7557   BlockAddressSDNode *BA = cast<BlockAddressSDNode>(Op);
7558   if (getTargetMachine().getCodeModel() == CodeModel::Large &&
7559       !Subtarget->isTargetMachO()) {
7560     return getAddrLarge(BA, DAG);
7561   } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) {
7562     return getAddrTiny(BA, DAG);
7563   }
7564   return getAddr(BA, DAG);
7565 }
7566 
7567 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
7568                                                  SelectionDAG &DAG) const {
7569   AArch64FunctionInfo *FuncInfo =
7570       DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
7571 
7572   SDLoc DL(Op);
7573   SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
7574                                  getPointerTy(DAG.getDataLayout()));
7575   FR = DAG.getZExtOrTrunc(FR, DL, getPointerMemTy(DAG.getDataLayout()));
7576   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7577   return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7578                       MachinePointerInfo(SV));
7579 }
7580 
7581 SDValue AArch64TargetLowering::LowerWin64_VASTART(SDValue Op,
7582                                                   SelectionDAG &DAG) const {
7583   AArch64FunctionInfo *FuncInfo =
7584       DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
7585 
7586   SDLoc DL(Op);
7587   SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsGPRSize() > 0
7588                                      ? FuncInfo->getVarArgsGPRIndex()
7589                                      : FuncInfo->getVarArgsStackIndex(),
7590                                  getPointerTy(DAG.getDataLayout()));
7591   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7592   return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7593                       MachinePointerInfo(SV));
7594 }
7595 
7596 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
7597                                                   SelectionDAG &DAG) const {
7598   // The layout of the va_list struct is specified in the AArch64 Procedure Call
7599   // Standard, section B.3.
7600   MachineFunction &MF = DAG.getMachineFunction();
7601   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
7602   unsigned PtrSize = Subtarget->isTargetILP32() ? 4 : 8;
7603   auto PtrMemVT = getPointerMemTy(DAG.getDataLayout());
7604   auto PtrVT = getPointerTy(DAG.getDataLayout());
7605   SDLoc DL(Op);
7606 
7607   SDValue Chain = Op.getOperand(0);
7608   SDValue VAList = Op.getOperand(1);
7609   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7610   SmallVector<SDValue, 4> MemOps;
7611 
7612   // void *__stack at offset 0
7613   unsigned Offset = 0;
7614   SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
7615   Stack = DAG.getZExtOrTrunc(Stack, DL, PtrMemVT);
7616   MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
7617                                 MachinePointerInfo(SV), Align(PtrSize)));
7618 
7619   // void *__gr_top at offset 8 (4 on ILP32)
7620   Offset += PtrSize;
7621   int GPRSize = FuncInfo->getVarArgsGPRSize();
7622   if (GPRSize > 0) {
7623     SDValue GRTop, GRTopAddr;
7624 
7625     GRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
7626                             DAG.getConstant(Offset, DL, PtrVT));
7627 
7628     GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
7629     GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
7630                         DAG.getConstant(GPRSize, DL, PtrVT));
7631     GRTop = DAG.getZExtOrTrunc(GRTop, DL, PtrMemVT);
7632 
7633     MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
7634                                   MachinePointerInfo(SV, Offset),
7635                                   Align(PtrSize)));
7636   }
7637 
7638   // void *__vr_top at offset 16 (8 on ILP32)
7639   Offset += PtrSize;
7640   int FPRSize = FuncInfo->getVarArgsFPRSize();
7641   if (FPRSize > 0) {
7642     SDValue VRTop, VRTopAddr;
7643     VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
7644                             DAG.getConstant(Offset, DL, PtrVT));
7645 
7646     VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
7647     VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
7648                         DAG.getConstant(FPRSize, DL, PtrVT));
7649     VRTop = DAG.getZExtOrTrunc(VRTop, DL, PtrMemVT);
7650 
7651     MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
7652                                   MachinePointerInfo(SV, Offset),
7653                                   Align(PtrSize)));
7654   }
7655 
7656   // int __gr_offs at offset 24 (12 on ILP32)
7657   Offset += PtrSize;
7658   SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
7659                                    DAG.getConstant(Offset, DL, PtrVT));
7660   MemOps.push_back(
7661       DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, DL, MVT::i32),
7662                    GROffsAddr, MachinePointerInfo(SV, Offset), Align(4)));
7663 
7664   // int __vr_offs at offset 28 (16 on ILP32)
7665   Offset += 4;
7666   SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
7667                                    DAG.getConstant(Offset, DL, PtrVT));
7668   MemOps.push_back(
7669       DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, DL, MVT::i32),
7670                    VROffsAddr, MachinePointerInfo(SV, Offset), Align(4)));
7671 
7672   return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
7673 }
7674 
7675 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
7676                                             SelectionDAG &DAG) const {
7677   MachineFunction &MF = DAG.getMachineFunction();
7678 
7679   if (Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv()))
7680     return LowerWin64_VASTART(Op, DAG);
7681   else if (Subtarget->isTargetDarwin())
7682     return LowerDarwin_VASTART(Op, DAG);
7683   else
7684     return LowerAAPCS_VASTART(Op, DAG);
7685 }
7686 
7687 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
7688                                            SelectionDAG &DAG) const {
7689   // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
7690   // pointer.
7691   SDLoc DL(Op);
7692   unsigned PtrSize = Subtarget->isTargetILP32() ? 4 : 8;
7693   unsigned VaListSize =
7694       (Subtarget->isTargetDarwin() || Subtarget->isTargetWindows())
7695           ? PtrSize
7696           : Subtarget->isTargetILP32() ? 20 : 32;
7697   const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7698   const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7699 
7700   return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1), Op.getOperand(2),
7701                        DAG.getConstant(VaListSize, DL, MVT::i32),
7702                        Align(PtrSize), false, false, false,
7703                        MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
7704 }
7705 
7706 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7707   assert(Subtarget->isTargetDarwin() &&
7708          "automatic va_arg instruction only works on Darwin");
7709 
7710   const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7711   EVT VT = Op.getValueType();
7712   SDLoc DL(Op);
7713   SDValue Chain = Op.getOperand(0);
7714   SDValue Addr = Op.getOperand(1);
7715   MaybeAlign Align(Op.getConstantOperandVal(3));
7716   unsigned MinSlotSize = Subtarget->isTargetILP32() ? 4 : 8;
7717   auto PtrVT = getPointerTy(DAG.getDataLayout());
7718   auto PtrMemVT = getPointerMemTy(DAG.getDataLayout());
7719   SDValue VAList =
7720       DAG.getLoad(PtrMemVT, DL, Chain, Addr, MachinePointerInfo(V));
7721   Chain = VAList.getValue(1);
7722   VAList = DAG.getZExtOrTrunc(VAList, DL, PtrVT);
7723 
7724   if (VT.isScalableVector())
7725     report_fatal_error("Passing SVE types to variadic functions is "
7726                        "currently not supported");
7727 
7728   if (Align && *Align > MinSlotSize) {
7729     VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
7730                          DAG.getConstant(Align->value() - 1, DL, PtrVT));
7731     VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
7732                          DAG.getConstant(-(int64_t)Align->value(), DL, PtrVT));
7733   }
7734 
7735   Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7736   unsigned ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
7737 
7738   // Scalar integer and FP values smaller than 64 bits are implicitly extended
7739   // up to 64 bits.  At the very least, we have to increase the striding of the
7740   // vaargs list to match this, and for FP values we need to introduce
7741   // FP_ROUND nodes as well.
7742   if (VT.isInteger() && !VT.isVector())
7743     ArgSize = std::max(ArgSize, MinSlotSize);
7744   bool NeedFPTrunc = false;
7745   if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
7746     ArgSize = 8;
7747     NeedFPTrunc = true;
7748   }
7749 
7750   // Increment the pointer, VAList, to the next vaarg
7751   SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
7752                                DAG.getConstant(ArgSize, DL, PtrVT));
7753   VANext = DAG.getZExtOrTrunc(VANext, DL, PtrMemVT);
7754 
7755   // Store the incremented VAList to the legalized pointer
7756   SDValue APStore =
7757       DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V));
7758 
7759   // Load the actual argument out of the pointer VAList
7760   if (NeedFPTrunc) {
7761     // Load the value as an f64.
7762     SDValue WideFP =
7763         DAG.getLoad(MVT::f64, DL, APStore, VAList, MachinePointerInfo());
7764     // Round the value down to an f32.
7765     SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
7766                                    DAG.getIntPtrConstant(1, DL));
7767     SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
7768     // Merge the rounded value with the chain output of the load.
7769     return DAG.getMergeValues(Ops, DL);
7770   }
7771 
7772   return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo());
7773 }
7774 
7775 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
7776                                               SelectionDAG &DAG) const {
7777   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
7778   MFI.setFrameAddressIsTaken(true);
7779 
7780   EVT VT = Op.getValueType();
7781   SDLoc DL(Op);
7782   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7783   SDValue FrameAddr =
7784       DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, MVT::i64);
7785   while (Depth--)
7786     FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
7787                             MachinePointerInfo());
7788 
7789   if (Subtarget->isTargetILP32())
7790     FrameAddr = DAG.getNode(ISD::AssertZext, DL, MVT::i64, FrameAddr,
7791                             DAG.getValueType(VT));
7792 
7793   return FrameAddr;
7794 }
7795 
7796 SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,
7797                                               SelectionDAG &DAG) const {
7798   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
7799 
7800   EVT VT = getPointerTy(DAG.getDataLayout());
7801   SDLoc DL(Op);
7802   int FI = MFI.CreateFixedObject(4, 0, false);
7803   return DAG.getFrameIndex(FI, VT);
7804 }
7805 
7806 #define GET_REGISTER_MATCHER
7807 #include "AArch64GenAsmMatcher.inc"
7808 
7809 // FIXME? Maybe this could be a TableGen attribute on some registers and
7810 // this table could be generated automatically from RegInfo.
7811 Register AArch64TargetLowering::
7812 getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const {
7813   Register Reg = MatchRegisterName(RegName);
7814   if (AArch64::X1 <= Reg && Reg <= AArch64::X28) {
7815     const MCRegisterInfo *MRI = Subtarget->getRegisterInfo();
7816     unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false);
7817     if (!Subtarget->isXRegisterReserved(DwarfRegNum))
7818       Reg = 0;
7819   }
7820   if (Reg)
7821     return Reg;
7822   report_fatal_error(Twine("Invalid register name \""
7823                               + StringRef(RegName)  + "\"."));
7824 }
7825 
7826 SDValue AArch64TargetLowering::LowerADDROFRETURNADDR(SDValue Op,
7827                                                      SelectionDAG &DAG) const {
7828   DAG.getMachineFunction().getFrameInfo().setFrameAddressIsTaken(true);
7829 
7830   EVT VT = Op.getValueType();
7831   SDLoc DL(Op);
7832 
7833   SDValue FrameAddr =
7834       DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
7835   SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
7836 
7837   return DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset);
7838 }
7839 
7840 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
7841                                                SelectionDAG &DAG) const {
7842   MachineFunction &MF = DAG.getMachineFunction();
7843   MachineFrameInfo &MFI = MF.getFrameInfo();
7844   MFI.setReturnAddressIsTaken(true);
7845 
7846   EVT VT = Op.getValueType();
7847   SDLoc DL(Op);
7848   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7849   SDValue ReturnAddress;
7850   if (Depth) {
7851     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7852     SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
7853     ReturnAddress = DAG.getLoad(
7854         VT, DL, DAG.getEntryNode(),
7855         DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), MachinePointerInfo());
7856   } else {
7857     // Return LR, which contains the return address. Mark it an implicit
7858     // live-in.
7859     unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
7860     ReturnAddress = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
7861   }
7862 
7863   // The XPACLRI instruction assembles to a hint-space instruction before
7864   // Armv8.3-A therefore this instruction can be safely used for any pre
7865   // Armv8.3-A architectures. On Armv8.3-A and onwards XPACI is available so use
7866   // that instead.
7867   SDNode *St;
7868   if (Subtarget->hasPAuth()) {
7869     St = DAG.getMachineNode(AArch64::XPACI, DL, VT, ReturnAddress);
7870   } else {
7871     // XPACLRI operates on LR therefore we must move the operand accordingly.
7872     SDValue Chain =
7873         DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::LR, ReturnAddress);
7874     St = DAG.getMachineNode(AArch64::XPACLRI, DL, VT, Chain);
7875   }
7876   return SDValue(St, 0);
7877 }
7878 
7879 /// LowerShiftParts - Lower SHL_PARTS/SRA_PARTS/SRL_PARTS, which returns two
7880 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
7881 SDValue AArch64TargetLowering::LowerShiftParts(SDValue Op,
7882                                                SelectionDAG &DAG) const {
7883   SDValue Lo, Hi;
7884   expandShiftParts(Op.getNode(), Lo, Hi, DAG);
7885   return DAG.getMergeValues({Lo, Hi}, SDLoc(Op));
7886 }
7887 
7888 bool AArch64TargetLowering::isOffsetFoldingLegal(
7889     const GlobalAddressSDNode *GA) const {
7890   // Offsets are folded in the DAG combine rather than here so that we can
7891   // intelligently choose an offset based on the uses.
7892   return false;
7893 }
7894 
7895 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
7896                                          bool OptForSize) const {
7897   bool IsLegal = false;
7898   // We can materialize #0.0 as fmov $Rd, XZR for 64-bit, 32-bit cases, and
7899   // 16-bit case when target has full fp16 support.
7900   // FIXME: We should be able to handle f128 as well with a clever lowering.
7901   const APInt ImmInt = Imm.bitcastToAPInt();
7902   if (VT == MVT::f64)
7903     IsLegal = AArch64_AM::getFP64Imm(ImmInt) != -1 || Imm.isPosZero();
7904   else if (VT == MVT::f32)
7905     IsLegal = AArch64_AM::getFP32Imm(ImmInt) != -1 || Imm.isPosZero();
7906   else if (VT == MVT::f16 && Subtarget->hasFullFP16())
7907     IsLegal = AArch64_AM::getFP16Imm(ImmInt) != -1 || Imm.isPosZero();
7908   // TODO: fmov h0, w0 is also legal, however on't have an isel pattern to
7909   //       generate that fmov.
7910 
7911   // If we can not materialize in immediate field for fmov, check if the
7912   // value can be encoded as the immediate operand of a logical instruction.
7913   // The immediate value will be created with either MOVZ, MOVN, or ORR.
7914   if (!IsLegal && (VT == MVT::f64 || VT == MVT::f32)) {
7915     // The cost is actually exactly the same for mov+fmov vs. adrp+ldr;
7916     // however the mov+fmov sequence is always better because of the reduced
7917     // cache pressure. The timings are still the same if you consider
7918     // movw+movk+fmov vs. adrp+ldr (it's one instruction longer, but the
7919     // movw+movk is fused). So we limit up to 2 instrdduction at most.
7920     SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
7921     AArch64_IMM::expandMOVImm(ImmInt.getZExtValue(), VT.getSizeInBits(),
7922 			      Insn);
7923     unsigned Limit = (OptForSize ? 1 : (Subtarget->hasFuseLiterals() ? 5 : 2));
7924     IsLegal = Insn.size() <= Limit;
7925   }
7926 
7927   LLVM_DEBUG(dbgs() << (IsLegal ? "Legal " : "Illegal ") << VT.getEVTString()
7928                     << " imm value: "; Imm.dump(););
7929   return IsLegal;
7930 }
7931 
7932 //===----------------------------------------------------------------------===//
7933 //                          AArch64 Optimization Hooks
7934 //===----------------------------------------------------------------------===//
7935 
7936 static SDValue getEstimate(const AArch64Subtarget *ST, unsigned Opcode,
7937                            SDValue Operand, SelectionDAG &DAG,
7938                            int &ExtraSteps) {
7939   EVT VT = Operand.getValueType();
7940   if (ST->hasNEON() &&
7941       (VT == MVT::f64 || VT == MVT::v1f64 || VT == MVT::v2f64 ||
7942        VT == MVT::f32 || VT == MVT::v1f32 ||
7943        VT == MVT::v2f32 || VT == MVT::v4f32)) {
7944     if (ExtraSteps == TargetLoweringBase::ReciprocalEstimate::Unspecified)
7945       // For the reciprocal estimates, convergence is quadratic, so the number
7946       // of digits is doubled after each iteration.  In ARMv8, the accuracy of
7947       // the initial estimate is 2^-8.  Thus the number of extra steps to refine
7948       // the result for float (23 mantissa bits) is 2 and for double (52
7949       // mantissa bits) is 3.
7950       ExtraSteps = VT.getScalarType() == MVT::f64 ? 3 : 2;
7951 
7952     return DAG.getNode(Opcode, SDLoc(Operand), VT, Operand);
7953   }
7954 
7955   return SDValue();
7956 }
7957 
7958 SDValue
7959 AArch64TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG,
7960                                         const DenormalMode &Mode) const {
7961   SDLoc DL(Op);
7962   EVT VT = Op.getValueType();
7963   EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
7964   SDValue FPZero = DAG.getConstantFP(0.0, DL, VT);
7965   return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ);
7966 }
7967 
7968 SDValue
7969 AArch64TargetLowering::getSqrtResultForDenormInput(SDValue Op,
7970                                                    SelectionDAG &DAG) const {
7971   return Op;
7972 }
7973 
7974 SDValue AArch64TargetLowering::getSqrtEstimate(SDValue Operand,
7975                                                SelectionDAG &DAG, int Enabled,
7976                                                int &ExtraSteps,
7977                                                bool &UseOneConst,
7978                                                bool Reciprocal) const {
7979   if (Enabled == ReciprocalEstimate::Enabled ||
7980       (Enabled == ReciprocalEstimate::Unspecified && Subtarget->useRSqrt()))
7981     if (SDValue Estimate = getEstimate(Subtarget, AArch64ISD::FRSQRTE, Operand,
7982                                        DAG, ExtraSteps)) {
7983       SDLoc DL(Operand);
7984       EVT VT = Operand.getValueType();
7985 
7986       SDNodeFlags Flags;
7987       Flags.setAllowReassociation(true);
7988 
7989       // Newton reciprocal square root iteration: E * 0.5 * (3 - X * E^2)
7990       // AArch64 reciprocal square root iteration instruction: 0.5 * (3 - M * N)
7991       for (int i = ExtraSteps; i > 0; --i) {
7992         SDValue Step = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Estimate,
7993                                    Flags);
7994         Step = DAG.getNode(AArch64ISD::FRSQRTS, DL, VT, Operand, Step, Flags);
7995         Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, Flags);
7996       }
7997       if (!Reciprocal)
7998         Estimate = DAG.getNode(ISD::FMUL, DL, VT, Operand, Estimate, Flags);
7999 
8000       ExtraSteps = 0;
8001       return Estimate;
8002     }
8003 
8004   return SDValue();
8005 }
8006 
8007 SDValue AArch64TargetLowering::getRecipEstimate(SDValue Operand,
8008                                                 SelectionDAG &DAG, int Enabled,
8009                                                 int &ExtraSteps) const {
8010   if (Enabled == ReciprocalEstimate::Enabled)
8011     if (SDValue Estimate = getEstimate(Subtarget, AArch64ISD::FRECPE, Operand,
8012                                        DAG, ExtraSteps)) {
8013       SDLoc DL(Operand);
8014       EVT VT = Operand.getValueType();
8015 
8016       SDNodeFlags Flags;
8017       Flags.setAllowReassociation(true);
8018 
8019       // Newton reciprocal iteration: E * (2 - X * E)
8020       // AArch64 reciprocal iteration instruction: (2 - M * N)
8021       for (int i = ExtraSteps; i > 0; --i) {
8022         SDValue Step = DAG.getNode(AArch64ISD::FRECPS, DL, VT, Operand,
8023                                    Estimate, Flags);
8024         Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, Flags);
8025       }
8026 
8027       ExtraSteps = 0;
8028       return Estimate;
8029     }
8030 
8031   return SDValue();
8032 }
8033 
8034 //===----------------------------------------------------------------------===//
8035 //                          AArch64 Inline Assembly Support
8036 //===----------------------------------------------------------------------===//
8037 
8038 // Table of Constraints
8039 // TODO: This is the current set of constraints supported by ARM for the
8040 // compiler, not all of them may make sense.
8041 //
8042 // r - A general register
8043 // w - An FP/SIMD register of some size in the range v0-v31
8044 // x - An FP/SIMD register of some size in the range v0-v15
8045 // I - Constant that can be used with an ADD instruction
8046 // J - Constant that can be used with a SUB instruction
8047 // K - Constant that can be used with a 32-bit logical instruction
8048 // L - Constant that can be used with a 64-bit logical instruction
8049 // M - Constant that can be used as a 32-bit MOV immediate
8050 // N - Constant that can be used as a 64-bit MOV immediate
8051 // Q - A memory reference with base register and no offset
8052 // S - A symbolic address
8053 // Y - Floating point constant zero
8054 // Z - Integer constant zero
8055 //
8056 //   Note that general register operands will be output using their 64-bit x
8057 // register name, whatever the size of the variable, unless the asm operand
8058 // is prefixed by the %w modifier. Floating-point and SIMD register operands
8059 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
8060 // %q modifier.
8061 const char *AArch64TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
8062   // At this point, we have to lower this constraint to something else, so we
8063   // lower it to an "r" or "w". However, by doing this we will force the result
8064   // to be in register, while the X constraint is much more permissive.
8065   //
8066   // Although we are correct (we are free to emit anything, without
8067   // constraints), we might break use cases that would expect us to be more
8068   // efficient and emit something else.
8069   if (!Subtarget->hasFPARMv8())
8070     return "r";
8071 
8072   if (ConstraintVT.isFloatingPoint())
8073     return "w";
8074 
8075   if (ConstraintVT.isVector() &&
8076      (ConstraintVT.getSizeInBits() == 64 ||
8077       ConstraintVT.getSizeInBits() == 128))
8078     return "w";
8079 
8080   return "r";
8081 }
8082 
8083 enum PredicateConstraint {
8084   Upl,
8085   Upa,
8086   Invalid
8087 };
8088 
8089 static PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
8090   PredicateConstraint P = PredicateConstraint::Invalid;
8091   if (Constraint == "Upa")
8092     P = PredicateConstraint::Upa;
8093   if (Constraint == "Upl")
8094     P = PredicateConstraint::Upl;
8095   return P;
8096 }
8097 
8098 /// getConstraintType - Given a constraint letter, return the type of
8099 /// constraint it is for this target.
8100 AArch64TargetLowering::ConstraintType
8101 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
8102   if (Constraint.size() == 1) {
8103     switch (Constraint[0]) {
8104     default:
8105       break;
8106     case 'x':
8107     case 'w':
8108     case 'y':
8109       return C_RegisterClass;
8110     // An address with a single base register. Due to the way we
8111     // currently handle addresses it is the same as 'r'.
8112     case 'Q':
8113       return C_Memory;
8114     case 'I':
8115     case 'J':
8116     case 'K':
8117     case 'L':
8118     case 'M':
8119     case 'N':
8120     case 'Y':
8121     case 'Z':
8122       return C_Immediate;
8123     case 'z':
8124     case 'S': // A symbolic address
8125       return C_Other;
8126     }
8127   } else if (parsePredicateConstraint(Constraint) !=
8128              PredicateConstraint::Invalid)
8129       return C_RegisterClass;
8130   return TargetLowering::getConstraintType(Constraint);
8131 }
8132 
8133 /// Examine constraint type and operand type and determine a weight value.
8134 /// This object must already have been set up with the operand type
8135 /// and the current alternative constraint selected.
8136 TargetLowering::ConstraintWeight
8137 AArch64TargetLowering::getSingleConstraintMatchWeight(
8138     AsmOperandInfo &info, const char *constraint) const {
8139   ConstraintWeight weight = CW_Invalid;
8140   Value *CallOperandVal = info.CallOperandVal;
8141   // If we don't have a value, we can't do a match,
8142   // but allow it at the lowest weight.
8143   if (!CallOperandVal)
8144     return CW_Default;
8145   Type *type = CallOperandVal->getType();
8146   // Look at the constraint type.
8147   switch (*constraint) {
8148   default:
8149     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8150     break;
8151   case 'x':
8152   case 'w':
8153   case 'y':
8154     if (type->isFloatingPointTy() || type->isVectorTy())
8155       weight = CW_Register;
8156     break;
8157   case 'z':
8158     weight = CW_Constant;
8159     break;
8160   case 'U':
8161     if (parsePredicateConstraint(constraint) != PredicateConstraint::Invalid)
8162       weight = CW_Register;
8163     break;
8164   }
8165   return weight;
8166 }
8167 
8168 std::pair<unsigned, const TargetRegisterClass *>
8169 AArch64TargetLowering::getRegForInlineAsmConstraint(
8170     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
8171   if (Constraint.size() == 1) {
8172     switch (Constraint[0]) {
8173     case 'r':
8174       if (VT.isScalableVector())
8175         return std::make_pair(0U, nullptr);
8176       if (VT.getFixedSizeInBits() == 64)
8177         return std::make_pair(0U, &AArch64::GPR64commonRegClass);
8178       return std::make_pair(0U, &AArch64::GPR32commonRegClass);
8179     case 'w': {
8180       if (!Subtarget->hasFPARMv8())
8181         break;
8182       if (VT.isScalableVector()) {
8183         if (VT.getVectorElementType() != MVT::i1)
8184           return std::make_pair(0U, &AArch64::ZPRRegClass);
8185         return std::make_pair(0U, nullptr);
8186       }
8187       uint64_t VTSize = VT.getFixedSizeInBits();
8188       if (VTSize == 16)
8189         return std::make_pair(0U, &AArch64::FPR16RegClass);
8190       if (VTSize == 32)
8191         return std::make_pair(0U, &AArch64::FPR32RegClass);
8192       if (VTSize == 64)
8193         return std::make_pair(0U, &AArch64::FPR64RegClass);
8194       if (VTSize == 128)
8195         return std::make_pair(0U, &AArch64::FPR128RegClass);
8196       break;
8197     }
8198     // The instructions that this constraint is designed for can
8199     // only take 128-bit registers so just use that regclass.
8200     case 'x':
8201       if (!Subtarget->hasFPARMv8())
8202         break;
8203       if (VT.isScalableVector())
8204         return std::make_pair(0U, &AArch64::ZPR_4bRegClass);
8205       if (VT.getSizeInBits() == 128)
8206         return std::make_pair(0U, &AArch64::FPR128_loRegClass);
8207       break;
8208     case 'y':
8209       if (!Subtarget->hasFPARMv8())
8210         break;
8211       if (VT.isScalableVector())
8212         return std::make_pair(0U, &AArch64::ZPR_3bRegClass);
8213       break;
8214     }
8215   } else {
8216     PredicateConstraint PC = parsePredicateConstraint(Constraint);
8217     if (PC != PredicateConstraint::Invalid) {
8218       if (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1)
8219         return std::make_pair(0U, nullptr);
8220       bool restricted = (PC == PredicateConstraint::Upl);
8221       return restricted ? std::make_pair(0U, &AArch64::PPR_3bRegClass)
8222                         : std::make_pair(0U, &AArch64::PPRRegClass);
8223     }
8224   }
8225   if (StringRef("{cc}").equals_insensitive(Constraint))
8226     return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
8227 
8228   // Use the default implementation in TargetLowering to convert the register
8229   // constraint into a member of a register class.
8230   std::pair<unsigned, const TargetRegisterClass *> Res;
8231   Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
8232 
8233   // Not found as a standard register?
8234   if (!Res.second) {
8235     unsigned Size = Constraint.size();
8236     if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
8237         tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
8238       int RegNo;
8239       bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
8240       if (!Failed && RegNo >= 0 && RegNo <= 31) {
8241         // v0 - v31 are aliases of q0 - q31 or d0 - d31 depending on size.
8242         // By default we'll emit v0-v31 for this unless there's a modifier where
8243         // we'll emit the correct register as well.
8244         if (VT != MVT::Other && VT.getSizeInBits() == 64) {
8245           Res.first = AArch64::FPR64RegClass.getRegister(RegNo);
8246           Res.second = &AArch64::FPR64RegClass;
8247         } else {
8248           Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
8249           Res.second = &AArch64::FPR128RegClass;
8250         }
8251       }
8252     }
8253   }
8254 
8255   if (Res.second && !Subtarget->hasFPARMv8() &&
8256       !AArch64::GPR32allRegClass.hasSubClassEq(Res.second) &&
8257       !AArch64::GPR64allRegClass.hasSubClassEq(Res.second))
8258     return std::make_pair(0U, nullptr);
8259 
8260   return Res;
8261 }
8262 
8263 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8264 /// vector.  If it is invalid, don't add anything to Ops.
8265 void AArch64TargetLowering::LowerAsmOperandForConstraint(
8266     SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
8267     SelectionDAG &DAG) const {
8268   SDValue Result;
8269 
8270   // Currently only support length 1 constraints.
8271   if (Constraint.length() != 1)
8272     return;
8273 
8274   char ConstraintLetter = Constraint[0];
8275   switch (ConstraintLetter) {
8276   default:
8277     break;
8278 
8279   // This set of constraints deal with valid constants for various instructions.
8280   // Validate and return a target constant for them if we can.
8281   case 'z': {
8282     // 'z' maps to xzr or wzr so it needs an input of 0.
8283     if (!isNullConstant(Op))
8284       return;
8285 
8286     if (Op.getValueType() == MVT::i64)
8287       Result = DAG.getRegister(AArch64::XZR, MVT::i64);
8288     else
8289       Result = DAG.getRegister(AArch64::WZR, MVT::i32);
8290     break;
8291   }
8292   case 'S': {
8293     // An absolute symbolic address or label reference.
8294     if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
8295       Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
8296                                           GA->getValueType(0));
8297     } else if (const BlockAddressSDNode *BA =
8298                    dyn_cast<BlockAddressSDNode>(Op)) {
8299       Result =
8300           DAG.getTargetBlockAddress(BA->getBlockAddress(), BA->getValueType(0));
8301     } else
8302       return;
8303     break;
8304   }
8305 
8306   case 'I':
8307   case 'J':
8308   case 'K':
8309   case 'L':
8310   case 'M':
8311   case 'N':
8312     ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
8313     if (!C)
8314       return;
8315 
8316     // Grab the value and do some validation.
8317     uint64_t CVal = C->getZExtValue();
8318     switch (ConstraintLetter) {
8319     // The I constraint applies only to simple ADD or SUB immediate operands:
8320     // i.e. 0 to 4095 with optional shift by 12
8321     // The J constraint applies only to ADD or SUB immediates that would be
8322     // valid when negated, i.e. if [an add pattern] were to be output as a SUB
8323     // instruction [or vice versa], in other words -1 to -4095 with optional
8324     // left shift by 12.
8325     case 'I':
8326       if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
8327         break;
8328       return;
8329     case 'J': {
8330       uint64_t NVal = -C->getSExtValue();
8331       if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
8332         CVal = C->getSExtValue();
8333         break;
8334       }
8335       return;
8336     }
8337     // The K and L constraints apply *only* to logical immediates, including
8338     // what used to be the MOVI alias for ORR (though the MOVI alias has now
8339     // been removed and MOV should be used). So these constraints have to
8340     // distinguish between bit patterns that are valid 32-bit or 64-bit
8341     // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
8342     // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
8343     // versa.
8344     case 'K':
8345       if (AArch64_AM::isLogicalImmediate(CVal, 32))
8346         break;
8347       return;
8348     case 'L':
8349       if (AArch64_AM::isLogicalImmediate(CVal, 64))
8350         break;
8351       return;
8352     // The M and N constraints are a superset of K and L respectively, for use
8353     // with the MOV (immediate) alias. As well as the logical immediates they
8354     // also match 32 or 64-bit immediates that can be loaded either using a
8355     // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
8356     // (M) or 64-bit 0x1234000000000000 (N) etc.
8357     // As a note some of this code is liberally stolen from the asm parser.
8358     case 'M': {
8359       if (!isUInt<32>(CVal))
8360         return;
8361       if (AArch64_AM::isLogicalImmediate(CVal, 32))
8362         break;
8363       if ((CVal & 0xFFFF) == CVal)
8364         break;
8365       if ((CVal & 0xFFFF0000ULL) == CVal)
8366         break;
8367       uint64_t NCVal = ~(uint32_t)CVal;
8368       if ((NCVal & 0xFFFFULL) == NCVal)
8369         break;
8370       if ((NCVal & 0xFFFF0000ULL) == NCVal)
8371         break;
8372       return;
8373     }
8374     case 'N': {
8375       if (AArch64_AM::isLogicalImmediate(CVal, 64))
8376         break;
8377       if ((CVal & 0xFFFFULL) == CVal)
8378         break;
8379       if ((CVal & 0xFFFF0000ULL) == CVal)
8380         break;
8381       if ((CVal & 0xFFFF00000000ULL) == CVal)
8382         break;
8383       if ((CVal & 0xFFFF000000000000ULL) == CVal)
8384         break;
8385       uint64_t NCVal = ~CVal;
8386       if ((NCVal & 0xFFFFULL) == NCVal)
8387         break;
8388       if ((NCVal & 0xFFFF0000ULL) == NCVal)
8389         break;
8390       if ((NCVal & 0xFFFF00000000ULL) == NCVal)
8391         break;
8392       if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
8393         break;
8394       return;
8395     }
8396     default:
8397       return;
8398     }
8399 
8400     // All assembler immediates are 64-bit integers.
8401     Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
8402     break;
8403   }
8404 
8405   if (Result.getNode()) {
8406     Ops.push_back(Result);
8407     return;
8408   }
8409 
8410   return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8411 }
8412 
8413 //===----------------------------------------------------------------------===//
8414 //                     AArch64 Advanced SIMD Support
8415 //===----------------------------------------------------------------------===//
8416 
8417 /// WidenVector - Given a value in the V64 register class, produce the
8418 /// equivalent value in the V128 register class.
8419 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
8420   EVT VT = V64Reg.getValueType();
8421   unsigned NarrowSize = VT.getVectorNumElements();
8422   MVT EltTy = VT.getVectorElementType().getSimpleVT();
8423   MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
8424   SDLoc DL(V64Reg);
8425 
8426   return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
8427                      V64Reg, DAG.getConstant(0, DL, MVT::i64));
8428 }
8429 
8430 /// getExtFactor - Determine the adjustment factor for the position when
8431 /// generating an "extract from vector registers" instruction.
8432 static unsigned getExtFactor(SDValue &V) {
8433   EVT EltType = V.getValueType().getVectorElementType();
8434   return EltType.getSizeInBits() / 8;
8435 }
8436 
8437 /// NarrowVector - Given a value in the V128 register class, produce the
8438 /// equivalent value in the V64 register class.
8439 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
8440   EVT VT = V128Reg.getValueType();
8441   unsigned WideSize = VT.getVectorNumElements();
8442   MVT EltTy = VT.getVectorElementType().getSimpleVT();
8443   MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
8444   SDLoc DL(V128Reg);
8445 
8446   return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
8447 }
8448 
8449 // Gather data to see if the operation can be modelled as a
8450 // shuffle in combination with VEXTs.
8451 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
8452                                                   SelectionDAG &DAG) const {
8453   assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
8454   LLVM_DEBUG(dbgs() << "AArch64TargetLowering::ReconstructShuffle\n");
8455   SDLoc dl(Op);
8456   EVT VT = Op.getValueType();
8457   assert(!VT.isScalableVector() &&
8458          "Scalable vectors cannot be used with ISD::BUILD_VECTOR");
8459   unsigned NumElts = VT.getVectorNumElements();
8460 
8461   struct ShuffleSourceInfo {
8462     SDValue Vec;
8463     unsigned MinElt;
8464     unsigned MaxElt;
8465 
8466     // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
8467     // be compatible with the shuffle we intend to construct. As a result
8468     // ShuffleVec will be some sliding window into the original Vec.
8469     SDValue ShuffleVec;
8470 
8471     // Code should guarantee that element i in Vec starts at element "WindowBase
8472     // + i * WindowScale in ShuffleVec".
8473     int WindowBase;
8474     int WindowScale;
8475 
8476     ShuffleSourceInfo(SDValue Vec)
8477       : Vec(Vec), MinElt(std::numeric_limits<unsigned>::max()), MaxElt(0),
8478           ShuffleVec(Vec), WindowBase(0), WindowScale(1) {}
8479 
8480     bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
8481   };
8482 
8483   // First gather all vectors used as an immediate source for this BUILD_VECTOR
8484   // node.
8485   SmallVector<ShuffleSourceInfo, 2> Sources;
8486   for (unsigned i = 0; i < NumElts; ++i) {
8487     SDValue V = Op.getOperand(i);
8488     if (V.isUndef())
8489       continue;
8490     else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8491              !isa<ConstantSDNode>(V.getOperand(1))) {
8492       LLVM_DEBUG(
8493           dbgs() << "Reshuffle failed: "
8494                     "a shuffle can only come from building a vector from "
8495                     "various elements of other vectors, provided their "
8496                     "indices are constant\n");
8497       return SDValue();
8498     }
8499 
8500     // Add this element source to the list if it's not already there.
8501     SDValue SourceVec = V.getOperand(0);
8502     auto Source = find(Sources, SourceVec);
8503     if (Source == Sources.end())
8504       Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
8505 
8506     // Update the minimum and maximum lane number seen.
8507     unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
8508     Source->MinElt = std::min(Source->MinElt, EltNo);
8509     Source->MaxElt = std::max(Source->MaxElt, EltNo);
8510   }
8511 
8512   if (Sources.size() > 2) {
8513     LLVM_DEBUG(
8514         dbgs() << "Reshuffle failed: currently only do something sane when at "
8515                   "most two source vectors are involved\n");
8516     return SDValue();
8517   }
8518 
8519   // Find out the smallest element size among result and two sources, and use
8520   // it as element size to build the shuffle_vector.
8521   EVT SmallestEltTy = VT.getVectorElementType();
8522   for (auto &Source : Sources) {
8523     EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
8524     if (SrcEltTy.bitsLT(SmallestEltTy)) {
8525       SmallestEltTy = SrcEltTy;
8526     }
8527   }
8528   unsigned ResMultiplier =
8529       VT.getScalarSizeInBits() / SmallestEltTy.getFixedSizeInBits();
8530   uint64_t VTSize = VT.getFixedSizeInBits();
8531   NumElts = VTSize / SmallestEltTy.getFixedSizeInBits();
8532   EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
8533 
8534   // If the source vector is too wide or too narrow, we may nevertheless be able
8535   // to construct a compatible shuffle either by concatenating it with UNDEF or
8536   // extracting a suitable range of elements.
8537   for (auto &Src : Sources) {
8538     EVT SrcVT = Src.ShuffleVec.getValueType();
8539 
8540     uint64_t SrcVTSize = SrcVT.getFixedSizeInBits();
8541     if (SrcVTSize == VTSize)
8542       continue;
8543 
8544     // This stage of the search produces a source with the same element type as
8545     // the original, but with a total width matching the BUILD_VECTOR output.
8546     EVT EltVT = SrcVT.getVectorElementType();
8547     unsigned NumSrcElts = VTSize / EltVT.getFixedSizeInBits();
8548     EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
8549 
8550     if (SrcVTSize < VTSize) {
8551       assert(2 * SrcVTSize == VTSize);
8552       // We can pad out the smaller vector for free, so if it's part of a
8553       // shuffle...
8554       Src.ShuffleVec =
8555           DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
8556                       DAG.getUNDEF(Src.ShuffleVec.getValueType()));
8557       continue;
8558     }
8559 
8560     if (SrcVTSize != 2 * VTSize) {
8561       LLVM_DEBUG(
8562           dbgs() << "Reshuffle failed: result vector too small to extract\n");
8563       return SDValue();
8564     }
8565 
8566     if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
8567       LLVM_DEBUG(
8568           dbgs() << "Reshuffle failed: span too large for a VEXT to cope\n");
8569       return SDValue();
8570     }
8571 
8572     if (Src.MinElt >= NumSrcElts) {
8573       // The extraction can just take the second half
8574       Src.ShuffleVec =
8575           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8576                       DAG.getConstant(NumSrcElts, dl, MVT::i64));
8577       Src.WindowBase = -NumSrcElts;
8578     } else if (Src.MaxElt < NumSrcElts) {
8579       // The extraction can just take the first half
8580       Src.ShuffleVec =
8581           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8582                       DAG.getConstant(0, dl, MVT::i64));
8583     } else {
8584       // An actual VEXT is needed
8585       SDValue VEXTSrc1 =
8586           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8587                       DAG.getConstant(0, dl, MVT::i64));
8588       SDValue VEXTSrc2 =
8589           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8590                       DAG.getConstant(NumSrcElts, dl, MVT::i64));
8591       unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
8592 
8593       if (!SrcVT.is64BitVector()) {
8594         LLVM_DEBUG(
8595           dbgs() << "Reshuffle failed: don't know how to lower AArch64ISD::EXT "
8596                     "for SVE vectors.");
8597         return SDValue();
8598       }
8599 
8600       Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
8601                                    VEXTSrc2,
8602                                    DAG.getConstant(Imm, dl, MVT::i32));
8603       Src.WindowBase = -Src.MinElt;
8604     }
8605   }
8606 
8607   // Another possible incompatibility occurs from the vector element types. We
8608   // can fix this by bitcasting the source vectors to the same type we intend
8609   // for the shuffle.
8610   for (auto &Src : Sources) {
8611     EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
8612     if (SrcEltTy == SmallestEltTy)
8613       continue;
8614     assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
8615     Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
8616     Src.WindowScale =
8617         SrcEltTy.getFixedSizeInBits() / SmallestEltTy.getFixedSizeInBits();
8618     Src.WindowBase *= Src.WindowScale;
8619   }
8620 
8621   // Final sanity check before we try to actually produce a shuffle.
8622   LLVM_DEBUG(for (auto Src
8623                   : Sources)
8624                  assert(Src.ShuffleVec.getValueType() == ShuffleVT););
8625 
8626   // The stars all align, our next step is to produce the mask for the shuffle.
8627   SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
8628   int BitsPerShuffleLane = ShuffleVT.getScalarSizeInBits();
8629   for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
8630     SDValue Entry = Op.getOperand(i);
8631     if (Entry.isUndef())
8632       continue;
8633 
8634     auto Src = find(Sources, Entry.getOperand(0));
8635     int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
8636 
8637     // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
8638     // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
8639     // segment.
8640     EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
8641     int BitsDefined = std::min(OrigEltTy.getScalarSizeInBits(),
8642                                VT.getScalarSizeInBits());
8643     int LanesDefined = BitsDefined / BitsPerShuffleLane;
8644 
8645     // This source is expected to fill ResMultiplier lanes of the final shuffle,
8646     // starting at the appropriate offset.
8647     int *LaneMask = &Mask[i * ResMultiplier];
8648 
8649     int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
8650     ExtractBase += NumElts * (Src - Sources.begin());
8651     for (int j = 0; j < LanesDefined; ++j)
8652       LaneMask[j] = ExtractBase + j;
8653   }
8654 
8655   // Final check before we try to produce nonsense...
8656   if (!isShuffleMaskLegal(Mask, ShuffleVT)) {
8657     LLVM_DEBUG(dbgs() << "Reshuffle failed: illegal shuffle mask\n");
8658     return SDValue();
8659   }
8660 
8661   SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
8662   for (unsigned i = 0; i < Sources.size(); ++i)
8663     ShuffleOps[i] = Sources[i].ShuffleVec;
8664 
8665   SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
8666                                          ShuffleOps[1], Mask);
8667   SDValue V = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
8668 
8669   LLVM_DEBUG(dbgs() << "Reshuffle, creating node: "; Shuffle.dump();
8670              dbgs() << "Reshuffle, creating node: "; V.dump(););
8671 
8672   return V;
8673 }
8674 
8675 // check if an EXT instruction can handle the shuffle mask when the
8676 // vector sources of the shuffle are the same.
8677 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
8678   unsigned NumElts = VT.getVectorNumElements();
8679 
8680   // Assume that the first shuffle index is not UNDEF.  Fail if it is.
8681   if (M[0] < 0)
8682     return false;
8683 
8684   Imm = M[0];
8685 
8686   // If this is a VEXT shuffle, the immediate value is the index of the first
8687   // element.  The other shuffle indices must be the successive elements after
8688   // the first one.
8689   unsigned ExpectedElt = Imm;
8690   for (unsigned i = 1; i < NumElts; ++i) {
8691     // Increment the expected index.  If it wraps around, just follow it
8692     // back to index zero and keep going.
8693     ++ExpectedElt;
8694     if (ExpectedElt == NumElts)
8695       ExpectedElt = 0;
8696 
8697     if (M[i] < 0)
8698       continue; // ignore UNDEF indices
8699     if (ExpectedElt != static_cast<unsigned>(M[i]))
8700       return false;
8701   }
8702 
8703   return true;
8704 }
8705 
8706 /// Check if a vector shuffle corresponds to a DUP instructions with a larger
8707 /// element width than the vector lane type. If that is the case the function
8708 /// returns true and writes the value of the DUP instruction lane operand into
8709 /// DupLaneOp
8710 static bool isWideDUPMask(ArrayRef<int> M, EVT VT, unsigned BlockSize,
8711                           unsigned &DupLaneOp) {
8712   assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
8713          "Only possible block sizes for wide DUP are: 16, 32, 64");
8714 
8715   if (BlockSize <= VT.getScalarSizeInBits())
8716     return false;
8717   if (BlockSize % VT.getScalarSizeInBits() != 0)
8718     return false;
8719   if (VT.getSizeInBits() % BlockSize != 0)
8720     return false;
8721 
8722   size_t SingleVecNumElements = VT.getVectorNumElements();
8723   size_t NumEltsPerBlock = BlockSize / VT.getScalarSizeInBits();
8724   size_t NumBlocks = VT.getSizeInBits() / BlockSize;
8725 
8726   // We are looking for masks like
8727   // [0, 1, 0, 1] or [2, 3, 2, 3] or [4, 5, 6, 7, 4, 5, 6, 7] where any element
8728   // might be replaced by 'undefined'. BlockIndices will eventually contain
8729   // lane indices of the duplicated block (i.e. [0, 1], [2, 3] and [4, 5, 6, 7]
8730   // for the above examples)
8731   SmallVector<int, 8> BlockElts(NumEltsPerBlock, -1);
8732   for (size_t BlockIndex = 0; BlockIndex < NumBlocks; BlockIndex++)
8733     for (size_t I = 0; I < NumEltsPerBlock; I++) {
8734       int Elt = M[BlockIndex * NumEltsPerBlock + I];
8735       if (Elt < 0)
8736         continue;
8737       // For now we don't support shuffles that use the second operand
8738       if ((unsigned)Elt >= SingleVecNumElements)
8739         return false;
8740       if (BlockElts[I] < 0)
8741         BlockElts[I] = Elt;
8742       else if (BlockElts[I] != Elt)
8743         return false;
8744     }
8745 
8746   // We found a candidate block (possibly with some undefs). It must be a
8747   // sequence of consecutive integers starting with a value divisible by
8748   // NumEltsPerBlock with some values possibly replaced by undef-s.
8749 
8750   // Find first non-undef element
8751   auto FirstRealEltIter = find_if(BlockElts, [](int Elt) { return Elt >= 0; });
8752   assert(FirstRealEltIter != BlockElts.end() &&
8753          "Shuffle with all-undefs must have been caught by previous cases, "
8754          "e.g. isSplat()");
8755   if (FirstRealEltIter == BlockElts.end()) {
8756     DupLaneOp = 0;
8757     return true;
8758   }
8759 
8760   // Index of FirstRealElt in BlockElts
8761   size_t FirstRealIndex = FirstRealEltIter - BlockElts.begin();
8762 
8763   if ((unsigned)*FirstRealEltIter < FirstRealIndex)
8764     return false;
8765   // BlockElts[0] must have the following value if it isn't undef:
8766   size_t Elt0 = *FirstRealEltIter - FirstRealIndex;
8767 
8768   // Check the first element
8769   if (Elt0 % NumEltsPerBlock != 0)
8770     return false;
8771   // Check that the sequence indeed consists of consecutive integers (modulo
8772   // undefs)
8773   for (size_t I = 0; I < NumEltsPerBlock; I++)
8774     if (BlockElts[I] >= 0 && (unsigned)BlockElts[I] != Elt0 + I)
8775       return false;
8776 
8777   DupLaneOp = Elt0 / NumEltsPerBlock;
8778   return true;
8779 }
8780 
8781 // check if an EXT instruction can handle the shuffle mask when the
8782 // vector sources of the shuffle are different.
8783 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
8784                       unsigned &Imm) {
8785   // Look for the first non-undef element.
8786   const int *FirstRealElt = find_if(M, [](int Elt) { return Elt >= 0; });
8787 
8788   // Benefit form APInt to handle overflow when calculating expected element.
8789   unsigned NumElts = VT.getVectorNumElements();
8790   unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
8791   APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
8792   // The following shuffle indices must be the successive elements after the
8793   // first real element.
8794   const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
8795       [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
8796   if (FirstWrongElt != M.end())
8797     return false;
8798 
8799   // The index of an EXT is the first element if it is not UNDEF.
8800   // Watch out for the beginning UNDEFs. The EXT index should be the expected
8801   // value of the first element.  E.g.
8802   // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
8803   // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
8804   // ExpectedElt is the last mask index plus 1.
8805   Imm = ExpectedElt.getZExtValue();
8806 
8807   // There are two difference cases requiring to reverse input vectors.
8808   // For example, for vector <4 x i32> we have the following cases,
8809   // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
8810   // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
8811   // For both cases, we finally use mask <5, 6, 7, 0>, which requires
8812   // to reverse two input vectors.
8813   if (Imm < NumElts)
8814     ReverseEXT = true;
8815   else
8816     Imm -= NumElts;
8817 
8818   return true;
8819 }
8820 
8821 /// isREVMask - Check if a vector shuffle corresponds to a REV
8822 /// instruction with the specified blocksize.  (The order of the elements
8823 /// within each block of the vector is reversed.)
8824 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
8825   assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
8826          "Only possible block sizes for REV are: 16, 32, 64");
8827 
8828   unsigned EltSz = VT.getScalarSizeInBits();
8829   if (EltSz == 64)
8830     return false;
8831 
8832   unsigned NumElts = VT.getVectorNumElements();
8833   unsigned BlockElts = M[0] + 1;
8834   // If the first shuffle index is UNDEF, be optimistic.
8835   if (M[0] < 0)
8836     BlockElts = BlockSize / EltSz;
8837 
8838   if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
8839     return false;
8840 
8841   for (unsigned i = 0; i < NumElts; ++i) {
8842     if (M[i] < 0)
8843       continue; // ignore UNDEF indices
8844     if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
8845       return false;
8846   }
8847 
8848   return true;
8849 }
8850 
8851 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
8852   unsigned NumElts = VT.getVectorNumElements();
8853   if (NumElts % 2 != 0)
8854     return false;
8855   WhichResult = (M[0] == 0 ? 0 : 1);
8856   unsigned Idx = WhichResult * NumElts / 2;
8857   for (unsigned i = 0; i != NumElts; i += 2) {
8858     if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
8859         (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
8860       return false;
8861     Idx += 1;
8862   }
8863 
8864   return true;
8865 }
8866 
8867 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
8868   unsigned NumElts = VT.getVectorNumElements();
8869   WhichResult = (M[0] == 0 ? 0 : 1);
8870   for (unsigned i = 0; i != NumElts; ++i) {
8871     if (M[i] < 0)
8872       continue; // ignore UNDEF indices
8873     if ((unsigned)M[i] != 2 * i + WhichResult)
8874       return false;
8875   }
8876 
8877   return true;
8878 }
8879 
8880 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
8881   unsigned NumElts = VT.getVectorNumElements();
8882   if (NumElts % 2 != 0)
8883     return false;
8884   WhichResult = (M[0] == 0 ? 0 : 1);
8885   for (unsigned i = 0; i < NumElts; i += 2) {
8886     if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
8887         (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
8888       return false;
8889   }
8890   return true;
8891 }
8892 
8893 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
8894 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
8895 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
8896 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
8897   unsigned NumElts = VT.getVectorNumElements();
8898   if (NumElts % 2 != 0)
8899     return false;
8900   WhichResult = (M[0] == 0 ? 0 : 1);
8901   unsigned Idx = WhichResult * NumElts / 2;
8902   for (unsigned i = 0; i != NumElts; i += 2) {
8903     if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
8904         (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
8905       return false;
8906     Idx += 1;
8907   }
8908 
8909   return true;
8910 }
8911 
8912 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
8913 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
8914 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
8915 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
8916   unsigned Half = VT.getVectorNumElements() / 2;
8917   WhichResult = (M[0] == 0 ? 0 : 1);
8918   for (unsigned j = 0; j != 2; ++j) {
8919     unsigned Idx = WhichResult;
8920     for (unsigned i = 0; i != Half; ++i) {
8921       int MIdx = M[i + j * Half];
8922       if (MIdx >= 0 && (unsigned)MIdx != Idx)
8923         return false;
8924       Idx += 2;
8925     }
8926   }
8927 
8928   return true;
8929 }
8930 
8931 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
8932 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
8933 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
8934 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
8935   unsigned NumElts = VT.getVectorNumElements();
8936   if (NumElts % 2 != 0)
8937     return false;
8938   WhichResult = (M[0] == 0 ? 0 : 1);
8939   for (unsigned i = 0; i < NumElts; i += 2) {
8940     if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
8941         (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
8942       return false;
8943   }
8944   return true;
8945 }
8946 
8947 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
8948                       bool &DstIsLeft, int &Anomaly) {
8949   if (M.size() != static_cast<size_t>(NumInputElements))
8950     return false;
8951 
8952   int NumLHSMatch = 0, NumRHSMatch = 0;
8953   int LastLHSMismatch = -1, LastRHSMismatch = -1;
8954 
8955   for (int i = 0; i < NumInputElements; ++i) {
8956     if (M[i] == -1) {
8957       ++NumLHSMatch;
8958       ++NumRHSMatch;
8959       continue;
8960     }
8961 
8962     if (M[i] == i)
8963       ++NumLHSMatch;
8964     else
8965       LastLHSMismatch = i;
8966 
8967     if (M[i] == i + NumInputElements)
8968       ++NumRHSMatch;
8969     else
8970       LastRHSMismatch = i;
8971   }
8972 
8973   if (NumLHSMatch == NumInputElements - 1) {
8974     DstIsLeft = true;
8975     Anomaly = LastLHSMismatch;
8976     return true;
8977   } else if (NumRHSMatch == NumInputElements - 1) {
8978     DstIsLeft = false;
8979     Anomaly = LastRHSMismatch;
8980     return true;
8981   }
8982 
8983   return false;
8984 }
8985 
8986 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
8987   if (VT.getSizeInBits() != 128)
8988     return false;
8989 
8990   unsigned NumElts = VT.getVectorNumElements();
8991 
8992   for (int I = 0, E = NumElts / 2; I != E; I++) {
8993     if (Mask[I] != I)
8994       return false;
8995   }
8996 
8997   int Offset = NumElts / 2;
8998   for (int I = NumElts / 2, E = NumElts; I != E; I++) {
8999     if (Mask[I] != I + SplitLHS * Offset)
9000       return false;
9001   }
9002 
9003   return true;
9004 }
9005 
9006 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
9007   SDLoc DL(Op);
9008   EVT VT = Op.getValueType();
9009   SDValue V0 = Op.getOperand(0);
9010   SDValue V1 = Op.getOperand(1);
9011   ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
9012 
9013   if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
9014       VT.getVectorElementType() != V1.getValueType().getVectorElementType())
9015     return SDValue();
9016 
9017   bool SplitV0 = V0.getValueSizeInBits() == 128;
9018 
9019   if (!isConcatMask(Mask, VT, SplitV0))
9020     return SDValue();
9021 
9022   EVT CastVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
9023   if (SplitV0) {
9024     V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
9025                      DAG.getConstant(0, DL, MVT::i64));
9026   }
9027   if (V1.getValueSizeInBits() == 128) {
9028     V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
9029                      DAG.getConstant(0, DL, MVT::i64));
9030   }
9031   return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
9032 }
9033 
9034 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
9035 /// the specified operations to build the shuffle.
9036 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
9037                                       SDValue RHS, SelectionDAG &DAG,
9038                                       const SDLoc &dl) {
9039   unsigned OpNum = (PFEntry >> 26) & 0x0F;
9040   unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
9041   unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
9042 
9043   enum {
9044     OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
9045     OP_VREV,
9046     OP_VDUP0,
9047     OP_VDUP1,
9048     OP_VDUP2,
9049     OP_VDUP3,
9050     OP_VEXT1,
9051     OP_VEXT2,
9052     OP_VEXT3,
9053     OP_VUZPL, // VUZP, left result
9054     OP_VUZPR, // VUZP, right result
9055     OP_VZIPL, // VZIP, left result
9056     OP_VZIPR, // VZIP, right result
9057     OP_VTRNL, // VTRN, left result
9058     OP_VTRNR  // VTRN, right result
9059   };
9060 
9061   if (OpNum == OP_COPY) {
9062     if (LHSID == (1 * 9 + 2) * 9 + 3)
9063       return LHS;
9064     assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
9065     return RHS;
9066   }
9067 
9068   SDValue OpLHS, OpRHS;
9069   OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
9070   OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
9071   EVT VT = OpLHS.getValueType();
9072 
9073   switch (OpNum) {
9074   default:
9075     llvm_unreachable("Unknown shuffle opcode!");
9076   case OP_VREV:
9077     // VREV divides the vector in half and swaps within the half.
9078     if (VT.getVectorElementType() == MVT::i32 ||
9079         VT.getVectorElementType() == MVT::f32)
9080       return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
9081     // vrev <4 x i16> -> REV32
9082     if (VT.getVectorElementType() == MVT::i16 ||
9083         VT.getVectorElementType() == MVT::f16 ||
9084         VT.getVectorElementType() == MVT::bf16)
9085       return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
9086     // vrev <4 x i8> -> REV16
9087     assert(VT.getVectorElementType() == MVT::i8);
9088     return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
9089   case OP_VDUP0:
9090   case OP_VDUP1:
9091   case OP_VDUP2:
9092   case OP_VDUP3: {
9093     EVT EltTy = VT.getVectorElementType();
9094     unsigned Opcode;
9095     if (EltTy == MVT::i8)
9096       Opcode = AArch64ISD::DUPLANE8;
9097     else if (EltTy == MVT::i16 || EltTy == MVT::f16 || EltTy == MVT::bf16)
9098       Opcode = AArch64ISD::DUPLANE16;
9099     else if (EltTy == MVT::i32 || EltTy == MVT::f32)
9100       Opcode = AArch64ISD::DUPLANE32;
9101     else if (EltTy == MVT::i64 || EltTy == MVT::f64)
9102       Opcode = AArch64ISD::DUPLANE64;
9103     else
9104       llvm_unreachable("Invalid vector element type?");
9105 
9106     if (VT.getSizeInBits() == 64)
9107       OpLHS = WidenVector(OpLHS, DAG);
9108     SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
9109     return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
9110   }
9111   case OP_VEXT1:
9112   case OP_VEXT2:
9113   case OP_VEXT3: {
9114     unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
9115     return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
9116                        DAG.getConstant(Imm, dl, MVT::i32));
9117   }
9118   case OP_VUZPL:
9119     return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
9120                        OpRHS);
9121   case OP_VUZPR:
9122     return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
9123                        OpRHS);
9124   case OP_VZIPL:
9125     return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
9126                        OpRHS);
9127   case OP_VZIPR:
9128     return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
9129                        OpRHS);
9130   case OP_VTRNL:
9131     return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
9132                        OpRHS);
9133   case OP_VTRNR:
9134     return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
9135                        OpRHS);
9136   }
9137 }
9138 
9139 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
9140                            SelectionDAG &DAG) {
9141   // Check to see if we can use the TBL instruction.
9142   SDValue V1 = Op.getOperand(0);
9143   SDValue V2 = Op.getOperand(1);
9144   SDLoc DL(Op);
9145 
9146   EVT EltVT = Op.getValueType().getVectorElementType();
9147   unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
9148 
9149   SmallVector<SDValue, 8> TBLMask;
9150   for (int Val : ShuffleMask) {
9151     for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
9152       unsigned Offset = Byte + Val * BytesPerElt;
9153       TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
9154     }
9155   }
9156 
9157   MVT IndexVT = MVT::v8i8;
9158   unsigned IndexLen = 8;
9159   if (Op.getValueSizeInBits() == 128) {
9160     IndexVT = MVT::v16i8;
9161     IndexLen = 16;
9162   }
9163 
9164   SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
9165   SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
9166 
9167   SDValue Shuffle;
9168   if (V2.getNode()->isUndef()) {
9169     if (IndexLen == 8)
9170       V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
9171     Shuffle = DAG.getNode(
9172         ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
9173         DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
9174         DAG.getBuildVector(IndexVT, DL,
9175                            makeArrayRef(TBLMask.data(), IndexLen)));
9176   } else {
9177     if (IndexLen == 8) {
9178       V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
9179       Shuffle = DAG.getNode(
9180           ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
9181           DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
9182           DAG.getBuildVector(IndexVT, DL,
9183                              makeArrayRef(TBLMask.data(), IndexLen)));
9184     } else {
9185       // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
9186       // cannot currently represent the register constraints on the input
9187       // table registers.
9188       //  Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
9189       //                   DAG.getBuildVector(IndexVT, DL, &TBLMask[0],
9190       //                   IndexLen));
9191       Shuffle = DAG.getNode(
9192           ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
9193           DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32), V1Cst,
9194           V2Cst, DAG.getBuildVector(IndexVT, DL,
9195                                     makeArrayRef(TBLMask.data(), IndexLen)));
9196     }
9197   }
9198   return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
9199 }
9200 
9201 static unsigned getDUPLANEOp(EVT EltType) {
9202   if (EltType == MVT::i8)
9203     return AArch64ISD::DUPLANE8;
9204   if (EltType == MVT::i16 || EltType == MVT::f16 || EltType == MVT::bf16)
9205     return AArch64ISD::DUPLANE16;
9206   if (EltType == MVT::i32 || EltType == MVT::f32)
9207     return AArch64ISD::DUPLANE32;
9208   if (EltType == MVT::i64 || EltType == MVT::f64)
9209     return AArch64ISD::DUPLANE64;
9210 
9211   llvm_unreachable("Invalid vector element type?");
9212 }
9213 
9214 static SDValue constructDup(SDValue V, int Lane, SDLoc dl, EVT VT,
9215                             unsigned Opcode, SelectionDAG &DAG) {
9216   // Try to eliminate a bitcasted extract subvector before a DUPLANE.
9217   auto getScaledOffsetDup = [](SDValue BitCast, int &LaneC, MVT &CastVT) {
9218     // Match: dup (bitcast (extract_subv X, C)), LaneC
9219     if (BitCast.getOpcode() != ISD::BITCAST ||
9220         BitCast.getOperand(0).getOpcode() != ISD::EXTRACT_SUBVECTOR)
9221       return false;
9222 
9223     // The extract index must align in the destination type. That may not
9224     // happen if the bitcast is from narrow to wide type.
9225     SDValue Extract = BitCast.getOperand(0);
9226     unsigned ExtIdx = Extract.getConstantOperandVal(1);
9227     unsigned SrcEltBitWidth = Extract.getScalarValueSizeInBits();
9228     unsigned ExtIdxInBits = ExtIdx * SrcEltBitWidth;
9229     unsigned CastedEltBitWidth = BitCast.getScalarValueSizeInBits();
9230     if (ExtIdxInBits % CastedEltBitWidth != 0)
9231       return false;
9232 
9233     // Update the lane value by offsetting with the scaled extract index.
9234     LaneC += ExtIdxInBits / CastedEltBitWidth;
9235 
9236     // Determine the casted vector type of the wide vector input.
9237     // dup (bitcast (extract_subv X, C)), LaneC --> dup (bitcast X), LaneC'
9238     // Examples:
9239     // dup (bitcast (extract_subv v2f64 X, 1) to v2f32), 1 --> dup v4f32 X, 3
9240     // dup (bitcast (extract_subv v16i8 X, 8) to v4i16), 1 --> dup v8i16 X, 5
9241     unsigned SrcVecNumElts =
9242         Extract.getOperand(0).getValueSizeInBits() / CastedEltBitWidth;
9243     CastVT = MVT::getVectorVT(BitCast.getSimpleValueType().getScalarType(),
9244                               SrcVecNumElts);
9245     return true;
9246   };
9247   MVT CastVT;
9248   if (getScaledOffsetDup(V, Lane, CastVT)) {
9249     V = DAG.getBitcast(CastVT, V.getOperand(0).getOperand(0));
9250   } else if (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
9251     // The lane is incremented by the index of the extract.
9252     // Example: dup v2f32 (extract v4f32 X, 2), 1 --> dup v4f32 X, 3
9253     Lane += V.getConstantOperandVal(1);
9254     V = V.getOperand(0);
9255   } else if (V.getOpcode() == ISD::CONCAT_VECTORS) {
9256     // The lane is decremented if we are splatting from the 2nd operand.
9257     // Example: dup v4i32 (concat v2i32 X, v2i32 Y), 3 --> dup v4i32 Y, 1
9258     unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
9259     Lane -= Idx * VT.getVectorNumElements() / 2;
9260     V = WidenVector(V.getOperand(Idx), DAG);
9261   } else if (VT.getSizeInBits() == 64) {
9262     // Widen the operand to 128-bit register with undef.
9263     V = WidenVector(V, DAG);
9264   }
9265   return DAG.getNode(Opcode, dl, VT, V, DAG.getConstant(Lane, dl, MVT::i64));
9266 }
9267 
9268 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
9269                                                    SelectionDAG &DAG) const {
9270   SDLoc dl(Op);
9271   EVT VT = Op.getValueType();
9272 
9273   ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
9274 
9275   if (useSVEForFixedLengthVectorVT(VT))
9276     return LowerFixedLengthVECTOR_SHUFFLEToSVE(Op, DAG);
9277 
9278   // Convert shuffles that are directly supported on NEON to target-specific
9279   // DAG nodes, instead of keeping them as shuffles and matching them again
9280   // during code selection.  This is more efficient and avoids the possibility
9281   // of inconsistencies between legalization and selection.
9282   ArrayRef<int> ShuffleMask = SVN->getMask();
9283 
9284   SDValue V1 = Op.getOperand(0);
9285   SDValue V2 = Op.getOperand(1);
9286 
9287   assert(V1.getValueType() == VT && "Unexpected VECTOR_SHUFFLE type!");
9288   assert(ShuffleMask.size() == VT.getVectorNumElements() &&
9289          "Unexpected VECTOR_SHUFFLE mask size!");
9290 
9291   if (SVN->isSplat()) {
9292     int Lane = SVN->getSplatIndex();
9293     // If this is undef splat, generate it via "just" vdup, if possible.
9294     if (Lane == -1)
9295       Lane = 0;
9296 
9297     if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
9298       return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
9299                          V1.getOperand(0));
9300     // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
9301     // constant. If so, we can just reference the lane's definition directly.
9302     if (V1.getOpcode() == ISD::BUILD_VECTOR &&
9303         !isa<ConstantSDNode>(V1.getOperand(Lane)))
9304       return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
9305 
9306     // Otherwise, duplicate from the lane of the input vector.
9307     unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
9308     return constructDup(V1, Lane, dl, VT, Opcode, DAG);
9309   }
9310 
9311   // Check if the mask matches a DUP for a wider element
9312   for (unsigned LaneSize : {64U, 32U, 16U}) {
9313     unsigned Lane = 0;
9314     if (isWideDUPMask(ShuffleMask, VT, LaneSize, Lane)) {
9315       unsigned Opcode = LaneSize == 64 ? AArch64ISD::DUPLANE64
9316                                        : LaneSize == 32 ? AArch64ISD::DUPLANE32
9317                                                         : AArch64ISD::DUPLANE16;
9318       // Cast V1 to an integer vector with required lane size
9319       MVT NewEltTy = MVT::getIntegerVT(LaneSize);
9320       unsigned NewEltCount = VT.getSizeInBits() / LaneSize;
9321       MVT NewVecTy = MVT::getVectorVT(NewEltTy, NewEltCount);
9322       V1 = DAG.getBitcast(NewVecTy, V1);
9323       // Constuct the DUP instruction
9324       V1 = constructDup(V1, Lane, dl, NewVecTy, Opcode, DAG);
9325       // Cast back to the original type
9326       return DAG.getBitcast(VT, V1);
9327     }
9328   }
9329 
9330   if (isREVMask(ShuffleMask, VT, 64))
9331     return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
9332   if (isREVMask(ShuffleMask, VT, 32))
9333     return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
9334   if (isREVMask(ShuffleMask, VT, 16))
9335     return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
9336 
9337   if (((VT.getVectorNumElements() == 8 && VT.getScalarSizeInBits() == 16) ||
9338        (VT.getVectorNumElements() == 16 && VT.getScalarSizeInBits() == 8)) &&
9339       ShuffleVectorInst::isReverseMask(ShuffleMask)) {
9340     SDValue Rev = DAG.getNode(AArch64ISD::REV64, dl, VT, V1);
9341     return DAG.getNode(AArch64ISD::EXT, dl, VT, Rev, Rev,
9342                        DAG.getConstant(8, dl, MVT::i32));
9343   }
9344 
9345   bool ReverseEXT = false;
9346   unsigned Imm;
9347   if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
9348     if (ReverseEXT)
9349       std::swap(V1, V2);
9350     Imm *= getExtFactor(V1);
9351     return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
9352                        DAG.getConstant(Imm, dl, MVT::i32));
9353   } else if (V2->isUndef() && isSingletonEXTMask(ShuffleMask, VT, Imm)) {
9354     Imm *= getExtFactor(V1);
9355     return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
9356                        DAG.getConstant(Imm, dl, MVT::i32));
9357   }
9358 
9359   unsigned WhichResult;
9360   if (isZIPMask(ShuffleMask, VT, WhichResult)) {
9361     unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
9362     return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
9363   }
9364   if (isUZPMask(ShuffleMask, VT, WhichResult)) {
9365     unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
9366     return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
9367   }
9368   if (isTRNMask(ShuffleMask, VT, WhichResult)) {
9369     unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
9370     return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
9371   }
9372 
9373   if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
9374     unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
9375     return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
9376   }
9377   if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
9378     unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
9379     return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
9380   }
9381   if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
9382     unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
9383     return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
9384   }
9385 
9386   if (SDValue Concat = tryFormConcatFromShuffle(Op, DAG))
9387     return Concat;
9388 
9389   bool DstIsLeft;
9390   int Anomaly;
9391   int NumInputElements = V1.getValueType().getVectorNumElements();
9392   if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
9393     SDValue DstVec = DstIsLeft ? V1 : V2;
9394     SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
9395 
9396     SDValue SrcVec = V1;
9397     int SrcLane = ShuffleMask[Anomaly];
9398     if (SrcLane >= NumInputElements) {
9399       SrcVec = V2;
9400       SrcLane -= VT.getVectorNumElements();
9401     }
9402     SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
9403 
9404     EVT ScalarVT = VT.getVectorElementType();
9405 
9406     if (ScalarVT.getFixedSizeInBits() < 32 && ScalarVT.isInteger())
9407       ScalarVT = MVT::i32;
9408 
9409     return DAG.getNode(
9410         ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
9411         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
9412         DstLaneV);
9413   }
9414 
9415   // If the shuffle is not directly supported and it has 4 elements, use
9416   // the PerfectShuffle-generated table to synthesize it from other shuffles.
9417   unsigned NumElts = VT.getVectorNumElements();
9418   if (NumElts == 4) {
9419     unsigned PFIndexes[4];
9420     for (unsigned i = 0; i != 4; ++i) {
9421       if (ShuffleMask[i] < 0)
9422         PFIndexes[i] = 8;
9423       else
9424         PFIndexes[i] = ShuffleMask[i];
9425     }
9426 
9427     // Compute the index in the perfect shuffle table.
9428     unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
9429                             PFIndexes[2] * 9 + PFIndexes[3];
9430     unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
9431     unsigned Cost = (PFEntry >> 30);
9432 
9433     if (Cost <= 4)
9434       return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
9435   }
9436 
9437   return GenerateTBL(Op, ShuffleMask, DAG);
9438 }
9439 
9440 SDValue AArch64TargetLowering::LowerSPLAT_VECTOR(SDValue Op,
9441                                                  SelectionDAG &DAG) const {
9442   SDLoc dl(Op);
9443   EVT VT = Op.getValueType();
9444   EVT ElemVT = VT.getScalarType();
9445   SDValue SplatVal = Op.getOperand(0);
9446 
9447   if (useSVEForFixedLengthVectorVT(VT))
9448     return LowerToScalableOp(Op, DAG);
9449 
9450   // Extend input splat value where needed to fit into a GPR (32b or 64b only)
9451   // FPRs don't have this restriction.
9452   switch (ElemVT.getSimpleVT().SimpleTy) {
9453   case MVT::i1: {
9454     // The only legal i1 vectors are SVE vectors, so we can use SVE-specific
9455     // lowering code.
9456     if (auto *ConstVal = dyn_cast<ConstantSDNode>(SplatVal)) {
9457       if (ConstVal->isOne())
9458         return getPTrue(DAG, dl, VT, AArch64SVEPredPattern::all);
9459       // TODO: Add special case for constant false
9460     }
9461     // The general case of i1.  There isn't any natural way to do this,
9462     // so we use some trickery with whilelo.
9463     SplatVal = DAG.getAnyExtOrTrunc(SplatVal, dl, MVT::i64);
9464     SplatVal = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i64, SplatVal,
9465                            DAG.getValueType(MVT::i1));
9466     SDValue ID = DAG.getTargetConstant(Intrinsic::aarch64_sve_whilelo, dl,
9467                                        MVT::i64);
9468     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, ID,
9469                        DAG.getConstant(0, dl, MVT::i64), SplatVal);
9470   }
9471   case MVT::i8:
9472   case MVT::i16:
9473   case MVT::i32:
9474     SplatVal = DAG.getAnyExtOrTrunc(SplatVal, dl, MVT::i32);
9475     break;
9476   case MVT::i64:
9477     SplatVal = DAG.getAnyExtOrTrunc(SplatVal, dl, MVT::i64);
9478     break;
9479   case MVT::f16:
9480   case MVT::bf16:
9481   case MVT::f32:
9482   case MVT::f64:
9483     // Fine as is
9484     break;
9485   default:
9486     report_fatal_error("Unsupported SPLAT_VECTOR input operand type");
9487   }
9488 
9489   return DAG.getNode(AArch64ISD::DUP, dl, VT, SplatVal);
9490 }
9491 
9492 SDValue AArch64TargetLowering::LowerDUPQLane(SDValue Op,
9493                                              SelectionDAG &DAG) const {
9494   SDLoc DL(Op);
9495 
9496   EVT VT = Op.getValueType();
9497   if (!isTypeLegal(VT) || !VT.isScalableVector())
9498     return SDValue();
9499 
9500   // Current lowering only supports the SVE-ACLE types.
9501   if (VT.getSizeInBits().getKnownMinSize() != AArch64::SVEBitsPerBlock)
9502     return SDValue();
9503 
9504   // The DUPQ operation is indepedent of element type so normalise to i64s.
9505   SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::nxv2i64, Op.getOperand(1));
9506   SDValue Idx128 = Op.getOperand(2);
9507 
9508   // DUPQ can be used when idx is in range.
9509   auto *CIdx = dyn_cast<ConstantSDNode>(Idx128);
9510   if (CIdx && (CIdx->getZExtValue() <= 3)) {
9511     SDValue CI = DAG.getTargetConstant(CIdx->getZExtValue(), DL, MVT::i64);
9512     SDNode *DUPQ =
9513         DAG.getMachineNode(AArch64::DUP_ZZI_Q, DL, MVT::nxv2i64, V, CI);
9514     return DAG.getNode(ISD::BITCAST, DL, VT, SDValue(DUPQ, 0));
9515   }
9516 
9517   // The ACLE says this must produce the same result as:
9518   //   svtbl(data, svadd_x(svptrue_b64(),
9519   //                       svand_x(svptrue_b64(), svindex_u64(0, 1), 1),
9520   //                       index * 2))
9521   SDValue One = DAG.getConstant(1, DL, MVT::i64);
9522   SDValue SplatOne = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::nxv2i64, One);
9523 
9524   // create the vector 0,1,0,1,...
9525   SDValue SV = DAG.getStepVector(DL, MVT::nxv2i64);
9526   SV = DAG.getNode(ISD::AND, DL, MVT::nxv2i64, SV, SplatOne);
9527 
9528   // create the vector idx64,idx64+1,idx64,idx64+1,...
9529   SDValue Idx64 = DAG.getNode(ISD::ADD, DL, MVT::i64, Idx128, Idx128);
9530   SDValue SplatIdx64 = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::nxv2i64, Idx64);
9531   SDValue ShuffleMask = DAG.getNode(ISD::ADD, DL, MVT::nxv2i64, SV, SplatIdx64);
9532 
9533   // create the vector Val[idx64],Val[idx64+1],Val[idx64],Val[idx64+1],...
9534   SDValue TBL = DAG.getNode(AArch64ISD::TBL, DL, MVT::nxv2i64, V, ShuffleMask);
9535   return DAG.getNode(ISD::BITCAST, DL, VT, TBL);
9536 }
9537 
9538 
9539 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
9540                                APInt &UndefBits) {
9541   EVT VT = BVN->getValueType(0);
9542   APInt SplatBits, SplatUndef;
9543   unsigned SplatBitSize;
9544   bool HasAnyUndefs;
9545   if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
9546     unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
9547 
9548     for (unsigned i = 0; i < NumSplats; ++i) {
9549       CnstBits <<= SplatBitSize;
9550       UndefBits <<= SplatBitSize;
9551       CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
9552       UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
9553     }
9554 
9555     return true;
9556   }
9557 
9558   return false;
9559 }
9560 
9561 // Try 64-bit splatted SIMD immediate.
9562 static SDValue tryAdvSIMDModImm64(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
9563                                  const APInt &Bits) {
9564   if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
9565     uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
9566     EVT VT = Op.getValueType();
9567     MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v2i64 : MVT::f64;
9568 
9569     if (AArch64_AM::isAdvSIMDModImmType10(Value)) {
9570       Value = AArch64_AM::encodeAdvSIMDModImmType10(Value);
9571 
9572       SDLoc dl(Op);
9573       SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
9574                                 DAG.getConstant(Value, dl, MVT::i32));
9575       return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
9576     }
9577   }
9578 
9579   return SDValue();
9580 }
9581 
9582 // Try 32-bit splatted SIMD immediate.
9583 static SDValue tryAdvSIMDModImm32(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
9584                                   const APInt &Bits,
9585                                   const SDValue *LHS = nullptr) {
9586   if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
9587     uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
9588     EVT VT = Op.getValueType();
9589     MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
9590     bool isAdvSIMDModImm = false;
9591     uint64_t Shift;
9592 
9593     if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType1(Value))) {
9594       Value = AArch64_AM::encodeAdvSIMDModImmType1(Value);
9595       Shift = 0;
9596     }
9597     else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType2(Value))) {
9598       Value = AArch64_AM::encodeAdvSIMDModImmType2(Value);
9599       Shift = 8;
9600     }
9601     else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType3(Value))) {
9602       Value = AArch64_AM::encodeAdvSIMDModImmType3(Value);
9603       Shift = 16;
9604     }
9605     else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType4(Value))) {
9606       Value = AArch64_AM::encodeAdvSIMDModImmType4(Value);
9607       Shift = 24;
9608     }
9609 
9610     if (isAdvSIMDModImm) {
9611       SDLoc dl(Op);
9612       SDValue Mov;
9613 
9614       if (LHS)
9615         Mov = DAG.getNode(NewOp, dl, MovTy, *LHS,
9616                           DAG.getConstant(Value, dl, MVT::i32),
9617                           DAG.getConstant(Shift, dl, MVT::i32));
9618       else
9619         Mov = DAG.getNode(NewOp, dl, MovTy,
9620                           DAG.getConstant(Value, dl, MVT::i32),
9621                           DAG.getConstant(Shift, dl, MVT::i32));
9622 
9623       return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
9624     }
9625   }
9626 
9627   return SDValue();
9628 }
9629 
9630 // Try 16-bit splatted SIMD immediate.
9631 static SDValue tryAdvSIMDModImm16(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
9632                                   const APInt &Bits,
9633                                   const SDValue *LHS = nullptr) {
9634   if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
9635     uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
9636     EVT VT = Op.getValueType();
9637     MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
9638     bool isAdvSIMDModImm = false;
9639     uint64_t Shift;
9640 
9641     if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType5(Value))) {
9642       Value = AArch64_AM::encodeAdvSIMDModImmType5(Value);
9643       Shift = 0;
9644     }
9645     else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType6(Value))) {
9646       Value = AArch64_AM::encodeAdvSIMDModImmType6(Value);
9647       Shift = 8;
9648     }
9649 
9650     if (isAdvSIMDModImm) {
9651       SDLoc dl(Op);
9652       SDValue Mov;
9653 
9654       if (LHS)
9655         Mov = DAG.getNode(NewOp, dl, MovTy, *LHS,
9656                           DAG.getConstant(Value, dl, MVT::i32),
9657                           DAG.getConstant(Shift, dl, MVT::i32));
9658       else
9659         Mov = DAG.getNode(NewOp, dl, MovTy,
9660                           DAG.getConstant(Value, dl, MVT::i32),
9661                           DAG.getConstant(Shift, dl, MVT::i32));
9662 
9663       return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
9664     }
9665   }
9666 
9667   return SDValue();
9668 }
9669 
9670 // Try 32-bit splatted SIMD immediate with shifted ones.
9671 static SDValue tryAdvSIMDModImm321s(unsigned NewOp, SDValue Op,
9672                                     SelectionDAG &DAG, const APInt &Bits) {
9673   if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
9674     uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
9675     EVT VT = Op.getValueType();
9676     MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
9677     bool isAdvSIMDModImm = false;
9678     uint64_t Shift;
9679 
9680     if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType7(Value))) {
9681       Value = AArch64_AM::encodeAdvSIMDModImmType7(Value);
9682       Shift = 264;
9683     }
9684     else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType8(Value))) {
9685       Value = AArch64_AM::encodeAdvSIMDModImmType8(Value);
9686       Shift = 272;
9687     }
9688 
9689     if (isAdvSIMDModImm) {
9690       SDLoc dl(Op);
9691       SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
9692                                 DAG.getConstant(Value, dl, MVT::i32),
9693                                 DAG.getConstant(Shift, dl, MVT::i32));
9694       return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
9695     }
9696   }
9697 
9698   return SDValue();
9699 }
9700 
9701 // Try 8-bit splatted SIMD immediate.
9702 static SDValue tryAdvSIMDModImm8(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
9703                                  const APInt &Bits) {
9704   if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
9705     uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
9706     EVT VT = Op.getValueType();
9707     MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
9708 
9709     if (AArch64_AM::isAdvSIMDModImmType9(Value)) {
9710       Value = AArch64_AM::encodeAdvSIMDModImmType9(Value);
9711 
9712       SDLoc dl(Op);
9713       SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
9714                                 DAG.getConstant(Value, dl, MVT::i32));
9715       return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
9716     }
9717   }
9718 
9719   return SDValue();
9720 }
9721 
9722 // Try FP splatted SIMD immediate.
9723 static SDValue tryAdvSIMDModImmFP(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
9724                                   const APInt &Bits) {
9725   if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
9726     uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
9727     EVT VT = Op.getValueType();
9728     bool isWide = (VT.getSizeInBits() == 128);
9729     MVT MovTy;
9730     bool isAdvSIMDModImm = false;
9731 
9732     if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType11(Value))) {
9733       Value = AArch64_AM::encodeAdvSIMDModImmType11(Value);
9734       MovTy = isWide ? MVT::v4f32 : MVT::v2f32;
9735     }
9736     else if (isWide &&
9737              (isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType12(Value))) {
9738       Value = AArch64_AM::encodeAdvSIMDModImmType12(Value);
9739       MovTy = MVT::v2f64;
9740     }
9741 
9742     if (isAdvSIMDModImm) {
9743       SDLoc dl(Op);
9744       SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
9745                                 DAG.getConstant(Value, dl, MVT::i32));
9746       return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
9747     }
9748   }
9749 
9750   return SDValue();
9751 }
9752 
9753 // Specialized code to quickly find if PotentialBVec is a BuildVector that
9754 // consists of only the same constant int value, returned in reference arg
9755 // ConstVal
9756 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
9757                                      uint64_t &ConstVal) {
9758   BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
9759   if (!Bvec)
9760     return false;
9761   ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
9762   if (!FirstElt)
9763     return false;
9764   EVT VT = Bvec->getValueType(0);
9765   unsigned NumElts = VT.getVectorNumElements();
9766   for (unsigned i = 1; i < NumElts; ++i)
9767     if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
9768       return false;
9769   ConstVal = FirstElt->getZExtValue();
9770   return true;
9771 }
9772 
9773 static unsigned getIntrinsicID(const SDNode *N) {
9774   unsigned Opcode = N->getOpcode();
9775   switch (Opcode) {
9776   default:
9777     return Intrinsic::not_intrinsic;
9778   case ISD::INTRINSIC_WO_CHAIN: {
9779     unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9780     if (IID < Intrinsic::num_intrinsics)
9781       return IID;
9782     return Intrinsic::not_intrinsic;
9783   }
9784   }
9785 }
9786 
9787 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
9788 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
9789 // BUILD_VECTORs with constant element C1, C2 is a constant, and:
9790 //   - for the SLI case: C1 == ~(Ones(ElemSizeInBits) << C2)
9791 //   - for the SRI case: C1 == ~(Ones(ElemSizeInBits) >> C2)
9792 // The (or (lsl Y, C2), (and X, BvecC1)) case is also handled.
9793 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
9794   EVT VT = N->getValueType(0);
9795 
9796   if (!VT.isVector())
9797     return SDValue();
9798 
9799   SDLoc DL(N);
9800 
9801   SDValue And;
9802   SDValue Shift;
9803 
9804   SDValue FirstOp = N->getOperand(0);
9805   unsigned FirstOpc = FirstOp.getOpcode();
9806   SDValue SecondOp = N->getOperand(1);
9807   unsigned SecondOpc = SecondOp.getOpcode();
9808 
9809   // Is one of the operands an AND or a BICi? The AND may have been optimised to
9810   // a BICi in order to use an immediate instead of a register.
9811   // Is the other operand an shl or lshr? This will have been turned into:
9812   // AArch64ISD::VSHL vector, #shift or AArch64ISD::VLSHR vector, #shift.
9813   if ((FirstOpc == ISD::AND || FirstOpc == AArch64ISD::BICi) &&
9814       (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR)) {
9815     And = FirstOp;
9816     Shift = SecondOp;
9817 
9818   } else if ((SecondOpc == ISD::AND || SecondOpc == AArch64ISD::BICi) &&
9819              (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR)) {
9820     And = SecondOp;
9821     Shift = FirstOp;
9822   } else
9823     return SDValue();
9824 
9825   bool IsAnd = And.getOpcode() == ISD::AND;
9826   bool IsShiftRight = Shift.getOpcode() == AArch64ISD::VLSHR;
9827 
9828   // Is the shift amount constant?
9829   ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
9830   if (!C2node)
9831     return SDValue();
9832 
9833   uint64_t C1;
9834   if (IsAnd) {
9835     // Is the and mask vector all constant?
9836     if (!isAllConstantBuildVector(And.getOperand(1), C1))
9837       return SDValue();
9838   } else {
9839     // Reconstruct the corresponding AND immediate from the two BICi immediates.
9840     ConstantSDNode *C1nodeImm = dyn_cast<ConstantSDNode>(And.getOperand(1));
9841     ConstantSDNode *C1nodeShift = dyn_cast<ConstantSDNode>(And.getOperand(2));
9842     assert(C1nodeImm && C1nodeShift);
9843     C1 = ~(C1nodeImm->getZExtValue() << C1nodeShift->getZExtValue());
9844   }
9845 
9846   // Is C1 == ~(Ones(ElemSizeInBits) << C2) or
9847   // C1 == ~(Ones(ElemSizeInBits) >> C2), taking into account
9848   // how much one can shift elements of a particular size?
9849   uint64_t C2 = C2node->getZExtValue();
9850   unsigned ElemSizeInBits = VT.getScalarSizeInBits();
9851   if (C2 > ElemSizeInBits)
9852     return SDValue();
9853 
9854   APInt C1AsAPInt(ElemSizeInBits, C1);
9855   APInt RequiredC1 = IsShiftRight ? APInt::getHighBitsSet(ElemSizeInBits, C2)
9856                                   : APInt::getLowBitsSet(ElemSizeInBits, C2);
9857   if (C1AsAPInt != RequiredC1)
9858     return SDValue();
9859 
9860   SDValue X = And.getOperand(0);
9861   SDValue Y = Shift.getOperand(0);
9862 
9863   unsigned Inst = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI;
9864   SDValue ResultSLI = DAG.getNode(Inst, DL, VT, X, Y, Shift.getOperand(1));
9865 
9866   LLVM_DEBUG(dbgs() << "aarch64-lower: transformed: \n");
9867   LLVM_DEBUG(N->dump(&DAG));
9868   LLVM_DEBUG(dbgs() << "into: \n");
9869   LLVM_DEBUG(ResultSLI->dump(&DAG));
9870 
9871   ++NumShiftInserts;
9872   return ResultSLI;
9873 }
9874 
9875 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
9876                                              SelectionDAG &DAG) const {
9877   if (useSVEForFixedLengthVectorVT(Op.getValueType()))
9878     return LowerToScalableOp(Op, DAG);
9879 
9880   // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
9881   if (SDValue Res = tryLowerToSLI(Op.getNode(), DAG))
9882     return Res;
9883 
9884   EVT VT = Op.getValueType();
9885 
9886   SDValue LHS = Op.getOperand(0);
9887   BuildVectorSDNode *BVN =
9888       dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
9889   if (!BVN) {
9890     // OR commutes, so try swapping the operands.
9891     LHS = Op.getOperand(1);
9892     BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
9893   }
9894   if (!BVN)
9895     return Op;
9896 
9897   APInt DefBits(VT.getSizeInBits(), 0);
9898   APInt UndefBits(VT.getSizeInBits(), 0);
9899   if (resolveBuildVector(BVN, DefBits, UndefBits)) {
9900     SDValue NewOp;
9901 
9902     if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG,
9903                                     DefBits, &LHS)) ||
9904         (NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG,
9905                                     DefBits, &LHS)))
9906       return NewOp;
9907 
9908     if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG,
9909                                     UndefBits, &LHS)) ||
9910         (NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG,
9911                                     UndefBits, &LHS)))
9912       return NewOp;
9913   }
9914 
9915   // We can always fall back to a non-immediate OR.
9916   return Op;
9917 }
9918 
9919 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
9920 // be truncated to fit element width.
9921 static SDValue NormalizeBuildVector(SDValue Op,
9922                                     SelectionDAG &DAG) {
9923   assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
9924   SDLoc dl(Op);
9925   EVT VT = Op.getValueType();
9926   EVT EltTy= VT.getVectorElementType();
9927 
9928   if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
9929     return Op;
9930 
9931   SmallVector<SDValue, 16> Ops;
9932   for (SDValue Lane : Op->ops()) {
9933     // For integer vectors, type legalization would have promoted the
9934     // operands already. Otherwise, if Op is a floating-point splat
9935     // (with operands cast to integers), then the only possibilities
9936     // are constants and UNDEFs.
9937     if (auto *CstLane = dyn_cast<ConstantSDNode>(Lane)) {
9938       APInt LowBits(EltTy.getSizeInBits(),
9939                     CstLane->getZExtValue());
9940       Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
9941     } else if (Lane.getNode()->isUndef()) {
9942       Lane = DAG.getUNDEF(MVT::i32);
9943     } else {
9944       assert(Lane.getValueType() == MVT::i32 &&
9945              "Unexpected BUILD_VECTOR operand type");
9946     }
9947     Ops.push_back(Lane);
9948   }
9949   return DAG.getBuildVector(VT, dl, Ops);
9950 }
9951 
9952 static SDValue ConstantBuildVector(SDValue Op, SelectionDAG &DAG) {
9953   EVT VT = Op.getValueType();
9954 
9955   APInt DefBits(VT.getSizeInBits(), 0);
9956   APInt UndefBits(VT.getSizeInBits(), 0);
9957   BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
9958   if (resolveBuildVector(BVN, DefBits, UndefBits)) {
9959     SDValue NewOp;
9960     if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
9961         (NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
9962         (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
9963         (NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
9964         (NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
9965         (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
9966       return NewOp;
9967 
9968     DefBits = ~DefBits;
9969     if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) ||
9970         (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) ||
9971         (NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits)))
9972       return NewOp;
9973 
9974     DefBits = UndefBits;
9975     if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
9976         (NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
9977         (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
9978         (NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
9979         (NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
9980         (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
9981       return NewOp;
9982 
9983     DefBits = ~UndefBits;
9984     if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) ||
9985         (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) ||
9986         (NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits)))
9987       return NewOp;
9988   }
9989 
9990   return SDValue();
9991 }
9992 
9993 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
9994                                                  SelectionDAG &DAG) const {
9995   EVT VT = Op.getValueType();
9996 
9997   // Try to build a simple constant vector.
9998   Op = NormalizeBuildVector(Op, DAG);
9999   if (VT.isInteger()) {
10000     // Certain vector constants, used to express things like logical NOT and
10001     // arithmetic NEG, are passed through unmodified.  This allows special
10002     // patterns for these operations to match, which will lower these constants
10003     // to whatever is proven necessary.
10004     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
10005     if (BVN->isConstant())
10006       if (ConstantSDNode *Const = BVN->getConstantSplatNode()) {
10007         unsigned BitSize = VT.getVectorElementType().getSizeInBits();
10008         APInt Val(BitSize,
10009                   Const->getAPIntValue().zextOrTrunc(BitSize).getZExtValue());
10010         if (Val.isNullValue() || Val.isAllOnesValue())
10011           return Op;
10012       }
10013   }
10014 
10015   if (SDValue V = ConstantBuildVector(Op, DAG))
10016     return V;
10017 
10018   // Scan through the operands to find some interesting properties we can
10019   // exploit:
10020   //   1) If only one value is used, we can use a DUP, or
10021   //   2) if only the low element is not undef, we can just insert that, or
10022   //   3) if only one constant value is used (w/ some non-constant lanes),
10023   //      we can splat the constant value into the whole vector then fill
10024   //      in the non-constant lanes.
10025   //   4) FIXME: If different constant values are used, but we can intelligently
10026   //             select the values we'll be overwriting for the non-constant
10027   //             lanes such that we can directly materialize the vector
10028   //             some other way (MOVI, e.g.), we can be sneaky.
10029   //   5) if all operands are EXTRACT_VECTOR_ELT, check for VUZP.
10030   SDLoc dl(Op);
10031   unsigned NumElts = VT.getVectorNumElements();
10032   bool isOnlyLowElement = true;
10033   bool usesOnlyOneValue = true;
10034   bool usesOnlyOneConstantValue = true;
10035   bool isConstant = true;
10036   bool AllLanesExtractElt = true;
10037   unsigned NumConstantLanes = 0;
10038   unsigned NumDifferentLanes = 0;
10039   unsigned NumUndefLanes = 0;
10040   SDValue Value;
10041   SDValue ConstantValue;
10042   for (unsigned i = 0; i < NumElts; ++i) {
10043     SDValue V = Op.getOperand(i);
10044     if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10045       AllLanesExtractElt = false;
10046     if (V.isUndef()) {
10047       ++NumUndefLanes;
10048       continue;
10049     }
10050     if (i > 0)
10051       isOnlyLowElement = false;
10052     if (!isIntOrFPConstant(V))
10053       isConstant = false;
10054 
10055     if (isIntOrFPConstant(V)) {
10056       ++NumConstantLanes;
10057       if (!ConstantValue.getNode())
10058         ConstantValue = V;
10059       else if (ConstantValue != V)
10060         usesOnlyOneConstantValue = false;
10061     }
10062 
10063     if (!Value.getNode())
10064       Value = V;
10065     else if (V != Value) {
10066       usesOnlyOneValue = false;
10067       ++NumDifferentLanes;
10068     }
10069   }
10070 
10071   if (!Value.getNode()) {
10072     LLVM_DEBUG(
10073         dbgs() << "LowerBUILD_VECTOR: value undefined, creating undef node\n");
10074     return DAG.getUNDEF(VT);
10075   }
10076 
10077   // Convert BUILD_VECTOR where all elements but the lowest are undef into
10078   // SCALAR_TO_VECTOR, except for when we have a single-element constant vector
10079   // as SimplifyDemandedBits will just turn that back into BUILD_VECTOR.
10080   if (isOnlyLowElement && !(NumElts == 1 && isIntOrFPConstant(Value))) {
10081     LLVM_DEBUG(dbgs() << "LowerBUILD_VECTOR: only low element used, creating 1 "
10082                          "SCALAR_TO_VECTOR node\n");
10083     return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
10084   }
10085 
10086   if (AllLanesExtractElt) {
10087     SDNode *Vector = nullptr;
10088     bool Even = false;
10089     bool Odd = false;
10090     // Check whether the extract elements match the Even pattern <0,2,4,...> or
10091     // the Odd pattern <1,3,5,...>.
10092     for (unsigned i = 0; i < NumElts; ++i) {
10093       SDValue V = Op.getOperand(i);
10094       const SDNode *N = V.getNode();
10095       if (!isa<ConstantSDNode>(N->getOperand(1)))
10096         break;
10097       SDValue N0 = N->getOperand(0);
10098 
10099       // All elements are extracted from the same vector.
10100       if (!Vector) {
10101         Vector = N0.getNode();
10102         // Check that the type of EXTRACT_VECTOR_ELT matches the type of
10103         // BUILD_VECTOR.
10104         if (VT.getVectorElementType() !=
10105             N0.getValueType().getVectorElementType())
10106           break;
10107       } else if (Vector != N0.getNode()) {
10108         Odd = false;
10109         Even = false;
10110         break;
10111       }
10112 
10113       // Extracted values are either at Even indices <0,2,4,...> or at Odd
10114       // indices <1,3,5,...>.
10115       uint64_t Val = N->getConstantOperandVal(1);
10116       if (Val == 2 * i) {
10117         Even = true;
10118         continue;
10119       }
10120       if (Val - 1 == 2 * i) {
10121         Odd = true;
10122         continue;
10123       }
10124 
10125       // Something does not match: abort.
10126       Odd = false;
10127       Even = false;
10128       break;
10129     }
10130     if (Even || Odd) {
10131       SDValue LHS =
10132           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SDValue(Vector, 0),
10133                       DAG.getConstant(0, dl, MVT::i64));
10134       SDValue RHS =
10135           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SDValue(Vector, 0),
10136                       DAG.getConstant(NumElts, dl, MVT::i64));
10137 
10138       if (Even && !Odd)
10139         return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), LHS,
10140                            RHS);
10141       if (Odd && !Even)
10142         return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), LHS,
10143                            RHS);
10144     }
10145   }
10146 
10147   // Use DUP for non-constant splats. For f32 constant splats, reduce to
10148   // i32 and try again.
10149   if (usesOnlyOneValue) {
10150     if (!isConstant) {
10151       if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10152           Value.getValueType() != VT) {
10153         LLVM_DEBUG(
10154             dbgs() << "LowerBUILD_VECTOR: use DUP for non-constant splats\n");
10155         return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
10156       }
10157 
10158       // This is actually a DUPLANExx operation, which keeps everything vectory.
10159 
10160       SDValue Lane = Value.getOperand(1);
10161       Value = Value.getOperand(0);
10162       if (Value.getValueSizeInBits() == 64) {
10163         LLVM_DEBUG(
10164             dbgs() << "LowerBUILD_VECTOR: DUPLANE works on 128-bit vectors, "
10165                       "widening it\n");
10166         Value = WidenVector(Value, DAG);
10167       }
10168 
10169       unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
10170       return DAG.getNode(Opcode, dl, VT, Value, Lane);
10171     }
10172 
10173     if (VT.getVectorElementType().isFloatingPoint()) {
10174       SmallVector<SDValue, 8> Ops;
10175       EVT EltTy = VT.getVectorElementType();
10176       assert ((EltTy == MVT::f16 || EltTy == MVT::bf16 || EltTy == MVT::f32 ||
10177                EltTy == MVT::f64) && "Unsupported floating-point vector type");
10178       LLVM_DEBUG(
10179           dbgs() << "LowerBUILD_VECTOR: float constant splats, creating int "
10180                     "BITCASTS, and try again\n");
10181       MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
10182       for (unsigned i = 0; i < NumElts; ++i)
10183         Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
10184       EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
10185       SDValue Val = DAG.getBuildVector(VecVT, dl, Ops);
10186       LLVM_DEBUG(dbgs() << "LowerBUILD_VECTOR: trying to lower new vector: ";
10187                  Val.dump(););
10188       Val = LowerBUILD_VECTOR(Val, DAG);
10189       if (Val.getNode())
10190         return DAG.getNode(ISD::BITCAST, dl, VT, Val);
10191     }
10192   }
10193 
10194   // If we need to insert a small number of different non-constant elements and
10195   // the vector width is sufficiently large, prefer using DUP with the common
10196   // value and INSERT_VECTOR_ELT for the different lanes. If DUP is preferred,
10197   // skip the constant lane handling below.
10198   bool PreferDUPAndInsert =
10199       !isConstant && NumDifferentLanes >= 1 &&
10200       NumDifferentLanes < ((NumElts - NumUndefLanes) / 2) &&
10201       NumDifferentLanes >= NumConstantLanes;
10202 
10203   // If there was only one constant value used and for more than one lane,
10204   // start by splatting that value, then replace the non-constant lanes. This
10205   // is better than the default, which will perform a separate initialization
10206   // for each lane.
10207   if (!PreferDUPAndInsert && NumConstantLanes > 0 && usesOnlyOneConstantValue) {
10208     // Firstly, try to materialize the splat constant.
10209     SDValue Vec = DAG.getSplatBuildVector(VT, dl, ConstantValue),
10210             Val = ConstantBuildVector(Vec, DAG);
10211     if (!Val) {
10212       // Otherwise, materialize the constant and splat it.
10213       Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
10214       DAG.ReplaceAllUsesWith(Vec.getNode(), &Val);
10215     }
10216 
10217     // Now insert the non-constant lanes.
10218     for (unsigned i = 0; i < NumElts; ++i) {
10219       SDValue V = Op.getOperand(i);
10220       SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
10221       if (!isIntOrFPConstant(V))
10222         // Note that type legalization likely mucked about with the VT of the
10223         // source operand, so we may have to convert it here before inserting.
10224         Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
10225     }
10226     return Val;
10227   }
10228 
10229   // This will generate a load from the constant pool.
10230   if (isConstant) {
10231     LLVM_DEBUG(
10232         dbgs() << "LowerBUILD_VECTOR: all elements are constant, use default "
10233                   "expansion\n");
10234     return SDValue();
10235   }
10236 
10237   // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
10238   if (NumElts >= 4) {
10239     if (SDValue shuffle = ReconstructShuffle(Op, DAG))
10240       return shuffle;
10241   }
10242 
10243   if (PreferDUPAndInsert) {
10244     // First, build a constant vector with the common element.
10245     SmallVector<SDValue, 8> Ops(NumElts, Value);
10246     SDValue NewVector = LowerBUILD_VECTOR(DAG.getBuildVector(VT, dl, Ops), DAG);
10247     // Next, insert the elements that do not match the common value.
10248     for (unsigned I = 0; I < NumElts; ++I)
10249       if (Op.getOperand(I) != Value)
10250         NewVector =
10251             DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, NewVector,
10252                         Op.getOperand(I), DAG.getConstant(I, dl, MVT::i64));
10253 
10254     return NewVector;
10255   }
10256 
10257   // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
10258   // know the default expansion would otherwise fall back on something even
10259   // worse. For a vector with one or two non-undef values, that's
10260   // scalar_to_vector for the elements followed by a shuffle (provided the
10261   // shuffle is valid for the target) and materialization element by element
10262   // on the stack followed by a load for everything else.
10263   if (!isConstant && !usesOnlyOneValue) {
10264     LLVM_DEBUG(
10265         dbgs() << "LowerBUILD_VECTOR: alternatives failed, creating sequence "
10266                   "of INSERT_VECTOR_ELT\n");
10267 
10268     SDValue Vec = DAG.getUNDEF(VT);
10269     SDValue Op0 = Op.getOperand(0);
10270     unsigned i = 0;
10271 
10272     // Use SCALAR_TO_VECTOR for lane zero to
10273     // a) Avoid a RMW dependency on the full vector register, and
10274     // b) Allow the register coalescer to fold away the copy if the
10275     //    value is already in an S or D register, and we're forced to emit an
10276     //    INSERT_SUBREG that we can't fold anywhere.
10277     //
10278     // We also allow types like i8 and i16 which are illegal scalar but legal
10279     // vector element types. After type-legalization the inserted value is
10280     // extended (i32) and it is safe to cast them to the vector type by ignoring
10281     // the upper bits of the lowest lane (e.g. v8i8, v4i16).
10282     if (!Op0.isUndef()) {
10283       LLVM_DEBUG(dbgs() << "Creating node for op0, it is not undefined:\n");
10284       Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0);
10285       ++i;
10286     }
10287     LLVM_DEBUG(if (i < NumElts) dbgs()
10288                    << "Creating nodes for the other vector elements:\n";);
10289     for (; i < NumElts; ++i) {
10290       SDValue V = Op.getOperand(i);
10291       if (V.isUndef())
10292         continue;
10293       SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
10294       Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
10295     }
10296     return Vec;
10297   }
10298 
10299   LLVM_DEBUG(
10300       dbgs() << "LowerBUILD_VECTOR: use default expansion, failed to find "
10301                 "better alternative\n");
10302   return SDValue();
10303 }
10304 
10305 SDValue AArch64TargetLowering::LowerCONCAT_VECTORS(SDValue Op,
10306                                                    SelectionDAG &DAG) const {
10307   if (useSVEForFixedLengthVectorVT(Op.getValueType()))
10308     return LowerFixedLengthConcatVectorsToSVE(Op, DAG);
10309 
10310   assert(Op.getValueType().isScalableVector() &&
10311          isTypeLegal(Op.getValueType()) &&
10312          "Expected legal scalable vector type!");
10313 
10314   if (isTypeLegal(Op.getOperand(0).getValueType()) && Op.getNumOperands() == 2)
10315     return Op;
10316 
10317   return SDValue();
10318 }
10319 
10320 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10321                                                       SelectionDAG &DAG) const {
10322   assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
10323 
10324   if (useSVEForFixedLengthVectorVT(Op.getValueType()))
10325     return LowerFixedLengthInsertVectorElt(Op, DAG);
10326 
10327   // Check for non-constant or out of range lane.
10328   EVT VT = Op.getOperand(0).getValueType();
10329 
10330   if (VT.getScalarType() == MVT::i1) {
10331     EVT VectorVT = getPromotedVTForPredicate(VT);
10332     SDLoc DL(Op);
10333     SDValue ExtendedVector =
10334         DAG.getAnyExtOrTrunc(Op.getOperand(0), DL, VectorVT);
10335     SDValue ExtendedValue =
10336         DAG.getAnyExtOrTrunc(Op.getOperand(1), DL,
10337                              VectorVT.getScalarType().getSizeInBits() < 32
10338                                  ? MVT::i32
10339                                  : VectorVT.getScalarType());
10340     ExtendedVector =
10341         DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VectorVT, ExtendedVector,
10342                     ExtendedValue, Op.getOperand(2));
10343     return DAG.getAnyExtOrTrunc(ExtendedVector, DL, VT);
10344   }
10345 
10346   ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
10347   if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
10348     return SDValue();
10349 
10350   // Insertion/extraction are legal for V128 types.
10351   if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
10352       VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
10353       VT == MVT::v8f16 || VT == MVT::v8bf16)
10354     return Op;
10355 
10356   if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
10357       VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16 &&
10358       VT != MVT::v4bf16)
10359     return SDValue();
10360 
10361   // For V64 types, we perform insertion by expanding the value
10362   // to a V128 type and perform the insertion on that.
10363   SDLoc DL(Op);
10364   SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
10365   EVT WideTy = WideVec.getValueType();
10366 
10367   SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
10368                              Op.getOperand(1), Op.getOperand(2));
10369   // Re-narrow the resultant vector.
10370   return NarrowVector(Node, DAG);
10371 }
10372 
10373 SDValue
10374 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10375                                                SelectionDAG &DAG) const {
10376   assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
10377   EVT VT = Op.getOperand(0).getValueType();
10378 
10379   if (VT.getScalarType() == MVT::i1) {
10380     // We can't directly extract from an SVE predicate; extend it first.
10381     // (This isn't the only possible lowering, but it's straightforward.)
10382     EVT VectorVT = getPromotedVTForPredicate(VT);
10383     SDLoc DL(Op);
10384     SDValue Extend =
10385         DAG.getNode(ISD::ANY_EXTEND, DL, VectorVT, Op.getOperand(0));
10386     MVT ExtractTy = VectorVT == MVT::nxv2i64 ? MVT::i64 : MVT::i32;
10387     SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractTy,
10388                                   Extend, Op.getOperand(1));
10389     return DAG.getAnyExtOrTrunc(Extract, DL, Op.getValueType());
10390   }
10391 
10392   if (useSVEForFixedLengthVectorVT(VT))
10393     return LowerFixedLengthExtractVectorElt(Op, DAG);
10394 
10395   // Check for non-constant or out of range lane.
10396   ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10397   if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
10398     return SDValue();
10399 
10400   // Insertion/extraction are legal for V128 types.
10401   if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
10402       VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
10403       VT == MVT::v8f16 || VT == MVT::v8bf16)
10404     return Op;
10405 
10406   if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
10407       VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16 &&
10408       VT != MVT::v4bf16)
10409     return SDValue();
10410 
10411   // For V64 types, we perform extraction by expanding the value
10412   // to a V128 type and perform the extraction on that.
10413   SDLoc DL(Op);
10414   SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
10415   EVT WideTy = WideVec.getValueType();
10416 
10417   EVT ExtrTy = WideTy.getVectorElementType();
10418   if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
10419     ExtrTy = MVT::i32;
10420 
10421   // For extractions, we just return the result directly.
10422   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
10423                      Op.getOperand(1));
10424 }
10425 
10426 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
10427                                                       SelectionDAG &DAG) const {
10428   assert(Op.getValueType().isFixedLengthVector() &&
10429          "Only cases that extract a fixed length vector are supported!");
10430 
10431   EVT InVT = Op.getOperand(0).getValueType();
10432   unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10433   unsigned Size = Op.getValueSizeInBits();
10434 
10435   if (InVT.isScalableVector()) {
10436     // This will be matched by custom code during ISelDAGToDAG.
10437     if (Idx == 0 && isPackedVectorType(InVT, DAG))
10438       return Op;
10439 
10440     return SDValue();
10441   }
10442 
10443   // This will get lowered to an appropriate EXTRACT_SUBREG in ISel.
10444   if (Idx == 0 && InVT.getSizeInBits() <= 128)
10445     return Op;
10446 
10447   // If this is extracting the upper 64-bits of a 128-bit vector, we match
10448   // that directly.
10449   if (Size == 64 && Idx * InVT.getScalarSizeInBits() == 64 &&
10450       InVT.getSizeInBits() == 128)
10451     return Op;
10452 
10453   return SDValue();
10454 }
10455 
10456 SDValue AArch64TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op,
10457                                                      SelectionDAG &DAG) const {
10458   assert(Op.getValueType().isScalableVector() &&
10459          "Only expect to lower inserts into scalable vectors!");
10460 
10461   EVT InVT = Op.getOperand(1).getValueType();
10462   unsigned Idx = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10463 
10464   if (InVT.isScalableVector()) {
10465     SDLoc DL(Op);
10466     EVT VT = Op.getValueType();
10467 
10468     if (!isTypeLegal(VT) || !VT.isInteger())
10469       return SDValue();
10470 
10471     SDValue Vec0 = Op.getOperand(0);
10472     SDValue Vec1 = Op.getOperand(1);
10473 
10474     // Ensure the subvector is half the size of the main vector.
10475     if (VT.getVectorElementCount() != (InVT.getVectorElementCount() * 2))
10476       return SDValue();
10477 
10478     // Extend elements of smaller vector...
10479     EVT WideVT = InVT.widenIntegerVectorElementType(*(DAG.getContext()));
10480     SDValue ExtVec = DAG.getNode(ISD::ANY_EXTEND, DL, WideVT, Vec1);
10481 
10482     if (Idx == 0) {
10483       SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0);
10484       return DAG.getNode(AArch64ISD::UZP1, DL, VT, ExtVec, HiVec0);
10485     } else if (Idx == InVT.getVectorMinNumElements()) {
10486       SDValue LoVec0 = DAG.getNode(AArch64ISD::UUNPKLO, DL, WideVT, Vec0);
10487       return DAG.getNode(AArch64ISD::UZP1, DL, VT, LoVec0, ExtVec);
10488     }
10489 
10490     return SDValue();
10491   }
10492 
10493   // This will be matched by custom code during ISelDAGToDAG.
10494   if (Idx == 0 && isPackedVectorType(InVT, DAG) && Op.getOperand(0).isUndef())
10495     return Op;
10496 
10497   return SDValue();
10498 }
10499 
10500 SDValue AArch64TargetLowering::LowerDIV(SDValue Op, SelectionDAG &DAG) const {
10501   EVT VT = Op.getValueType();
10502 
10503   if (useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true))
10504     return LowerFixedLengthVectorIntDivideToSVE(Op, DAG);
10505 
10506   assert(VT.isScalableVector() && "Expected a scalable vector.");
10507 
10508   bool Signed = Op.getOpcode() == ISD::SDIV;
10509   unsigned PredOpcode = Signed ? AArch64ISD::SDIV_PRED : AArch64ISD::UDIV_PRED;
10510 
10511   if (VT == MVT::nxv4i32 || VT == MVT::nxv2i64)
10512     return LowerToPredicatedOp(Op, DAG, PredOpcode);
10513 
10514   // SVE doesn't have i8 and i16 DIV operations; widen them to 32-bit
10515   // operations, and truncate the result.
10516   EVT WidenedVT;
10517   if (VT == MVT::nxv16i8)
10518     WidenedVT = MVT::nxv8i16;
10519   else if (VT == MVT::nxv8i16)
10520     WidenedVT = MVT::nxv4i32;
10521   else
10522     llvm_unreachable("Unexpected Custom DIV operation");
10523 
10524   SDLoc dl(Op);
10525   unsigned UnpkLo = Signed ? AArch64ISD::SUNPKLO : AArch64ISD::UUNPKLO;
10526   unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI;
10527   SDValue Op0Lo = DAG.getNode(UnpkLo, dl, WidenedVT, Op.getOperand(0));
10528   SDValue Op1Lo = DAG.getNode(UnpkLo, dl, WidenedVT, Op.getOperand(1));
10529   SDValue Op0Hi = DAG.getNode(UnpkHi, dl, WidenedVT, Op.getOperand(0));
10530   SDValue Op1Hi = DAG.getNode(UnpkHi, dl, WidenedVT, Op.getOperand(1));
10531   SDValue ResultLo = DAG.getNode(Op.getOpcode(), dl, WidenedVT, Op0Lo, Op1Lo);
10532   SDValue ResultHi = DAG.getNode(Op.getOpcode(), dl, WidenedVT, Op0Hi, Op1Hi);
10533   return DAG.getNode(AArch64ISD::UZP1, dl, VT, ResultLo, ResultHi);
10534 }
10535 
10536 bool AArch64TargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
10537   // Currently no fixed length shuffles that require SVE are legal.
10538   if (useSVEForFixedLengthVectorVT(VT))
10539     return false;
10540 
10541   if (VT.getVectorNumElements() == 4 &&
10542       (VT.is128BitVector() || VT.is64BitVector())) {
10543     unsigned PFIndexes[4];
10544     for (unsigned i = 0; i != 4; ++i) {
10545       if (M[i] < 0)
10546         PFIndexes[i] = 8;
10547       else
10548         PFIndexes[i] = M[i];
10549     }
10550 
10551     // Compute the index in the perfect shuffle table.
10552     unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
10553                             PFIndexes[2] * 9 + PFIndexes[3];
10554     unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
10555     unsigned Cost = (PFEntry >> 30);
10556 
10557     if (Cost <= 4)
10558       return true;
10559   }
10560 
10561   bool DummyBool;
10562   int DummyInt;
10563   unsigned DummyUnsigned;
10564 
10565   return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
10566           isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
10567           isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
10568           // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
10569           isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
10570           isZIPMask(M, VT, DummyUnsigned) ||
10571           isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
10572           isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
10573           isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
10574           isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
10575           isConcatMask(M, VT, VT.getSizeInBits() == 128));
10576 }
10577 
10578 /// getVShiftImm - Check if this is a valid build_vector for the immediate
10579 /// operand of a vector shift operation, where all the elements of the
10580 /// build_vector must have the same constant integer value.
10581 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
10582   // Ignore bit_converts.
10583   while (Op.getOpcode() == ISD::BITCAST)
10584     Op = Op.getOperand(0);
10585   BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
10586   APInt SplatBits, SplatUndef;
10587   unsigned SplatBitSize;
10588   bool HasAnyUndefs;
10589   if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
10590                                     HasAnyUndefs, ElementBits) ||
10591       SplatBitSize > ElementBits)
10592     return false;
10593   Cnt = SplatBits.getSExtValue();
10594   return true;
10595 }
10596 
10597 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
10598 /// operand of a vector shift left operation.  That value must be in the range:
10599 ///   0 <= Value < ElementBits for a left shift; or
10600 ///   0 <= Value <= ElementBits for a long left shift.
10601 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
10602   assert(VT.isVector() && "vector shift count is not a vector type");
10603   int64_t ElementBits = VT.getScalarSizeInBits();
10604   if (!getVShiftImm(Op, ElementBits, Cnt))
10605     return false;
10606   return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
10607 }
10608 
10609 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
10610 /// operand of a vector shift right operation. The value must be in the range:
10611 ///   1 <= Value <= ElementBits for a right shift; or
10612 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
10613   assert(VT.isVector() && "vector shift count is not a vector type");
10614   int64_t ElementBits = VT.getScalarSizeInBits();
10615   if (!getVShiftImm(Op, ElementBits, Cnt))
10616     return false;
10617   return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
10618 }
10619 
10620 SDValue AArch64TargetLowering::LowerTRUNCATE(SDValue Op,
10621                                              SelectionDAG &DAG) const {
10622   EVT VT = Op.getValueType();
10623 
10624   if (VT.getScalarType() == MVT::i1) {
10625     // Lower i1 truncate to `(x & 1) != 0`.
10626     SDLoc dl(Op);
10627     EVT OpVT = Op.getOperand(0).getValueType();
10628     SDValue Zero = DAG.getConstant(0, dl, OpVT);
10629     SDValue One = DAG.getConstant(1, dl, OpVT);
10630     SDValue And = DAG.getNode(ISD::AND, dl, OpVT, Op.getOperand(0), One);
10631     return DAG.getSetCC(dl, VT, And, Zero, ISD::SETNE);
10632   }
10633 
10634   if (!VT.isVector() || VT.isScalableVector())
10635     return SDValue();
10636 
10637   if (useSVEForFixedLengthVectorVT(Op.getOperand(0).getValueType()))
10638     return LowerFixedLengthVectorTruncateToSVE(Op, DAG);
10639 
10640   return SDValue();
10641 }
10642 
10643 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
10644                                                       SelectionDAG &DAG) const {
10645   EVT VT = Op.getValueType();
10646   SDLoc DL(Op);
10647   int64_t Cnt;
10648 
10649   if (!Op.getOperand(1).getValueType().isVector())
10650     return Op;
10651   unsigned EltSize = VT.getScalarSizeInBits();
10652 
10653   switch (Op.getOpcode()) {
10654   default:
10655     llvm_unreachable("unexpected shift opcode");
10656 
10657   case ISD::SHL:
10658     if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT))
10659       return LowerToPredicatedOp(Op, DAG, AArch64ISD::SHL_PRED);
10660 
10661     if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
10662       return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
10663                          DAG.getConstant(Cnt, DL, MVT::i32));
10664     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10665                        DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
10666                                        MVT::i32),
10667                        Op.getOperand(0), Op.getOperand(1));
10668   case ISD::SRA:
10669   case ISD::SRL:
10670     if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT)) {
10671       unsigned Opc = Op.getOpcode() == ISD::SRA ? AArch64ISD::SRA_PRED
10672                                                 : AArch64ISD::SRL_PRED;
10673       return LowerToPredicatedOp(Op, DAG, Opc);
10674     }
10675 
10676     // Right shift immediate
10677     if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
10678       unsigned Opc =
10679           (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
10680       return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
10681                          DAG.getConstant(Cnt, DL, MVT::i32));
10682     }
10683 
10684     // Right shift register.  Note, there is not a shift right register
10685     // instruction, but the shift left register instruction takes a signed
10686     // value, where negative numbers specify a right shift.
10687     unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
10688                                                 : Intrinsic::aarch64_neon_ushl;
10689     // negate the shift amount
10690     SDValue NegShift = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
10691                                    Op.getOperand(1));
10692     SDValue NegShiftLeft =
10693         DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10694                     DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
10695                     NegShift);
10696     return NegShiftLeft;
10697   }
10698 
10699   return SDValue();
10700 }
10701 
10702 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
10703                                     AArch64CC::CondCode CC, bool NoNans, EVT VT,
10704                                     const SDLoc &dl, SelectionDAG &DAG) {
10705   EVT SrcVT = LHS.getValueType();
10706   assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
10707          "function only supposed to emit natural comparisons");
10708 
10709   BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
10710   APInt CnstBits(VT.getSizeInBits(), 0);
10711   APInt UndefBits(VT.getSizeInBits(), 0);
10712   bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
10713   bool IsZero = IsCnst && (CnstBits == 0);
10714 
10715   if (SrcVT.getVectorElementType().isFloatingPoint()) {
10716     switch (CC) {
10717     default:
10718       return SDValue();
10719     case AArch64CC::NE: {
10720       SDValue Fcmeq;
10721       if (IsZero)
10722         Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
10723       else
10724         Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
10725       return DAG.getNOT(dl, Fcmeq, VT);
10726     }
10727     case AArch64CC::EQ:
10728       if (IsZero)
10729         return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
10730       return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
10731     case AArch64CC::GE:
10732       if (IsZero)
10733         return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
10734       return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
10735     case AArch64CC::GT:
10736       if (IsZero)
10737         return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
10738       return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
10739     case AArch64CC::LS:
10740       if (IsZero)
10741         return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
10742       return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
10743     case AArch64CC::LT:
10744       if (!NoNans)
10745         return SDValue();
10746       // If we ignore NaNs then we can use to the MI implementation.
10747       LLVM_FALLTHROUGH;
10748     case AArch64CC::MI:
10749       if (IsZero)
10750         return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
10751       return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
10752     }
10753   }
10754 
10755   switch (CC) {
10756   default:
10757     return SDValue();
10758   case AArch64CC::NE: {
10759     SDValue Cmeq;
10760     if (IsZero)
10761       Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
10762     else
10763       Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
10764     return DAG.getNOT(dl, Cmeq, VT);
10765   }
10766   case AArch64CC::EQ:
10767     if (IsZero)
10768       return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
10769     return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
10770   case AArch64CC::GE:
10771     if (IsZero)
10772       return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
10773     return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
10774   case AArch64CC::GT:
10775     if (IsZero)
10776       return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
10777     return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
10778   case AArch64CC::LE:
10779     if (IsZero)
10780       return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
10781     return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
10782   case AArch64CC::LS:
10783     return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
10784   case AArch64CC::LO:
10785     return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
10786   case AArch64CC::LT:
10787     if (IsZero)
10788       return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
10789     return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
10790   case AArch64CC::HI:
10791     return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
10792   case AArch64CC::HS:
10793     return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
10794   }
10795 }
10796 
10797 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
10798                                            SelectionDAG &DAG) const {
10799   if (Op.getValueType().isScalableVector())
10800     return LowerToPredicatedOp(Op, DAG, AArch64ISD::SETCC_MERGE_ZERO);
10801 
10802   if (useSVEForFixedLengthVectorVT(Op.getOperand(0).getValueType()))
10803     return LowerFixedLengthVectorSetccToSVE(Op, DAG);
10804 
10805   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10806   SDValue LHS = Op.getOperand(0);
10807   SDValue RHS = Op.getOperand(1);
10808   EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
10809   SDLoc dl(Op);
10810 
10811   if (LHS.getValueType().getVectorElementType().isInteger()) {
10812     assert(LHS.getValueType() == RHS.getValueType());
10813     AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
10814     SDValue Cmp =
10815         EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
10816     return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
10817   }
10818 
10819   const bool FullFP16 =
10820     static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
10821 
10822   // Make v4f16 (only) fcmp operations utilise vector instructions
10823   // v8f16 support will be a litle more complicated
10824   if (!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) {
10825     if (LHS.getValueType().getVectorNumElements() == 4) {
10826       LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS);
10827       RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS);
10828       SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC);
10829       DAG.ReplaceAllUsesWith(Op, NewSetcc);
10830       CmpVT = MVT::v4i32;
10831     } else
10832       return SDValue();
10833   }
10834 
10835   assert((!FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16) ||
10836           LHS.getValueType().getVectorElementType() != MVT::f128);
10837 
10838   // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
10839   // clean.  Some of them require two branches to implement.
10840   AArch64CC::CondCode CC1, CC2;
10841   bool ShouldInvert;
10842   changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
10843 
10844   bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
10845   SDValue Cmp =
10846       EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
10847   if (!Cmp.getNode())
10848     return SDValue();
10849 
10850   if (CC2 != AArch64CC::AL) {
10851     SDValue Cmp2 =
10852         EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
10853     if (!Cmp2.getNode())
10854       return SDValue();
10855 
10856     Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
10857   }
10858 
10859   Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
10860 
10861   if (ShouldInvert)
10862     Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
10863 
10864   return Cmp;
10865 }
10866 
10867 static SDValue getReductionSDNode(unsigned Op, SDLoc DL, SDValue ScalarOp,
10868                                   SelectionDAG &DAG) {
10869   SDValue VecOp = ScalarOp.getOperand(0);
10870   auto Rdx = DAG.getNode(Op, DL, VecOp.getSimpleValueType(), VecOp);
10871   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarOp.getValueType(), Rdx,
10872                      DAG.getConstant(0, DL, MVT::i64));
10873 }
10874 
10875 SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
10876                                               SelectionDAG &DAG) const {
10877   SDValue Src = Op.getOperand(0);
10878 
10879   // Try to lower fixed length reductions to SVE.
10880   EVT SrcVT = Src.getValueType();
10881   bool OverrideNEON = Op.getOpcode() == ISD::VECREDUCE_AND ||
10882                       Op.getOpcode() == ISD::VECREDUCE_OR ||
10883                       Op.getOpcode() == ISD::VECREDUCE_XOR ||
10884                       Op.getOpcode() == ISD::VECREDUCE_FADD ||
10885                       (Op.getOpcode() != ISD::VECREDUCE_ADD &&
10886                        SrcVT.getVectorElementType() == MVT::i64);
10887   if (SrcVT.isScalableVector() ||
10888       useSVEForFixedLengthVectorVT(SrcVT, OverrideNEON)) {
10889 
10890     if (SrcVT.getVectorElementType() == MVT::i1)
10891       return LowerPredReductionToSVE(Op, DAG);
10892 
10893     switch (Op.getOpcode()) {
10894     case ISD::VECREDUCE_ADD:
10895       return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG);
10896     case ISD::VECREDUCE_AND:
10897       return LowerReductionToSVE(AArch64ISD::ANDV_PRED, Op, DAG);
10898     case ISD::VECREDUCE_OR:
10899       return LowerReductionToSVE(AArch64ISD::ORV_PRED, Op, DAG);
10900     case ISD::VECREDUCE_SMAX:
10901       return LowerReductionToSVE(AArch64ISD::SMAXV_PRED, Op, DAG);
10902     case ISD::VECREDUCE_SMIN:
10903       return LowerReductionToSVE(AArch64ISD::SMINV_PRED, Op, DAG);
10904     case ISD::VECREDUCE_UMAX:
10905       return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG);
10906     case ISD::VECREDUCE_UMIN:
10907       return LowerReductionToSVE(AArch64ISD::UMINV_PRED, Op, DAG);
10908     case ISD::VECREDUCE_XOR:
10909       return LowerReductionToSVE(AArch64ISD::EORV_PRED, Op, DAG);
10910     case ISD::VECREDUCE_FADD:
10911       return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG);
10912     case ISD::VECREDUCE_FMAX:
10913       return LowerReductionToSVE(AArch64ISD::FMAXNMV_PRED, Op, DAG);
10914     case ISD::VECREDUCE_FMIN:
10915       return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG);
10916     default:
10917       llvm_unreachable("Unhandled fixed length reduction");
10918     }
10919   }
10920 
10921   // Lower NEON reductions.
10922   SDLoc dl(Op);
10923   switch (Op.getOpcode()) {
10924   case ISD::VECREDUCE_ADD:
10925     return getReductionSDNode(AArch64ISD::UADDV, dl, Op, DAG);
10926   case ISD::VECREDUCE_SMAX:
10927     return getReductionSDNode(AArch64ISD::SMAXV, dl, Op, DAG);
10928   case ISD::VECREDUCE_SMIN:
10929     return getReductionSDNode(AArch64ISD::SMINV, dl, Op, DAG);
10930   case ISD::VECREDUCE_UMAX:
10931     return getReductionSDNode(AArch64ISD::UMAXV, dl, Op, DAG);
10932   case ISD::VECREDUCE_UMIN:
10933     return getReductionSDNode(AArch64ISD::UMINV, dl, Op, DAG);
10934   case ISD::VECREDUCE_FMAX: {
10935     return DAG.getNode(
10936         ISD::INTRINSIC_WO_CHAIN, dl, Op.getValueType(),
10937         DAG.getConstant(Intrinsic::aarch64_neon_fmaxnmv, dl, MVT::i32),
10938         Src);
10939   }
10940   case ISD::VECREDUCE_FMIN: {
10941     return DAG.getNode(
10942         ISD::INTRINSIC_WO_CHAIN, dl, Op.getValueType(),
10943         DAG.getConstant(Intrinsic::aarch64_neon_fminnmv, dl, MVT::i32),
10944         Src);
10945   }
10946   default:
10947     llvm_unreachable("Unhandled reduction");
10948   }
10949 }
10950 
10951 SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op,
10952                                                     SelectionDAG &DAG) const {
10953   auto &Subtarget = static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
10954   if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics())
10955     return SDValue();
10956 
10957   // LSE has an atomic load-add instruction, but not a load-sub.
10958   SDLoc dl(Op);
10959   MVT VT = Op.getSimpleValueType();
10960   SDValue RHS = Op.getOperand(2);
10961   AtomicSDNode *AN = cast<AtomicSDNode>(Op.getNode());
10962   RHS = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), RHS);
10963   return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, AN->getMemoryVT(),
10964                        Op.getOperand(0), Op.getOperand(1), RHS,
10965                        AN->getMemOperand());
10966 }
10967 
10968 SDValue AArch64TargetLowering::LowerATOMIC_LOAD_AND(SDValue Op,
10969                                                     SelectionDAG &DAG) const {
10970   auto &Subtarget = static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
10971   if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics())
10972     return SDValue();
10973 
10974   // LSE has an atomic load-clear instruction, but not a load-and.
10975   SDLoc dl(Op);
10976   MVT VT = Op.getSimpleValueType();
10977   SDValue RHS = Op.getOperand(2);
10978   AtomicSDNode *AN = cast<AtomicSDNode>(Op.getNode());
10979   RHS = DAG.getNode(ISD::XOR, dl, VT, DAG.getConstant(-1ULL, dl, VT), RHS);
10980   return DAG.getAtomic(ISD::ATOMIC_LOAD_CLR, dl, AN->getMemoryVT(),
10981                        Op.getOperand(0), Op.getOperand(1), RHS,
10982                        AN->getMemOperand());
10983 }
10984 
10985 SDValue AArch64TargetLowering::LowerWindowsDYNAMIC_STACKALLOC(
10986     SDValue Op, SDValue Chain, SDValue &Size, SelectionDAG &DAG) const {
10987   SDLoc dl(Op);
10988   EVT PtrVT = getPointerTy(DAG.getDataLayout());
10989   SDValue Callee = DAG.getTargetExternalSymbol("__chkstk", PtrVT, 0);
10990 
10991   const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
10992   const uint32_t *Mask = TRI->getWindowsStackProbePreservedMask();
10993   if (Subtarget->hasCustomCallingConv())
10994     TRI->UpdateCustomCallPreservedMask(DAG.getMachineFunction(), &Mask);
10995 
10996   Size = DAG.getNode(ISD::SRL, dl, MVT::i64, Size,
10997                      DAG.getConstant(4, dl, MVT::i64));
10998   Chain = DAG.getCopyToReg(Chain, dl, AArch64::X15, Size, SDValue());
10999   Chain =
11000       DAG.getNode(AArch64ISD::CALL, dl, DAG.getVTList(MVT::Other, MVT::Glue),
11001                   Chain, Callee, DAG.getRegister(AArch64::X15, MVT::i64),
11002                   DAG.getRegisterMask(Mask), Chain.getValue(1));
11003   // To match the actual intent better, we should read the output from X15 here
11004   // again (instead of potentially spilling it to the stack), but rereading Size
11005   // from X15 here doesn't work at -O0, since it thinks that X15 is undefined
11006   // here.
11007 
11008   Size = DAG.getNode(ISD::SHL, dl, MVT::i64, Size,
11009                      DAG.getConstant(4, dl, MVT::i64));
11010   return Chain;
11011 }
11012 
11013 SDValue
11014 AArch64TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
11015                                                SelectionDAG &DAG) const {
11016   assert(Subtarget->isTargetWindows() &&
11017          "Only Windows alloca probing supported");
11018   SDLoc dl(Op);
11019   // Get the inputs.
11020   SDNode *Node = Op.getNode();
11021   SDValue Chain = Op.getOperand(0);
11022   SDValue Size = Op.getOperand(1);
11023   MaybeAlign Align =
11024       cast<ConstantSDNode>(Op.getOperand(2))->getMaybeAlignValue();
11025   EVT VT = Node->getValueType(0);
11026 
11027   if (DAG.getMachineFunction().getFunction().hasFnAttribute(
11028           "no-stack-arg-probe")) {
11029     SDValue SP = DAG.getCopyFromReg(Chain, dl, AArch64::SP, MVT::i64);
11030     Chain = SP.getValue(1);
11031     SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
11032     if (Align)
11033       SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
11034                        DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
11035     Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
11036     SDValue Ops[2] = {SP, Chain};
11037     return DAG.getMergeValues(Ops, dl);
11038   }
11039 
11040   Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
11041 
11042   Chain = LowerWindowsDYNAMIC_STACKALLOC(Op, Chain, Size, DAG);
11043 
11044   SDValue SP = DAG.getCopyFromReg(Chain, dl, AArch64::SP, MVT::i64);
11045   Chain = SP.getValue(1);
11046   SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
11047   if (Align)
11048     SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
11049                      DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
11050   Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
11051 
11052   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
11053                              DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
11054 
11055   SDValue Ops[2] = {SP, Chain};
11056   return DAG.getMergeValues(Ops, dl);
11057 }
11058 
11059 SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op,
11060                                            SelectionDAG &DAG) const {
11061   EVT VT = Op.getValueType();
11062   assert(VT != MVT::i64 && "Expected illegal VSCALE node");
11063 
11064   SDLoc DL(Op);
11065   APInt MulImm = cast<ConstantSDNode>(Op.getOperand(0))->getAPIntValue();
11066   return DAG.getZExtOrTrunc(DAG.getVScale(DL, MVT::i64, MulImm.sextOrSelf(64)),
11067                             DL, VT);
11068 }
11069 
11070 /// Set the IntrinsicInfo for the `aarch64_sve_st<N>` intrinsics.
11071 template <unsigned NumVecs>
11072 static bool
11073 setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL,
11074               AArch64TargetLowering::IntrinsicInfo &Info, const CallInst &CI) {
11075   Info.opc = ISD::INTRINSIC_VOID;
11076   // Retrieve EC from first vector argument.
11077   const EVT VT = TLI.getMemValueType(DL, CI.getArgOperand(0)->getType());
11078   ElementCount EC = VT.getVectorElementCount();
11079 #ifndef NDEBUG
11080   // Check the assumption that all input vectors are the same type.
11081   for (unsigned I = 0; I < NumVecs; ++I)
11082     assert(VT == TLI.getMemValueType(DL, CI.getArgOperand(I)->getType()) &&
11083            "Invalid type.");
11084 #endif
11085   // memVT is `NumVecs * VT`.
11086   Info.memVT = EVT::getVectorVT(CI.getType()->getContext(), VT.getScalarType(),
11087                                 EC * NumVecs);
11088   Info.ptrVal = CI.getArgOperand(CI.getNumArgOperands() - 1);
11089   Info.offset = 0;
11090   Info.align.reset();
11091   Info.flags = MachineMemOperand::MOStore;
11092   return true;
11093 }
11094 
11095 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
11096 /// MemIntrinsicNodes.  The associated MachineMemOperands record the alignment
11097 /// specified in the intrinsic calls.
11098 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11099                                                const CallInst &I,
11100                                                MachineFunction &MF,
11101                                                unsigned Intrinsic) const {
11102   auto &DL = I.getModule()->getDataLayout();
11103   switch (Intrinsic) {
11104   case Intrinsic::aarch64_sve_st2:
11105     return setInfoSVEStN<2>(*this, DL, Info, I);
11106   case Intrinsic::aarch64_sve_st3:
11107     return setInfoSVEStN<3>(*this, DL, Info, I);
11108   case Intrinsic::aarch64_sve_st4:
11109     return setInfoSVEStN<4>(*this, DL, Info, I);
11110   case Intrinsic::aarch64_neon_ld2:
11111   case Intrinsic::aarch64_neon_ld3:
11112   case Intrinsic::aarch64_neon_ld4:
11113   case Intrinsic::aarch64_neon_ld1x2:
11114   case Intrinsic::aarch64_neon_ld1x3:
11115   case Intrinsic::aarch64_neon_ld1x4:
11116   case Intrinsic::aarch64_neon_ld2lane:
11117   case Intrinsic::aarch64_neon_ld3lane:
11118   case Intrinsic::aarch64_neon_ld4lane:
11119   case Intrinsic::aarch64_neon_ld2r:
11120   case Intrinsic::aarch64_neon_ld3r:
11121   case Intrinsic::aarch64_neon_ld4r: {
11122     Info.opc = ISD::INTRINSIC_W_CHAIN;
11123     // Conservatively set memVT to the entire set of vectors loaded.
11124     uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
11125     Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11126     Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
11127     Info.offset = 0;
11128     Info.align.reset();
11129     // volatile loads with NEON intrinsics not supported
11130     Info.flags = MachineMemOperand::MOLoad;
11131     return true;
11132   }
11133   case Intrinsic::aarch64_neon_st2:
11134   case Intrinsic::aarch64_neon_st3:
11135   case Intrinsic::aarch64_neon_st4:
11136   case Intrinsic::aarch64_neon_st1x2:
11137   case Intrinsic::aarch64_neon_st1x3:
11138   case Intrinsic::aarch64_neon_st1x4:
11139   case Intrinsic::aarch64_neon_st2lane:
11140   case Intrinsic::aarch64_neon_st3lane:
11141   case Intrinsic::aarch64_neon_st4lane: {
11142     Info.opc = ISD::INTRINSIC_VOID;
11143     // Conservatively set memVT to the entire set of vectors stored.
11144     unsigned NumElts = 0;
11145     for (unsigned ArgI = 0, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11146       Type *ArgTy = I.getArgOperand(ArgI)->getType();
11147       if (!ArgTy->isVectorTy())
11148         break;
11149       NumElts += DL.getTypeSizeInBits(ArgTy) / 64;
11150     }
11151     Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11152     Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
11153     Info.offset = 0;
11154     Info.align.reset();
11155     // volatile stores with NEON intrinsics not supported
11156     Info.flags = MachineMemOperand::MOStore;
11157     return true;
11158   }
11159   case Intrinsic::aarch64_ldaxr:
11160   case Intrinsic::aarch64_ldxr: {
11161     PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
11162     Info.opc = ISD::INTRINSIC_W_CHAIN;
11163     Info.memVT = MVT::getVT(PtrTy->getElementType());
11164     Info.ptrVal = I.getArgOperand(0);
11165     Info.offset = 0;
11166     Info.align = DL.getABITypeAlign(PtrTy->getElementType());
11167     Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
11168     return true;
11169   }
11170   case Intrinsic::aarch64_stlxr:
11171   case Intrinsic::aarch64_stxr: {
11172     PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11173     Info.opc = ISD::INTRINSIC_W_CHAIN;
11174     Info.memVT = MVT::getVT(PtrTy->getElementType());
11175     Info.ptrVal = I.getArgOperand(1);
11176     Info.offset = 0;
11177     Info.align = DL.getABITypeAlign(PtrTy->getElementType());
11178     Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
11179     return true;
11180   }
11181   case Intrinsic::aarch64_ldaxp:
11182   case Intrinsic::aarch64_ldxp:
11183     Info.opc = ISD::INTRINSIC_W_CHAIN;
11184     Info.memVT = MVT::i128;
11185     Info.ptrVal = I.getArgOperand(0);
11186     Info.offset = 0;
11187     Info.align = Align(16);
11188     Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
11189     return true;
11190   case Intrinsic::aarch64_stlxp:
11191   case Intrinsic::aarch64_stxp:
11192     Info.opc = ISD::INTRINSIC_W_CHAIN;
11193     Info.memVT = MVT::i128;
11194     Info.ptrVal = I.getArgOperand(2);
11195     Info.offset = 0;
11196     Info.align = Align(16);
11197     Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
11198     return true;
11199   case Intrinsic::aarch64_sve_ldnt1: {
11200     PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11201     Info.opc = ISD::INTRINSIC_W_CHAIN;
11202     Info.memVT = MVT::getVT(I.getType());
11203     Info.ptrVal = I.getArgOperand(1);
11204     Info.offset = 0;
11205     Info.align = DL.getABITypeAlign(PtrTy->getElementType());
11206     Info.flags = MachineMemOperand::MOLoad;
11207     if (Intrinsic == Intrinsic::aarch64_sve_ldnt1)
11208       Info.flags |= MachineMemOperand::MONonTemporal;
11209     return true;
11210   }
11211   case Intrinsic::aarch64_sve_stnt1: {
11212     PointerType *PtrTy = cast<PointerType>(I.getArgOperand(2)->getType());
11213     Info.opc = ISD::INTRINSIC_W_CHAIN;
11214     Info.memVT = MVT::getVT(I.getOperand(0)->getType());
11215     Info.ptrVal = I.getArgOperand(2);
11216     Info.offset = 0;
11217     Info.align = DL.getABITypeAlign(PtrTy->getElementType());
11218     Info.flags = MachineMemOperand::MOStore;
11219     if (Intrinsic == Intrinsic::aarch64_sve_stnt1)
11220       Info.flags |= MachineMemOperand::MONonTemporal;
11221     return true;
11222   }
11223   default:
11224     break;
11225   }
11226 
11227   return false;
11228 }
11229 
11230 bool AArch64TargetLowering::shouldReduceLoadWidth(SDNode *Load,
11231                                                   ISD::LoadExtType ExtTy,
11232                                                   EVT NewVT) const {
11233   // TODO: This may be worth removing. Check regression tests for diffs.
11234   if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
11235     return false;
11236 
11237   // If we're reducing the load width in order to avoid having to use an extra
11238   // instruction to do extension then it's probably a good idea.
11239   if (ExtTy != ISD::NON_EXTLOAD)
11240     return true;
11241   // Don't reduce load width if it would prevent us from combining a shift into
11242   // the offset.
11243   MemSDNode *Mem = dyn_cast<MemSDNode>(Load);
11244   assert(Mem);
11245   const SDValue &Base = Mem->getBasePtr();
11246   if (Base.getOpcode() == ISD::ADD &&
11247       Base.getOperand(1).getOpcode() == ISD::SHL &&
11248       Base.getOperand(1).hasOneUse() &&
11249       Base.getOperand(1).getOperand(1).getOpcode() == ISD::Constant) {
11250     // The shift can be combined if it matches the size of the value being
11251     // loaded (and so reducing the width would make it not match).
11252     uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1);
11253     uint64_t LoadBytes = Mem->getMemoryVT().getSizeInBits()/8;
11254     if (ShiftAmount == Log2_32(LoadBytes))
11255       return false;
11256   }
11257   // We have no reason to disallow reducing the load width, so allow it.
11258   return true;
11259 }
11260 
11261 // Truncations from 64-bit GPR to 32-bit GPR is free.
11262 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11263   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11264     return false;
11265   uint64_t NumBits1 = Ty1->getPrimitiveSizeInBits().getFixedSize();
11266   uint64_t NumBits2 = Ty2->getPrimitiveSizeInBits().getFixedSize();
11267   return NumBits1 > NumBits2;
11268 }
11269 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11270   if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
11271     return false;
11272   uint64_t NumBits1 = VT1.getFixedSizeInBits();
11273   uint64_t NumBits2 = VT2.getFixedSizeInBits();
11274   return NumBits1 > NumBits2;
11275 }
11276 
11277 /// Check if it is profitable to hoist instruction in then/else to if.
11278 /// Not profitable if I and it's user can form a FMA instruction
11279 /// because we prefer FMSUB/FMADD.
11280 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
11281   if (I->getOpcode() != Instruction::FMul)
11282     return true;
11283 
11284   if (!I->hasOneUse())
11285     return true;
11286 
11287   Instruction *User = I->user_back();
11288 
11289   if (User &&
11290       !(User->getOpcode() == Instruction::FSub ||
11291         User->getOpcode() == Instruction::FAdd))
11292     return true;
11293 
11294   const TargetOptions &Options = getTargetMachine().Options;
11295   const Function *F = I->getFunction();
11296   const DataLayout &DL = F->getParent()->getDataLayout();
11297   Type *Ty = User->getOperand(0)->getType();
11298 
11299   return !(isFMAFasterThanFMulAndFAdd(*F, Ty) &&
11300            isOperationLegalOrCustom(ISD::FMA, getValueType(DL, Ty)) &&
11301            (Options.AllowFPOpFusion == FPOpFusion::Fast ||
11302             Options.UnsafeFPMath));
11303 }
11304 
11305 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
11306 // 64-bit GPR.
11307 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11308   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11309     return false;
11310   unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11311   unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11312   return NumBits1 == 32 && NumBits2 == 64;
11313 }
11314 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11315   if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
11316     return false;
11317   unsigned NumBits1 = VT1.getSizeInBits();
11318   unsigned NumBits2 = VT2.getSizeInBits();
11319   return NumBits1 == 32 && NumBits2 == 64;
11320 }
11321 
11322 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11323   EVT VT1 = Val.getValueType();
11324   if (isZExtFree(VT1, VT2)) {
11325     return true;
11326   }
11327 
11328   if (Val.getOpcode() != ISD::LOAD)
11329     return false;
11330 
11331   // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
11332   return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
11333           VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
11334           VT1.getSizeInBits() <= 32);
11335 }
11336 
11337 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
11338   if (isa<FPExtInst>(Ext))
11339     return false;
11340 
11341   // Vector types are not free.
11342   if (Ext->getType()->isVectorTy())
11343     return false;
11344 
11345   for (const Use &U : Ext->uses()) {
11346     // The extension is free if we can fold it with a left shift in an
11347     // addressing mode or an arithmetic operation: add, sub, and cmp.
11348 
11349     // Is there a shift?
11350     const Instruction *Instr = cast<Instruction>(U.getUser());
11351 
11352     // Is this a constant shift?
11353     switch (Instr->getOpcode()) {
11354     case Instruction::Shl:
11355       if (!isa<ConstantInt>(Instr->getOperand(1)))
11356         return false;
11357       break;
11358     case Instruction::GetElementPtr: {
11359       gep_type_iterator GTI = gep_type_begin(Instr);
11360       auto &DL = Ext->getModule()->getDataLayout();
11361       std::advance(GTI, U.getOperandNo()-1);
11362       Type *IdxTy = GTI.getIndexedType();
11363       // This extension will end up with a shift because of the scaling factor.
11364       // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
11365       // Get the shift amount based on the scaling factor:
11366       // log2(sizeof(IdxTy)) - log2(8).
11367       uint64_t ShiftAmt =
11368         countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy).getFixedSize()) - 3;
11369       // Is the constant foldable in the shift of the addressing mode?
11370       // I.e., shift amount is between 1 and 4 inclusive.
11371       if (ShiftAmt == 0 || ShiftAmt > 4)
11372         return false;
11373       break;
11374     }
11375     case Instruction::Trunc:
11376       // Check if this is a noop.
11377       // trunc(sext ty1 to ty2) to ty1.
11378       if (Instr->getType() == Ext->getOperand(0)->getType())
11379         continue;
11380       LLVM_FALLTHROUGH;
11381     default:
11382       return false;
11383     }
11384 
11385     // At this point we can use the bfm family, so this extension is free
11386     // for that use.
11387   }
11388   return true;
11389 }
11390 
11391 /// Check if both Op1 and Op2 are shufflevector extracts of either the lower
11392 /// or upper half of the vector elements.
11393 static bool areExtractShuffleVectors(Value *Op1, Value *Op2) {
11394   auto areTypesHalfed = [](Value *FullV, Value *HalfV) {
11395     auto *FullTy = FullV->getType();
11396     auto *HalfTy = HalfV->getType();
11397     return FullTy->getPrimitiveSizeInBits().getFixedSize() ==
11398            2 * HalfTy->getPrimitiveSizeInBits().getFixedSize();
11399   };
11400 
11401   auto extractHalf = [](Value *FullV, Value *HalfV) {
11402     auto *FullVT = cast<FixedVectorType>(FullV->getType());
11403     auto *HalfVT = cast<FixedVectorType>(HalfV->getType());
11404     return FullVT->getNumElements() == 2 * HalfVT->getNumElements();
11405   };
11406 
11407   ArrayRef<int> M1, M2;
11408   Value *S1Op1, *S2Op1;
11409   if (!match(Op1, m_Shuffle(m_Value(S1Op1), m_Undef(), m_Mask(M1))) ||
11410       !match(Op2, m_Shuffle(m_Value(S2Op1), m_Undef(), m_Mask(M2))))
11411     return false;
11412 
11413   // Check that the operands are half as wide as the result and we extract
11414   // half of the elements of the input vectors.
11415   if (!areTypesHalfed(S1Op1, Op1) || !areTypesHalfed(S2Op1, Op2) ||
11416       !extractHalf(S1Op1, Op1) || !extractHalf(S2Op1, Op2))
11417     return false;
11418 
11419   // Check the mask extracts either the lower or upper half of vector
11420   // elements.
11421   int M1Start = -1;
11422   int M2Start = -1;
11423   int NumElements = cast<FixedVectorType>(Op1->getType())->getNumElements() * 2;
11424   if (!ShuffleVectorInst::isExtractSubvectorMask(M1, NumElements, M1Start) ||
11425       !ShuffleVectorInst::isExtractSubvectorMask(M2, NumElements, M2Start) ||
11426       M1Start != M2Start || (M1Start != 0 && M2Start != (NumElements / 2)))
11427     return false;
11428 
11429   return true;
11430 }
11431 
11432 /// Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth
11433 /// of the vector elements.
11434 static bool areExtractExts(Value *Ext1, Value *Ext2) {
11435   auto areExtDoubled = [](Instruction *Ext) {
11436     return Ext->getType()->getScalarSizeInBits() ==
11437            2 * Ext->getOperand(0)->getType()->getScalarSizeInBits();
11438   };
11439 
11440   if (!match(Ext1, m_ZExtOrSExt(m_Value())) ||
11441       !match(Ext2, m_ZExtOrSExt(m_Value())) ||
11442       !areExtDoubled(cast<Instruction>(Ext1)) ||
11443       !areExtDoubled(cast<Instruction>(Ext2)))
11444     return false;
11445 
11446   return true;
11447 }
11448 
11449 /// Check if Op could be used with vmull_high_p64 intrinsic.
11450 static bool isOperandOfVmullHighP64(Value *Op) {
11451   Value *VectorOperand = nullptr;
11452   ConstantInt *ElementIndex = nullptr;
11453   return match(Op, m_ExtractElt(m_Value(VectorOperand),
11454                                 m_ConstantInt(ElementIndex))) &&
11455          ElementIndex->getValue() == 1 &&
11456          isa<FixedVectorType>(VectorOperand->getType()) &&
11457          cast<FixedVectorType>(VectorOperand->getType())->getNumElements() == 2;
11458 }
11459 
11460 /// Check if Op1 and Op2 could be used with vmull_high_p64 intrinsic.
11461 static bool areOperandsOfVmullHighP64(Value *Op1, Value *Op2) {
11462   return isOperandOfVmullHighP64(Op1) && isOperandOfVmullHighP64(Op2);
11463 }
11464 
11465 /// Check if sinking \p I's operands to I's basic block is profitable, because
11466 /// the operands can be folded into a target instruction, e.g.
11467 /// shufflevectors extracts and/or sext/zext can be folded into (u,s)subl(2).
11468 bool AArch64TargetLowering::shouldSinkOperands(
11469     Instruction *I, SmallVectorImpl<Use *> &Ops) const {
11470   if (!I->getType()->isVectorTy())
11471     return false;
11472 
11473   if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
11474     switch (II->getIntrinsicID()) {
11475     case Intrinsic::aarch64_neon_umull:
11476       if (!areExtractShuffleVectors(II->getOperand(0), II->getOperand(1)))
11477         return false;
11478       Ops.push_back(&II->getOperandUse(0));
11479       Ops.push_back(&II->getOperandUse(1));
11480       return true;
11481 
11482     case Intrinsic::aarch64_neon_pmull64:
11483       if (!areOperandsOfVmullHighP64(II->getArgOperand(0),
11484                                      II->getArgOperand(1)))
11485         return false;
11486       Ops.push_back(&II->getArgOperandUse(0));
11487       Ops.push_back(&II->getArgOperandUse(1));
11488       return true;
11489 
11490     default:
11491       return false;
11492     }
11493   }
11494 
11495   switch (I->getOpcode()) {
11496   case Instruction::Sub:
11497   case Instruction::Add: {
11498     if (!areExtractExts(I->getOperand(0), I->getOperand(1)))
11499       return false;
11500 
11501     // If the exts' operands extract either the lower or upper elements, we
11502     // can sink them too.
11503     auto Ext1 = cast<Instruction>(I->getOperand(0));
11504     auto Ext2 = cast<Instruction>(I->getOperand(1));
11505     if (areExtractShuffleVectors(Ext1, Ext2)) {
11506       Ops.push_back(&Ext1->getOperandUse(0));
11507       Ops.push_back(&Ext2->getOperandUse(0));
11508     }
11509 
11510     Ops.push_back(&I->getOperandUse(0));
11511     Ops.push_back(&I->getOperandUse(1));
11512 
11513     return true;
11514   }
11515   case Instruction::Mul: {
11516     bool IsProfitable = false;
11517     for (auto &Op : I->operands()) {
11518       // Make sure we are not already sinking this operand
11519       if (any_of(Ops, [&](Use *U) { return U->get() == Op; }))
11520         continue;
11521 
11522       ShuffleVectorInst *Shuffle = dyn_cast<ShuffleVectorInst>(Op);
11523       if (!Shuffle || !Shuffle->isZeroEltSplat())
11524         continue;
11525 
11526       Value *ShuffleOperand = Shuffle->getOperand(0);
11527       InsertElementInst *Insert = dyn_cast<InsertElementInst>(ShuffleOperand);
11528       if (!Insert)
11529         continue;
11530 
11531       Instruction *OperandInstr = dyn_cast<Instruction>(Insert->getOperand(1));
11532       if (!OperandInstr)
11533         continue;
11534 
11535       ConstantInt *ElementConstant =
11536           dyn_cast<ConstantInt>(Insert->getOperand(2));
11537       // Check that the insertelement is inserting into element 0
11538       if (!ElementConstant || ElementConstant->getZExtValue() != 0)
11539         continue;
11540 
11541       unsigned Opcode = OperandInstr->getOpcode();
11542       if (Opcode != Instruction::SExt && Opcode != Instruction::ZExt)
11543         continue;
11544 
11545       Ops.push_back(&Shuffle->getOperandUse(0));
11546       Ops.push_back(&Op);
11547       IsProfitable = true;
11548     }
11549 
11550     return IsProfitable;
11551   }
11552   default:
11553     return false;
11554   }
11555   return false;
11556 }
11557 
11558 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
11559                                           Align &RequiredAligment) const {
11560   if (!LoadedType.isSimple() ||
11561       (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
11562     return false;
11563   // Cyclone supports unaligned accesses.
11564   RequiredAligment = Align(1);
11565   unsigned NumBits = LoadedType.getSizeInBits();
11566   return NumBits == 32 || NumBits == 64;
11567 }
11568 
11569 /// A helper function for determining the number of interleaved accesses we
11570 /// will generate when lowering accesses of the given type.
11571 unsigned
11572 AArch64TargetLowering::getNumInterleavedAccesses(VectorType *VecTy,
11573                                                  const DataLayout &DL) const {
11574   return (DL.getTypeSizeInBits(VecTy) + 127) / 128;
11575 }
11576 
11577 MachineMemOperand::Flags
11578 AArch64TargetLowering::getTargetMMOFlags(const Instruction &I) const {
11579   if (Subtarget->getProcFamily() == AArch64Subtarget::Falkor &&
11580       I.getMetadata(FALKOR_STRIDED_ACCESS_MD) != nullptr)
11581     return MOStridedAccess;
11582   return MachineMemOperand::MONone;
11583 }
11584 
11585 bool AArch64TargetLowering::isLegalInterleavedAccessType(
11586     VectorType *VecTy, const DataLayout &DL) const {
11587 
11588   unsigned VecSize = DL.getTypeSizeInBits(VecTy);
11589   unsigned ElSize = DL.getTypeSizeInBits(VecTy->getElementType());
11590 
11591   // Ensure the number of vector elements is greater than 1.
11592   if (cast<FixedVectorType>(VecTy)->getNumElements() < 2)
11593     return false;
11594 
11595   // Ensure the element type is legal.
11596   if (ElSize != 8 && ElSize != 16 && ElSize != 32 && ElSize != 64)
11597     return false;
11598 
11599   // Ensure the total vector size is 64 or a multiple of 128. Types larger than
11600   // 128 will be split into multiple interleaved accesses.
11601   return VecSize == 64 || VecSize % 128 == 0;
11602 }
11603 
11604 /// Lower an interleaved load into a ldN intrinsic.
11605 ///
11606 /// E.g. Lower an interleaved load (Factor = 2):
11607 ///        %wide.vec = load <8 x i32>, <8 x i32>* %ptr
11608 ///        %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>  ; Extract even elements
11609 ///        %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>  ; Extract odd elements
11610 ///
11611 ///      Into:
11612 ///        %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
11613 ///        %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
11614 ///        %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
11615 bool AArch64TargetLowering::lowerInterleavedLoad(
11616     LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
11617     ArrayRef<unsigned> Indices, unsigned Factor) const {
11618   assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
11619          "Invalid interleave factor");
11620   assert(!Shuffles.empty() && "Empty shufflevector input");
11621   assert(Shuffles.size() == Indices.size() &&
11622          "Unmatched number of shufflevectors and indices");
11623 
11624   const DataLayout &DL = LI->getModule()->getDataLayout();
11625 
11626   VectorType *VTy = Shuffles[0]->getType();
11627 
11628   // Skip if we do not have NEON and skip illegal vector types. We can
11629   // "legalize" wide vector types into multiple interleaved accesses as long as
11630   // the vector types are divisible by 128.
11631   if (!Subtarget->hasNEON() || !isLegalInterleavedAccessType(VTy, DL))
11632     return false;
11633 
11634   unsigned NumLoads = getNumInterleavedAccesses(VTy, DL);
11635 
11636   auto *FVTy = cast<FixedVectorType>(VTy);
11637 
11638   // A pointer vector can not be the return type of the ldN intrinsics. Need to
11639   // load integer vectors first and then convert to pointer vectors.
11640   Type *EltTy = FVTy->getElementType();
11641   if (EltTy->isPointerTy())
11642     FVTy =
11643         FixedVectorType::get(DL.getIntPtrType(EltTy), FVTy->getNumElements());
11644 
11645   IRBuilder<> Builder(LI);
11646 
11647   // The base address of the load.
11648   Value *BaseAddr = LI->getPointerOperand();
11649 
11650   if (NumLoads > 1) {
11651     // If we're going to generate more than one load, reset the sub-vector type
11652     // to something legal.
11653     FVTy = FixedVectorType::get(FVTy->getElementType(),
11654                                 FVTy->getNumElements() / NumLoads);
11655 
11656     // We will compute the pointer operand of each load from the original base
11657     // address using GEPs. Cast the base address to a pointer to the scalar
11658     // element type.
11659     BaseAddr = Builder.CreateBitCast(
11660         BaseAddr,
11661         FVTy->getElementType()->getPointerTo(LI->getPointerAddressSpace()));
11662   }
11663 
11664   Type *PtrTy = FVTy->getPointerTo(LI->getPointerAddressSpace());
11665   Type *Tys[2] = {FVTy, PtrTy};
11666   static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
11667                                             Intrinsic::aarch64_neon_ld3,
11668                                             Intrinsic::aarch64_neon_ld4};
11669   Function *LdNFunc =
11670       Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
11671 
11672   // Holds sub-vectors extracted from the load intrinsic return values. The
11673   // sub-vectors are associated with the shufflevector instructions they will
11674   // replace.
11675   DenseMap<ShuffleVectorInst *, SmallVector<Value *, 4>> SubVecs;
11676 
11677   for (unsigned LoadCount = 0; LoadCount < NumLoads; ++LoadCount) {
11678 
11679     // If we're generating more than one load, compute the base address of
11680     // subsequent loads as an offset from the previous.
11681     if (LoadCount > 0)
11682       BaseAddr = Builder.CreateConstGEP1_32(FVTy->getElementType(), BaseAddr,
11683                                             FVTy->getNumElements() * Factor);
11684 
11685     CallInst *LdN = Builder.CreateCall(
11686         LdNFunc, Builder.CreateBitCast(BaseAddr, PtrTy), "ldN");
11687 
11688     // Extract and store the sub-vectors returned by the load intrinsic.
11689     for (unsigned i = 0; i < Shuffles.size(); i++) {
11690       ShuffleVectorInst *SVI = Shuffles[i];
11691       unsigned Index = Indices[i];
11692 
11693       Value *SubVec = Builder.CreateExtractValue(LdN, Index);
11694 
11695       // Convert the integer vector to pointer vector if the element is pointer.
11696       if (EltTy->isPointerTy())
11697         SubVec = Builder.CreateIntToPtr(
11698             SubVec, FixedVectorType::get(SVI->getType()->getElementType(),
11699                                          FVTy->getNumElements()));
11700       SubVecs[SVI].push_back(SubVec);
11701     }
11702   }
11703 
11704   // Replace uses of the shufflevector instructions with the sub-vectors
11705   // returned by the load intrinsic. If a shufflevector instruction is
11706   // associated with more than one sub-vector, those sub-vectors will be
11707   // concatenated into a single wide vector.
11708   for (ShuffleVectorInst *SVI : Shuffles) {
11709     auto &SubVec = SubVecs[SVI];
11710     auto *WideVec =
11711         SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0];
11712     SVI->replaceAllUsesWith(WideVec);
11713   }
11714 
11715   return true;
11716 }
11717 
11718 /// Lower an interleaved store into a stN intrinsic.
11719 ///
11720 /// E.g. Lower an interleaved store (Factor = 3):
11721 ///        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
11722 ///                 <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
11723 ///        store <12 x i32> %i.vec, <12 x i32>* %ptr
11724 ///
11725 ///      Into:
11726 ///        %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
11727 ///        %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
11728 ///        %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
11729 ///        call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
11730 ///
11731 /// Note that the new shufflevectors will be removed and we'll only generate one
11732 /// st3 instruction in CodeGen.
11733 ///
11734 /// Example for a more general valid mask (Factor 3). Lower:
11735 ///        %i.vec = shuffle <32 x i32> %v0, <32 x i32> %v1,
11736 ///                 <4, 32, 16, 5, 33, 17, 6, 34, 18, 7, 35, 19>
11737 ///        store <12 x i32> %i.vec, <12 x i32>* %ptr
11738 ///
11739 ///      Into:
11740 ///        %sub.v0 = shuffle <32 x i32> %v0, <32 x i32> v1, <4, 5, 6, 7>
11741 ///        %sub.v1 = shuffle <32 x i32> %v0, <32 x i32> v1, <32, 33, 34, 35>
11742 ///        %sub.v2 = shuffle <32 x i32> %v0, <32 x i32> v1, <16, 17, 18, 19>
11743 ///        call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
11744 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
11745                                                   ShuffleVectorInst *SVI,
11746                                                   unsigned Factor) const {
11747   assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
11748          "Invalid interleave factor");
11749 
11750   auto *VecTy = cast<FixedVectorType>(SVI->getType());
11751   assert(VecTy->getNumElements() % Factor == 0 && "Invalid interleaved store");
11752 
11753   unsigned LaneLen = VecTy->getNumElements() / Factor;
11754   Type *EltTy = VecTy->getElementType();
11755   auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen);
11756 
11757   const DataLayout &DL = SI->getModule()->getDataLayout();
11758 
11759   // Skip if we do not have NEON and skip illegal vector types. We can
11760   // "legalize" wide vector types into multiple interleaved accesses as long as
11761   // the vector types are divisible by 128.
11762   if (!Subtarget->hasNEON() || !isLegalInterleavedAccessType(SubVecTy, DL))
11763     return false;
11764 
11765   unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL);
11766 
11767   Value *Op0 = SVI->getOperand(0);
11768   Value *Op1 = SVI->getOperand(1);
11769   IRBuilder<> Builder(SI);
11770 
11771   // StN intrinsics don't support pointer vectors as arguments. Convert pointer
11772   // vectors to integer vectors.
11773   if (EltTy->isPointerTy()) {
11774     Type *IntTy = DL.getIntPtrType(EltTy);
11775     unsigned NumOpElts =
11776         cast<FixedVectorType>(Op0->getType())->getNumElements();
11777 
11778     // Convert to the corresponding integer vector.
11779     auto *IntVecTy = FixedVectorType::get(IntTy, NumOpElts);
11780     Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
11781     Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
11782 
11783     SubVecTy = FixedVectorType::get(IntTy, LaneLen);
11784   }
11785 
11786   // The base address of the store.
11787   Value *BaseAddr = SI->getPointerOperand();
11788 
11789   if (NumStores > 1) {
11790     // If we're going to generate more than one store, reset the lane length
11791     // and sub-vector type to something legal.
11792     LaneLen /= NumStores;
11793     SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen);
11794 
11795     // We will compute the pointer operand of each store from the original base
11796     // address using GEPs. Cast the base address to a pointer to the scalar
11797     // element type.
11798     BaseAddr = Builder.CreateBitCast(
11799         BaseAddr,
11800         SubVecTy->getElementType()->getPointerTo(SI->getPointerAddressSpace()));
11801   }
11802 
11803   auto Mask = SVI->getShuffleMask();
11804 
11805   Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
11806   Type *Tys[2] = {SubVecTy, PtrTy};
11807   static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
11808                                              Intrinsic::aarch64_neon_st3,
11809                                              Intrinsic::aarch64_neon_st4};
11810   Function *StNFunc =
11811       Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
11812 
11813   for (unsigned StoreCount = 0; StoreCount < NumStores; ++StoreCount) {
11814 
11815     SmallVector<Value *, 5> Ops;
11816 
11817     // Split the shufflevector operands into sub vectors for the new stN call.
11818     for (unsigned i = 0; i < Factor; i++) {
11819       unsigned IdxI = StoreCount * LaneLen * Factor + i;
11820       if (Mask[IdxI] >= 0) {
11821         Ops.push_back(Builder.CreateShuffleVector(
11822             Op0, Op1, createSequentialMask(Mask[IdxI], LaneLen, 0)));
11823       } else {
11824         unsigned StartMask = 0;
11825         for (unsigned j = 1; j < LaneLen; j++) {
11826           unsigned IdxJ = StoreCount * LaneLen * Factor + j;
11827           if (Mask[IdxJ * Factor + IdxI] >= 0) {
11828             StartMask = Mask[IdxJ * Factor + IdxI] - IdxJ;
11829             break;
11830           }
11831         }
11832         // Note: Filling undef gaps with random elements is ok, since
11833         // those elements were being written anyway (with undefs).
11834         // In the case of all undefs we're defaulting to using elems from 0
11835         // Note: StartMask cannot be negative, it's checked in
11836         // isReInterleaveMask
11837         Ops.push_back(Builder.CreateShuffleVector(
11838             Op0, Op1, createSequentialMask(StartMask, LaneLen, 0)));
11839       }
11840     }
11841 
11842     // If we generating more than one store, we compute the base address of
11843     // subsequent stores as an offset from the previous.
11844     if (StoreCount > 0)
11845       BaseAddr = Builder.CreateConstGEP1_32(SubVecTy->getElementType(),
11846                                             BaseAddr, LaneLen * Factor);
11847 
11848     Ops.push_back(Builder.CreateBitCast(BaseAddr, PtrTy));
11849     Builder.CreateCall(StNFunc, Ops);
11850   }
11851   return true;
11852 }
11853 
11854 // Lower an SVE structured load intrinsic returning a tuple type to target
11855 // specific intrinsic taking the same input but returning a multi-result value
11856 // of the split tuple type.
11857 //
11858 // E.g. Lowering an LD3:
11859 //
11860 //  call <vscale x 12 x i32> @llvm.aarch64.sve.ld3.nxv12i32(
11861 //                                                    <vscale x 4 x i1> %pred,
11862 //                                                    <vscale x 4 x i32>* %addr)
11863 //
11864 //  Output DAG:
11865 //
11866 //    t0: ch = EntryToken
11867 //        t2: nxv4i1,ch = CopyFromReg t0, Register:nxv4i1 %0
11868 //        t4: i64,ch = CopyFromReg t0, Register:i64 %1
11869 //    t5: nxv4i32,nxv4i32,nxv4i32,ch = AArch64ISD::SVE_LD3 t0, t2, t4
11870 //    t6: nxv12i32 = concat_vectors t5, t5:1, t5:2
11871 //
11872 // This is called pre-legalization to avoid widening/splitting issues with
11873 // non-power-of-2 tuple types used for LD3, such as nxv12i32.
11874 SDValue AArch64TargetLowering::LowerSVEStructLoad(unsigned Intrinsic,
11875                                                   ArrayRef<SDValue> LoadOps,
11876                                                   EVT VT, SelectionDAG &DAG,
11877                                                   const SDLoc &DL) const {
11878   assert(VT.isScalableVector() && "Can only lower scalable vectors");
11879 
11880   unsigned N, Opcode;
11881   static std::map<unsigned, std::pair<unsigned, unsigned>> IntrinsicMap = {
11882       {Intrinsic::aarch64_sve_ld2, {2, AArch64ISD::SVE_LD2_MERGE_ZERO}},
11883       {Intrinsic::aarch64_sve_ld3, {3, AArch64ISD::SVE_LD3_MERGE_ZERO}},
11884       {Intrinsic::aarch64_sve_ld4, {4, AArch64ISD::SVE_LD4_MERGE_ZERO}}};
11885 
11886   std::tie(N, Opcode) = IntrinsicMap[Intrinsic];
11887   assert(VT.getVectorElementCount().getKnownMinValue() % N == 0 &&
11888          "invalid tuple vector type!");
11889 
11890   EVT SplitVT =
11891       EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
11892                        VT.getVectorElementCount().divideCoefficientBy(N));
11893   assert(isTypeLegal(SplitVT));
11894 
11895   SmallVector<EVT, 5> VTs(N, SplitVT);
11896   VTs.push_back(MVT::Other); // Chain
11897   SDVTList NodeTys = DAG.getVTList(VTs);
11898 
11899   SDValue PseudoLoad = DAG.getNode(Opcode, DL, NodeTys, LoadOps);
11900   SmallVector<SDValue, 4> PseudoLoadOps;
11901   for (unsigned I = 0; I < N; ++I)
11902     PseudoLoadOps.push_back(SDValue(PseudoLoad.getNode(), I));
11903   return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, PseudoLoadOps);
11904 }
11905 
11906 EVT AArch64TargetLowering::getOptimalMemOpType(
11907     const MemOp &Op, const AttributeList &FuncAttributes) const {
11908   bool CanImplicitFloat =
11909       !FuncAttributes.hasFnAttribute(Attribute::NoImplicitFloat);
11910   bool CanUseNEON = Subtarget->hasNEON() && CanImplicitFloat;
11911   bool CanUseFP = Subtarget->hasFPARMv8() && CanImplicitFloat;
11912   // Only use AdvSIMD to implement memset of 32-byte and above. It would have
11913   // taken one instruction to materialize the v2i64 zero and one store (with
11914   // restrictive addressing mode). Just do i64 stores.
11915   bool IsSmallMemset = Op.isMemset() && Op.size() < 32;
11916   auto AlignmentIsAcceptable = [&](EVT VT, Align AlignCheck) {
11917     if (Op.isAligned(AlignCheck))
11918       return true;
11919     bool Fast;
11920     return allowsMisalignedMemoryAccesses(VT, 0, Align(1),
11921                                           MachineMemOperand::MONone, &Fast) &&
11922            Fast;
11923   };
11924 
11925   if (CanUseNEON && Op.isMemset() && !IsSmallMemset &&
11926       AlignmentIsAcceptable(MVT::v2i64, Align(16)))
11927     return MVT::v2i64;
11928   if (CanUseFP && !IsSmallMemset && AlignmentIsAcceptable(MVT::f128, Align(16)))
11929     return MVT::f128;
11930   if (Op.size() >= 8 && AlignmentIsAcceptable(MVT::i64, Align(8)))
11931     return MVT::i64;
11932   if (Op.size() >= 4 && AlignmentIsAcceptable(MVT::i32, Align(4)))
11933     return MVT::i32;
11934   return MVT::Other;
11935 }
11936 
11937 LLT AArch64TargetLowering::getOptimalMemOpLLT(
11938     const MemOp &Op, const AttributeList &FuncAttributes) const {
11939   bool CanImplicitFloat =
11940       !FuncAttributes.hasFnAttribute(Attribute::NoImplicitFloat);
11941   bool CanUseNEON = Subtarget->hasNEON() && CanImplicitFloat;
11942   bool CanUseFP = Subtarget->hasFPARMv8() && CanImplicitFloat;
11943   // Only use AdvSIMD to implement memset of 32-byte and above. It would have
11944   // taken one instruction to materialize the v2i64 zero and one store (with
11945   // restrictive addressing mode). Just do i64 stores.
11946   bool IsSmallMemset = Op.isMemset() && Op.size() < 32;
11947   auto AlignmentIsAcceptable = [&](EVT VT, Align AlignCheck) {
11948     if (Op.isAligned(AlignCheck))
11949       return true;
11950     bool Fast;
11951     return allowsMisalignedMemoryAccesses(VT, 0, Align(1),
11952                                           MachineMemOperand::MONone, &Fast) &&
11953            Fast;
11954   };
11955 
11956   if (CanUseNEON && Op.isMemset() && !IsSmallMemset &&
11957       AlignmentIsAcceptable(MVT::v2i64, Align(16)))
11958     return LLT::fixed_vector(2, 64);
11959   if (CanUseFP && !IsSmallMemset && AlignmentIsAcceptable(MVT::f128, Align(16)))
11960     return LLT::scalar(128);
11961   if (Op.size() >= 8 && AlignmentIsAcceptable(MVT::i64, Align(8)))
11962     return LLT::scalar(64);
11963   if (Op.size() >= 4 && AlignmentIsAcceptable(MVT::i32, Align(4)))
11964     return LLT::scalar(32);
11965   return LLT();
11966 }
11967 
11968 // 12-bit optionally shifted immediates are legal for adds.
11969 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
11970   if (Immed == std::numeric_limits<int64_t>::min()) {
11971     LLVM_DEBUG(dbgs() << "Illegal add imm " << Immed
11972                       << ": avoid UB for INT64_MIN\n");
11973     return false;
11974   }
11975   // Same encoding for add/sub, just flip the sign.
11976   Immed = std::abs(Immed);
11977   bool IsLegal = ((Immed >> 12) == 0 ||
11978                   ((Immed & 0xfff) == 0 && Immed >> 24 == 0));
11979   LLVM_DEBUG(dbgs() << "Is " << Immed
11980                     << " legal add imm: " << (IsLegal ? "yes" : "no") << "\n");
11981   return IsLegal;
11982 }
11983 
11984 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
11985 // immediates is the same as for an add or a sub.
11986 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
11987   return isLegalAddImmediate(Immed);
11988 }
11989 
11990 /// isLegalAddressingMode - Return true if the addressing mode represented
11991 /// by AM is legal for this target, for a load/store of the specified type.
11992 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
11993                                                   const AddrMode &AM, Type *Ty,
11994                                                   unsigned AS, Instruction *I) const {
11995   // AArch64 has five basic addressing modes:
11996   //  reg
11997   //  reg + 9-bit signed offset
11998   //  reg + SIZE_IN_BYTES * 12-bit unsigned offset
11999   //  reg1 + reg2
12000   //  reg + SIZE_IN_BYTES * reg
12001 
12002   // No global is ever allowed as a base.
12003   if (AM.BaseGV)
12004     return false;
12005 
12006   // No reg+reg+imm addressing.
12007   if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
12008     return false;
12009 
12010   // FIXME: Update this method to support scalable addressing modes.
12011   if (isa<ScalableVectorType>(Ty)) {
12012     uint64_t VecElemNumBytes =
12013         DL.getTypeSizeInBits(cast<VectorType>(Ty)->getElementType()) / 8;
12014     return AM.HasBaseReg && !AM.BaseOffs &&
12015            (AM.Scale == 0 || (uint64_t)AM.Scale == VecElemNumBytes);
12016   }
12017 
12018   // check reg + imm case:
12019   // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
12020   uint64_t NumBytes = 0;
12021   if (Ty->isSized()) {
12022     uint64_t NumBits = DL.getTypeSizeInBits(Ty);
12023     NumBytes = NumBits / 8;
12024     if (!isPowerOf2_64(NumBits))
12025       NumBytes = 0;
12026   }
12027 
12028   if (!AM.Scale) {
12029     int64_t Offset = AM.BaseOffs;
12030 
12031     // 9-bit signed offset
12032     if (isInt<9>(Offset))
12033       return true;
12034 
12035     // 12-bit unsigned offset
12036     unsigned shift = Log2_64(NumBytes);
12037     if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
12038         // Must be a multiple of NumBytes (NumBytes is a power of 2)
12039         (Offset >> shift) << shift == Offset)
12040       return true;
12041     return false;
12042   }
12043 
12044   // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
12045 
12046   return AM.Scale == 1 || (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes);
12047 }
12048 
12049 bool AArch64TargetLowering::shouldConsiderGEPOffsetSplit() const {
12050   // Consider splitting large offset of struct or array.
12051   return true;
12052 }
12053 
12054 InstructionCost AArch64TargetLowering::getScalingFactorCost(
12055     const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const {
12056   // Scaling factors are not free at all.
12057   // Operands                     | Rt Latency
12058   // -------------------------------------------
12059   // Rt, [Xn, Xm]                 | 4
12060   // -------------------------------------------
12061   // Rt, [Xn, Xm, lsl #imm]       | Rn: 4 Rm: 5
12062   // Rt, [Xn, Wm, <extend> #imm]  |
12063   if (isLegalAddressingMode(DL, AM, Ty, AS))
12064     // Scale represents reg2 * scale, thus account for 1 if
12065     // it is not equal to 0 or 1.
12066     return AM.Scale != 0 && AM.Scale != 1;
12067   return -1;
12068 }
12069 
12070 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(
12071     const MachineFunction &MF, EVT VT) const {
12072   VT = VT.getScalarType();
12073 
12074   if (!VT.isSimple())
12075     return false;
12076 
12077   switch (VT.getSimpleVT().SimpleTy) {
12078   case MVT::f16:
12079     return Subtarget->hasFullFP16();
12080   case MVT::f32:
12081   case MVT::f64:
12082     return true;
12083   default:
12084     break;
12085   }
12086 
12087   return false;
12088 }
12089 
12090 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F,
12091                                                        Type *Ty) const {
12092   switch (Ty->getScalarType()->getTypeID()) {
12093   case Type::FloatTyID:
12094   case Type::DoubleTyID:
12095     return true;
12096   default:
12097     return false;
12098   }
12099 }
12100 
12101 bool AArch64TargetLowering::generateFMAsInMachineCombiner(
12102     EVT VT, CodeGenOpt::Level OptLevel) const {
12103   return (OptLevel >= CodeGenOpt::Aggressive) && !VT.isScalableVector();
12104 }
12105 
12106 const MCPhysReg *
12107 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
12108   // LR is a callee-save register, but we must treat it as clobbered by any call
12109   // site. Hence we include LR in the scratch registers, which are in turn added
12110   // as implicit-defs for stackmaps and patchpoints.
12111   static const MCPhysReg ScratchRegs[] = {
12112     AArch64::X16, AArch64::X17, AArch64::LR, 0
12113   };
12114   return ScratchRegs;
12115 }
12116 
12117 bool
12118 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
12119                                                      CombineLevel Level) const {
12120   N = N->getOperand(0).getNode();
12121   EVT VT = N->getValueType(0);
12122     // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
12123     // it with shift to let it be lowered to UBFX.
12124   if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
12125       isa<ConstantSDNode>(N->getOperand(1))) {
12126     uint64_t TruncMask = N->getConstantOperandVal(1);
12127     if (isMask_64(TruncMask) &&
12128       N->getOperand(0).getOpcode() == ISD::SRL &&
12129       isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
12130       return false;
12131   }
12132   return true;
12133 }
12134 
12135 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
12136                                                               Type *Ty) const {
12137   assert(Ty->isIntegerTy());
12138 
12139   unsigned BitSize = Ty->getPrimitiveSizeInBits();
12140   if (BitSize == 0)
12141     return false;
12142 
12143   int64_t Val = Imm.getSExtValue();
12144   if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
12145     return true;
12146 
12147   if ((int64_t)Val < 0)
12148     Val = ~Val;
12149   if (BitSize == 32)
12150     Val &= (1LL << 32) - 1;
12151 
12152   unsigned LZ = countLeadingZeros((uint64_t)Val);
12153   unsigned Shift = (63 - LZ) / 16;
12154   // MOVZ is free so return true for one or fewer MOVK.
12155   return Shift < 3;
12156 }
12157 
12158 bool AArch64TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
12159                                                     unsigned Index) const {
12160   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
12161     return false;
12162 
12163   return (Index == 0 || Index == ResVT.getVectorNumElements());
12164 }
12165 
12166 /// Turn vector tests of the signbit in the form of:
12167 ///   xor (sra X, elt_size(X)-1), -1
12168 /// into:
12169 ///   cmge X, X, #0
12170 static SDValue foldVectorXorShiftIntoCmp(SDNode *N, SelectionDAG &DAG,
12171                                          const AArch64Subtarget *Subtarget) {
12172   EVT VT = N->getValueType(0);
12173   if (!Subtarget->hasNEON() || !VT.isVector())
12174     return SDValue();
12175 
12176   // There must be a shift right algebraic before the xor, and the xor must be a
12177   // 'not' operation.
12178   SDValue Shift = N->getOperand(0);
12179   SDValue Ones = N->getOperand(1);
12180   if (Shift.getOpcode() != AArch64ISD::VASHR || !Shift.hasOneUse() ||
12181       !ISD::isBuildVectorAllOnes(Ones.getNode()))
12182     return SDValue();
12183 
12184   // The shift should be smearing the sign bit across each vector element.
12185   auto *ShiftAmt = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
12186   EVT ShiftEltTy = Shift.getValueType().getVectorElementType();
12187   if (!ShiftAmt || ShiftAmt->getZExtValue() != ShiftEltTy.getSizeInBits() - 1)
12188     return SDValue();
12189 
12190   return DAG.getNode(AArch64ISD::CMGEz, SDLoc(N), VT, Shift.getOperand(0));
12191 }
12192 
12193 // Given a vecreduce_add node, detect the below pattern and convert it to the
12194 // node sequence with UABDL, [S|U]ADB and UADDLP.
12195 //
12196 // i32 vecreduce_add(
12197 //  v16i32 abs(
12198 //    v16i32 sub(
12199 //     v16i32 [sign|zero]_extend(v16i8 a), v16i32 [sign|zero]_extend(v16i8 b))))
12200 // =================>
12201 // i32 vecreduce_add(
12202 //   v4i32 UADDLP(
12203 //     v8i16 add(
12204 //       v8i16 zext(
12205 //         v8i8 [S|U]ABD low8:v16i8 a, low8:v16i8 b
12206 //       v8i16 zext(
12207 //         v8i8 [S|U]ABD high8:v16i8 a, high8:v16i8 b
12208 static SDValue performVecReduceAddCombineWithUADDLP(SDNode *N,
12209                                                     SelectionDAG &DAG) {
12210   // Assumed i32 vecreduce_add
12211   if (N->getValueType(0) != MVT::i32)
12212     return SDValue();
12213 
12214   SDValue VecReduceOp0 = N->getOperand(0);
12215   unsigned Opcode = VecReduceOp0.getOpcode();
12216   // Assumed v16i32 abs
12217   if (Opcode != ISD::ABS || VecReduceOp0->getValueType(0) != MVT::v16i32)
12218     return SDValue();
12219 
12220   SDValue ABS = VecReduceOp0;
12221   // Assumed v16i32 sub
12222   if (ABS->getOperand(0)->getOpcode() != ISD::SUB ||
12223       ABS->getOperand(0)->getValueType(0) != MVT::v16i32)
12224     return SDValue();
12225 
12226   SDValue SUB = ABS->getOperand(0);
12227   unsigned Opcode0 = SUB->getOperand(0).getOpcode();
12228   unsigned Opcode1 = SUB->getOperand(1).getOpcode();
12229   // Assumed v16i32 type
12230   if (SUB->getOperand(0)->getValueType(0) != MVT::v16i32 ||
12231       SUB->getOperand(1)->getValueType(0) != MVT::v16i32)
12232     return SDValue();
12233 
12234   // Assumed zext or sext
12235   bool IsZExt = false;
12236   if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) {
12237     IsZExt = true;
12238   } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) {
12239     IsZExt = false;
12240   } else
12241     return SDValue();
12242 
12243   SDValue EXT0 = SUB->getOperand(0);
12244   SDValue EXT1 = SUB->getOperand(1);
12245   // Assumed zext's operand has v16i8 type
12246   if (EXT0->getOperand(0)->getValueType(0) != MVT::v16i8 ||
12247       EXT1->getOperand(0)->getValueType(0) != MVT::v16i8)
12248     return SDValue();
12249 
12250   // Pattern is dectected. Let's convert it to sequence of nodes.
12251   SDLoc DL(N);
12252 
12253   // First, create the node pattern of UABD/SABD.
12254   SDValue UABDHigh8Op0 =
12255       DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, EXT0->getOperand(0),
12256                   DAG.getConstant(8, DL, MVT::i64));
12257   SDValue UABDHigh8Op1 =
12258       DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, EXT1->getOperand(0),
12259                   DAG.getConstant(8, DL, MVT::i64));
12260   SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8,
12261                                   UABDHigh8Op0, UABDHigh8Op1);
12262   SDValue UABDL = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, UABDHigh8);
12263 
12264   // Second, create the node pattern of UABAL.
12265   SDValue UABDLo8Op0 =
12266       DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, EXT0->getOperand(0),
12267                   DAG.getConstant(0, DL, MVT::i64));
12268   SDValue UABDLo8Op1 =
12269       DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, EXT1->getOperand(0),
12270                   DAG.getConstant(0, DL, MVT::i64));
12271   SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8,
12272                                 UABDLo8Op0, UABDLo8Op1);
12273   SDValue ZExtUABD = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, UABDLo8);
12274   SDValue UABAL = DAG.getNode(ISD::ADD, DL, MVT::v8i16, UABDL, ZExtUABD);
12275 
12276   // Third, create the node of UADDLP.
12277   SDValue UADDLP = DAG.getNode(AArch64ISD::UADDLP, DL, MVT::v4i32, UABAL);
12278 
12279   // Fourth, create the node of VECREDUCE_ADD.
12280   return DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, UADDLP);
12281 }
12282 
12283 // Turn a v8i8/v16i8 extended vecreduce into a udot/sdot and vecreduce
12284 //   vecreduce.add(ext(A)) to vecreduce.add(DOT(zero, A, one))
12285 //   vecreduce.add(mul(ext(A), ext(B))) to vecreduce.add(DOT(zero, A, B))
12286 static SDValue performVecReduceAddCombine(SDNode *N, SelectionDAG &DAG,
12287                                           const AArch64Subtarget *ST) {
12288   if (!ST->hasDotProd())
12289     return performVecReduceAddCombineWithUADDLP(N, DAG);
12290 
12291   SDValue Op0 = N->getOperand(0);
12292   if (N->getValueType(0) != MVT::i32 ||
12293       Op0.getValueType().getVectorElementType() != MVT::i32)
12294     return SDValue();
12295 
12296   unsigned ExtOpcode = Op0.getOpcode();
12297   SDValue A = Op0;
12298   SDValue B;
12299   if (ExtOpcode == ISD::MUL) {
12300     A = Op0.getOperand(0);
12301     B = Op0.getOperand(1);
12302     if (A.getOpcode() != B.getOpcode() ||
12303         A.getOperand(0).getValueType() != B.getOperand(0).getValueType())
12304       return SDValue();
12305     ExtOpcode = A.getOpcode();
12306   }
12307   if (ExtOpcode != ISD::ZERO_EXTEND && ExtOpcode != ISD::SIGN_EXTEND)
12308     return SDValue();
12309 
12310   EVT Op0VT = A.getOperand(0).getValueType();
12311   if (Op0VT != MVT::v8i8 && Op0VT != MVT::v16i8)
12312     return SDValue();
12313 
12314   SDLoc DL(Op0);
12315   // For non-mla reductions B can be set to 1. For MLA we take the operand of
12316   // the extend B.
12317   if (!B)
12318     B = DAG.getConstant(1, DL, Op0VT);
12319   else
12320     B = B.getOperand(0);
12321 
12322   SDValue Zeros =
12323       DAG.getConstant(0, DL, Op0VT == MVT::v8i8 ? MVT::v2i32 : MVT::v4i32);
12324   auto DotOpcode =
12325       (ExtOpcode == ISD::ZERO_EXTEND) ? AArch64ISD::UDOT : AArch64ISD::SDOT;
12326   SDValue Dot = DAG.getNode(DotOpcode, DL, Zeros.getValueType(), Zeros,
12327                             A.getOperand(0), B);
12328   return DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0), Dot);
12329 }
12330 
12331 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
12332                                  TargetLowering::DAGCombinerInfo &DCI,
12333                                  const AArch64Subtarget *Subtarget) {
12334   if (DCI.isBeforeLegalizeOps())
12335     return SDValue();
12336 
12337   return foldVectorXorShiftIntoCmp(N, DAG, Subtarget);
12338 }
12339 
12340 SDValue
12341 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
12342                                      SelectionDAG &DAG,
12343                                      SmallVectorImpl<SDNode *> &Created) const {
12344   AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
12345   if (isIntDivCheap(N->getValueType(0), Attr))
12346     return SDValue(N,0); // Lower SDIV as SDIV
12347 
12348   // fold (sdiv X, pow2)
12349   EVT VT = N->getValueType(0);
12350   if ((VT != MVT::i32 && VT != MVT::i64) ||
12351       !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
12352     return SDValue();
12353 
12354   SDLoc DL(N);
12355   SDValue N0 = N->getOperand(0);
12356   unsigned Lg2 = Divisor.countTrailingZeros();
12357   SDValue Zero = DAG.getConstant(0, DL, VT);
12358   SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
12359 
12360   // Add (N0 < 0) ? Pow2 - 1 : 0;
12361   SDValue CCVal;
12362   SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
12363   SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
12364   SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
12365 
12366   Created.push_back(Cmp.getNode());
12367   Created.push_back(Add.getNode());
12368   Created.push_back(CSel.getNode());
12369 
12370   // Divide by pow2.
12371   SDValue SRA =
12372       DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
12373 
12374   // If we're dividing by a positive value, we're done.  Otherwise, we must
12375   // negate the result.
12376   if (Divisor.isNonNegative())
12377     return SRA;
12378 
12379   Created.push_back(SRA.getNode());
12380   return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
12381 }
12382 
12383 static bool IsSVECntIntrinsic(SDValue S) {
12384   switch(getIntrinsicID(S.getNode())) {
12385   default:
12386     break;
12387   case Intrinsic::aarch64_sve_cntb:
12388   case Intrinsic::aarch64_sve_cnth:
12389   case Intrinsic::aarch64_sve_cntw:
12390   case Intrinsic::aarch64_sve_cntd:
12391     return true;
12392   }
12393   return false;
12394 }
12395 
12396 /// Calculates what the pre-extend type is, based on the extension
12397 /// operation node provided by \p Extend.
12398 ///
12399 /// In the case that \p Extend is a SIGN_EXTEND or a ZERO_EXTEND, the
12400 /// pre-extend type is pulled directly from the operand, while other extend
12401 /// operations need a bit more inspection to get this information.
12402 ///
12403 /// \param Extend The SDNode from the DAG that represents the extend operation
12404 /// \param DAG The SelectionDAG hosting the \p Extend node
12405 ///
12406 /// \returns The type representing the \p Extend source type, or \p MVT::Other
12407 /// if no valid type can be determined
12408 static EVT calculatePreExtendType(SDValue Extend, SelectionDAG &DAG) {
12409   switch (Extend.getOpcode()) {
12410   case ISD::SIGN_EXTEND:
12411   case ISD::ZERO_EXTEND:
12412     return Extend.getOperand(0).getValueType();
12413   case ISD::AssertSext:
12414   case ISD::AssertZext:
12415   case ISD::SIGN_EXTEND_INREG: {
12416     VTSDNode *TypeNode = dyn_cast<VTSDNode>(Extend.getOperand(1));
12417     if (!TypeNode)
12418       return MVT::Other;
12419     return TypeNode->getVT();
12420   }
12421   case ISD::AND: {
12422     ConstantSDNode *Constant =
12423         dyn_cast<ConstantSDNode>(Extend.getOperand(1).getNode());
12424     if (!Constant)
12425       return MVT::Other;
12426 
12427     uint32_t Mask = Constant->getZExtValue();
12428 
12429     if (Mask == UCHAR_MAX)
12430       return MVT::i8;
12431     else if (Mask == USHRT_MAX)
12432       return MVT::i16;
12433     else if (Mask == UINT_MAX)
12434       return MVT::i32;
12435 
12436     return MVT::Other;
12437   }
12438   default:
12439     return MVT::Other;
12440   }
12441 
12442   llvm_unreachable("Code path unhandled in calculatePreExtendType!");
12443 }
12444 
12445 /// Combines a dup(sext/zext) node pattern into sext/zext(dup)
12446 /// making use of the vector SExt/ZExt rather than the scalar SExt/ZExt
12447 static SDValue performCommonVectorExtendCombine(SDValue VectorShuffle,
12448                                                 SelectionDAG &DAG) {
12449 
12450   ShuffleVectorSDNode *ShuffleNode =
12451       dyn_cast<ShuffleVectorSDNode>(VectorShuffle.getNode());
12452   if (!ShuffleNode)
12453     return SDValue();
12454 
12455   // Ensuring the mask is zero before continuing
12456   if (!ShuffleNode->isSplat() || ShuffleNode->getSplatIndex() != 0)
12457     return SDValue();
12458 
12459   SDValue InsertVectorElt = VectorShuffle.getOperand(0);
12460 
12461   if (InsertVectorElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
12462     return SDValue();
12463 
12464   SDValue InsertLane = InsertVectorElt.getOperand(2);
12465   ConstantSDNode *Constant = dyn_cast<ConstantSDNode>(InsertLane.getNode());
12466   // Ensures the insert is inserting into lane 0
12467   if (!Constant || Constant->getZExtValue() != 0)
12468     return SDValue();
12469 
12470   SDValue Extend = InsertVectorElt.getOperand(1);
12471   unsigned ExtendOpcode = Extend.getOpcode();
12472 
12473   bool IsSExt = ExtendOpcode == ISD::SIGN_EXTEND ||
12474                 ExtendOpcode == ISD::SIGN_EXTEND_INREG ||
12475                 ExtendOpcode == ISD::AssertSext;
12476   if (!IsSExt && ExtendOpcode != ISD::ZERO_EXTEND &&
12477       ExtendOpcode != ISD::AssertZext && ExtendOpcode != ISD::AND)
12478     return SDValue();
12479 
12480   EVT TargetType = VectorShuffle.getValueType();
12481   EVT PreExtendType = calculatePreExtendType(Extend, DAG);
12482 
12483   if ((TargetType != MVT::v8i16 && TargetType != MVT::v4i32 &&
12484        TargetType != MVT::v2i64) ||
12485       (PreExtendType == MVT::Other))
12486     return SDValue();
12487 
12488   // Restrict valid pre-extend data type
12489   if (PreExtendType != MVT::i8 && PreExtendType != MVT::i16 &&
12490       PreExtendType != MVT::i32)
12491     return SDValue();
12492 
12493   EVT PreExtendVT = TargetType.changeVectorElementType(PreExtendType);
12494 
12495   if (PreExtendVT.getVectorElementCount() != TargetType.getVectorElementCount())
12496     return SDValue();
12497 
12498   if (TargetType.getScalarSizeInBits() != PreExtendVT.getScalarSizeInBits() * 2)
12499     return SDValue();
12500 
12501   SDLoc DL(VectorShuffle);
12502 
12503   SDValue InsertVectorNode = DAG.getNode(
12504       InsertVectorElt.getOpcode(), DL, PreExtendVT, DAG.getUNDEF(PreExtendVT),
12505       DAG.getAnyExtOrTrunc(Extend.getOperand(0), DL, PreExtendType),
12506       DAG.getConstant(0, DL, MVT::i64));
12507 
12508   std::vector<int> ShuffleMask(TargetType.getVectorElementCount().getValue());
12509 
12510   SDValue VectorShuffleNode =
12511       DAG.getVectorShuffle(PreExtendVT, DL, InsertVectorNode,
12512                            DAG.getUNDEF(PreExtendVT), ShuffleMask);
12513 
12514   SDValue ExtendNode = DAG.getNode(IsSExt ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
12515                                    DL, TargetType, VectorShuffleNode);
12516 
12517   return ExtendNode;
12518 }
12519 
12520 /// Combines a mul(dup(sext/zext)) node pattern into mul(sext/zext(dup))
12521 /// making use of the vector SExt/ZExt rather than the scalar SExt/ZExt
12522 static SDValue performMulVectorExtendCombine(SDNode *Mul, SelectionDAG &DAG) {
12523   // If the value type isn't a vector, none of the operands are going to be dups
12524   if (!Mul->getValueType(0).isVector())
12525     return SDValue();
12526 
12527   SDValue Op0 = performCommonVectorExtendCombine(Mul->getOperand(0), DAG);
12528   SDValue Op1 = performCommonVectorExtendCombine(Mul->getOperand(1), DAG);
12529 
12530   // Neither operands have been changed, don't make any further changes
12531   if (!Op0 && !Op1)
12532     return SDValue();
12533 
12534   SDLoc DL(Mul);
12535   return DAG.getNode(Mul->getOpcode(), DL, Mul->getValueType(0),
12536                      Op0 ? Op0 : Mul->getOperand(0),
12537                      Op1 ? Op1 : Mul->getOperand(1));
12538 }
12539 
12540 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
12541                                  TargetLowering::DAGCombinerInfo &DCI,
12542                                  const AArch64Subtarget *Subtarget) {
12543 
12544   if (SDValue Ext = performMulVectorExtendCombine(N, DAG))
12545     return Ext;
12546 
12547   if (DCI.isBeforeLegalizeOps())
12548     return SDValue();
12549 
12550   // The below optimizations require a constant RHS.
12551   if (!isa<ConstantSDNode>(N->getOperand(1)))
12552     return SDValue();
12553 
12554   SDValue N0 = N->getOperand(0);
12555   ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
12556   const APInt &ConstValue = C->getAPIntValue();
12557 
12558   // Allow the scaling to be folded into the `cnt` instruction by preventing
12559   // the scaling to be obscured here. This makes it easier to pattern match.
12560   if (IsSVECntIntrinsic(N0) ||
12561      (N0->getOpcode() == ISD::TRUNCATE &&
12562       (IsSVECntIntrinsic(N0->getOperand(0)))))
12563        if (ConstValue.sge(1) && ConstValue.sle(16))
12564          return SDValue();
12565 
12566   // Multiplication of a power of two plus/minus one can be done more
12567   // cheaply as as shift+add/sub. For now, this is true unilaterally. If
12568   // future CPUs have a cheaper MADD instruction, this may need to be
12569   // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
12570   // 64-bit is 5 cycles, so this is always a win.
12571   // More aggressively, some multiplications N0 * C can be lowered to
12572   // shift+add+shift if the constant C = A * B where A = 2^N + 1 and B = 2^M,
12573   // e.g. 6=3*2=(2+1)*2.
12574   // TODO: consider lowering more cases, e.g. C = 14, -6, -14 or even 45
12575   // which equals to (1+2)*16-(1+2).
12576 
12577   // TrailingZeroes is used to test if the mul can be lowered to
12578   // shift+add+shift.
12579   unsigned TrailingZeroes = ConstValue.countTrailingZeros();
12580   if (TrailingZeroes) {
12581     // Conservatively do not lower to shift+add+shift if the mul might be
12582     // folded into smul or umul.
12583     if (N0->hasOneUse() && (isSignExtended(N0.getNode(), DAG) ||
12584                             isZeroExtended(N0.getNode(), DAG)))
12585       return SDValue();
12586     // Conservatively do not lower to shift+add+shift if the mul might be
12587     // folded into madd or msub.
12588     if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ADD ||
12589                            N->use_begin()->getOpcode() == ISD::SUB))
12590       return SDValue();
12591   }
12592   // Use ShiftedConstValue instead of ConstValue to support both shift+add/sub
12593   // and shift+add+shift.
12594   APInt ShiftedConstValue = ConstValue.ashr(TrailingZeroes);
12595 
12596   unsigned ShiftAmt, AddSubOpc;
12597   // Is the shifted value the LHS operand of the add/sub?
12598   bool ShiftValUseIsN0 = true;
12599   // Do we need to negate the result?
12600   bool NegateResult = false;
12601 
12602   if (ConstValue.isNonNegative()) {
12603     // (mul x, 2^N + 1) => (add (shl x, N), x)
12604     // (mul x, 2^N - 1) => (sub (shl x, N), x)
12605     // (mul x, (2^N + 1) * 2^M) => (shl (add (shl x, N), x), M)
12606     APInt SCVMinus1 = ShiftedConstValue - 1;
12607     APInt CVPlus1 = ConstValue + 1;
12608     if (SCVMinus1.isPowerOf2()) {
12609       ShiftAmt = SCVMinus1.logBase2();
12610       AddSubOpc = ISD::ADD;
12611     } else if (CVPlus1.isPowerOf2()) {
12612       ShiftAmt = CVPlus1.logBase2();
12613       AddSubOpc = ISD::SUB;
12614     } else
12615       return SDValue();
12616   } else {
12617     // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
12618     // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
12619     APInt CVNegPlus1 = -ConstValue + 1;
12620     APInt CVNegMinus1 = -ConstValue - 1;
12621     if (CVNegPlus1.isPowerOf2()) {
12622       ShiftAmt = CVNegPlus1.logBase2();
12623       AddSubOpc = ISD::SUB;
12624       ShiftValUseIsN0 = false;
12625     } else if (CVNegMinus1.isPowerOf2()) {
12626       ShiftAmt = CVNegMinus1.logBase2();
12627       AddSubOpc = ISD::ADD;
12628       NegateResult = true;
12629     } else
12630       return SDValue();
12631   }
12632 
12633   SDLoc DL(N);
12634   EVT VT = N->getValueType(0);
12635   SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0,
12636                                    DAG.getConstant(ShiftAmt, DL, MVT::i64));
12637 
12638   SDValue AddSubN0 = ShiftValUseIsN0 ? ShiftedVal : N0;
12639   SDValue AddSubN1 = ShiftValUseIsN0 ? N0 : ShiftedVal;
12640   SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1);
12641   assert(!(NegateResult && TrailingZeroes) &&
12642          "NegateResult and TrailingZeroes cannot both be true for now.");
12643   // Negate the result.
12644   if (NegateResult)
12645     return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Res);
12646   // Shift the result.
12647   if (TrailingZeroes)
12648     return DAG.getNode(ISD::SHL, DL, VT, Res,
12649                        DAG.getConstant(TrailingZeroes, DL, MVT::i64));
12650   return Res;
12651 }
12652 
12653 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
12654                                                          SelectionDAG &DAG) {
12655   // Take advantage of vector comparisons producing 0 or -1 in each lane to
12656   // optimize away operation when it's from a constant.
12657   //
12658   // The general transformation is:
12659   //    UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
12660   //       AND(VECTOR_CMP(x,y), constant2)
12661   //    constant2 = UNARYOP(constant)
12662 
12663   // Early exit if this isn't a vector operation, the operand of the
12664   // unary operation isn't a bitwise AND, or if the sizes of the operations
12665   // aren't the same.
12666   EVT VT = N->getValueType(0);
12667   if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
12668       N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
12669       VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
12670     return SDValue();
12671 
12672   // Now check that the other operand of the AND is a constant. We could
12673   // make the transformation for non-constant splats as well, but it's unclear
12674   // that would be a benefit as it would not eliminate any operations, just
12675   // perform one more step in scalar code before moving to the vector unit.
12676   if (BuildVectorSDNode *BV =
12677           dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
12678     // Bail out if the vector isn't a constant.
12679     if (!BV->isConstant())
12680       return SDValue();
12681 
12682     // Everything checks out. Build up the new and improved node.
12683     SDLoc DL(N);
12684     EVT IntVT = BV->getValueType(0);
12685     // Create a new constant of the appropriate type for the transformed
12686     // DAG.
12687     SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
12688     // The AND node needs bitcasts to/from an integer vector type around it.
12689     SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
12690     SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
12691                                  N->getOperand(0)->getOperand(0), MaskConst);
12692     SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
12693     return Res;
12694   }
12695 
12696   return SDValue();
12697 }
12698 
12699 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
12700                                      const AArch64Subtarget *Subtarget) {
12701   // First try to optimize away the conversion when it's conditionally from
12702   // a constant. Vectors only.
12703   if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
12704     return Res;
12705 
12706   EVT VT = N->getValueType(0);
12707   if (VT != MVT::f32 && VT != MVT::f64)
12708     return SDValue();
12709 
12710   // Only optimize when the source and destination types have the same width.
12711   if (VT.getSizeInBits() != N->getOperand(0).getValueSizeInBits())
12712     return SDValue();
12713 
12714   // If the result of an integer load is only used by an integer-to-float
12715   // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
12716   // This eliminates an "integer-to-vector-move" UOP and improves throughput.
12717   SDValue N0 = N->getOperand(0);
12718   if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
12719       // Do not change the width of a volatile load.
12720       !cast<LoadSDNode>(N0)->isVolatile()) {
12721     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
12722     SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
12723                                LN0->getPointerInfo(), LN0->getAlignment(),
12724                                LN0->getMemOperand()->getFlags());
12725 
12726     // Make sure successors of the original load stay after it by updating them
12727     // to use the new Chain.
12728     DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
12729 
12730     unsigned Opcode =
12731         (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
12732     return DAG.getNode(Opcode, SDLoc(N), VT, Load);
12733   }
12734 
12735   return SDValue();
12736 }
12737 
12738 /// Fold a floating-point multiply by power of two into floating-point to
12739 /// fixed-point conversion.
12740 static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
12741                                      TargetLowering::DAGCombinerInfo &DCI,
12742                                      const AArch64Subtarget *Subtarget) {
12743   if (!Subtarget->hasNEON())
12744     return SDValue();
12745 
12746   if (!N->getValueType(0).isSimple())
12747     return SDValue();
12748 
12749   SDValue Op = N->getOperand(0);
12750   if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
12751       Op.getOpcode() != ISD::FMUL)
12752     return SDValue();
12753 
12754   SDValue ConstVec = Op->getOperand(1);
12755   if (!isa<BuildVectorSDNode>(ConstVec))
12756     return SDValue();
12757 
12758   MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
12759   uint32_t FloatBits = FloatTy.getSizeInBits();
12760   if (FloatBits != 32 && FloatBits != 64)
12761     return SDValue();
12762 
12763   MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
12764   uint32_t IntBits = IntTy.getSizeInBits();
12765   if (IntBits != 16 && IntBits != 32 && IntBits != 64)
12766     return SDValue();
12767 
12768   // Avoid conversions where iN is larger than the float (e.g., float -> i64).
12769   if (IntBits > FloatBits)
12770     return SDValue();
12771 
12772   BitVector UndefElements;
12773   BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
12774   int32_t Bits = IntBits == 64 ? 64 : 32;
12775   int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, Bits + 1);
12776   if (C == -1 || C == 0 || C > Bits)
12777     return SDValue();
12778 
12779   MVT ResTy;
12780   unsigned NumLanes = Op.getValueType().getVectorNumElements();
12781   switch (NumLanes) {
12782   default:
12783     return SDValue();
12784   case 2:
12785     ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
12786     break;
12787   case 4:
12788     ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64;
12789     break;
12790   }
12791 
12792   if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
12793     return SDValue();
12794 
12795   assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) &&
12796          "Illegal vector type after legalization");
12797 
12798   SDLoc DL(N);
12799   bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12800   unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfp2fxs
12801                                       : Intrinsic::aarch64_neon_vcvtfp2fxu;
12802   SDValue FixConv =
12803       DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, ResTy,
12804                   DAG.getConstant(IntrinsicOpcode, DL, MVT::i32),
12805                   Op->getOperand(0), DAG.getConstant(C, DL, MVT::i32));
12806   // We can handle smaller integers by generating an extra trunc.
12807   if (IntBits < FloatBits)
12808     FixConv = DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), FixConv);
12809 
12810   return FixConv;
12811 }
12812 
12813 /// Fold a floating-point divide by power of two into fixed-point to
12814 /// floating-point conversion.
12815 static SDValue performFDivCombine(SDNode *N, SelectionDAG &DAG,
12816                                   TargetLowering::DAGCombinerInfo &DCI,
12817                                   const AArch64Subtarget *Subtarget) {
12818   if (!Subtarget->hasNEON())
12819     return SDValue();
12820 
12821   SDValue Op = N->getOperand(0);
12822   unsigned Opc = Op->getOpcode();
12823   if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
12824       !Op.getOperand(0).getValueType().isSimple() ||
12825       (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP))
12826     return SDValue();
12827 
12828   SDValue ConstVec = N->getOperand(1);
12829   if (!isa<BuildVectorSDNode>(ConstVec))
12830     return SDValue();
12831 
12832   MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
12833   int32_t IntBits = IntTy.getSizeInBits();
12834   if (IntBits != 16 && IntBits != 32 && IntBits != 64)
12835     return SDValue();
12836 
12837   MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
12838   int32_t FloatBits = FloatTy.getSizeInBits();
12839   if (FloatBits != 32 && FloatBits != 64)
12840     return SDValue();
12841 
12842   // Avoid conversions where iN is larger than the float (e.g., i64 -> float).
12843   if (IntBits > FloatBits)
12844     return SDValue();
12845 
12846   BitVector UndefElements;
12847   BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
12848   int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, FloatBits + 1);
12849   if (C == -1 || C == 0 || C > FloatBits)
12850     return SDValue();
12851 
12852   MVT ResTy;
12853   unsigned NumLanes = Op.getValueType().getVectorNumElements();
12854   switch (NumLanes) {
12855   default:
12856     return SDValue();
12857   case 2:
12858     ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
12859     break;
12860   case 4:
12861     ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64;
12862     break;
12863   }
12864 
12865   if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
12866     return SDValue();
12867 
12868   SDLoc DL(N);
12869   SDValue ConvInput = Op.getOperand(0);
12870   bool IsSigned = Opc == ISD::SINT_TO_FP;
12871   if (IntBits < FloatBits)
12872     ConvInput = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL,
12873                             ResTy, ConvInput);
12874 
12875   unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfxs2fp
12876                                       : Intrinsic::aarch64_neon_vcvtfxu2fp;
12877   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(),
12878                      DAG.getConstant(IntrinsicOpcode, DL, MVT::i32), ConvInput,
12879                      DAG.getConstant(C, DL, MVT::i32));
12880 }
12881 
12882 /// An EXTR instruction is made up of two shifts, ORed together. This helper
12883 /// searches for and classifies those shifts.
12884 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
12885                          bool &FromHi) {
12886   if (N.getOpcode() == ISD::SHL)
12887     FromHi = false;
12888   else if (N.getOpcode() == ISD::SRL)
12889     FromHi = true;
12890   else
12891     return false;
12892 
12893   if (!isa<ConstantSDNode>(N.getOperand(1)))
12894     return false;
12895 
12896   ShiftAmount = N->getConstantOperandVal(1);
12897   Src = N->getOperand(0);
12898   return true;
12899 }
12900 
12901 /// EXTR instruction extracts a contiguous chunk of bits from two existing
12902 /// registers viewed as a high/low pair. This function looks for the pattern:
12903 /// <tt>(or (shl VAL1, \#N), (srl VAL2, \#RegWidth-N))</tt> and replaces it
12904 /// with an EXTR. Can't quite be done in TableGen because the two immediates
12905 /// aren't independent.
12906 static SDValue tryCombineToEXTR(SDNode *N,
12907                                 TargetLowering::DAGCombinerInfo &DCI) {
12908   SelectionDAG &DAG = DCI.DAG;
12909   SDLoc DL(N);
12910   EVT VT = N->getValueType(0);
12911 
12912   assert(N->getOpcode() == ISD::OR && "Unexpected root");
12913 
12914   if (VT != MVT::i32 && VT != MVT::i64)
12915     return SDValue();
12916 
12917   SDValue LHS;
12918   uint32_t ShiftLHS = 0;
12919   bool LHSFromHi = false;
12920   if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
12921     return SDValue();
12922 
12923   SDValue RHS;
12924   uint32_t ShiftRHS = 0;
12925   bool RHSFromHi = false;
12926   if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
12927     return SDValue();
12928 
12929   // If they're both trying to come from the high part of the register, they're
12930   // not really an EXTR.
12931   if (LHSFromHi == RHSFromHi)
12932     return SDValue();
12933 
12934   if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
12935     return SDValue();
12936 
12937   if (LHSFromHi) {
12938     std::swap(LHS, RHS);
12939     std::swap(ShiftLHS, ShiftRHS);
12940   }
12941 
12942   return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
12943                      DAG.getConstant(ShiftRHS, DL, MVT::i64));
12944 }
12945 
12946 static SDValue tryCombineToBSL(SDNode *N,
12947                                 TargetLowering::DAGCombinerInfo &DCI) {
12948   EVT VT = N->getValueType(0);
12949   SelectionDAG &DAG = DCI.DAG;
12950   SDLoc DL(N);
12951 
12952   if (!VT.isVector())
12953     return SDValue();
12954 
12955   // The combining code currently only works for NEON vectors. In particular,
12956   // it does not work for SVE when dealing with vectors wider than 128 bits.
12957   if (!VT.is64BitVector() && !VT.is128BitVector())
12958     return SDValue();
12959 
12960   SDValue N0 = N->getOperand(0);
12961   if (N0.getOpcode() != ISD::AND)
12962     return SDValue();
12963 
12964   SDValue N1 = N->getOperand(1);
12965   if (N1.getOpcode() != ISD::AND)
12966     return SDValue();
12967 
12968   // InstCombine does (not (neg a)) => (add a -1).
12969   // Try: (or (and (neg a) b) (and (add a -1) c)) => (bsl (neg a) b c)
12970   // Loop over all combinations of AND operands.
12971   for (int i = 1; i >= 0; --i) {
12972     for (int j = 1; j >= 0; --j) {
12973       SDValue O0 = N0->getOperand(i);
12974       SDValue O1 = N1->getOperand(j);
12975       SDValue Sub, Add, SubSibling, AddSibling;
12976 
12977       // Find a SUB and an ADD operand, one from each AND.
12978       if (O0.getOpcode() == ISD::SUB && O1.getOpcode() == ISD::ADD) {
12979         Sub = O0;
12980         Add = O1;
12981         SubSibling = N0->getOperand(1 - i);
12982         AddSibling = N1->getOperand(1 - j);
12983       } else if (O0.getOpcode() == ISD::ADD && O1.getOpcode() == ISD::SUB) {
12984         Add = O0;
12985         Sub = O1;
12986         AddSibling = N0->getOperand(1 - i);
12987         SubSibling = N1->getOperand(1 - j);
12988       } else
12989         continue;
12990 
12991       if (!ISD::isBuildVectorAllZeros(Sub.getOperand(0).getNode()))
12992         continue;
12993 
12994       // Constant ones is always righthand operand of the Add.
12995       if (!ISD::isBuildVectorAllOnes(Add.getOperand(1).getNode()))
12996         continue;
12997 
12998       if (Sub.getOperand(1) != Add.getOperand(0))
12999         continue;
13000 
13001       return DAG.getNode(AArch64ISD::BSP, DL, VT, Sub, SubSibling, AddSibling);
13002     }
13003   }
13004 
13005   // (or (and a b) (and (not a) c)) => (bsl a b c)
13006   // We only have to look for constant vectors here since the general, variable
13007   // case can be handled in TableGen.
13008   unsigned Bits = VT.getScalarSizeInBits();
13009   uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
13010   for (int i = 1; i >= 0; --i)
13011     for (int j = 1; j >= 0; --j) {
13012       BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
13013       BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
13014       if (!BVN0 || !BVN1)
13015         continue;
13016 
13017       bool FoundMatch = true;
13018       for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
13019         ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
13020         ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
13021         if (!CN0 || !CN1 ||
13022             CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
13023           FoundMatch = false;
13024           break;
13025         }
13026       }
13027 
13028       if (FoundMatch)
13029         return DAG.getNode(AArch64ISD::BSP, DL, VT, SDValue(BVN0, 0),
13030                            N0->getOperand(1 - i), N1->getOperand(1 - j));
13031     }
13032 
13033   return SDValue();
13034 }
13035 
13036 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
13037                                 const AArch64Subtarget *Subtarget) {
13038   // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
13039   SelectionDAG &DAG = DCI.DAG;
13040   EVT VT = N->getValueType(0);
13041 
13042   if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13043     return SDValue();
13044 
13045   if (SDValue Res = tryCombineToEXTR(N, DCI))
13046     return Res;
13047 
13048   if (SDValue Res = tryCombineToBSL(N, DCI))
13049     return Res;
13050 
13051   return SDValue();
13052 }
13053 
13054 static bool isConstantSplatVectorMaskForType(SDNode *N, EVT MemVT) {
13055   if (!MemVT.getVectorElementType().isSimple())
13056     return false;
13057 
13058   uint64_t MaskForTy = 0ull;
13059   switch (MemVT.getVectorElementType().getSimpleVT().SimpleTy) {
13060   case MVT::i8:
13061     MaskForTy = 0xffull;
13062     break;
13063   case MVT::i16:
13064     MaskForTy = 0xffffull;
13065     break;
13066   case MVT::i32:
13067     MaskForTy = 0xffffffffull;
13068     break;
13069   default:
13070     return false;
13071     break;
13072   }
13073 
13074   if (N->getOpcode() == AArch64ISD::DUP || N->getOpcode() == ISD::SPLAT_VECTOR)
13075     if (auto *Op0 = dyn_cast<ConstantSDNode>(N->getOperand(0)))
13076       return Op0->getAPIntValue().getLimitedValue() == MaskForTy;
13077 
13078   return false;
13079 }
13080 
13081 static SDValue performSVEAndCombine(SDNode *N,
13082                                     TargetLowering::DAGCombinerInfo &DCI) {
13083   if (DCI.isBeforeLegalizeOps())
13084     return SDValue();
13085 
13086   SelectionDAG &DAG = DCI.DAG;
13087   SDValue Src = N->getOperand(0);
13088   unsigned Opc = Src->getOpcode();
13089 
13090   // Zero/any extend of an unsigned unpack
13091   if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) {
13092     SDValue UnpkOp = Src->getOperand(0);
13093     SDValue Dup = N->getOperand(1);
13094 
13095     if (Dup.getOpcode() != AArch64ISD::DUP)
13096       return SDValue();
13097 
13098     SDLoc DL(N);
13099     ConstantSDNode *C = dyn_cast<ConstantSDNode>(Dup->getOperand(0));
13100     uint64_t ExtVal = C->getZExtValue();
13101 
13102     // If the mask is fully covered by the unpack, we don't need to push
13103     // a new AND onto the operand
13104     EVT EltTy = UnpkOp->getValueType(0).getVectorElementType();
13105     if ((ExtVal == 0xFF && EltTy == MVT::i8) ||
13106         (ExtVal == 0xFFFF && EltTy == MVT::i16) ||
13107         (ExtVal == 0xFFFFFFFF && EltTy == MVT::i32))
13108       return Src;
13109 
13110     // Truncate to prevent a DUP with an over wide constant
13111     APInt Mask = C->getAPIntValue().trunc(EltTy.getSizeInBits());
13112 
13113     // Otherwise, make sure we propagate the AND to the operand
13114     // of the unpack
13115     Dup = DAG.getNode(AArch64ISD::DUP, DL,
13116                       UnpkOp->getValueType(0),
13117                       DAG.getConstant(Mask.zextOrTrunc(32), DL, MVT::i32));
13118 
13119     SDValue And = DAG.getNode(ISD::AND, DL,
13120                               UnpkOp->getValueType(0), UnpkOp, Dup);
13121 
13122     return DAG.getNode(Opc, DL, N->getValueType(0), And);
13123   }
13124 
13125   if (!EnableCombineMGatherIntrinsics)
13126     return SDValue();
13127 
13128   SDValue Mask = N->getOperand(1);
13129 
13130   if (!Src.hasOneUse())
13131     return SDValue();
13132 
13133   EVT MemVT;
13134 
13135   // SVE load instructions perform an implicit zero-extend, which makes them
13136   // perfect candidates for combining.
13137   switch (Opc) {
13138   case AArch64ISD::LD1_MERGE_ZERO:
13139   case AArch64ISD::LDNF1_MERGE_ZERO:
13140   case AArch64ISD::LDFF1_MERGE_ZERO:
13141     MemVT = cast<VTSDNode>(Src->getOperand(3))->getVT();
13142     break;
13143   case AArch64ISD::GLD1_MERGE_ZERO:
13144   case AArch64ISD::GLD1_SCALED_MERGE_ZERO:
13145   case AArch64ISD::GLD1_SXTW_MERGE_ZERO:
13146   case AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO:
13147   case AArch64ISD::GLD1_UXTW_MERGE_ZERO:
13148   case AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO:
13149   case AArch64ISD::GLD1_IMM_MERGE_ZERO:
13150   case AArch64ISD::GLDFF1_MERGE_ZERO:
13151   case AArch64ISD::GLDFF1_SCALED_MERGE_ZERO:
13152   case AArch64ISD::GLDFF1_SXTW_MERGE_ZERO:
13153   case AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO:
13154   case AArch64ISD::GLDFF1_UXTW_MERGE_ZERO:
13155   case AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO:
13156   case AArch64ISD::GLDFF1_IMM_MERGE_ZERO:
13157   case AArch64ISD::GLDNT1_MERGE_ZERO:
13158     MemVT = cast<VTSDNode>(Src->getOperand(4))->getVT();
13159     break;
13160   default:
13161     return SDValue();
13162   }
13163 
13164   if (isConstantSplatVectorMaskForType(Mask.getNode(), MemVT))
13165     return Src;
13166 
13167   return SDValue();
13168 }
13169 
13170 static SDValue performANDCombine(SDNode *N,
13171                                  TargetLowering::DAGCombinerInfo &DCI) {
13172   SelectionDAG &DAG = DCI.DAG;
13173   SDValue LHS = N->getOperand(0);
13174   EVT VT = N->getValueType(0);
13175   if (!VT.isVector() || !DAG.getTargetLoweringInfo().isTypeLegal(VT))
13176     return SDValue();
13177 
13178   if (VT.isScalableVector())
13179     return performSVEAndCombine(N, DCI);
13180 
13181   // The combining code below works only for NEON vectors. In particular, it
13182   // does not work for SVE when dealing with vectors wider than 128 bits.
13183   if (!(VT.is64BitVector() || VT.is128BitVector()))
13184     return SDValue();
13185 
13186   BuildVectorSDNode *BVN =
13187       dyn_cast<BuildVectorSDNode>(N->getOperand(1).getNode());
13188   if (!BVN)
13189     return SDValue();
13190 
13191   // AND does not accept an immediate, so check if we can use a BIC immediate
13192   // instruction instead. We do this here instead of using a (and x, (mvni imm))
13193   // pattern in isel, because some immediates may be lowered to the preferred
13194   // (and x, (movi imm)) form, even though an mvni representation also exists.
13195   APInt DefBits(VT.getSizeInBits(), 0);
13196   APInt UndefBits(VT.getSizeInBits(), 0);
13197   if (resolveBuildVector(BVN, DefBits, UndefBits)) {
13198     SDValue NewOp;
13199 
13200     DefBits = ~DefBits;
13201     if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, SDValue(N, 0), DAG,
13202                                     DefBits, &LHS)) ||
13203         (NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, SDValue(N, 0), DAG,
13204                                     DefBits, &LHS)))
13205       return NewOp;
13206 
13207     UndefBits = ~UndefBits;
13208     if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, SDValue(N, 0), DAG,
13209                                     UndefBits, &LHS)) ||
13210         (NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, SDValue(N, 0), DAG,
13211                                     UndefBits, &LHS)))
13212       return NewOp;
13213   }
13214 
13215   return SDValue();
13216 }
13217 
13218 static SDValue performSRLCombine(SDNode *N,
13219                                  TargetLowering::DAGCombinerInfo &DCI) {
13220   SelectionDAG &DAG = DCI.DAG;
13221   EVT VT = N->getValueType(0);
13222   if (VT != MVT::i32 && VT != MVT::i64)
13223     return SDValue();
13224 
13225   // Canonicalize (srl (bswap i32 x), 16) to (rotr (bswap i32 x), 16), if the
13226   // high 16-bits of x are zero. Similarly, canonicalize (srl (bswap i64 x), 32)
13227   // to (rotr (bswap i64 x), 32), if the high 32-bits of x are zero.
13228   SDValue N0 = N->getOperand(0);
13229   if (N0.getOpcode() == ISD::BSWAP) {
13230     SDLoc DL(N);
13231     SDValue N1 = N->getOperand(1);
13232     SDValue N00 = N0.getOperand(0);
13233     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
13234       uint64_t ShiftAmt = C->getZExtValue();
13235       if (VT == MVT::i32 && ShiftAmt == 16 &&
13236           DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(32, 16)))
13237         return DAG.getNode(ISD::ROTR, DL, VT, N0, N1);
13238       if (VT == MVT::i64 && ShiftAmt == 32 &&
13239           DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(64, 32)))
13240         return DAG.getNode(ISD::ROTR, DL, VT, N0, N1);
13241     }
13242   }
13243   return SDValue();
13244 }
13245 
13246 // Attempt to form urhadd(OpA, OpB) from
13247 // truncate(vlshr(sub(zext(OpB), xor(zext(OpA), Ones(ElemSizeInBits))), 1))
13248 // or uhadd(OpA, OpB) from truncate(vlshr(add(zext(OpA), zext(OpB)), 1)).
13249 // The original form of the first expression is
13250 // truncate(srl(add(zext(OpB), add(zext(OpA), 1)), 1)) and the
13251 // (OpA + OpB + 1) subexpression will have been changed to (OpB - (~OpA)).
13252 // Before this function is called the srl will have been lowered to
13253 // AArch64ISD::VLSHR.
13254 // This pass can also recognize signed variants of the patterns that use sign
13255 // extension instead of zero extension and form a srhadd(OpA, OpB) or a
13256 // shadd(OpA, OpB) from them.
13257 static SDValue
13258 performVectorTruncateCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
13259                              SelectionDAG &DAG) {
13260   EVT VT = N->getValueType(0);
13261 
13262   // Since we are looking for a right shift by a constant value of 1 and we are
13263   // operating on types at least 16 bits in length (sign/zero extended OpA and
13264   // OpB, which are at least 8 bits), it follows that the truncate will always
13265   // discard the shifted-in bit and therefore the right shift will be logical
13266   // regardless of the signedness of OpA and OpB.
13267   SDValue Shift = N->getOperand(0);
13268   if (Shift.getOpcode() != AArch64ISD::VLSHR)
13269     return SDValue();
13270 
13271   // Is the right shift using an immediate value of 1?
13272   uint64_t ShiftAmount = Shift.getConstantOperandVal(1);
13273   if (ShiftAmount != 1)
13274     return SDValue();
13275 
13276   SDValue ExtendOpA, ExtendOpB;
13277   SDValue ShiftOp0 = Shift.getOperand(0);
13278   unsigned ShiftOp0Opc = ShiftOp0.getOpcode();
13279   if (ShiftOp0Opc == ISD::SUB) {
13280 
13281     SDValue Xor = ShiftOp0.getOperand(1);
13282     if (Xor.getOpcode() != ISD::XOR)
13283       return SDValue();
13284 
13285     // Is the XOR using a constant amount of all ones in the right hand side?
13286     uint64_t C;
13287     if (!isAllConstantBuildVector(Xor.getOperand(1), C))
13288       return SDValue();
13289 
13290     unsigned ElemSizeInBits = VT.getScalarSizeInBits();
13291     APInt CAsAPInt(ElemSizeInBits, C);
13292     if (CAsAPInt != APInt::getAllOnesValue(ElemSizeInBits))
13293       return SDValue();
13294 
13295     ExtendOpA = Xor.getOperand(0);
13296     ExtendOpB = ShiftOp0.getOperand(0);
13297   } else if (ShiftOp0Opc == ISD::ADD) {
13298     ExtendOpA = ShiftOp0.getOperand(0);
13299     ExtendOpB = ShiftOp0.getOperand(1);
13300   } else
13301     return SDValue();
13302 
13303   unsigned ExtendOpAOpc = ExtendOpA.getOpcode();
13304   unsigned ExtendOpBOpc = ExtendOpB.getOpcode();
13305   if (!(ExtendOpAOpc == ExtendOpBOpc &&
13306         (ExtendOpAOpc == ISD::ZERO_EXTEND || ExtendOpAOpc == ISD::SIGN_EXTEND)))
13307     return SDValue();
13308 
13309   // Is the result of the right shift being truncated to the same value type as
13310   // the original operands, OpA and OpB?
13311   SDValue OpA = ExtendOpA.getOperand(0);
13312   SDValue OpB = ExtendOpB.getOperand(0);
13313   EVT OpAVT = OpA.getValueType();
13314   assert(ExtendOpA.getValueType() == ExtendOpB.getValueType());
13315   if (!(VT == OpAVT && OpAVT == OpB.getValueType()))
13316     return SDValue();
13317 
13318   SDLoc DL(N);
13319   bool IsSignExtend = ExtendOpAOpc == ISD::SIGN_EXTEND;
13320   bool IsRHADD = ShiftOp0Opc == ISD::SUB;
13321   unsigned HADDOpc = IsSignExtend
13322                          ? (IsRHADD ? AArch64ISD::SRHADD : AArch64ISD::SHADD)
13323                          : (IsRHADD ? AArch64ISD::URHADD : AArch64ISD::UHADD);
13324   SDValue ResultHADD = DAG.getNode(HADDOpc, DL, VT, OpA, OpB);
13325 
13326   return ResultHADD;
13327 }
13328 
13329 static bool hasPairwiseAdd(unsigned Opcode, EVT VT, bool FullFP16) {
13330   switch (Opcode) {
13331   case ISD::FADD:
13332     return (FullFP16 && VT == MVT::f16) || VT == MVT::f32 || VT == MVT::f64;
13333   case ISD::ADD:
13334     return VT == MVT::i64;
13335   default:
13336     return false;
13337   }
13338 }
13339 
13340 static SDValue performExtractVectorEltCombine(SDNode *N, SelectionDAG &DAG) {
13341   SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
13342   ConstantSDNode *ConstantN1 = dyn_cast<ConstantSDNode>(N1);
13343 
13344   EVT VT = N->getValueType(0);
13345   const bool FullFP16 =
13346       static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
13347 
13348   // Rewrite for pairwise fadd pattern
13349   //   (f32 (extract_vector_elt
13350   //           (fadd (vXf32 Other)
13351   //                 (vector_shuffle (vXf32 Other) undef <1,X,...> )) 0))
13352   // ->
13353   //   (f32 (fadd (extract_vector_elt (vXf32 Other) 0)
13354   //              (extract_vector_elt (vXf32 Other) 1))
13355   if (ConstantN1 && ConstantN1->getZExtValue() == 0 &&
13356       hasPairwiseAdd(N0->getOpcode(), VT, FullFP16)) {
13357     SDLoc DL(N0);
13358     SDValue N00 = N0->getOperand(0);
13359     SDValue N01 = N0->getOperand(1);
13360 
13361     ShuffleVectorSDNode *Shuffle = dyn_cast<ShuffleVectorSDNode>(N01);
13362     SDValue Other = N00;
13363 
13364     // And handle the commutative case.
13365     if (!Shuffle) {
13366       Shuffle = dyn_cast<ShuffleVectorSDNode>(N00);
13367       Other = N01;
13368     }
13369 
13370     if (Shuffle && Shuffle->getMaskElt(0) == 1 &&
13371         Other == Shuffle->getOperand(0)) {
13372       return DAG.getNode(N0->getOpcode(), DL, VT,
13373                          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Other,
13374                                      DAG.getConstant(0, DL, MVT::i64)),
13375                          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Other,
13376                                      DAG.getConstant(1, DL, MVT::i64)));
13377     }
13378   }
13379 
13380   return SDValue();
13381 }
13382 
13383 static SDValue performConcatVectorsCombine(SDNode *N,
13384                                            TargetLowering::DAGCombinerInfo &DCI,
13385                                            SelectionDAG &DAG) {
13386   SDLoc dl(N);
13387   EVT VT = N->getValueType(0);
13388   SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
13389   unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode();
13390 
13391   // Optimize concat_vectors of truncated vectors, where the intermediate
13392   // type is illegal, to avoid said illegality,  e.g.,
13393   //   (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
13394   //                          (v2i16 (truncate (v2i64)))))
13395   // ->
13396   //   (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
13397   //                                    (v4i32 (bitcast (v2i64))),
13398   //                                    <0, 2, 4, 6>)))
13399   // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
13400   // on both input and result type, so we might generate worse code.
13401   // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
13402   if (N->getNumOperands() == 2 && N0Opc == ISD::TRUNCATE &&
13403       N1Opc == ISD::TRUNCATE) {
13404     SDValue N00 = N0->getOperand(0);
13405     SDValue N10 = N1->getOperand(0);
13406     EVT N00VT = N00.getValueType();
13407 
13408     if (N00VT == N10.getValueType() &&
13409         (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
13410         N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
13411       MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
13412       SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
13413       for (size_t i = 0; i < Mask.size(); ++i)
13414         Mask[i] = i * 2;
13415       return DAG.getNode(ISD::TRUNCATE, dl, VT,
13416                          DAG.getVectorShuffle(
13417                              MidVT, dl,
13418                              DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
13419                              DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
13420     }
13421   }
13422 
13423   // Wait 'til after everything is legalized to try this. That way we have
13424   // legal vector types and such.
13425   if (DCI.isBeforeLegalizeOps())
13426     return SDValue();
13427 
13428   // Optimise concat_vectors of two [us]rhadds or [us]hadds that use extracted
13429   // subvectors from the same original vectors. Combine these into a single
13430   // [us]rhadd or [us]hadd that operates on the two original vectors. Example:
13431   //  (v16i8 (concat_vectors (v8i8 (urhadd (extract_subvector (v16i8 OpA, <0>),
13432   //                                        extract_subvector (v16i8 OpB,
13433   //                                        <0>))),
13434   //                         (v8i8 (urhadd (extract_subvector (v16i8 OpA, <8>),
13435   //                                        extract_subvector (v16i8 OpB,
13436   //                                        <8>)))))
13437   // ->
13438   //  (v16i8(urhadd(v16i8 OpA, v16i8 OpB)))
13439   if (N->getNumOperands() == 2 && N0Opc == N1Opc &&
13440       (N0Opc == AArch64ISD::URHADD || N0Opc == AArch64ISD::SRHADD ||
13441        N0Opc == AArch64ISD::UHADD || N0Opc == AArch64ISD::SHADD)) {
13442     SDValue N00 = N0->getOperand(0);
13443     SDValue N01 = N0->getOperand(1);
13444     SDValue N10 = N1->getOperand(0);
13445     SDValue N11 = N1->getOperand(1);
13446 
13447     EVT N00VT = N00.getValueType();
13448     EVT N10VT = N10.getValueType();
13449 
13450     if (N00->getOpcode() == ISD::EXTRACT_SUBVECTOR &&
13451         N01->getOpcode() == ISD::EXTRACT_SUBVECTOR &&
13452         N10->getOpcode() == ISD::EXTRACT_SUBVECTOR &&
13453         N11->getOpcode() == ISD::EXTRACT_SUBVECTOR && N00VT == N10VT) {
13454       SDValue N00Source = N00->getOperand(0);
13455       SDValue N01Source = N01->getOperand(0);
13456       SDValue N10Source = N10->getOperand(0);
13457       SDValue N11Source = N11->getOperand(0);
13458 
13459       if (N00Source == N10Source && N01Source == N11Source &&
13460           N00Source.getValueType() == VT && N01Source.getValueType() == VT) {
13461         assert(N0.getValueType() == N1.getValueType());
13462 
13463         uint64_t N00Index = N00.getConstantOperandVal(1);
13464         uint64_t N01Index = N01.getConstantOperandVal(1);
13465         uint64_t N10Index = N10.getConstantOperandVal(1);
13466         uint64_t N11Index = N11.getConstantOperandVal(1);
13467 
13468         if (N00Index == N01Index && N10Index == N11Index && N00Index == 0 &&
13469             N10Index == N00VT.getVectorNumElements())
13470           return DAG.getNode(N0Opc, dl, VT, N00Source, N01Source);
13471       }
13472     }
13473   }
13474 
13475   // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
13476   // splat. The indexed instructions are going to be expecting a DUPLANE64, so
13477   // canonicalise to that.
13478   if (N0 == N1 && VT.getVectorNumElements() == 2) {
13479     assert(VT.getScalarSizeInBits() == 64);
13480     return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
13481                        DAG.getConstant(0, dl, MVT::i64));
13482   }
13483 
13484   // Canonicalise concat_vectors so that the right-hand vector has as few
13485   // bit-casts as possible before its real operation. The primary matching
13486   // destination for these operations will be the narrowing "2" instructions,
13487   // which depend on the operation being performed on this right-hand vector.
13488   // For example,
13489   //    (concat_vectors LHS,  (v1i64 (bitconvert (v4i16 RHS))))
13490   // becomes
13491   //    (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
13492 
13493   if (N1Opc != ISD::BITCAST)
13494     return SDValue();
13495   SDValue RHS = N1->getOperand(0);
13496   MVT RHSTy = RHS.getValueType().getSimpleVT();
13497   // If the RHS is not a vector, this is not the pattern we're looking for.
13498   if (!RHSTy.isVector())
13499     return SDValue();
13500 
13501   LLVM_DEBUG(
13502       dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
13503 
13504   MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
13505                                   RHSTy.getVectorNumElements() * 2);
13506   return DAG.getNode(ISD::BITCAST, dl, VT,
13507                      DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
13508                                  DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
13509                                  RHS));
13510 }
13511 
13512 static SDValue tryCombineFixedPointConvert(SDNode *N,
13513                                            TargetLowering::DAGCombinerInfo &DCI,
13514                                            SelectionDAG &DAG) {
13515   // Wait until after everything is legalized to try this. That way we have
13516   // legal vector types and such.
13517   if (DCI.isBeforeLegalizeOps())
13518     return SDValue();
13519   // Transform a scalar conversion of a value from a lane extract into a
13520   // lane extract of a vector conversion. E.g., from foo1 to foo2:
13521   // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
13522   // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
13523   //
13524   // The second form interacts better with instruction selection and the
13525   // register allocator to avoid cross-class register copies that aren't
13526   // coalescable due to a lane reference.
13527 
13528   // Check the operand and see if it originates from a lane extract.
13529   SDValue Op1 = N->getOperand(1);
13530   if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
13531     // Yep, no additional predication needed. Perform the transform.
13532     SDValue IID = N->getOperand(0);
13533     SDValue Shift = N->getOperand(2);
13534     SDValue Vec = Op1.getOperand(0);
13535     SDValue Lane = Op1.getOperand(1);
13536     EVT ResTy = N->getValueType(0);
13537     EVT VecResTy;
13538     SDLoc DL(N);
13539 
13540     // The vector width should be 128 bits by the time we get here, even
13541     // if it started as 64 bits (the extract_vector handling will have
13542     // done so).
13543     assert(Vec.getValueSizeInBits() == 128 &&
13544            "unexpected vector size on extract_vector_elt!");
13545     if (Vec.getValueType() == MVT::v4i32)
13546       VecResTy = MVT::v4f32;
13547     else if (Vec.getValueType() == MVT::v2i64)
13548       VecResTy = MVT::v2f64;
13549     else
13550       llvm_unreachable("unexpected vector type!");
13551 
13552     SDValue Convert =
13553         DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
13554     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
13555   }
13556   return SDValue();
13557 }
13558 
13559 // AArch64 high-vector "long" operations are formed by performing the non-high
13560 // version on an extract_subvector of each operand which gets the high half:
13561 //
13562 //  (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
13563 //
13564 // However, there are cases which don't have an extract_high explicitly, but
13565 // have another operation that can be made compatible with one for free. For
13566 // example:
13567 //
13568 //  (dupv64 scalar) --> (extract_high (dup128 scalar))
13569 //
13570 // This routine does the actual conversion of such DUPs, once outer routines
13571 // have determined that everything else is in order.
13572 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
13573 // similarly here.
13574 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
13575   switch (N.getOpcode()) {
13576   case AArch64ISD::DUP:
13577   case AArch64ISD::DUPLANE8:
13578   case AArch64ISD::DUPLANE16:
13579   case AArch64ISD::DUPLANE32:
13580   case AArch64ISD::DUPLANE64:
13581   case AArch64ISD::MOVI:
13582   case AArch64ISD::MOVIshift:
13583   case AArch64ISD::MOVIedit:
13584   case AArch64ISD::MOVImsl:
13585   case AArch64ISD::MVNIshift:
13586   case AArch64ISD::MVNImsl:
13587     break;
13588   default:
13589     // FMOV could be supported, but isn't very useful, as it would only occur
13590     // if you passed a bitcast' floating point immediate to an eligible long
13591     // integer op (addl, smull, ...).
13592     return SDValue();
13593   }
13594 
13595   MVT NarrowTy = N.getSimpleValueType();
13596   if (!NarrowTy.is64BitVector())
13597     return SDValue();
13598 
13599   MVT ElementTy = NarrowTy.getVectorElementType();
13600   unsigned NumElems = NarrowTy.getVectorNumElements();
13601   MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
13602 
13603   SDLoc dl(N);
13604   return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
13605                      DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
13606                      DAG.getConstant(NumElems, dl, MVT::i64));
13607 }
13608 
13609 static bool isEssentiallyExtractHighSubvector(SDValue N) {
13610   if (N.getOpcode() == ISD::BITCAST)
13611     N = N.getOperand(0);
13612   if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR)
13613     return false;
13614   return cast<ConstantSDNode>(N.getOperand(1))->getAPIntValue() ==
13615          N.getOperand(0).getValueType().getVectorNumElements() / 2;
13616 }
13617 
13618 /// Helper structure to keep track of ISD::SET_CC operands.
13619 struct GenericSetCCInfo {
13620   const SDValue *Opnd0;
13621   const SDValue *Opnd1;
13622   ISD::CondCode CC;
13623 };
13624 
13625 /// Helper structure to keep track of a SET_CC lowered into AArch64 code.
13626 struct AArch64SetCCInfo {
13627   const SDValue *Cmp;
13628   AArch64CC::CondCode CC;
13629 };
13630 
13631 /// Helper structure to keep track of SetCC information.
13632 union SetCCInfo {
13633   GenericSetCCInfo Generic;
13634   AArch64SetCCInfo AArch64;
13635 };
13636 
13637 /// Helper structure to be able to read SetCC information.  If set to
13638 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
13639 /// GenericSetCCInfo.
13640 struct SetCCInfoAndKind {
13641   SetCCInfo Info;
13642   bool IsAArch64;
13643 };
13644 
13645 /// Check whether or not \p Op is a SET_CC operation, either a generic or
13646 /// an
13647 /// AArch64 lowered one.
13648 /// \p SetCCInfo is filled accordingly.
13649 /// \post SetCCInfo is meanginfull only when this function returns true.
13650 /// \return True when Op is a kind of SET_CC operation.
13651 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
13652   // If this is a setcc, this is straight forward.
13653   if (Op.getOpcode() == ISD::SETCC) {
13654     SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
13655     SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
13656     SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13657     SetCCInfo.IsAArch64 = false;
13658     return true;
13659   }
13660   // Otherwise, check if this is a matching csel instruction.
13661   // In other words:
13662   // - csel 1, 0, cc
13663   // - csel 0, 1, !cc
13664   if (Op.getOpcode() != AArch64ISD::CSEL)
13665     return false;
13666   // Set the information about the operands.
13667   // TODO: we want the operands of the Cmp not the csel
13668   SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
13669   SetCCInfo.IsAArch64 = true;
13670   SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
13671       cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13672 
13673   // Check that the operands matches the constraints:
13674   // (1) Both operands must be constants.
13675   // (2) One must be 1 and the other must be 0.
13676   ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
13677   ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13678 
13679   // Check (1).
13680   if (!TValue || !FValue)
13681     return false;
13682 
13683   // Check (2).
13684   if (!TValue->isOne()) {
13685     // Update the comparison when we are interested in !cc.
13686     std::swap(TValue, FValue);
13687     SetCCInfo.Info.AArch64.CC =
13688         AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
13689   }
13690   return TValue->isOne() && FValue->isNullValue();
13691 }
13692 
13693 // Returns true if Op is setcc or zext of setcc.
13694 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
13695   if (isSetCC(Op, Info))
13696     return true;
13697   return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
13698     isSetCC(Op->getOperand(0), Info));
13699 }
13700 
13701 // The folding we want to perform is:
13702 // (add x, [zext] (setcc cc ...) )
13703 //   -->
13704 // (csel x, (add x, 1), !cc ...)
13705 //
13706 // The latter will get matched to a CSINC instruction.
13707 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
13708   assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
13709   SDValue LHS = Op->getOperand(0);
13710   SDValue RHS = Op->getOperand(1);
13711   SetCCInfoAndKind InfoAndKind;
13712 
13713   // If both operands are a SET_CC, then we don't want to perform this
13714   // folding and create another csel as this results in more instructions
13715   // (and higher register usage).
13716   if (isSetCCOrZExtSetCC(LHS, InfoAndKind) &&
13717       isSetCCOrZExtSetCC(RHS, InfoAndKind))
13718     return SDValue();
13719 
13720   // If neither operand is a SET_CC, give up.
13721   if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
13722     std::swap(LHS, RHS);
13723     if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
13724       return SDValue();
13725   }
13726 
13727   // FIXME: This could be generatized to work for FP comparisons.
13728   EVT CmpVT = InfoAndKind.IsAArch64
13729                   ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
13730                   : InfoAndKind.Info.Generic.Opnd0->getValueType();
13731   if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
13732     return SDValue();
13733 
13734   SDValue CCVal;
13735   SDValue Cmp;
13736   SDLoc dl(Op);
13737   if (InfoAndKind.IsAArch64) {
13738     CCVal = DAG.getConstant(
13739         AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
13740         MVT::i32);
13741     Cmp = *InfoAndKind.Info.AArch64.Cmp;
13742   } else
13743     Cmp = getAArch64Cmp(
13744         *InfoAndKind.Info.Generic.Opnd0, *InfoAndKind.Info.Generic.Opnd1,
13745         ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, CmpVT), CCVal, DAG,
13746         dl);
13747 
13748   EVT VT = Op->getValueType(0);
13749   LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
13750   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
13751 }
13752 
13753 // ADD(UADDV a, UADDV b) -->  UADDV(ADD a, b)
13754 static SDValue performUADDVCombine(SDNode *N, SelectionDAG &DAG) {
13755   EVT VT = N->getValueType(0);
13756   // Only scalar integer and vector types.
13757   if (N->getOpcode() != ISD::ADD || !VT.isScalarInteger())
13758     return SDValue();
13759 
13760   SDValue LHS = N->getOperand(0);
13761   SDValue RHS = N->getOperand(1);
13762   if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
13763       RHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || LHS.getValueType() != VT)
13764     return SDValue();
13765 
13766   auto *LHSN1 = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
13767   auto *RHSN1 = dyn_cast<ConstantSDNode>(RHS->getOperand(1));
13768   if (!LHSN1 || LHSN1 != RHSN1 || !RHSN1->isNullValue())
13769     return SDValue();
13770 
13771   SDValue Op1 = LHS->getOperand(0);
13772   SDValue Op2 = RHS->getOperand(0);
13773   EVT OpVT1 = Op1.getValueType();
13774   EVT OpVT2 = Op2.getValueType();
13775   if (Op1.getOpcode() != AArch64ISD::UADDV || OpVT1 != OpVT2 ||
13776       Op2.getOpcode() != AArch64ISD::UADDV ||
13777       OpVT1.getVectorElementType() != VT)
13778     return SDValue();
13779 
13780   SDValue Val1 = Op1.getOperand(0);
13781   SDValue Val2 = Op2.getOperand(0);
13782   EVT ValVT = Val1->getValueType(0);
13783   SDLoc DL(N);
13784   SDValue AddVal = DAG.getNode(ISD::ADD, DL, ValVT, Val1, Val2);
13785   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13786                      DAG.getNode(AArch64ISD::UADDV, DL, ValVT, AddVal),
13787                      DAG.getConstant(0, DL, MVT::i64));
13788 }
13789 
13790 // ADD(UDOT(zero, x, y), A) -->  UDOT(A, x, y)
13791 static SDValue performAddDotCombine(SDNode *N, SelectionDAG &DAG) {
13792   EVT VT = N->getValueType(0);
13793   if (N->getOpcode() != ISD::ADD)
13794     return SDValue();
13795 
13796   SDValue Dot = N->getOperand(0);
13797   SDValue A = N->getOperand(1);
13798   // Handle commutivity
13799   auto isZeroDot = [](SDValue Dot) {
13800     return (Dot.getOpcode() == AArch64ISD::UDOT ||
13801             Dot.getOpcode() == AArch64ISD::SDOT) &&
13802            isZerosVector(Dot.getOperand(0).getNode());
13803   };
13804   if (!isZeroDot(Dot))
13805     std::swap(Dot, A);
13806   if (!isZeroDot(Dot))
13807     return SDValue();
13808 
13809   return DAG.getNode(Dot.getOpcode(), SDLoc(N), VT, A, Dot.getOperand(1),
13810                      Dot.getOperand(2));
13811 }
13812 
13813 // The basic add/sub long vector instructions have variants with "2" on the end
13814 // which act on the high-half of their inputs. They are normally matched by
13815 // patterns like:
13816 //
13817 // (add (zeroext (extract_high LHS)),
13818 //      (zeroext (extract_high RHS)))
13819 // -> uaddl2 vD, vN, vM
13820 //
13821 // However, if one of the extracts is something like a duplicate, this
13822 // instruction can still be used profitably. This function puts the DAG into a
13823 // more appropriate form for those patterns to trigger.
13824 static SDValue performAddSubLongCombine(SDNode *N,
13825                                         TargetLowering::DAGCombinerInfo &DCI,
13826                                         SelectionDAG &DAG) {
13827   if (DCI.isBeforeLegalizeOps())
13828     return SDValue();
13829 
13830   MVT VT = N->getSimpleValueType(0);
13831   if (!VT.is128BitVector()) {
13832     if (N->getOpcode() == ISD::ADD)
13833       return performSetccAddFolding(N, DAG);
13834     return SDValue();
13835   }
13836 
13837   // Make sure both branches are extended in the same way.
13838   SDValue LHS = N->getOperand(0);
13839   SDValue RHS = N->getOperand(1);
13840   if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
13841        LHS.getOpcode() != ISD::SIGN_EXTEND) ||
13842       LHS.getOpcode() != RHS.getOpcode())
13843     return SDValue();
13844 
13845   unsigned ExtType = LHS.getOpcode();
13846 
13847   // It's not worth doing if at least one of the inputs isn't already an
13848   // extract, but we don't know which it'll be so we have to try both.
13849   if (isEssentiallyExtractHighSubvector(LHS.getOperand(0))) {
13850     RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
13851     if (!RHS.getNode())
13852       return SDValue();
13853 
13854     RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
13855   } else if (isEssentiallyExtractHighSubvector(RHS.getOperand(0))) {
13856     LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
13857     if (!LHS.getNode())
13858       return SDValue();
13859 
13860     LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
13861   }
13862 
13863   return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
13864 }
13865 
13866 static SDValue performAddSubCombine(SDNode *N,
13867                                     TargetLowering::DAGCombinerInfo &DCI,
13868                                     SelectionDAG &DAG) {
13869   // Try to change sum of two reductions.
13870   if (SDValue Val = performUADDVCombine(N, DAG))
13871     return Val;
13872   if (SDValue Val = performAddDotCombine(N, DAG))
13873     return Val;
13874 
13875   return performAddSubLongCombine(N, DCI, DAG);
13876 }
13877 
13878 // Massage DAGs which we can use the high-half "long" operations on into
13879 // something isel will recognize better. E.g.
13880 //
13881 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
13882 //   (aarch64_neon_umull (extract_high (v2i64 vec)))
13883 //                     (extract_high (v2i64 (dup128 scalar)))))
13884 //
13885 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
13886                                        TargetLowering::DAGCombinerInfo &DCI,
13887                                        SelectionDAG &DAG) {
13888   if (DCI.isBeforeLegalizeOps())
13889     return SDValue();
13890 
13891   SDValue LHS = N->getOperand((IID == Intrinsic::not_intrinsic) ? 0 : 1);
13892   SDValue RHS = N->getOperand((IID == Intrinsic::not_intrinsic) ? 1 : 2);
13893   assert(LHS.getValueType().is64BitVector() &&
13894          RHS.getValueType().is64BitVector() &&
13895          "unexpected shape for long operation");
13896 
13897   // Either node could be a DUP, but it's not worth doing both of them (you'd
13898   // just as well use the non-high version) so look for a corresponding extract
13899   // operation on the other "wing".
13900   if (isEssentiallyExtractHighSubvector(LHS)) {
13901     RHS = tryExtendDUPToExtractHigh(RHS, DAG);
13902     if (!RHS.getNode())
13903       return SDValue();
13904   } else if (isEssentiallyExtractHighSubvector(RHS)) {
13905     LHS = tryExtendDUPToExtractHigh(LHS, DAG);
13906     if (!LHS.getNode())
13907       return SDValue();
13908   }
13909 
13910   if (IID == Intrinsic::not_intrinsic)
13911     return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), LHS, RHS);
13912 
13913   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
13914                      N->getOperand(0), LHS, RHS);
13915 }
13916 
13917 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
13918   MVT ElemTy = N->getSimpleValueType(0).getScalarType();
13919   unsigned ElemBits = ElemTy.getSizeInBits();
13920 
13921   int64_t ShiftAmount;
13922   if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
13923     APInt SplatValue, SplatUndef;
13924     unsigned SplatBitSize;
13925     bool HasAnyUndefs;
13926     if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
13927                               HasAnyUndefs, ElemBits) ||
13928         SplatBitSize != ElemBits)
13929       return SDValue();
13930 
13931     ShiftAmount = SplatValue.getSExtValue();
13932   } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
13933     ShiftAmount = CVN->getSExtValue();
13934   } else
13935     return SDValue();
13936 
13937   unsigned Opcode;
13938   bool IsRightShift;
13939   switch (IID) {
13940   default:
13941     llvm_unreachable("Unknown shift intrinsic");
13942   case Intrinsic::aarch64_neon_sqshl:
13943     Opcode = AArch64ISD::SQSHL_I;
13944     IsRightShift = false;
13945     break;
13946   case Intrinsic::aarch64_neon_uqshl:
13947     Opcode = AArch64ISD::UQSHL_I;
13948     IsRightShift = false;
13949     break;
13950   case Intrinsic::aarch64_neon_srshl:
13951     Opcode = AArch64ISD::SRSHR_I;
13952     IsRightShift = true;
13953     break;
13954   case Intrinsic::aarch64_neon_urshl:
13955     Opcode = AArch64ISD::URSHR_I;
13956     IsRightShift = true;
13957     break;
13958   case Intrinsic::aarch64_neon_sqshlu:
13959     Opcode = AArch64ISD::SQSHLU_I;
13960     IsRightShift = false;
13961     break;
13962   case Intrinsic::aarch64_neon_sshl:
13963   case Intrinsic::aarch64_neon_ushl:
13964     // For positive shift amounts we can use SHL, as ushl/sshl perform a regular
13965     // left shift for positive shift amounts. Below, we only replace the current
13966     // node with VSHL, if this condition is met.
13967     Opcode = AArch64ISD::VSHL;
13968     IsRightShift = false;
13969     break;
13970   }
13971 
13972   if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
13973     SDLoc dl(N);
13974     return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
13975                        DAG.getConstant(-ShiftAmount, dl, MVT::i32));
13976   } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
13977     SDLoc dl(N);
13978     return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
13979                        DAG.getConstant(ShiftAmount, dl, MVT::i32));
13980   }
13981 
13982   return SDValue();
13983 }
13984 
13985 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
13986 // the intrinsics must be legal and take an i32, this means there's almost
13987 // certainly going to be a zext in the DAG which we can eliminate.
13988 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
13989   SDValue AndN = N->getOperand(2);
13990   if (AndN.getOpcode() != ISD::AND)
13991     return SDValue();
13992 
13993   ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
13994   if (!CMask || CMask->getZExtValue() != Mask)
13995     return SDValue();
13996 
13997   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
13998                      N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
13999 }
14000 
14001 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
14002                                            SelectionDAG &DAG) {
14003   SDLoc dl(N);
14004   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
14005                      DAG.getNode(Opc, dl,
14006                                  N->getOperand(1).getSimpleValueType(),
14007                                  N->getOperand(1)),
14008                      DAG.getConstant(0, dl, MVT::i64));
14009 }
14010 
14011 static SDValue LowerSVEIntrinsicIndex(SDNode *N, SelectionDAG &DAG) {
14012   SDLoc DL(N);
14013   SDValue Op1 = N->getOperand(1);
14014   SDValue Op2 = N->getOperand(2);
14015   EVT ScalarTy = Op2.getValueType();
14016   if ((ScalarTy == MVT::i8) || (ScalarTy == MVT::i16))
14017     ScalarTy = MVT::i32;
14018 
14019   // Lower index_vector(base, step) to mul(step step_vector(1)) + splat(base).
14020   SDValue StepVector = DAG.getStepVector(DL, N->getValueType(0));
14021   SDValue Step = DAG.getNode(ISD::SPLAT_VECTOR, DL, N->getValueType(0), Op2);
14022   SDValue Mul = DAG.getNode(ISD::MUL, DL, N->getValueType(0), StepVector, Step);
14023   SDValue Base = DAG.getNode(ISD::SPLAT_VECTOR, DL, N->getValueType(0), Op1);
14024   return DAG.getNode(ISD::ADD, DL, N->getValueType(0), Mul, Base);
14025 }
14026 
14027 static SDValue LowerSVEIntrinsicDUP(SDNode *N, SelectionDAG &DAG) {
14028   SDLoc dl(N);
14029   SDValue Scalar = N->getOperand(3);
14030   EVT ScalarTy = Scalar.getValueType();
14031 
14032   if ((ScalarTy == MVT::i8) || (ScalarTy == MVT::i16))
14033     Scalar = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Scalar);
14034 
14035   SDValue Passthru = N->getOperand(1);
14036   SDValue Pred = N->getOperand(2);
14037   return DAG.getNode(AArch64ISD::DUP_MERGE_PASSTHRU, dl, N->getValueType(0),
14038                      Pred, Scalar, Passthru);
14039 }
14040 
14041 static SDValue LowerSVEIntrinsicEXT(SDNode *N, SelectionDAG &DAG) {
14042   SDLoc dl(N);
14043   LLVMContext &Ctx = *DAG.getContext();
14044   EVT VT = N->getValueType(0);
14045 
14046   assert(VT.isScalableVector() && "Expected a scalable vector.");
14047 
14048   // Current lowering only supports the SVE-ACLE types.
14049   if (VT.getSizeInBits().getKnownMinSize() != AArch64::SVEBitsPerBlock)
14050     return SDValue();
14051 
14052   unsigned ElemSize = VT.getVectorElementType().getSizeInBits() / 8;
14053   unsigned ByteSize = VT.getSizeInBits().getKnownMinSize() / 8;
14054   EVT ByteVT =
14055       EVT::getVectorVT(Ctx, MVT::i8, ElementCount::getScalable(ByteSize));
14056 
14057   // Convert everything to the domain of EXT (i.e bytes).
14058   SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, ByteVT, N->getOperand(1));
14059   SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, ByteVT, N->getOperand(2));
14060   SDValue Op2 = DAG.getNode(ISD::MUL, dl, MVT::i32, N->getOperand(3),
14061                             DAG.getConstant(ElemSize, dl, MVT::i32));
14062 
14063   SDValue EXT = DAG.getNode(AArch64ISD::EXT, dl, ByteVT, Op0, Op1, Op2);
14064   return DAG.getNode(ISD::BITCAST, dl, VT, EXT);
14065 }
14066 
14067 static SDValue tryConvertSVEWideCompare(SDNode *N, ISD::CondCode CC,
14068                                         TargetLowering::DAGCombinerInfo &DCI,
14069                                         SelectionDAG &DAG) {
14070   if (DCI.isBeforeLegalize())
14071     return SDValue();
14072 
14073   SDValue Comparator = N->getOperand(3);
14074   if (Comparator.getOpcode() == AArch64ISD::DUP ||
14075       Comparator.getOpcode() == ISD::SPLAT_VECTOR) {
14076     unsigned IID = getIntrinsicID(N);
14077     EVT VT = N->getValueType(0);
14078     EVT CmpVT = N->getOperand(2).getValueType();
14079     SDValue Pred = N->getOperand(1);
14080     SDValue Imm;
14081     SDLoc DL(N);
14082 
14083     switch (IID) {
14084     default:
14085       llvm_unreachable("Called with wrong intrinsic!");
14086       break;
14087 
14088     // Signed comparisons
14089     case Intrinsic::aarch64_sve_cmpeq_wide:
14090     case Intrinsic::aarch64_sve_cmpne_wide:
14091     case Intrinsic::aarch64_sve_cmpge_wide:
14092     case Intrinsic::aarch64_sve_cmpgt_wide:
14093     case Intrinsic::aarch64_sve_cmplt_wide:
14094     case Intrinsic::aarch64_sve_cmple_wide: {
14095       if (auto *CN = dyn_cast<ConstantSDNode>(Comparator.getOperand(0))) {
14096         int64_t ImmVal = CN->getSExtValue();
14097         if (ImmVal >= -16 && ImmVal <= 15)
14098           Imm = DAG.getConstant(ImmVal, DL, MVT::i32);
14099         else
14100           return SDValue();
14101       }
14102       break;
14103     }
14104     // Unsigned comparisons
14105     case Intrinsic::aarch64_sve_cmphs_wide:
14106     case Intrinsic::aarch64_sve_cmphi_wide:
14107     case Intrinsic::aarch64_sve_cmplo_wide:
14108     case Intrinsic::aarch64_sve_cmpls_wide:  {
14109       if (auto *CN = dyn_cast<ConstantSDNode>(Comparator.getOperand(0))) {
14110         uint64_t ImmVal = CN->getZExtValue();
14111         if (ImmVal <= 127)
14112           Imm = DAG.getConstant(ImmVal, DL, MVT::i32);
14113         else
14114           return SDValue();
14115       }
14116       break;
14117     }
14118     }
14119 
14120     if (!Imm)
14121       return SDValue();
14122 
14123     SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, DL, CmpVT, Imm);
14124     return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, VT, Pred,
14125                        N->getOperand(2), Splat, DAG.getCondCode(CC));
14126   }
14127 
14128   return SDValue();
14129 }
14130 
14131 static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
14132                         AArch64CC::CondCode Cond) {
14133   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14134 
14135   SDLoc DL(Op);
14136   assert(Op.getValueType().isScalableVector() &&
14137          TLI.isTypeLegal(Op.getValueType()) &&
14138          "Expected legal scalable vector type!");
14139 
14140   // Ensure target specific opcodes are using legal type.
14141   EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
14142   SDValue TVal = DAG.getConstant(1, DL, OutVT);
14143   SDValue FVal = DAG.getConstant(0, DL, OutVT);
14144 
14145   // Set condition code (CC) flags.
14146   SDValue Test = DAG.getNode(AArch64ISD::PTEST, DL, MVT::Other, Pg, Op);
14147 
14148   // Convert CC to integer based on requested condition.
14149   // NOTE: Cond is inverted to promote CSEL's removal when it feeds a compare.
14150   SDValue CC = DAG.getConstant(getInvertedCondCode(Cond), DL, MVT::i32);
14151   SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);
14152   return DAG.getZExtOrTrunc(Res, DL, VT);
14153 }
14154 
14155 static SDValue combineSVEReductionInt(SDNode *N, unsigned Opc,
14156                                       SelectionDAG &DAG) {
14157   SDLoc DL(N);
14158 
14159   SDValue Pred = N->getOperand(1);
14160   SDValue VecToReduce = N->getOperand(2);
14161 
14162   // NOTE: The integer reduction's result type is not always linked to the
14163   // operand's element type so we construct it from the intrinsic's result type.
14164   EVT ReduceVT = getPackedSVEVectorVT(N->getValueType(0));
14165   SDValue Reduce = DAG.getNode(Opc, DL, ReduceVT, Pred, VecToReduce);
14166 
14167   // SVE reductions set the whole vector register with the first element
14168   // containing the reduction result, which we'll now extract.
14169   SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
14170   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0), Reduce,
14171                      Zero);
14172 }
14173 
14174 static SDValue combineSVEReductionFP(SDNode *N, unsigned Opc,
14175                                      SelectionDAG &DAG) {
14176   SDLoc DL(N);
14177 
14178   SDValue Pred = N->getOperand(1);
14179   SDValue VecToReduce = N->getOperand(2);
14180 
14181   EVT ReduceVT = VecToReduce.getValueType();
14182   SDValue Reduce = DAG.getNode(Opc, DL, ReduceVT, Pred, VecToReduce);
14183 
14184   // SVE reductions set the whole vector register with the first element
14185   // containing the reduction result, which we'll now extract.
14186   SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
14187   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0), Reduce,
14188                      Zero);
14189 }
14190 
14191 static SDValue combineSVEReductionOrderedFP(SDNode *N, unsigned Opc,
14192                                             SelectionDAG &DAG) {
14193   SDLoc DL(N);
14194 
14195   SDValue Pred = N->getOperand(1);
14196   SDValue InitVal = N->getOperand(2);
14197   SDValue VecToReduce = N->getOperand(3);
14198   EVT ReduceVT = VecToReduce.getValueType();
14199 
14200   // Ordered reductions use the first lane of the result vector as the
14201   // reduction's initial value.
14202   SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
14203   InitVal = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ReduceVT,
14204                         DAG.getUNDEF(ReduceVT), InitVal, Zero);
14205 
14206   SDValue Reduce = DAG.getNode(Opc, DL, ReduceVT, Pred, InitVal, VecToReduce);
14207 
14208   // SVE reductions set the whole vector register with the first element
14209   // containing the reduction result, which we'll now extract.
14210   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0), Reduce,
14211                      Zero);
14212 }
14213 
14214 static bool isAllActivePredicate(SDValue N) {
14215   unsigned NumElts = N.getValueType().getVectorMinNumElements();
14216 
14217   // Look through cast.
14218   while (N.getOpcode() == AArch64ISD::REINTERPRET_CAST) {
14219     N = N.getOperand(0);
14220     // When reinterpreting from a type with fewer elements the "new" elements
14221     // are not active, so bail if they're likely to be used.
14222     if (N.getValueType().getVectorMinNumElements() < NumElts)
14223       return false;
14224   }
14225 
14226   // "ptrue p.<ty>, all" can be considered all active when <ty> is the same size
14227   // or smaller than the implicit element type represented by N.
14228   // NOTE: A larger element count implies a smaller element type.
14229   if (N.getOpcode() == AArch64ISD::PTRUE &&
14230       N.getConstantOperandVal(0) == AArch64SVEPredPattern::all)
14231     return N.getValueType().getVectorMinNumElements() >= NumElts;
14232 
14233   return false;
14234 }
14235 
14236 // If a merged operation has no inactive lanes we can relax it to a predicated
14237 // or unpredicated operation, which potentially allows better isel (perhaps
14238 // using immediate forms) or relaxing register reuse requirements.
14239 static SDValue convertMergedOpToPredOp(SDNode *N, unsigned Opc,
14240                                        SelectionDAG &DAG,
14241                                        bool UnpredOp = false) {
14242   assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN && "Expected intrinsic!");
14243   assert(N->getNumOperands() == 4 && "Expected 3 operand intrinsic!");
14244   SDValue Pg = N->getOperand(1);
14245 
14246   // ISD way to specify an all active predicate.
14247   if (isAllActivePredicate(Pg)) {
14248     if (UnpredOp)
14249       return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), N->getOperand(2),
14250                          N->getOperand(3));
14251     else
14252       return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), Pg,
14253                          N->getOperand(2), N->getOperand(3));
14254   }
14255 
14256   // FUTURE: SplatVector(true)
14257   return SDValue();
14258 }
14259 
14260 static SDValue performIntrinsicCombine(SDNode *N,
14261                                        TargetLowering::DAGCombinerInfo &DCI,
14262                                        const AArch64Subtarget *Subtarget) {
14263   SelectionDAG &DAG = DCI.DAG;
14264   unsigned IID = getIntrinsicID(N);
14265   switch (IID) {
14266   default:
14267     break;
14268   case Intrinsic::aarch64_neon_vcvtfxs2fp:
14269   case Intrinsic::aarch64_neon_vcvtfxu2fp:
14270     return tryCombineFixedPointConvert(N, DCI, DAG);
14271   case Intrinsic::aarch64_neon_saddv:
14272     return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
14273   case Intrinsic::aarch64_neon_uaddv:
14274     return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
14275   case Intrinsic::aarch64_neon_sminv:
14276     return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
14277   case Intrinsic::aarch64_neon_uminv:
14278     return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
14279   case Intrinsic::aarch64_neon_smaxv:
14280     return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
14281   case Intrinsic::aarch64_neon_umaxv:
14282     return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
14283   case Intrinsic::aarch64_neon_fmax:
14284     return DAG.getNode(ISD::FMAXIMUM, SDLoc(N), N->getValueType(0),
14285                        N->getOperand(1), N->getOperand(2));
14286   case Intrinsic::aarch64_neon_fmin:
14287     return DAG.getNode(ISD::FMINIMUM, SDLoc(N), N->getValueType(0),
14288                        N->getOperand(1), N->getOperand(2));
14289   case Intrinsic::aarch64_neon_fmaxnm:
14290     return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0),
14291                        N->getOperand(1), N->getOperand(2));
14292   case Intrinsic::aarch64_neon_fminnm:
14293     return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0),
14294                        N->getOperand(1), N->getOperand(2));
14295   case Intrinsic::aarch64_neon_smull:
14296   case Intrinsic::aarch64_neon_umull:
14297   case Intrinsic::aarch64_neon_pmull:
14298   case Intrinsic::aarch64_neon_sqdmull:
14299     return tryCombineLongOpWithDup(IID, N, DCI, DAG);
14300   case Intrinsic::aarch64_neon_sqshl:
14301   case Intrinsic::aarch64_neon_uqshl:
14302   case Intrinsic::aarch64_neon_sqshlu:
14303   case Intrinsic::aarch64_neon_srshl:
14304   case Intrinsic::aarch64_neon_urshl:
14305   case Intrinsic::aarch64_neon_sshl:
14306   case Intrinsic::aarch64_neon_ushl:
14307     return tryCombineShiftImm(IID, N, DAG);
14308   case Intrinsic::aarch64_crc32b:
14309   case Intrinsic::aarch64_crc32cb:
14310     return tryCombineCRC32(0xff, N, DAG);
14311   case Intrinsic::aarch64_crc32h:
14312   case Intrinsic::aarch64_crc32ch:
14313     return tryCombineCRC32(0xffff, N, DAG);
14314   case Intrinsic::aarch64_sve_saddv:
14315     // There is no i64 version of SADDV because the sign is irrelevant.
14316     if (N->getOperand(2)->getValueType(0).getVectorElementType() == MVT::i64)
14317       return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG);
14318     else
14319       return combineSVEReductionInt(N, AArch64ISD::SADDV_PRED, DAG);
14320   case Intrinsic::aarch64_sve_uaddv:
14321     return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG);
14322   case Intrinsic::aarch64_sve_smaxv:
14323     return combineSVEReductionInt(N, AArch64ISD::SMAXV_PRED, DAG);
14324   case Intrinsic::aarch64_sve_umaxv:
14325     return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG);
14326   case Intrinsic::aarch64_sve_sminv:
14327     return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG);
14328   case Intrinsic::aarch64_sve_uminv:
14329     return combineSVEReductionInt(N, AArch64ISD::UMINV_PRED, DAG);
14330   case Intrinsic::aarch64_sve_orv:
14331     return combineSVEReductionInt(N, AArch64ISD::ORV_PRED, DAG);
14332   case Intrinsic::aarch64_sve_eorv:
14333     return combineSVEReductionInt(N, AArch64ISD::EORV_PRED, DAG);
14334   case Intrinsic::aarch64_sve_andv:
14335     return combineSVEReductionInt(N, AArch64ISD::ANDV_PRED, DAG);
14336   case Intrinsic::aarch64_sve_index:
14337     return LowerSVEIntrinsicIndex(N, DAG);
14338   case Intrinsic::aarch64_sve_dup:
14339     return LowerSVEIntrinsicDUP(N, DAG);
14340   case Intrinsic::aarch64_sve_dup_x:
14341     return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), N->getValueType(0),
14342                        N->getOperand(1));
14343   case Intrinsic::aarch64_sve_ext:
14344     return LowerSVEIntrinsicEXT(N, DAG);
14345   case Intrinsic::aarch64_sve_mul:
14346     return convertMergedOpToPredOp(N, AArch64ISD::MUL_PRED, DAG);
14347   case Intrinsic::aarch64_sve_smulh:
14348     return convertMergedOpToPredOp(N, AArch64ISD::MULHS_PRED, DAG);
14349   case Intrinsic::aarch64_sve_umulh:
14350     return convertMergedOpToPredOp(N, AArch64ISD::MULHU_PRED, DAG);
14351   case Intrinsic::aarch64_sve_smin:
14352     return convertMergedOpToPredOp(N, AArch64ISD::SMIN_PRED, DAG);
14353   case Intrinsic::aarch64_sve_umin:
14354     return convertMergedOpToPredOp(N, AArch64ISD::UMIN_PRED, DAG);
14355   case Intrinsic::aarch64_sve_smax:
14356     return convertMergedOpToPredOp(N, AArch64ISD::SMAX_PRED, DAG);
14357   case Intrinsic::aarch64_sve_umax:
14358     return convertMergedOpToPredOp(N, AArch64ISD::UMAX_PRED, DAG);
14359   case Intrinsic::aarch64_sve_lsl:
14360     return convertMergedOpToPredOp(N, AArch64ISD::SHL_PRED, DAG);
14361   case Intrinsic::aarch64_sve_lsr:
14362     return convertMergedOpToPredOp(N, AArch64ISD::SRL_PRED, DAG);
14363   case Intrinsic::aarch64_sve_asr:
14364     return convertMergedOpToPredOp(N, AArch64ISD::SRA_PRED, DAG);
14365   case Intrinsic::aarch64_sve_fadd:
14366     return convertMergedOpToPredOp(N, AArch64ISD::FADD_PRED, DAG);
14367   case Intrinsic::aarch64_sve_fsub:
14368     return convertMergedOpToPredOp(N, AArch64ISD::FSUB_PRED, DAG);
14369   case Intrinsic::aarch64_sve_fmul:
14370     return convertMergedOpToPredOp(N, AArch64ISD::FMUL_PRED, DAG);
14371   case Intrinsic::aarch64_sve_add:
14372     return convertMergedOpToPredOp(N, ISD::ADD, DAG, true);
14373   case Intrinsic::aarch64_sve_sub:
14374     return convertMergedOpToPredOp(N, ISD::SUB, DAG, true);
14375   case Intrinsic::aarch64_sve_and:
14376     return convertMergedOpToPredOp(N, ISD::AND, DAG, true);
14377   case Intrinsic::aarch64_sve_bic:
14378     return convertMergedOpToPredOp(N, AArch64ISD::BIC, DAG, true);
14379   case Intrinsic::aarch64_sve_eor:
14380     return convertMergedOpToPredOp(N, ISD::XOR, DAG, true);
14381   case Intrinsic::aarch64_sve_orr:
14382     return convertMergedOpToPredOp(N, ISD::OR, DAG, true);
14383   case Intrinsic::aarch64_sve_sqadd:
14384     return convertMergedOpToPredOp(N, ISD::SADDSAT, DAG, true);
14385   case Intrinsic::aarch64_sve_sqsub:
14386     return convertMergedOpToPredOp(N, ISD::SSUBSAT, DAG, true);
14387   case Intrinsic::aarch64_sve_uqadd:
14388     return convertMergedOpToPredOp(N, ISD::UADDSAT, DAG, true);
14389   case Intrinsic::aarch64_sve_uqsub:
14390     return convertMergedOpToPredOp(N, ISD::USUBSAT, DAG, true);
14391   case Intrinsic::aarch64_sve_sqadd_x:
14392     return DAG.getNode(ISD::SADDSAT, SDLoc(N), N->getValueType(0),
14393                        N->getOperand(1), N->getOperand(2));
14394   case Intrinsic::aarch64_sve_sqsub_x:
14395     return DAG.getNode(ISD::SSUBSAT, SDLoc(N), N->getValueType(0),
14396                        N->getOperand(1), N->getOperand(2));
14397   case Intrinsic::aarch64_sve_uqadd_x:
14398     return DAG.getNode(ISD::UADDSAT, SDLoc(N), N->getValueType(0),
14399                        N->getOperand(1), N->getOperand(2));
14400   case Intrinsic::aarch64_sve_uqsub_x:
14401     return DAG.getNode(ISD::USUBSAT, SDLoc(N), N->getValueType(0),
14402                        N->getOperand(1), N->getOperand(2));
14403   case Intrinsic::aarch64_sve_cmphs:
14404     if (!N->getOperand(2).getValueType().isFloatingPoint())
14405       return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, SDLoc(N),
14406                          N->getValueType(0), N->getOperand(1), N->getOperand(2),
14407                          N->getOperand(3), DAG.getCondCode(ISD::SETUGE));
14408     break;
14409   case Intrinsic::aarch64_sve_cmphi:
14410     if (!N->getOperand(2).getValueType().isFloatingPoint())
14411       return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, SDLoc(N),
14412                          N->getValueType(0), N->getOperand(1), N->getOperand(2),
14413                          N->getOperand(3), DAG.getCondCode(ISD::SETUGT));
14414     break;
14415   case Intrinsic::aarch64_sve_fcmpge:
14416   case Intrinsic::aarch64_sve_cmpge:
14417     return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, SDLoc(N),
14418                        N->getValueType(0), N->getOperand(1), N->getOperand(2),
14419                        N->getOperand(3), DAG.getCondCode(ISD::SETGE));
14420     break;
14421   case Intrinsic::aarch64_sve_fcmpgt:
14422   case Intrinsic::aarch64_sve_cmpgt:
14423     return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, SDLoc(N),
14424                        N->getValueType(0), N->getOperand(1), N->getOperand(2),
14425                        N->getOperand(3), DAG.getCondCode(ISD::SETGT));
14426     break;
14427   case Intrinsic::aarch64_sve_fcmpeq:
14428   case Intrinsic::aarch64_sve_cmpeq:
14429     return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, SDLoc(N),
14430                        N->getValueType(0), N->getOperand(1), N->getOperand(2),
14431                        N->getOperand(3), DAG.getCondCode(ISD::SETEQ));
14432     break;
14433   case Intrinsic::aarch64_sve_fcmpne:
14434   case Intrinsic::aarch64_sve_cmpne:
14435     return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, SDLoc(N),
14436                        N->getValueType(0), N->getOperand(1), N->getOperand(2),
14437                        N->getOperand(3), DAG.getCondCode(ISD::SETNE));
14438     break;
14439   case Intrinsic::aarch64_sve_fcmpuo:
14440     return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, SDLoc(N),
14441                        N->getValueType(0), N->getOperand(1), N->getOperand(2),
14442                        N->getOperand(3), DAG.getCondCode(ISD::SETUO));
14443     break;
14444   case Intrinsic::aarch64_sve_fadda:
14445     return combineSVEReductionOrderedFP(N, AArch64ISD::FADDA_PRED, DAG);
14446   case Intrinsic::aarch64_sve_faddv:
14447     return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG);
14448   case Intrinsic::aarch64_sve_fmaxnmv:
14449     return combineSVEReductionFP(N, AArch64ISD::FMAXNMV_PRED, DAG);
14450   case Intrinsic::aarch64_sve_fmaxv:
14451     return combineSVEReductionFP(N, AArch64ISD::FMAXV_PRED, DAG);
14452   case Intrinsic::aarch64_sve_fminnmv:
14453     return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG);
14454   case Intrinsic::aarch64_sve_fminv:
14455     return combineSVEReductionFP(N, AArch64ISD::FMINV_PRED, DAG);
14456   case Intrinsic::aarch64_sve_sel:
14457     return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0),
14458                        N->getOperand(1), N->getOperand(2), N->getOperand(3));
14459   case Intrinsic::aarch64_sve_cmpeq_wide:
14460     return tryConvertSVEWideCompare(N, ISD::SETEQ, DCI, DAG);
14461   case Intrinsic::aarch64_sve_cmpne_wide:
14462     return tryConvertSVEWideCompare(N, ISD::SETNE, DCI, DAG);
14463   case Intrinsic::aarch64_sve_cmpge_wide:
14464     return tryConvertSVEWideCompare(N, ISD::SETGE, DCI, DAG);
14465   case Intrinsic::aarch64_sve_cmpgt_wide:
14466     return tryConvertSVEWideCompare(N, ISD::SETGT, DCI, DAG);
14467   case Intrinsic::aarch64_sve_cmplt_wide:
14468     return tryConvertSVEWideCompare(N, ISD::SETLT, DCI, DAG);
14469   case Intrinsic::aarch64_sve_cmple_wide:
14470     return tryConvertSVEWideCompare(N, ISD::SETLE, DCI, DAG);
14471   case Intrinsic::aarch64_sve_cmphs_wide:
14472     return tryConvertSVEWideCompare(N, ISD::SETUGE, DCI, DAG);
14473   case Intrinsic::aarch64_sve_cmphi_wide:
14474     return tryConvertSVEWideCompare(N, ISD::SETUGT, DCI, DAG);
14475   case Intrinsic::aarch64_sve_cmplo_wide:
14476     return tryConvertSVEWideCompare(N, ISD::SETULT, DCI, DAG);
14477   case Intrinsic::aarch64_sve_cmpls_wide:
14478     return tryConvertSVEWideCompare(N, ISD::SETULE, DCI, DAG);
14479   case Intrinsic::aarch64_sve_ptest_any:
14480     return getPTest(DAG, N->getValueType(0), N->getOperand(1), N->getOperand(2),
14481                     AArch64CC::ANY_ACTIVE);
14482   case Intrinsic::aarch64_sve_ptest_first:
14483     return getPTest(DAG, N->getValueType(0), N->getOperand(1), N->getOperand(2),
14484                     AArch64CC::FIRST_ACTIVE);
14485   case Intrinsic::aarch64_sve_ptest_last:
14486     return getPTest(DAG, N->getValueType(0), N->getOperand(1), N->getOperand(2),
14487                     AArch64CC::LAST_ACTIVE);
14488   }
14489   return SDValue();
14490 }
14491 
14492 static SDValue performExtendCombine(SDNode *N,
14493                                     TargetLowering::DAGCombinerInfo &DCI,
14494                                     SelectionDAG &DAG) {
14495   // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
14496   // we can convert that DUP into another extract_high (of a bigger DUP), which
14497   // helps the backend to decide that an sabdl2 would be useful, saving a real
14498   // extract_high operation.
14499   if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
14500       (N->getOperand(0).getOpcode() == ISD::ABDU ||
14501        N->getOperand(0).getOpcode() == ISD::ABDS)) {
14502     SDNode *ABDNode = N->getOperand(0).getNode();
14503     SDValue NewABD =
14504         tryCombineLongOpWithDup(Intrinsic::not_intrinsic, ABDNode, DCI, DAG);
14505     if (!NewABD.getNode())
14506       return SDValue();
14507 
14508     return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), NewABD);
14509   }
14510   return SDValue();
14511 }
14512 
14513 static SDValue splitStoreSplat(SelectionDAG &DAG, StoreSDNode &St,
14514                                SDValue SplatVal, unsigned NumVecElts) {
14515   assert(!St.isTruncatingStore() && "cannot split truncating vector store");
14516   unsigned OrigAlignment = St.getAlignment();
14517   unsigned EltOffset = SplatVal.getValueType().getSizeInBits() / 8;
14518 
14519   // Create scalar stores. This is at least as good as the code sequence for a
14520   // split unaligned store which is a dup.s, ext.b, and two stores.
14521   // Most of the time the three stores should be replaced by store pair
14522   // instructions (stp).
14523   SDLoc DL(&St);
14524   SDValue BasePtr = St.getBasePtr();
14525   uint64_t BaseOffset = 0;
14526 
14527   const MachinePointerInfo &PtrInfo = St.getPointerInfo();
14528   SDValue NewST1 =
14529       DAG.getStore(St.getChain(), DL, SplatVal, BasePtr, PtrInfo,
14530                    OrigAlignment, St.getMemOperand()->getFlags());
14531 
14532   // As this in ISel, we will not merge this add which may degrade results.
14533   if (BasePtr->getOpcode() == ISD::ADD &&
14534       isa<ConstantSDNode>(BasePtr->getOperand(1))) {
14535     BaseOffset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
14536     BasePtr = BasePtr->getOperand(0);
14537   }
14538 
14539   unsigned Offset = EltOffset;
14540   while (--NumVecElts) {
14541     unsigned Alignment = MinAlign(OrigAlignment, Offset);
14542     SDValue OffsetPtr =
14543         DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
14544                     DAG.getConstant(BaseOffset + Offset, DL, MVT::i64));
14545     NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
14546                           PtrInfo.getWithOffset(Offset), Alignment,
14547                           St.getMemOperand()->getFlags());
14548     Offset += EltOffset;
14549   }
14550   return NewST1;
14551 }
14552 
14553 // Returns an SVE type that ContentTy can be trivially sign or zero extended
14554 // into.
14555 static MVT getSVEContainerType(EVT ContentTy) {
14556   assert(ContentTy.isSimple() && "No SVE containers for extended types");
14557 
14558   switch (ContentTy.getSimpleVT().SimpleTy) {
14559   default:
14560     llvm_unreachable("No known SVE container for this MVT type");
14561   case MVT::nxv2i8:
14562   case MVT::nxv2i16:
14563   case MVT::nxv2i32:
14564   case MVT::nxv2i64:
14565   case MVT::nxv2f32:
14566   case MVT::nxv2f64:
14567     return MVT::nxv2i64;
14568   case MVT::nxv4i8:
14569   case MVT::nxv4i16:
14570   case MVT::nxv4i32:
14571   case MVT::nxv4f32:
14572     return MVT::nxv4i32;
14573   case MVT::nxv8i8:
14574   case MVT::nxv8i16:
14575   case MVT::nxv8f16:
14576   case MVT::nxv8bf16:
14577     return MVT::nxv8i16;
14578   case MVT::nxv16i8:
14579     return MVT::nxv16i8;
14580   }
14581 }
14582 
14583 static SDValue performLD1Combine(SDNode *N, SelectionDAG &DAG, unsigned Opc) {
14584   SDLoc DL(N);
14585   EVT VT = N->getValueType(0);
14586 
14587   if (VT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock)
14588     return SDValue();
14589 
14590   EVT ContainerVT = VT;
14591   if (ContainerVT.isInteger())
14592     ContainerVT = getSVEContainerType(ContainerVT);
14593 
14594   SDVTList VTs = DAG.getVTList(ContainerVT, MVT::Other);
14595   SDValue Ops[] = { N->getOperand(0), // Chain
14596                     N->getOperand(2), // Pg
14597                     N->getOperand(3), // Base
14598                     DAG.getValueType(VT) };
14599 
14600   SDValue Load = DAG.getNode(Opc, DL, VTs, Ops);
14601   SDValue LoadChain = SDValue(Load.getNode(), 1);
14602 
14603   if (ContainerVT.isInteger() && (VT != ContainerVT))
14604     Load = DAG.getNode(ISD::TRUNCATE, DL, VT, Load.getValue(0));
14605 
14606   return DAG.getMergeValues({ Load, LoadChain }, DL);
14607 }
14608 
14609 static SDValue performLDNT1Combine(SDNode *N, SelectionDAG &DAG) {
14610   SDLoc DL(N);
14611   EVT VT = N->getValueType(0);
14612   EVT PtrTy = N->getOperand(3).getValueType();
14613 
14614   if (VT == MVT::nxv8bf16 &&
14615       !static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasBF16())
14616     return SDValue();
14617 
14618   EVT LoadVT = VT;
14619   if (VT.isFloatingPoint())
14620     LoadVT = VT.changeTypeToInteger();
14621 
14622   auto *MINode = cast<MemIntrinsicSDNode>(N);
14623   SDValue PassThru = DAG.getConstant(0, DL, LoadVT);
14624   SDValue L = DAG.getMaskedLoad(LoadVT, DL, MINode->getChain(),
14625                                 MINode->getOperand(3), DAG.getUNDEF(PtrTy),
14626                                 MINode->getOperand(2), PassThru,
14627                                 MINode->getMemoryVT(), MINode->getMemOperand(),
14628                                 ISD::UNINDEXED, ISD::NON_EXTLOAD, false);
14629 
14630    if (VT.isFloatingPoint()) {
14631      SDValue Ops[] = { DAG.getNode(ISD::BITCAST, DL, VT, L), L.getValue(1) };
14632      return DAG.getMergeValues(Ops, DL);
14633    }
14634 
14635   return L;
14636 }
14637 
14638 template <unsigned Opcode>
14639 static SDValue performLD1ReplicateCombine(SDNode *N, SelectionDAG &DAG) {
14640   static_assert(Opcode == AArch64ISD::LD1RQ_MERGE_ZERO ||
14641                     Opcode == AArch64ISD::LD1RO_MERGE_ZERO,
14642                 "Unsupported opcode.");
14643   SDLoc DL(N);
14644   EVT VT = N->getValueType(0);
14645   if (VT == MVT::nxv8bf16 &&
14646       !static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasBF16())
14647     return SDValue();
14648 
14649   EVT LoadVT = VT;
14650   if (VT.isFloatingPoint())
14651     LoadVT = VT.changeTypeToInteger();
14652 
14653   SDValue Ops[] = {N->getOperand(0), N->getOperand(2), N->getOperand(3)};
14654   SDValue Load = DAG.getNode(Opcode, DL, {LoadVT, MVT::Other}, Ops);
14655   SDValue LoadChain = SDValue(Load.getNode(), 1);
14656 
14657   if (VT.isFloatingPoint())
14658     Load = DAG.getNode(ISD::BITCAST, DL, VT, Load.getValue(0));
14659 
14660   return DAG.getMergeValues({Load, LoadChain}, DL);
14661 }
14662 
14663 static SDValue performST1Combine(SDNode *N, SelectionDAG &DAG) {
14664   SDLoc DL(N);
14665   SDValue Data = N->getOperand(2);
14666   EVT DataVT = Data.getValueType();
14667   EVT HwSrcVt = getSVEContainerType(DataVT);
14668   SDValue InputVT = DAG.getValueType(DataVT);
14669 
14670   if (DataVT == MVT::nxv8bf16 &&
14671       !static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasBF16())
14672     return SDValue();
14673 
14674   if (DataVT.isFloatingPoint())
14675     InputVT = DAG.getValueType(HwSrcVt);
14676 
14677   SDValue SrcNew;
14678   if (Data.getValueType().isFloatingPoint())
14679     SrcNew = DAG.getNode(ISD::BITCAST, DL, HwSrcVt, Data);
14680   else
14681     SrcNew = DAG.getNode(ISD::ANY_EXTEND, DL, HwSrcVt, Data);
14682 
14683   SDValue Ops[] = { N->getOperand(0), // Chain
14684                     SrcNew,
14685                     N->getOperand(4), // Base
14686                     N->getOperand(3), // Pg
14687                     InputVT
14688                   };
14689 
14690   return DAG.getNode(AArch64ISD::ST1_PRED, DL, N->getValueType(0), Ops);
14691 }
14692 
14693 static SDValue performSTNT1Combine(SDNode *N, SelectionDAG &DAG) {
14694   SDLoc DL(N);
14695 
14696   SDValue Data = N->getOperand(2);
14697   EVT DataVT = Data.getValueType();
14698   EVT PtrTy = N->getOperand(4).getValueType();
14699 
14700   if (DataVT == MVT::nxv8bf16 &&
14701       !static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasBF16())
14702     return SDValue();
14703 
14704   if (DataVT.isFloatingPoint())
14705     Data = DAG.getNode(ISD::BITCAST, DL, DataVT.changeTypeToInteger(), Data);
14706 
14707   auto *MINode = cast<MemIntrinsicSDNode>(N);
14708   return DAG.getMaskedStore(MINode->getChain(), DL, Data, MINode->getOperand(4),
14709                             DAG.getUNDEF(PtrTy), MINode->getOperand(3),
14710                             MINode->getMemoryVT(), MINode->getMemOperand(),
14711                             ISD::UNINDEXED, false, false);
14712 }
14713 
14714 /// Replace a splat of zeros to a vector store by scalar stores of WZR/XZR.  The
14715 /// load store optimizer pass will merge them to store pair stores.  This should
14716 /// be better than a movi to create the vector zero followed by a vector store
14717 /// if the zero constant is not re-used, since one instructions and one register
14718 /// live range will be removed.
14719 ///
14720 /// For example, the final generated code should be:
14721 ///
14722 ///   stp xzr, xzr, [x0]
14723 ///
14724 /// instead of:
14725 ///
14726 ///   movi v0.2d, #0
14727 ///   str q0, [x0]
14728 ///
14729 static SDValue replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) {
14730   SDValue StVal = St.getValue();
14731   EVT VT = StVal.getValueType();
14732 
14733   // Avoid scalarizing zero splat stores for scalable vectors.
14734   if (VT.isScalableVector())
14735     return SDValue();
14736 
14737   // It is beneficial to scalarize a zero splat store for 2 or 3 i64 elements or
14738   // 2, 3 or 4 i32 elements.
14739   int NumVecElts = VT.getVectorNumElements();
14740   if (!(((NumVecElts == 2 || NumVecElts == 3) &&
14741          VT.getVectorElementType().getSizeInBits() == 64) ||
14742         ((NumVecElts == 2 || NumVecElts == 3 || NumVecElts == 4) &&
14743          VT.getVectorElementType().getSizeInBits() == 32)))
14744     return SDValue();
14745 
14746   if (StVal.getOpcode() != ISD::BUILD_VECTOR)
14747     return SDValue();
14748 
14749   // If the zero constant has more than one use then the vector store could be
14750   // better since the constant mov will be amortized and stp q instructions
14751   // should be able to be formed.
14752   if (!StVal.hasOneUse())
14753     return SDValue();
14754 
14755   // If the store is truncating then it's going down to i16 or smaller, which
14756   // means it can be implemented in a single store anyway.
14757   if (St.isTruncatingStore())
14758     return SDValue();
14759 
14760   // If the immediate offset of the address operand is too large for the stp
14761   // instruction, then bail out.
14762   if (DAG.isBaseWithConstantOffset(St.getBasePtr())) {
14763     int64_t Offset = St.getBasePtr()->getConstantOperandVal(1);
14764     if (Offset < -512 || Offset > 504)
14765       return SDValue();
14766   }
14767 
14768   for (int I = 0; I < NumVecElts; ++I) {
14769     SDValue EltVal = StVal.getOperand(I);
14770     if (!isNullConstant(EltVal) && !isNullFPConstant(EltVal))
14771       return SDValue();
14772   }
14773 
14774   // Use a CopyFromReg WZR/XZR here to prevent
14775   // DAGCombiner::MergeConsecutiveStores from undoing this transformation.
14776   SDLoc DL(&St);
14777   unsigned ZeroReg;
14778   EVT ZeroVT;
14779   if (VT.getVectorElementType().getSizeInBits() == 32) {
14780     ZeroReg = AArch64::WZR;
14781     ZeroVT = MVT::i32;
14782   } else {
14783     ZeroReg = AArch64::XZR;
14784     ZeroVT = MVT::i64;
14785   }
14786   SDValue SplatVal =
14787       DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT);
14788   return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
14789 }
14790 
14791 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
14792 /// value. The load store optimizer pass will merge them to store pair stores.
14793 /// This has better performance than a splat of the scalar followed by a split
14794 /// vector store. Even if the stores are not merged it is four stores vs a dup,
14795 /// followed by an ext.b and two stores.
14796 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode &St) {
14797   SDValue StVal = St.getValue();
14798   EVT VT = StVal.getValueType();
14799 
14800   // Don't replace floating point stores, they possibly won't be transformed to
14801   // stp because of the store pair suppress pass.
14802   if (VT.isFloatingPoint())
14803     return SDValue();
14804 
14805   // We can express a splat as store pair(s) for 2 or 4 elements.
14806   unsigned NumVecElts = VT.getVectorNumElements();
14807   if (NumVecElts != 4 && NumVecElts != 2)
14808     return SDValue();
14809 
14810   // If the store is truncating then it's going down to i16 or smaller, which
14811   // means it can be implemented in a single store anyway.
14812   if (St.isTruncatingStore())
14813     return SDValue();
14814 
14815   // Check that this is a splat.
14816   // Make sure that each of the relevant vector element locations are inserted
14817   // to, i.e. 0 and 1 for v2i64 and 0, 1, 2, 3 for v4i32.
14818   std::bitset<4> IndexNotInserted((1 << NumVecElts) - 1);
14819   SDValue SplatVal;
14820   for (unsigned I = 0; I < NumVecElts; ++I) {
14821     // Check for insert vector elements.
14822     if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
14823       return SDValue();
14824 
14825     // Check that same value is inserted at each vector element.
14826     if (I == 0)
14827       SplatVal = StVal.getOperand(1);
14828     else if (StVal.getOperand(1) != SplatVal)
14829       return SDValue();
14830 
14831     // Check insert element index.
14832     ConstantSDNode *CIndex = dyn_cast<ConstantSDNode>(StVal.getOperand(2));
14833     if (!CIndex)
14834       return SDValue();
14835     uint64_t IndexVal = CIndex->getZExtValue();
14836     if (IndexVal >= NumVecElts)
14837       return SDValue();
14838     IndexNotInserted.reset(IndexVal);
14839 
14840     StVal = StVal.getOperand(0);
14841   }
14842   // Check that all vector element locations were inserted to.
14843   if (IndexNotInserted.any())
14844       return SDValue();
14845 
14846   return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
14847 }
14848 
14849 static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
14850                            SelectionDAG &DAG,
14851                            const AArch64Subtarget *Subtarget) {
14852 
14853   StoreSDNode *S = cast<StoreSDNode>(N);
14854   if (S->isVolatile() || S->isIndexed())
14855     return SDValue();
14856 
14857   SDValue StVal = S->getValue();
14858   EVT VT = StVal.getValueType();
14859 
14860   if (!VT.isFixedLengthVector())
14861     return SDValue();
14862 
14863   // If we get a splat of zeros, convert this vector store to a store of
14864   // scalars. They will be merged into store pairs of xzr thereby removing one
14865   // instruction and one register.
14866   if (SDValue ReplacedZeroSplat = replaceZeroVectorStore(DAG, *S))
14867     return ReplacedZeroSplat;
14868 
14869   // FIXME: The logic for deciding if an unaligned store should be split should
14870   // be included in TLI.allowsMisalignedMemoryAccesses(), and there should be
14871   // a call to that function here.
14872 
14873   if (!Subtarget->isMisaligned128StoreSlow())
14874     return SDValue();
14875 
14876   // Don't split at -Oz.
14877   if (DAG.getMachineFunction().getFunction().hasMinSize())
14878     return SDValue();
14879 
14880   // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
14881   // those up regresses performance on micro-benchmarks and olden/bh.
14882   if (VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
14883     return SDValue();
14884 
14885   // Split unaligned 16B stores. They are terrible for performance.
14886   // Don't split stores with alignment of 1 or 2. Code that uses clang vector
14887   // extensions can use this to mark that it does not want splitting to happen
14888   // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
14889   // eliminating alignment hazards is only 1 in 8 for alignment of 2.
14890   if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
14891       S->getAlignment() <= 2)
14892     return SDValue();
14893 
14894   // If we get a splat of a scalar convert this vector store to a store of
14895   // scalars. They will be merged into store pairs thereby removing two
14896   // instructions.
14897   if (SDValue ReplacedSplat = replaceSplatVectorStore(DAG, *S))
14898     return ReplacedSplat;
14899 
14900   SDLoc DL(S);
14901 
14902   // Split VT into two.
14903   EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
14904   unsigned NumElts = HalfVT.getVectorNumElements();
14905   SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
14906                                    DAG.getConstant(0, DL, MVT::i64));
14907   SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
14908                                    DAG.getConstant(NumElts, DL, MVT::i64));
14909   SDValue BasePtr = S->getBasePtr();
14910   SDValue NewST1 =
14911       DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
14912                    S->getAlignment(), S->getMemOperand()->getFlags());
14913   SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
14914                                   DAG.getConstant(8, DL, MVT::i64));
14915   return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
14916                       S->getPointerInfo(), S->getAlignment(),
14917                       S->getMemOperand()->getFlags());
14918 }
14919 
14920 static SDValue performSpliceCombine(SDNode *N, SelectionDAG &DAG) {
14921   assert(N->getOpcode() == AArch64ISD::SPLICE && "Unexepected Opcode!");
14922 
14923   // splice(pg, op1, undef) -> op1
14924   if (N->getOperand(2).isUndef())
14925     return N->getOperand(1);
14926 
14927   return SDValue();
14928 }
14929 
14930 static SDValue performUzpCombine(SDNode *N, SelectionDAG &DAG) {
14931   SDLoc DL(N);
14932   SDValue Op0 = N->getOperand(0);
14933   SDValue Op1 = N->getOperand(1);
14934   EVT ResVT = N->getValueType(0);
14935 
14936   // uzp1(unpklo(uzp1(x, y)), z) => uzp1(x, z)
14937   if (Op0.getOpcode() == AArch64ISD::UUNPKLO) {
14938     if (Op0.getOperand(0).getOpcode() == AArch64ISD::UZP1) {
14939       SDValue X = Op0.getOperand(0).getOperand(0);
14940       return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, X, Op1);
14941     }
14942   }
14943 
14944   // uzp1(x, unpkhi(uzp1(y, z))) => uzp1(x, z)
14945   if (Op1.getOpcode() == AArch64ISD::UUNPKHI) {
14946     if (Op1.getOperand(0).getOpcode() == AArch64ISD::UZP1) {
14947       SDValue Z = Op1.getOperand(0).getOperand(1);
14948       return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, Op0, Z);
14949     }
14950   }
14951 
14952   return SDValue();
14953 }
14954 
14955 static SDValue performGLD1Combine(SDNode *N, SelectionDAG &DAG) {
14956   unsigned Opc = N->getOpcode();
14957 
14958   assert(((Opc >= AArch64ISD::GLD1_MERGE_ZERO && // unsigned gather loads
14959            Opc <= AArch64ISD::GLD1_IMM_MERGE_ZERO) ||
14960           (Opc >= AArch64ISD::GLD1S_MERGE_ZERO && // signed gather loads
14961            Opc <= AArch64ISD::GLD1S_IMM_MERGE_ZERO)) &&
14962          "Invalid opcode.");
14963 
14964   const bool Scaled = Opc == AArch64ISD::GLD1_SCALED_MERGE_ZERO ||
14965                       Opc == AArch64ISD::GLD1S_SCALED_MERGE_ZERO;
14966   const bool Signed = Opc == AArch64ISD::GLD1S_MERGE_ZERO ||
14967                       Opc == AArch64ISD::GLD1S_SCALED_MERGE_ZERO;
14968   const bool Extended = Opc == AArch64ISD::GLD1_SXTW_MERGE_ZERO ||
14969                         Opc == AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO ||
14970                         Opc == AArch64ISD::GLD1_UXTW_MERGE_ZERO ||
14971                         Opc == AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO;
14972 
14973   SDLoc DL(N);
14974   SDValue Chain = N->getOperand(0);
14975   SDValue Pg = N->getOperand(1);
14976   SDValue Base = N->getOperand(2);
14977   SDValue Offset = N->getOperand(3);
14978   SDValue Ty = N->getOperand(4);
14979 
14980   EVT ResVT = N->getValueType(0);
14981 
14982   const auto OffsetOpc = Offset.getOpcode();
14983   const bool OffsetIsZExt =
14984       OffsetOpc == AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU;
14985   const bool OffsetIsSExt =
14986       OffsetOpc == AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU;
14987 
14988   // Fold sign/zero extensions of vector offsets into GLD1 nodes where possible.
14989   if (!Extended && (OffsetIsSExt || OffsetIsZExt)) {
14990     SDValue ExtPg = Offset.getOperand(0);
14991     VTSDNode *ExtFrom = cast<VTSDNode>(Offset.getOperand(2).getNode());
14992     EVT ExtFromEVT = ExtFrom->getVT().getVectorElementType();
14993 
14994     // If the predicate for the sign- or zero-extended offset is the
14995     // same as the predicate used for this load and the sign-/zero-extension
14996     // was from a 32-bits...
14997     if (ExtPg == Pg && ExtFromEVT == MVT::i32) {
14998       SDValue UnextendedOffset = Offset.getOperand(1);
14999 
15000       unsigned NewOpc = getGatherVecOpcode(Scaled, OffsetIsSExt, true);
15001       if (Signed)
15002         NewOpc = getSignExtendedGatherOpcode(NewOpc);
15003 
15004       return DAG.getNode(NewOpc, DL, {ResVT, MVT::Other},
15005                          {Chain, Pg, Base, UnextendedOffset, Ty});
15006     }
15007   }
15008 
15009   return SDValue();
15010 }
15011 
15012 /// Optimize a vector shift instruction and its operand if shifted out
15013 /// bits are not used.
15014 static SDValue performVectorShiftCombine(SDNode *N,
15015                                          const AArch64TargetLowering &TLI,
15016                                          TargetLowering::DAGCombinerInfo &DCI) {
15017   assert(N->getOpcode() == AArch64ISD::VASHR ||
15018          N->getOpcode() == AArch64ISD::VLSHR);
15019 
15020   SDValue Op = N->getOperand(0);
15021   unsigned OpScalarSize = Op.getScalarValueSizeInBits();
15022 
15023   unsigned ShiftImm = N->getConstantOperandVal(1);
15024   assert(OpScalarSize > ShiftImm && "Invalid shift imm");
15025 
15026   APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm);
15027   APInt DemandedMask = ~ShiftedOutBits;
15028 
15029   if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI))
15030     return SDValue(N, 0);
15031 
15032   return SDValue();
15033 }
15034 
15035 /// Target-specific DAG combine function for post-increment LD1 (lane) and
15036 /// post-increment LD1R.
15037 static SDValue performPostLD1Combine(SDNode *N,
15038                                      TargetLowering::DAGCombinerInfo &DCI,
15039                                      bool IsLaneOp) {
15040   if (DCI.isBeforeLegalizeOps())
15041     return SDValue();
15042 
15043   SelectionDAG &DAG = DCI.DAG;
15044   EVT VT = N->getValueType(0);
15045 
15046   if (VT.isScalableVector())
15047     return SDValue();
15048 
15049   unsigned LoadIdx = IsLaneOp ? 1 : 0;
15050   SDNode *LD = N->getOperand(LoadIdx).getNode();
15051   // If it is not LOAD, can not do such combine.
15052   if (LD->getOpcode() != ISD::LOAD)
15053     return SDValue();
15054 
15055   // The vector lane must be a constant in the LD1LANE opcode.
15056   SDValue Lane;
15057   if (IsLaneOp) {
15058     Lane = N->getOperand(2);
15059     auto *LaneC = dyn_cast<ConstantSDNode>(Lane);
15060     if (!LaneC || LaneC->getZExtValue() >= VT.getVectorNumElements())
15061       return SDValue();
15062   }
15063 
15064   LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
15065   EVT MemVT = LoadSDN->getMemoryVT();
15066   // Check if memory operand is the same type as the vector element.
15067   if (MemVT != VT.getVectorElementType())
15068     return SDValue();
15069 
15070   // Check if there are other uses. If so, do not combine as it will introduce
15071   // an extra load.
15072   for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
15073        ++UI) {
15074     if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
15075       continue;
15076     if (*UI != N)
15077       return SDValue();
15078   }
15079 
15080   SDValue Addr = LD->getOperand(1);
15081   SDValue Vector = N->getOperand(0);
15082   // Search for a use of the address operand that is an increment.
15083   for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
15084        Addr.getNode()->use_end(); UI != UE; ++UI) {
15085     SDNode *User = *UI;
15086     if (User->getOpcode() != ISD::ADD
15087         || UI.getUse().getResNo() != Addr.getResNo())
15088       continue;
15089 
15090     // If the increment is a constant, it must match the memory ref size.
15091     SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
15092     if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
15093       uint32_t IncVal = CInc->getZExtValue();
15094       unsigned NumBytes = VT.getScalarSizeInBits() / 8;
15095       if (IncVal != NumBytes)
15096         continue;
15097       Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
15098     }
15099 
15100     // To avoid cycle construction make sure that neither the load nor the add
15101     // are predecessors to each other or the Vector.
15102     SmallPtrSet<const SDNode *, 32> Visited;
15103     SmallVector<const SDNode *, 16> Worklist;
15104     Visited.insert(Addr.getNode());
15105     Worklist.push_back(User);
15106     Worklist.push_back(LD);
15107     Worklist.push_back(Vector.getNode());
15108     if (SDNode::hasPredecessorHelper(LD, Visited, Worklist) ||
15109         SDNode::hasPredecessorHelper(User, Visited, Worklist))
15110       continue;
15111 
15112     SmallVector<SDValue, 8> Ops;
15113     Ops.push_back(LD->getOperand(0));  // Chain
15114     if (IsLaneOp) {
15115       Ops.push_back(Vector);           // The vector to be inserted
15116       Ops.push_back(Lane);             // The lane to be inserted in the vector
15117     }
15118     Ops.push_back(Addr);
15119     Ops.push_back(Inc);
15120 
15121     EVT Tys[3] = { VT, MVT::i64, MVT::Other };
15122     SDVTList SDTys = DAG.getVTList(Tys);
15123     unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
15124     SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
15125                                            MemVT,
15126                                            LoadSDN->getMemOperand());
15127 
15128     // Update the uses.
15129     SDValue NewResults[] = {
15130         SDValue(LD, 0),            // The result of load
15131         SDValue(UpdN.getNode(), 2) // Chain
15132     };
15133     DCI.CombineTo(LD, NewResults);
15134     DCI.CombineTo(N, SDValue(UpdN.getNode(), 0));     // Dup/Inserted Result
15135     DCI.CombineTo(User, SDValue(UpdN.getNode(), 1));  // Write back register
15136 
15137     break;
15138   }
15139   return SDValue();
15140 }
15141 
15142 /// Simplify ``Addr`` given that the top byte of it is ignored by HW during
15143 /// address translation.
15144 static bool performTBISimplification(SDValue Addr,
15145                                      TargetLowering::DAGCombinerInfo &DCI,
15146                                      SelectionDAG &DAG) {
15147   APInt DemandedMask = APInt::getLowBitsSet(64, 56);
15148   KnownBits Known;
15149   TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
15150                                         !DCI.isBeforeLegalizeOps());
15151   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15152   if (TLI.SimplifyDemandedBits(Addr, DemandedMask, Known, TLO)) {
15153     DCI.CommitTargetLoweringOpt(TLO);
15154     return true;
15155   }
15156   return false;
15157 }
15158 
15159 static SDValue foldTruncStoreOfExt(SelectionDAG &DAG, SDNode *N) {
15160   assert(N->getOpcode() == ISD::STORE ||
15161          N->getOpcode() == ISD::MSTORE && "Expected STORE dag node in input!");
15162 
15163   if (auto Store = dyn_cast<StoreSDNode>(N)) {
15164     if (!Store->isTruncatingStore() || Store->isIndexed())
15165       return SDValue();
15166     SDValue Ext = Store->getValue();
15167     auto ExtOpCode = Ext.getOpcode();
15168     if (ExtOpCode != ISD::ZERO_EXTEND && ExtOpCode != ISD::SIGN_EXTEND &&
15169         ExtOpCode != ISD::ANY_EXTEND)
15170       return SDValue();
15171     SDValue Orig = Ext->getOperand(0);
15172     if (Store->getMemoryVT() != Orig->getValueType(0))
15173       return SDValue();
15174     return DAG.getStore(Store->getChain(), SDLoc(Store), Orig,
15175                         Store->getBasePtr(), Store->getPointerInfo(),
15176                         Store->getAlign());
15177   }
15178 
15179   return SDValue();
15180 }
15181 
15182 static SDValue performSTORECombine(SDNode *N,
15183                                    TargetLowering::DAGCombinerInfo &DCI,
15184                                    SelectionDAG &DAG,
15185                                    const AArch64Subtarget *Subtarget) {
15186   if (SDValue Split = splitStores(N, DCI, DAG, Subtarget))
15187     return Split;
15188 
15189   if (Subtarget->supportsAddressTopByteIgnored() &&
15190       performTBISimplification(N->getOperand(2), DCI, DAG))
15191     return SDValue(N, 0);
15192 
15193   if (SDValue Store = foldTruncStoreOfExt(DAG, N))
15194     return Store;
15195 
15196   return SDValue();
15197 }
15198 
15199 /// Target-specific DAG combine function for NEON load/store intrinsics
15200 /// to merge base address updates.
15201 static SDValue performNEONPostLDSTCombine(SDNode *N,
15202                                           TargetLowering::DAGCombinerInfo &DCI,
15203                                           SelectionDAG &DAG) {
15204   if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15205     return SDValue();
15206 
15207   unsigned AddrOpIdx = N->getNumOperands() - 1;
15208   SDValue Addr = N->getOperand(AddrOpIdx);
15209 
15210   // Search for a use of the address operand that is an increment.
15211   for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
15212        UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
15213     SDNode *User = *UI;
15214     if (User->getOpcode() != ISD::ADD ||
15215         UI.getUse().getResNo() != Addr.getResNo())
15216       continue;
15217 
15218     // Check that the add is independent of the load/store.  Otherwise, folding
15219     // it would create a cycle.
15220     SmallPtrSet<const SDNode *, 32> Visited;
15221     SmallVector<const SDNode *, 16> Worklist;
15222     Visited.insert(Addr.getNode());
15223     Worklist.push_back(N);
15224     Worklist.push_back(User);
15225     if (SDNode::hasPredecessorHelper(N, Visited, Worklist) ||
15226         SDNode::hasPredecessorHelper(User, Visited, Worklist))
15227       continue;
15228 
15229     // Find the new opcode for the updating load/store.
15230     bool IsStore = false;
15231     bool IsLaneOp = false;
15232     bool IsDupOp = false;
15233     unsigned NewOpc = 0;
15234     unsigned NumVecs = 0;
15235     unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
15236     switch (IntNo) {
15237     default: llvm_unreachable("unexpected intrinsic for Neon base update");
15238     case Intrinsic::aarch64_neon_ld2:       NewOpc = AArch64ISD::LD2post;
15239       NumVecs = 2; break;
15240     case Intrinsic::aarch64_neon_ld3:       NewOpc = AArch64ISD::LD3post;
15241       NumVecs = 3; break;
15242     case Intrinsic::aarch64_neon_ld4:       NewOpc = AArch64ISD::LD4post;
15243       NumVecs = 4; break;
15244     case Intrinsic::aarch64_neon_st2:       NewOpc = AArch64ISD::ST2post;
15245       NumVecs = 2; IsStore = true; break;
15246     case Intrinsic::aarch64_neon_st3:       NewOpc = AArch64ISD::ST3post;
15247       NumVecs = 3; IsStore = true; break;
15248     case Intrinsic::aarch64_neon_st4:       NewOpc = AArch64ISD::ST4post;
15249       NumVecs = 4; IsStore = true; break;
15250     case Intrinsic::aarch64_neon_ld1x2:     NewOpc = AArch64ISD::LD1x2post;
15251       NumVecs = 2; break;
15252     case Intrinsic::aarch64_neon_ld1x3:     NewOpc = AArch64ISD::LD1x3post;
15253       NumVecs = 3; break;
15254     case Intrinsic::aarch64_neon_ld1x4:     NewOpc = AArch64ISD::LD1x4post;
15255       NumVecs = 4; break;
15256     case Intrinsic::aarch64_neon_st1x2:     NewOpc = AArch64ISD::ST1x2post;
15257       NumVecs = 2; IsStore = true; break;
15258     case Intrinsic::aarch64_neon_st1x3:     NewOpc = AArch64ISD::ST1x3post;
15259       NumVecs = 3; IsStore = true; break;
15260     case Intrinsic::aarch64_neon_st1x4:     NewOpc = AArch64ISD::ST1x4post;
15261       NumVecs = 4; IsStore = true; break;
15262     case Intrinsic::aarch64_neon_ld2r:      NewOpc = AArch64ISD::LD2DUPpost;
15263       NumVecs = 2; IsDupOp = true; break;
15264     case Intrinsic::aarch64_neon_ld3r:      NewOpc = AArch64ISD::LD3DUPpost;
15265       NumVecs = 3; IsDupOp = true; break;
15266     case Intrinsic::aarch64_neon_ld4r:      NewOpc = AArch64ISD::LD4DUPpost;
15267       NumVecs = 4; IsDupOp = true; break;
15268     case Intrinsic::aarch64_neon_ld2lane:   NewOpc = AArch64ISD::LD2LANEpost;
15269       NumVecs = 2; IsLaneOp = true; break;
15270     case Intrinsic::aarch64_neon_ld3lane:   NewOpc = AArch64ISD::LD3LANEpost;
15271       NumVecs = 3; IsLaneOp = true; break;
15272     case Intrinsic::aarch64_neon_ld4lane:   NewOpc = AArch64ISD::LD4LANEpost;
15273       NumVecs = 4; IsLaneOp = true; break;
15274     case Intrinsic::aarch64_neon_st2lane:   NewOpc = AArch64ISD::ST2LANEpost;
15275       NumVecs = 2; IsStore = true; IsLaneOp = true; break;
15276     case Intrinsic::aarch64_neon_st3lane:   NewOpc = AArch64ISD::ST3LANEpost;
15277       NumVecs = 3; IsStore = true; IsLaneOp = true; break;
15278     case Intrinsic::aarch64_neon_st4lane:   NewOpc = AArch64ISD::ST4LANEpost;
15279       NumVecs = 4; IsStore = true; IsLaneOp = true; break;
15280     }
15281 
15282     EVT VecTy;
15283     if (IsStore)
15284       VecTy = N->getOperand(2).getValueType();
15285     else
15286       VecTy = N->getValueType(0);
15287 
15288     // If the increment is a constant, it must match the memory ref size.
15289     SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
15290     if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
15291       uint32_t IncVal = CInc->getZExtValue();
15292       unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
15293       if (IsLaneOp || IsDupOp)
15294         NumBytes /= VecTy.getVectorNumElements();
15295       if (IncVal != NumBytes)
15296         continue;
15297       Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
15298     }
15299     SmallVector<SDValue, 8> Ops;
15300     Ops.push_back(N->getOperand(0)); // Incoming chain
15301     // Load lane and store have vector list as input.
15302     if (IsLaneOp || IsStore)
15303       for (unsigned i = 2; i < AddrOpIdx; ++i)
15304         Ops.push_back(N->getOperand(i));
15305     Ops.push_back(Addr); // Base register
15306     Ops.push_back(Inc);
15307 
15308     // Return Types.
15309     EVT Tys[6];
15310     unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
15311     unsigned n;
15312     for (n = 0; n < NumResultVecs; ++n)
15313       Tys[n] = VecTy;
15314     Tys[n++] = MVT::i64;  // Type of write back register
15315     Tys[n] = MVT::Other;  // Type of the chain
15316     SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
15317 
15318     MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
15319     SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
15320                                            MemInt->getMemoryVT(),
15321                                            MemInt->getMemOperand());
15322 
15323     // Update the uses.
15324     std::vector<SDValue> NewResults;
15325     for (unsigned i = 0; i < NumResultVecs; ++i) {
15326       NewResults.push_back(SDValue(UpdN.getNode(), i));
15327     }
15328     NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
15329     DCI.CombineTo(N, NewResults);
15330     DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
15331 
15332     break;
15333   }
15334   return SDValue();
15335 }
15336 
15337 // Checks to see if the value is the prescribed width and returns information
15338 // about its extension mode.
15339 static
15340 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
15341   ExtType = ISD::NON_EXTLOAD;
15342   switch(V.getNode()->getOpcode()) {
15343   default:
15344     return false;
15345   case ISD::LOAD: {
15346     LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
15347     if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
15348        || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
15349       ExtType = LoadNode->getExtensionType();
15350       return true;
15351     }
15352     return false;
15353   }
15354   case ISD::AssertSext: {
15355     VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
15356     if ((TypeNode->getVT() == MVT::i8 && width == 8)
15357        || (TypeNode->getVT() == MVT::i16 && width == 16)) {
15358       ExtType = ISD::SEXTLOAD;
15359       return true;
15360     }
15361     return false;
15362   }
15363   case ISD::AssertZext: {
15364     VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
15365     if ((TypeNode->getVT() == MVT::i8 && width == 8)
15366        || (TypeNode->getVT() == MVT::i16 && width == 16)) {
15367       ExtType = ISD::ZEXTLOAD;
15368       return true;
15369     }
15370     return false;
15371   }
15372   case ISD::Constant:
15373   case ISD::TargetConstant: {
15374     return std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
15375            1LL << (width - 1);
15376   }
15377   }
15378 
15379   return true;
15380 }
15381 
15382 // This function does a whole lot of voodoo to determine if the tests are
15383 // equivalent without and with a mask. Essentially what happens is that given a
15384 // DAG resembling:
15385 //
15386 //  +-------------+ +-------------+ +-------------+ +-------------+
15387 //  |    Input    | | AddConstant | | CompConstant| |     CC      |
15388 //  +-------------+ +-------------+ +-------------+ +-------------+
15389 //           |           |           |               |
15390 //           V           V           |    +----------+
15391 //          +-------------+  +----+  |    |
15392 //          |     ADD     |  |0xff|  |    |
15393 //          +-------------+  +----+  |    |
15394 //                  |           |    |    |
15395 //                  V           V    |    |
15396 //                 +-------------+   |    |
15397 //                 |     AND     |   |    |
15398 //                 +-------------+   |    |
15399 //                      |            |    |
15400 //                      +-----+      |    |
15401 //                            |      |    |
15402 //                            V      V    V
15403 //                           +-------------+
15404 //                           |     CMP     |
15405 //                           +-------------+
15406 //
15407 // The AND node may be safely removed for some combinations of inputs. In
15408 // particular we need to take into account the extension type of the Input,
15409 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
15410 // width of the input (this can work for any width inputs, the above graph is
15411 // specific to 8 bits.
15412 //
15413 // The specific equations were worked out by generating output tables for each
15414 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
15415 // problem was simplified by working with 4 bit inputs, which means we only
15416 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
15417 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
15418 // patterns present in both extensions (0,7). For every distinct set of
15419 // AddConstant and CompConstants bit patterns we can consider the masked and
15420 // unmasked versions to be equivalent if the result of this function is true for
15421 // all 16 distinct bit patterns of for the current extension type of Input (w0).
15422 //
15423 //   sub      w8, w0, w1
15424 //   and      w10, w8, #0x0f
15425 //   cmp      w8, w2
15426 //   cset     w9, AArch64CC
15427 //   cmp      w10, w2
15428 //   cset     w11, AArch64CC
15429 //   cmp      w9, w11
15430 //   cset     w0, eq
15431 //   ret
15432 //
15433 // Since the above function shows when the outputs are equivalent it defines
15434 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
15435 // would be expensive to run during compiles. The equations below were written
15436 // in a test harness that confirmed they gave equivalent outputs to the above
15437 // for all inputs function, so they can be used determine if the removal is
15438 // legal instead.
15439 //
15440 // isEquivalentMaskless() is the code for testing if the AND can be removed
15441 // factored out of the DAG recognition as the DAG can take several forms.
15442 
15443 static bool isEquivalentMaskless(unsigned CC, unsigned width,
15444                                  ISD::LoadExtType ExtType, int AddConstant,
15445                                  int CompConstant) {
15446   // By being careful about our equations and only writing the in term
15447   // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
15448   // make them generally applicable to all bit widths.
15449   int MaxUInt = (1 << width);
15450 
15451   // For the purposes of these comparisons sign extending the type is
15452   // equivalent to zero extending the add and displacing it by half the integer
15453   // width. Provided we are careful and make sure our equations are valid over
15454   // the whole range we can just adjust the input and avoid writing equations
15455   // for sign extended inputs.
15456   if (ExtType == ISD::SEXTLOAD)
15457     AddConstant -= (1 << (width-1));
15458 
15459   switch(CC) {
15460   case AArch64CC::LE:
15461   case AArch64CC::GT:
15462     if ((AddConstant == 0) ||
15463         (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
15464         (AddConstant >= 0 && CompConstant < 0) ||
15465         (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
15466       return true;
15467     break;
15468   case AArch64CC::LT:
15469   case AArch64CC::GE:
15470     if ((AddConstant == 0) ||
15471         (AddConstant >= 0 && CompConstant <= 0) ||
15472         (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
15473       return true;
15474     break;
15475   case AArch64CC::HI:
15476   case AArch64CC::LS:
15477     if ((AddConstant >= 0 && CompConstant < 0) ||
15478        (AddConstant <= 0 && CompConstant >= -1 &&
15479         CompConstant < AddConstant + MaxUInt))
15480       return true;
15481    break;
15482   case AArch64CC::PL:
15483   case AArch64CC::MI:
15484     if ((AddConstant == 0) ||
15485         (AddConstant > 0 && CompConstant <= 0) ||
15486         (AddConstant < 0 && CompConstant <= AddConstant))
15487       return true;
15488     break;
15489   case AArch64CC::LO:
15490   case AArch64CC::HS:
15491     if ((AddConstant >= 0 && CompConstant <= 0) ||
15492         (AddConstant <= 0 && CompConstant >= 0 &&
15493          CompConstant <= AddConstant + MaxUInt))
15494       return true;
15495     break;
15496   case AArch64CC::EQ:
15497   case AArch64CC::NE:
15498     if ((AddConstant > 0 && CompConstant < 0) ||
15499         (AddConstant < 0 && CompConstant >= 0 &&
15500          CompConstant < AddConstant + MaxUInt) ||
15501         (AddConstant >= 0 && CompConstant >= 0 &&
15502          CompConstant >= AddConstant) ||
15503         (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
15504       return true;
15505     break;
15506   case AArch64CC::VS:
15507   case AArch64CC::VC:
15508   case AArch64CC::AL:
15509   case AArch64CC::NV:
15510     return true;
15511   case AArch64CC::Invalid:
15512     break;
15513   }
15514 
15515   return false;
15516 }
15517 
15518 static
15519 SDValue performCONDCombine(SDNode *N,
15520                            TargetLowering::DAGCombinerInfo &DCI,
15521                            SelectionDAG &DAG, unsigned CCIndex,
15522                            unsigned CmpIndex) {
15523   unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
15524   SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
15525   unsigned CondOpcode = SubsNode->getOpcode();
15526 
15527   if (CondOpcode != AArch64ISD::SUBS)
15528     return SDValue();
15529 
15530   // There is a SUBS feeding this condition. Is it fed by a mask we can
15531   // use?
15532 
15533   SDNode *AndNode = SubsNode->getOperand(0).getNode();
15534   unsigned MaskBits = 0;
15535 
15536   if (AndNode->getOpcode() != ISD::AND)
15537     return SDValue();
15538 
15539   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
15540     uint32_t CNV = CN->getZExtValue();
15541     if (CNV == 255)
15542       MaskBits = 8;
15543     else if (CNV == 65535)
15544       MaskBits = 16;
15545   }
15546 
15547   if (!MaskBits)
15548     return SDValue();
15549 
15550   SDValue AddValue = AndNode->getOperand(0);
15551 
15552   if (AddValue.getOpcode() != ISD::ADD)
15553     return SDValue();
15554 
15555   // The basic dag structure is correct, grab the inputs and validate them.
15556 
15557   SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
15558   SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
15559   SDValue SubsInputValue = SubsNode->getOperand(1);
15560 
15561   // The mask is present and the provenance of all the values is a smaller type,
15562   // lets see if the mask is superfluous.
15563 
15564   if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
15565       !isa<ConstantSDNode>(SubsInputValue.getNode()))
15566     return SDValue();
15567 
15568   ISD::LoadExtType ExtType;
15569 
15570   if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
15571       !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
15572       !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
15573     return SDValue();
15574 
15575   if(!isEquivalentMaskless(CC, MaskBits, ExtType,
15576                 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
15577                 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
15578     return SDValue();
15579 
15580   // The AND is not necessary, remove it.
15581 
15582   SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
15583                                SubsNode->getValueType(1));
15584   SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
15585 
15586   SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
15587   DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
15588 
15589   return SDValue(N, 0);
15590 }
15591 
15592 // Optimize compare with zero and branch.
15593 static SDValue performBRCONDCombine(SDNode *N,
15594                                     TargetLowering::DAGCombinerInfo &DCI,
15595                                     SelectionDAG &DAG) {
15596   MachineFunction &MF = DAG.getMachineFunction();
15597   // Speculation tracking/SLH assumes that optimized TB(N)Z/CB(N)Z instructions
15598   // will not be produced, as they are conditional branch instructions that do
15599   // not set flags.
15600   if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
15601     return SDValue();
15602 
15603   if (SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3))
15604     N = NV.getNode();
15605   SDValue Chain = N->getOperand(0);
15606   SDValue Dest = N->getOperand(1);
15607   SDValue CCVal = N->getOperand(2);
15608   SDValue Cmp = N->getOperand(3);
15609 
15610   assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
15611   unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
15612   if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
15613     return SDValue();
15614 
15615   unsigned CmpOpc = Cmp.getOpcode();
15616   if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
15617     return SDValue();
15618 
15619   // Only attempt folding if there is only one use of the flag and no use of the
15620   // value.
15621   if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
15622     return SDValue();
15623 
15624   SDValue LHS = Cmp.getOperand(0);
15625   SDValue RHS = Cmp.getOperand(1);
15626 
15627   assert(LHS.getValueType() == RHS.getValueType() &&
15628          "Expected the value type to be the same for both operands!");
15629   if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
15630     return SDValue();
15631 
15632   if (isNullConstant(LHS))
15633     std::swap(LHS, RHS);
15634 
15635   if (!isNullConstant(RHS))
15636     return SDValue();
15637 
15638   if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
15639       LHS.getOpcode() == ISD::SRL)
15640     return SDValue();
15641 
15642   // Fold the compare into the branch instruction.
15643   SDValue BR;
15644   if (CC == AArch64CC::EQ)
15645     BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
15646   else
15647     BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
15648 
15649   // Do not add new nodes to DAG combiner worklist.
15650   DCI.CombineTo(N, BR, false);
15651 
15652   return SDValue();
15653 }
15654 
15655 // Optimize CSEL instructions
15656 static SDValue performCSELCombine(SDNode *N,
15657                                   TargetLowering::DAGCombinerInfo &DCI,
15658                                   SelectionDAG &DAG) {
15659   // CSEL x, x, cc -> x
15660   if (N->getOperand(0) == N->getOperand(1))
15661     return N->getOperand(0);
15662 
15663   return performCONDCombine(N, DCI, DAG, 2, 3);
15664 }
15665 
15666 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15667   assert(N->getOpcode() == ISD::SETCC && "Unexpected opcode!");
15668   SDValue LHS = N->getOperand(0);
15669   SDValue RHS = N->getOperand(1);
15670   ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
15671 
15672   // setcc (csel 0, 1, cond, X), 1, ne ==> csel 0, 1, !cond, X
15673   if (Cond == ISD::SETNE && isOneConstant(RHS) &&
15674       LHS->getOpcode() == AArch64ISD::CSEL &&
15675       isNullConstant(LHS->getOperand(0)) && isOneConstant(LHS->getOperand(1)) &&
15676       LHS->hasOneUse()) {
15677     SDLoc DL(N);
15678 
15679     // Invert CSEL's condition.
15680     auto *OpCC = cast<ConstantSDNode>(LHS.getOperand(2));
15681     auto OldCond = static_cast<AArch64CC::CondCode>(OpCC->getZExtValue());
15682     auto NewCond = getInvertedCondCode(OldCond);
15683 
15684     // csel 0, 1, !cond, X
15685     SDValue CSEL =
15686         DAG.getNode(AArch64ISD::CSEL, DL, LHS.getValueType(), LHS.getOperand(0),
15687                     LHS.getOperand(1), DAG.getConstant(NewCond, DL, MVT::i32),
15688                     LHS.getOperand(3));
15689     return DAG.getZExtOrTrunc(CSEL, DL, N->getValueType(0));
15690   }
15691 
15692   return SDValue();
15693 }
15694 
15695 static SDValue performSetccMergeZeroCombine(SDNode *N, SelectionDAG &DAG) {
15696   assert(N->getOpcode() == AArch64ISD::SETCC_MERGE_ZERO &&
15697          "Unexpected opcode!");
15698 
15699   SDValue Pred = N->getOperand(0);
15700   SDValue LHS = N->getOperand(1);
15701   SDValue RHS = N->getOperand(2);
15702   ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(3))->get();
15703 
15704   // setcc_merge_zero pred (sign_extend (setcc_merge_zero ... pred ...)), 0, ne
15705   //    => inner setcc_merge_zero
15706   if (Cond == ISD::SETNE && isZerosVector(RHS.getNode()) &&
15707       LHS->getOpcode() == ISD::SIGN_EXTEND &&
15708       LHS->getOperand(0)->getValueType(0) == N->getValueType(0) &&
15709       LHS->getOperand(0)->getOpcode() == AArch64ISD::SETCC_MERGE_ZERO &&
15710       LHS->getOperand(0)->getOperand(0) == Pred)
15711     return LHS->getOperand(0);
15712 
15713   return SDValue();
15714 }
15715 
15716 // Optimize some simple tbz/tbnz cases.  Returns the new operand and bit to test
15717 // as well as whether the test should be inverted.  This code is required to
15718 // catch these cases (as opposed to standard dag combines) because
15719 // AArch64ISD::TBZ is matched during legalization.
15720 static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert,
15721                                  SelectionDAG &DAG) {
15722 
15723   if (!Op->hasOneUse())
15724     return Op;
15725 
15726   // We don't handle undef/constant-fold cases below, as they should have
15727   // already been taken care of (e.g. and of 0, test of undefined shifted bits,
15728   // etc.)
15729 
15730   // (tbz (trunc x), b) -> (tbz x, b)
15731   // This case is just here to enable more of the below cases to be caught.
15732   if (Op->getOpcode() == ISD::TRUNCATE &&
15733       Bit < Op->getValueType(0).getSizeInBits()) {
15734     return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
15735   }
15736 
15737   // (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
15738   if (Op->getOpcode() == ISD::ANY_EXTEND &&
15739       Bit < Op->getOperand(0).getValueSizeInBits()) {
15740     return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
15741   }
15742 
15743   if (Op->getNumOperands() != 2)
15744     return Op;
15745 
15746   auto *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
15747   if (!C)
15748     return Op;
15749 
15750   switch (Op->getOpcode()) {
15751   default:
15752     return Op;
15753 
15754   // (tbz (and x, m), b) -> (tbz x, b)
15755   case ISD::AND:
15756     if ((C->getZExtValue() >> Bit) & 1)
15757       return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
15758     return Op;
15759 
15760   // (tbz (shl x, c), b) -> (tbz x, b-c)
15761   case ISD::SHL:
15762     if (C->getZExtValue() <= Bit &&
15763         (Bit - C->getZExtValue()) < Op->getValueType(0).getSizeInBits()) {
15764       Bit = Bit - C->getZExtValue();
15765       return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
15766     }
15767     return Op;
15768 
15769   // (tbz (sra x, c), b) -> (tbz x, b+c) or (tbz x, msb) if b+c is > # bits in x
15770   case ISD::SRA:
15771     Bit = Bit + C->getZExtValue();
15772     if (Bit >= Op->getValueType(0).getSizeInBits())
15773       Bit = Op->getValueType(0).getSizeInBits() - 1;
15774     return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
15775 
15776   // (tbz (srl x, c), b) -> (tbz x, b+c)
15777   case ISD::SRL:
15778     if ((Bit + C->getZExtValue()) < Op->getValueType(0).getSizeInBits()) {
15779       Bit = Bit + C->getZExtValue();
15780       return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
15781     }
15782     return Op;
15783 
15784   // (tbz (xor x, -1), b) -> (tbnz x, b)
15785   case ISD::XOR:
15786     if ((C->getZExtValue() >> Bit) & 1)
15787       Invert = !Invert;
15788     return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
15789   }
15790 }
15791 
15792 // Optimize test single bit zero/non-zero and branch.
15793 static SDValue performTBZCombine(SDNode *N,
15794                                  TargetLowering::DAGCombinerInfo &DCI,
15795                                  SelectionDAG &DAG) {
15796   unsigned Bit = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
15797   bool Invert = false;
15798   SDValue TestSrc = N->getOperand(1);
15799   SDValue NewTestSrc = getTestBitOperand(TestSrc, Bit, Invert, DAG);
15800 
15801   if (TestSrc == NewTestSrc)
15802     return SDValue();
15803 
15804   unsigned NewOpc = N->getOpcode();
15805   if (Invert) {
15806     if (NewOpc == AArch64ISD::TBZ)
15807       NewOpc = AArch64ISD::TBNZ;
15808     else {
15809       assert(NewOpc == AArch64ISD::TBNZ);
15810       NewOpc = AArch64ISD::TBZ;
15811     }
15812   }
15813 
15814   SDLoc DL(N);
15815   return DAG.getNode(NewOpc, DL, MVT::Other, N->getOperand(0), NewTestSrc,
15816                      DAG.getConstant(Bit, DL, MVT::i64), N->getOperand(3));
15817 }
15818 
15819 // vselect (v1i1 setcc) ->
15820 //     vselect (v1iXX setcc)  (XX is the size of the compared operand type)
15821 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
15822 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
15823 // such VSELECT.
15824 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
15825   SDValue N0 = N->getOperand(0);
15826   EVT CCVT = N0.getValueType();
15827 
15828   // Check for sign pattern (VSELECT setgt, iN lhs, -1, 1, -1) and transform
15829   // into (OR (ASR lhs, N-1), 1), which requires less instructions for the
15830   // supported types.
15831   SDValue SetCC = N->getOperand(0);
15832   if (SetCC.getOpcode() == ISD::SETCC &&
15833       SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) {
15834     SDValue CmpLHS = SetCC.getOperand(0);
15835     EVT VT = CmpLHS.getValueType();
15836     SDNode *CmpRHS = SetCC.getOperand(1).getNode();
15837     SDNode *SplatLHS = N->getOperand(1).getNode();
15838     SDNode *SplatRHS = N->getOperand(2).getNode();
15839     APInt SplatLHSVal;
15840     if (CmpLHS.getValueType() == N->getOperand(1).getValueType() &&
15841         VT.isSimple() &&
15842         is_contained(
15843             makeArrayRef({MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
15844                           MVT::v2i32, MVT::v4i32, MVT::v2i64}),
15845             VT.getSimpleVT().SimpleTy) &&
15846         ISD::isConstantSplatVector(SplatLHS, SplatLHSVal) &&
15847         SplatLHSVal.isOneValue() && ISD::isConstantSplatVectorAllOnes(CmpRHS) &&
15848         ISD::isConstantSplatVectorAllOnes(SplatRHS)) {
15849       unsigned NumElts = VT.getVectorNumElements();
15850       SmallVector<SDValue, 8> Ops(
15851           NumElts, DAG.getConstant(VT.getScalarSizeInBits() - 1, SDLoc(N),
15852                                    VT.getScalarType()));
15853       SDValue Val = DAG.getBuildVector(VT, SDLoc(N), Ops);
15854 
15855       auto Shift = DAG.getNode(ISD::SRA, SDLoc(N), VT, CmpLHS, Val);
15856       auto Or = DAG.getNode(ISD::OR, SDLoc(N), VT, Shift, N->getOperand(1));
15857       return Or;
15858     }
15859   }
15860 
15861   if (N0.getOpcode() != ISD::SETCC ||
15862       CCVT.getVectorElementCount() != ElementCount::getFixed(1) ||
15863       CCVT.getVectorElementType() != MVT::i1)
15864     return SDValue();
15865 
15866   EVT ResVT = N->getValueType(0);
15867   EVT CmpVT = N0.getOperand(0).getValueType();
15868   // Only combine when the result type is of the same size as the compared
15869   // operands.
15870   if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
15871     return SDValue();
15872 
15873   SDValue IfTrue = N->getOperand(1);
15874   SDValue IfFalse = N->getOperand(2);
15875   SetCC = DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
15876                        N0.getOperand(0), N0.getOperand(1),
15877                        cast<CondCodeSDNode>(N0.getOperand(2))->get());
15878   return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
15879                      IfTrue, IfFalse);
15880 }
15881 
15882 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
15883 /// the compare-mask instructions rather than going via NZCV, even if LHS and
15884 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
15885 /// with a vector one followed by a DUP shuffle on the result.
15886 static SDValue performSelectCombine(SDNode *N,
15887                                     TargetLowering::DAGCombinerInfo &DCI) {
15888   SelectionDAG &DAG = DCI.DAG;
15889   SDValue N0 = N->getOperand(0);
15890   EVT ResVT = N->getValueType(0);
15891 
15892   if (N0.getOpcode() != ISD::SETCC)
15893     return SDValue();
15894 
15895   if (ResVT.isScalableVector())
15896     return SDValue();
15897 
15898   // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
15899   // scalar SetCCResultType. We also don't expect vectors, because we assume
15900   // that selects fed by vector SETCCs are canonicalized to VSELECT.
15901   assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
15902          "Scalar-SETCC feeding SELECT has unexpected result type!");
15903 
15904   // If NumMaskElts == 0, the comparison is larger than select result. The
15905   // largest real NEON comparison is 64-bits per lane, which means the result is
15906   // at most 32-bits and an illegal vector. Just bail out for now.
15907   EVT SrcVT = N0.getOperand(0).getValueType();
15908 
15909   // Don't try to do this optimization when the setcc itself has i1 operands.
15910   // There are no legal vectors of i1, so this would be pointless.
15911   if (SrcVT == MVT::i1)
15912     return SDValue();
15913 
15914   int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
15915   if (!ResVT.isVector() || NumMaskElts == 0)
15916     return SDValue();
15917 
15918   SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
15919   EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
15920 
15921   // Also bail out if the vector CCVT isn't the same size as ResVT.
15922   // This can happen if the SETCC operand size doesn't divide the ResVT size
15923   // (e.g., f64 vs v3f32).
15924   if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
15925     return SDValue();
15926 
15927   // Make sure we didn't create illegal types, if we're not supposed to.
15928   assert(DCI.isBeforeLegalize() ||
15929          DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
15930 
15931   // First perform a vector comparison, where lane 0 is the one we're interested
15932   // in.
15933   SDLoc DL(N0);
15934   SDValue LHS =
15935       DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
15936   SDValue RHS =
15937       DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
15938   SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
15939 
15940   // Now duplicate the comparison mask we want across all other lanes.
15941   SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
15942   SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask);
15943   Mask = DAG.getNode(ISD::BITCAST, DL,
15944                      ResVT.changeVectorElementTypeToInteger(), Mask);
15945 
15946   return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
15947 }
15948 
15949 /// Get rid of unnecessary NVCASTs (that don't change the type).
15950 static SDValue performNVCASTCombine(SDNode *N) {
15951   if (N->getValueType(0) == N->getOperand(0).getValueType())
15952     return N->getOperand(0);
15953 
15954   return SDValue();
15955 }
15956 
15957 // If all users of the globaladdr are of the form (globaladdr + constant), find
15958 // the smallest constant, fold it into the globaladdr's offset and rewrite the
15959 // globaladdr as (globaladdr + constant) - constant.
15960 static SDValue performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG,
15961                                            const AArch64Subtarget *Subtarget,
15962                                            const TargetMachine &TM) {
15963   auto *GN = cast<GlobalAddressSDNode>(N);
15964   if (Subtarget->ClassifyGlobalReference(GN->getGlobal(), TM) !=
15965       AArch64II::MO_NO_FLAG)
15966     return SDValue();
15967 
15968   uint64_t MinOffset = -1ull;
15969   for (SDNode *N : GN->uses()) {
15970     if (N->getOpcode() != ISD::ADD)
15971       return SDValue();
15972     auto *C = dyn_cast<ConstantSDNode>(N->getOperand(0));
15973     if (!C)
15974       C = dyn_cast<ConstantSDNode>(N->getOperand(1));
15975     if (!C)
15976       return SDValue();
15977     MinOffset = std::min(MinOffset, C->getZExtValue());
15978   }
15979   uint64_t Offset = MinOffset + GN->getOffset();
15980 
15981   // Require that the new offset is larger than the existing one. Otherwise, we
15982   // can end up oscillating between two possible DAGs, for example,
15983   // (add (add globaladdr + 10, -1), 1) and (add globaladdr + 9, 1).
15984   if (Offset <= uint64_t(GN->getOffset()))
15985     return SDValue();
15986 
15987   // Check whether folding this offset is legal. It must not go out of bounds of
15988   // the referenced object to avoid violating the code model, and must be
15989   // smaller than 2^21 because this is the largest offset expressible in all
15990   // object formats.
15991   //
15992   // This check also prevents us from folding negative offsets, which will end
15993   // up being treated in the same way as large positive ones. They could also
15994   // cause code model violations, and aren't really common enough to matter.
15995   if (Offset >= (1 << 21))
15996     return SDValue();
15997 
15998   const GlobalValue *GV = GN->getGlobal();
15999   Type *T = GV->getValueType();
16000   if (!T->isSized() ||
16001       Offset > GV->getParent()->getDataLayout().getTypeAllocSize(T))
16002     return SDValue();
16003 
16004   SDLoc DL(GN);
16005   SDValue Result = DAG.getGlobalAddress(GV, DL, MVT::i64, Offset);
16006   return DAG.getNode(ISD::SUB, DL, MVT::i64, Result,
16007                      DAG.getConstant(MinOffset, DL, MVT::i64));
16008 }
16009 
16010 // Turns the vector of indices into a vector of byte offstes by scaling Offset
16011 // by (BitWidth / 8).
16012 static SDValue getScaledOffsetForBitWidth(SelectionDAG &DAG, SDValue Offset,
16013                                           SDLoc DL, unsigned BitWidth) {
16014   assert(Offset.getValueType().isScalableVector() &&
16015          "This method is only for scalable vectors of offsets");
16016 
16017   SDValue Shift = DAG.getConstant(Log2_32(BitWidth / 8), DL, MVT::i64);
16018   SDValue SplatShift = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::nxv2i64, Shift);
16019 
16020   return DAG.getNode(ISD::SHL, DL, MVT::nxv2i64, Offset, SplatShift);
16021 }
16022 
16023 /// Check if the value of \p OffsetInBytes can be used as an immediate for
16024 /// the gather load/prefetch and scatter store instructions with vector base and
16025 /// immediate offset addressing mode:
16026 ///
16027 ///      [<Zn>.[S|D]{, #<imm>}]
16028 ///
16029 /// where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.
16030 inline static bool isValidImmForSVEVecImmAddrMode(unsigned OffsetInBytes,
16031                                                   unsigned ScalarSizeInBytes) {
16032   // The immediate is not a multiple of the scalar size.
16033   if (OffsetInBytes % ScalarSizeInBytes)
16034     return false;
16035 
16036   // The immediate is out of range.
16037   if (OffsetInBytes / ScalarSizeInBytes > 31)
16038     return false;
16039 
16040   return true;
16041 }
16042 
16043 /// Check if the value of \p Offset represents a valid immediate for the SVE
16044 /// gather load/prefetch and scatter store instructiona with vector base and
16045 /// immediate offset addressing mode:
16046 ///
16047 ///      [<Zn>.[S|D]{, #<imm>}]
16048 ///
16049 /// where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.
16050 static bool isValidImmForSVEVecImmAddrMode(SDValue Offset,
16051                                            unsigned ScalarSizeInBytes) {
16052   ConstantSDNode *OffsetConst = dyn_cast<ConstantSDNode>(Offset.getNode());
16053   return OffsetConst && isValidImmForSVEVecImmAddrMode(
16054                             OffsetConst->getZExtValue(), ScalarSizeInBytes);
16055 }
16056 
16057 static SDValue performScatterStoreCombine(SDNode *N, SelectionDAG &DAG,
16058                                           unsigned Opcode,
16059                                           bool OnlyPackedOffsets = true) {
16060   const SDValue Src = N->getOperand(2);
16061   const EVT SrcVT = Src->getValueType(0);
16062   assert(SrcVT.isScalableVector() &&
16063          "Scatter stores are only possible for SVE vectors");
16064 
16065   SDLoc DL(N);
16066   MVT SrcElVT = SrcVT.getVectorElementType().getSimpleVT();
16067 
16068   // Make sure that source data will fit into an SVE register
16069   if (SrcVT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock)
16070     return SDValue();
16071 
16072   // For FPs, ACLE only supports _packed_ single and double precision types.
16073   if (SrcElVT.isFloatingPoint())
16074     if ((SrcVT != MVT::nxv4f32) && (SrcVT != MVT::nxv2f64))
16075       return SDValue();
16076 
16077   // Depending on the addressing mode, this is either a pointer or a vector of
16078   // pointers (that fits into one register)
16079   SDValue Base = N->getOperand(4);
16080   // Depending on the addressing mode, this is either a single offset or a
16081   // vector of offsets  (that fits into one register)
16082   SDValue Offset = N->getOperand(5);
16083 
16084   // For "scalar + vector of indices", just scale the indices. This only
16085   // applies to non-temporal scatters because there's no instruction that takes
16086   // indicies.
16087   if (Opcode == AArch64ISD::SSTNT1_INDEX_PRED) {
16088     Offset =
16089         getScaledOffsetForBitWidth(DAG, Offset, DL, SrcElVT.getSizeInBits());
16090     Opcode = AArch64ISD::SSTNT1_PRED;
16091   }
16092 
16093   // In the case of non-temporal gather loads there's only one SVE instruction
16094   // per data-size: "scalar + vector", i.e.
16095   //    * stnt1{b|h|w|d} { z0.s }, p0/z, [z0.s, x0]
16096   // Since we do have intrinsics that allow the arguments to be in a different
16097   // order, we may need to swap them to match the spec.
16098   if (Opcode == AArch64ISD::SSTNT1_PRED && Offset.getValueType().isVector())
16099     std::swap(Base, Offset);
16100 
16101   // SST1_IMM requires that the offset is an immediate that is:
16102   //    * a multiple of #SizeInBytes,
16103   //    * in the range [0, 31 x #SizeInBytes],
16104   // where #SizeInBytes is the size in bytes of the stored items. For
16105   // immediates outside that range and non-immediate scalar offsets use SST1 or
16106   // SST1_UXTW instead.
16107   if (Opcode == AArch64ISD::SST1_IMM_PRED) {
16108     if (!isValidImmForSVEVecImmAddrMode(Offset,
16109                                         SrcVT.getScalarSizeInBits() / 8)) {
16110       if (MVT::nxv4i32 == Base.getValueType().getSimpleVT().SimpleTy)
16111         Opcode = AArch64ISD::SST1_UXTW_PRED;
16112       else
16113         Opcode = AArch64ISD::SST1_PRED;
16114 
16115       std::swap(Base, Offset);
16116     }
16117   }
16118 
16119   auto &TLI = DAG.getTargetLoweringInfo();
16120   if (!TLI.isTypeLegal(Base.getValueType()))
16121     return SDValue();
16122 
16123   // Some scatter store variants allow unpacked offsets, but only as nxv2i32
16124   // vectors. These are implicitly sign (sxtw) or zero (zxtw) extend to
16125   // nxv2i64. Legalize accordingly.
16126   if (!OnlyPackedOffsets &&
16127       Offset.getValueType().getSimpleVT().SimpleTy == MVT::nxv2i32)
16128     Offset = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::nxv2i64, Offset).getValue(0);
16129 
16130   if (!TLI.isTypeLegal(Offset.getValueType()))
16131     return SDValue();
16132 
16133   // Source value type that is representable in hardware
16134   EVT HwSrcVt = getSVEContainerType(SrcVT);
16135 
16136   // Keep the original type of the input data to store - this is needed to be
16137   // able to select the correct instruction, e.g. ST1B, ST1H, ST1W and ST1D. For
16138   // FP values we want the integer equivalent, so just use HwSrcVt.
16139   SDValue InputVT = DAG.getValueType(SrcVT);
16140   if (SrcVT.isFloatingPoint())
16141     InputVT = DAG.getValueType(HwSrcVt);
16142 
16143   SDVTList VTs = DAG.getVTList(MVT::Other);
16144   SDValue SrcNew;
16145 
16146   if (Src.getValueType().isFloatingPoint())
16147     SrcNew = DAG.getNode(ISD::BITCAST, DL, HwSrcVt, Src);
16148   else
16149     SrcNew = DAG.getNode(ISD::ANY_EXTEND, DL, HwSrcVt, Src);
16150 
16151   SDValue Ops[] = {N->getOperand(0), // Chain
16152                    SrcNew,
16153                    N->getOperand(3), // Pg
16154                    Base,
16155                    Offset,
16156                    InputVT};
16157 
16158   return DAG.getNode(Opcode, DL, VTs, Ops);
16159 }
16160 
16161 static SDValue performGatherLoadCombine(SDNode *N, SelectionDAG &DAG,
16162                                         unsigned Opcode,
16163                                         bool OnlyPackedOffsets = true) {
16164   const EVT RetVT = N->getValueType(0);
16165   assert(RetVT.isScalableVector() &&
16166          "Gather loads are only possible for SVE vectors");
16167 
16168   SDLoc DL(N);
16169 
16170   // Make sure that the loaded data will fit into an SVE register
16171   if (RetVT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock)
16172     return SDValue();
16173 
16174   // Depending on the addressing mode, this is either a pointer or a vector of
16175   // pointers (that fits into one register)
16176   SDValue Base = N->getOperand(3);
16177   // Depending on the addressing mode, this is either a single offset or a
16178   // vector of offsets  (that fits into one register)
16179   SDValue Offset = N->getOperand(4);
16180 
16181   // For "scalar + vector of indices", just scale the indices. This only
16182   // applies to non-temporal gathers because there's no instruction that takes
16183   // indicies.
16184   if (Opcode == AArch64ISD::GLDNT1_INDEX_MERGE_ZERO) {
16185     Offset = getScaledOffsetForBitWidth(DAG, Offset, DL,
16186                                         RetVT.getScalarSizeInBits());
16187     Opcode = AArch64ISD::GLDNT1_MERGE_ZERO;
16188   }
16189 
16190   // In the case of non-temporal gather loads there's only one SVE instruction
16191   // per data-size: "scalar + vector", i.e.
16192   //    * ldnt1{b|h|w|d} { z0.s }, p0/z, [z0.s, x0]
16193   // Since we do have intrinsics that allow the arguments to be in a different
16194   // order, we may need to swap them to match the spec.
16195   if (Opcode == AArch64ISD::GLDNT1_MERGE_ZERO &&
16196       Offset.getValueType().isVector())
16197     std::swap(Base, Offset);
16198 
16199   // GLD{FF}1_IMM requires that the offset is an immediate that is:
16200   //    * a multiple of #SizeInBytes,
16201   //    * in the range [0, 31 x #SizeInBytes],
16202   // where #SizeInBytes is the size in bytes of the loaded items. For
16203   // immediates outside that range and non-immediate scalar offsets use
16204   // GLD1_MERGE_ZERO or GLD1_UXTW_MERGE_ZERO instead.
16205   if (Opcode == AArch64ISD::GLD1_IMM_MERGE_ZERO ||
16206       Opcode == AArch64ISD::GLDFF1_IMM_MERGE_ZERO) {
16207     if (!isValidImmForSVEVecImmAddrMode(Offset,
16208                                         RetVT.getScalarSizeInBits() / 8)) {
16209       if (MVT::nxv4i32 == Base.getValueType().getSimpleVT().SimpleTy)
16210         Opcode = (Opcode == AArch64ISD::GLD1_IMM_MERGE_ZERO)
16211                      ? AArch64ISD::GLD1_UXTW_MERGE_ZERO
16212                      : AArch64ISD::GLDFF1_UXTW_MERGE_ZERO;
16213       else
16214         Opcode = (Opcode == AArch64ISD::GLD1_IMM_MERGE_ZERO)
16215                      ? AArch64ISD::GLD1_MERGE_ZERO
16216                      : AArch64ISD::GLDFF1_MERGE_ZERO;
16217 
16218       std::swap(Base, Offset);
16219     }
16220   }
16221 
16222   auto &TLI = DAG.getTargetLoweringInfo();
16223   if (!TLI.isTypeLegal(Base.getValueType()))
16224     return SDValue();
16225 
16226   // Some gather load variants allow unpacked offsets, but only as nxv2i32
16227   // vectors. These are implicitly sign (sxtw) or zero (zxtw) extend to
16228   // nxv2i64. Legalize accordingly.
16229   if (!OnlyPackedOffsets &&
16230       Offset.getValueType().getSimpleVT().SimpleTy == MVT::nxv2i32)
16231     Offset = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::nxv2i64, Offset).getValue(0);
16232 
16233   // Return value type that is representable in hardware
16234   EVT HwRetVt = getSVEContainerType(RetVT);
16235 
16236   // Keep the original output value type around - this is needed to be able to
16237   // select the correct instruction, e.g. LD1B, LD1H, LD1W and LD1D. For FP
16238   // values we want the integer equivalent, so just use HwRetVT.
16239   SDValue OutVT = DAG.getValueType(RetVT);
16240   if (RetVT.isFloatingPoint())
16241     OutVT = DAG.getValueType(HwRetVt);
16242 
16243   SDVTList VTs = DAG.getVTList(HwRetVt, MVT::Other);
16244   SDValue Ops[] = {N->getOperand(0), // Chain
16245                    N->getOperand(2), // Pg
16246                    Base, Offset, OutVT};
16247 
16248   SDValue Load = DAG.getNode(Opcode, DL, VTs, Ops);
16249   SDValue LoadChain = SDValue(Load.getNode(), 1);
16250 
16251   if (RetVT.isInteger() && (RetVT != HwRetVt))
16252     Load = DAG.getNode(ISD::TRUNCATE, DL, RetVT, Load.getValue(0));
16253 
16254   // If the original return value was FP, bitcast accordingly. Doing it here
16255   // means that we can avoid adding TableGen patterns for FPs.
16256   if (RetVT.isFloatingPoint())
16257     Load = DAG.getNode(ISD::BITCAST, DL, RetVT, Load.getValue(0));
16258 
16259   return DAG.getMergeValues({Load, LoadChain}, DL);
16260 }
16261 
16262 static SDValue
16263 performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
16264                               SelectionDAG &DAG) {
16265   SDLoc DL(N);
16266   SDValue Src = N->getOperand(0);
16267   unsigned Opc = Src->getOpcode();
16268 
16269   // Sign extend of an unsigned unpack -> signed unpack
16270   if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) {
16271 
16272     unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI
16273                                                : AArch64ISD::SUNPKLO;
16274 
16275     // Push the sign extend to the operand of the unpack
16276     // This is necessary where, for example, the operand of the unpack
16277     // is another unpack:
16278     // 4i32 sign_extend_inreg (4i32 uunpklo(8i16 uunpklo (16i8 opnd)), from 4i8)
16279     // ->
16280     // 4i32 sunpklo (8i16 sign_extend_inreg(8i16 uunpklo (16i8 opnd), from 8i8)
16281     // ->
16282     // 4i32 sunpklo(8i16 sunpklo(16i8 opnd))
16283     SDValue ExtOp = Src->getOperand(0);
16284     auto VT = cast<VTSDNode>(N->getOperand(1))->getVT();
16285     EVT EltTy = VT.getVectorElementType();
16286     (void)EltTy;
16287 
16288     assert((EltTy == MVT::i8 || EltTy == MVT::i16 || EltTy == MVT::i32) &&
16289            "Sign extending from an invalid type");
16290 
16291     EVT ExtVT = VT.getDoubleNumVectorElementsVT(*DAG.getContext());
16292 
16293     SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(),
16294                               ExtOp, DAG.getValueType(ExtVT));
16295 
16296     return DAG.getNode(SOpc, DL, N->getValueType(0), Ext);
16297   }
16298 
16299   if (DCI.isBeforeLegalizeOps())
16300     return SDValue();
16301 
16302   if (!EnableCombineMGatherIntrinsics)
16303     return SDValue();
16304 
16305   // SVE load nodes (e.g. AArch64ISD::GLD1) are straightforward candidates
16306   // for DAG Combine with SIGN_EXTEND_INREG. Bail out for all other nodes.
16307   unsigned NewOpc;
16308   unsigned MemVTOpNum = 4;
16309   switch (Opc) {
16310   case AArch64ISD::LD1_MERGE_ZERO:
16311     NewOpc = AArch64ISD::LD1S_MERGE_ZERO;
16312     MemVTOpNum = 3;
16313     break;
16314   case AArch64ISD::LDNF1_MERGE_ZERO:
16315     NewOpc = AArch64ISD::LDNF1S_MERGE_ZERO;
16316     MemVTOpNum = 3;
16317     break;
16318   case AArch64ISD::LDFF1_MERGE_ZERO:
16319     NewOpc = AArch64ISD::LDFF1S_MERGE_ZERO;
16320     MemVTOpNum = 3;
16321     break;
16322   case AArch64ISD::GLD1_MERGE_ZERO:
16323     NewOpc = AArch64ISD::GLD1S_MERGE_ZERO;
16324     break;
16325   case AArch64ISD::GLD1_SCALED_MERGE_ZERO:
16326     NewOpc = AArch64ISD::GLD1S_SCALED_MERGE_ZERO;
16327     break;
16328   case AArch64ISD::GLD1_SXTW_MERGE_ZERO:
16329     NewOpc = AArch64ISD::GLD1S_SXTW_MERGE_ZERO;
16330     break;
16331   case AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO:
16332     NewOpc = AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO;
16333     break;
16334   case AArch64ISD::GLD1_UXTW_MERGE_ZERO:
16335     NewOpc = AArch64ISD::GLD1S_UXTW_MERGE_ZERO;
16336     break;
16337   case AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO:
16338     NewOpc = AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO;
16339     break;
16340   case AArch64ISD::GLD1_IMM_MERGE_ZERO:
16341     NewOpc = AArch64ISD::GLD1S_IMM_MERGE_ZERO;
16342     break;
16343   case AArch64ISD::GLDFF1_MERGE_ZERO:
16344     NewOpc = AArch64ISD::GLDFF1S_MERGE_ZERO;
16345     break;
16346   case AArch64ISD::GLDFF1_SCALED_MERGE_ZERO:
16347     NewOpc = AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO;
16348     break;
16349   case AArch64ISD::GLDFF1_SXTW_MERGE_ZERO:
16350     NewOpc = AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO;
16351     break;
16352   case AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO:
16353     NewOpc = AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO;
16354     break;
16355   case AArch64ISD::GLDFF1_UXTW_MERGE_ZERO:
16356     NewOpc = AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO;
16357     break;
16358   case AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO:
16359     NewOpc = AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO;
16360     break;
16361   case AArch64ISD::GLDFF1_IMM_MERGE_ZERO:
16362     NewOpc = AArch64ISD::GLDFF1S_IMM_MERGE_ZERO;
16363     break;
16364   case AArch64ISD::GLDNT1_MERGE_ZERO:
16365     NewOpc = AArch64ISD::GLDNT1S_MERGE_ZERO;
16366     break;
16367   default:
16368     return SDValue();
16369   }
16370 
16371   EVT SignExtSrcVT = cast<VTSDNode>(N->getOperand(1))->getVT();
16372   EVT SrcMemVT = cast<VTSDNode>(Src->getOperand(MemVTOpNum))->getVT();
16373 
16374   if ((SignExtSrcVT != SrcMemVT) || !Src.hasOneUse())
16375     return SDValue();
16376 
16377   EVT DstVT = N->getValueType(0);
16378   SDVTList VTs = DAG.getVTList(DstVT, MVT::Other);
16379 
16380   SmallVector<SDValue, 5> Ops;
16381   for (unsigned I = 0; I < Src->getNumOperands(); ++I)
16382     Ops.push_back(Src->getOperand(I));
16383 
16384   SDValue ExtLoad = DAG.getNode(NewOpc, SDLoc(N), VTs, Ops);
16385   DCI.CombineTo(N, ExtLoad);
16386   DCI.CombineTo(Src.getNode(), ExtLoad, ExtLoad.getValue(1));
16387 
16388   // Return N so it doesn't get rechecked
16389   return SDValue(N, 0);
16390 }
16391 
16392 /// Legalize the gather prefetch (scalar + vector addressing mode) when the
16393 /// offset vector is an unpacked 32-bit scalable vector. The other cases (Offset
16394 /// != nxv2i32) do not need legalization.
16395 static SDValue legalizeSVEGatherPrefetchOffsVec(SDNode *N, SelectionDAG &DAG) {
16396   const unsigned OffsetPos = 4;
16397   SDValue Offset = N->getOperand(OffsetPos);
16398 
16399   // Not an unpacked vector, bail out.
16400   if (Offset.getValueType().getSimpleVT().SimpleTy != MVT::nxv2i32)
16401     return SDValue();
16402 
16403   // Extend the unpacked offset vector to 64-bit lanes.
16404   SDLoc DL(N);
16405   Offset = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::nxv2i64, Offset);
16406   SmallVector<SDValue, 5> Ops(N->op_begin(), N->op_end());
16407   // Replace the offset operand with the 64-bit one.
16408   Ops[OffsetPos] = Offset;
16409 
16410   return DAG.getNode(N->getOpcode(), DL, DAG.getVTList(MVT::Other), Ops);
16411 }
16412 
16413 /// Combines a node carrying the intrinsic
16414 /// `aarch64_sve_prf<T>_gather_scalar_offset` into a node that uses
16415 /// `aarch64_sve_prfb_gather_uxtw_index` when the scalar offset passed to
16416 /// `aarch64_sve_prf<T>_gather_scalar_offset` is not a valid immediate for the
16417 /// sve gather prefetch instruction with vector plus immediate addressing mode.
16418 static SDValue combineSVEPrefetchVecBaseImmOff(SDNode *N, SelectionDAG &DAG,
16419                                                unsigned ScalarSizeInBytes) {
16420   const unsigned ImmPos = 4, OffsetPos = 3;
16421   // No need to combine the node if the immediate is valid...
16422   if (isValidImmForSVEVecImmAddrMode(N->getOperand(ImmPos), ScalarSizeInBytes))
16423     return SDValue();
16424 
16425   // ...otherwise swap the offset base with the offset...
16426   SmallVector<SDValue, 5> Ops(N->op_begin(), N->op_end());
16427   std::swap(Ops[ImmPos], Ops[OffsetPos]);
16428   // ...and remap the intrinsic `aarch64_sve_prf<T>_gather_scalar_offset` to
16429   // `aarch64_sve_prfb_gather_uxtw_index`.
16430   SDLoc DL(N);
16431   Ops[1] = DAG.getConstant(Intrinsic::aarch64_sve_prfb_gather_uxtw_index, DL,
16432                            MVT::i64);
16433 
16434   return DAG.getNode(N->getOpcode(), DL, DAG.getVTList(MVT::Other), Ops);
16435 }
16436 
16437 // Return true if the vector operation can guarantee only the first lane of its
16438 // result contains data, with all bits in other lanes set to zero.
16439 static bool isLanes1toNKnownZero(SDValue Op) {
16440   switch (Op.getOpcode()) {
16441   default:
16442     return false;
16443   case AArch64ISD::ANDV_PRED:
16444   case AArch64ISD::EORV_PRED:
16445   case AArch64ISD::FADDA_PRED:
16446   case AArch64ISD::FADDV_PRED:
16447   case AArch64ISD::FMAXNMV_PRED:
16448   case AArch64ISD::FMAXV_PRED:
16449   case AArch64ISD::FMINNMV_PRED:
16450   case AArch64ISD::FMINV_PRED:
16451   case AArch64ISD::ORV_PRED:
16452   case AArch64ISD::SADDV_PRED:
16453   case AArch64ISD::SMAXV_PRED:
16454   case AArch64ISD::SMINV_PRED:
16455   case AArch64ISD::UADDV_PRED:
16456   case AArch64ISD::UMAXV_PRED:
16457   case AArch64ISD::UMINV_PRED:
16458     return true;
16459   }
16460 }
16461 
16462 static SDValue removeRedundantInsertVectorElt(SDNode *N) {
16463   assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && "Unexpected node!");
16464   SDValue InsertVec = N->getOperand(0);
16465   SDValue InsertElt = N->getOperand(1);
16466   SDValue InsertIdx = N->getOperand(2);
16467 
16468   // We only care about inserts into the first element...
16469   if (!isNullConstant(InsertIdx))
16470     return SDValue();
16471   // ...of a zero'd vector...
16472   if (!ISD::isConstantSplatVectorAllZeros(InsertVec.getNode()))
16473     return SDValue();
16474   // ...where the inserted data was previously extracted...
16475   if (InsertElt.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16476     return SDValue();
16477 
16478   SDValue ExtractVec = InsertElt.getOperand(0);
16479   SDValue ExtractIdx = InsertElt.getOperand(1);
16480 
16481   // ...from the first element of a vector.
16482   if (!isNullConstant(ExtractIdx))
16483     return SDValue();
16484 
16485   // If we get here we are effectively trying to zero lanes 1-N of a vector.
16486 
16487   // Ensure there's no type conversion going on.
16488   if (N->getValueType(0) != ExtractVec.getValueType())
16489     return SDValue();
16490 
16491   if (!isLanes1toNKnownZero(ExtractVec))
16492     return SDValue();
16493 
16494   // The explicit zeroing is redundant.
16495   return ExtractVec;
16496 }
16497 
16498 static SDValue
16499 performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
16500   if (SDValue Res = removeRedundantInsertVectorElt(N))
16501     return Res;
16502 
16503   return performPostLD1Combine(N, DCI, true);
16504 }
16505 
16506 SDValue performSVESpliceCombine(SDNode *N, SelectionDAG &DAG) {
16507   EVT Ty = N->getValueType(0);
16508   if (Ty.isInteger())
16509     return SDValue();
16510 
16511   EVT IntTy = Ty.changeVectorElementTypeToInteger();
16512   EVT ExtIntTy = getPackedSVEVectorVT(IntTy.getVectorElementCount());
16513   if (ExtIntTy.getVectorElementType().getScalarSizeInBits() <
16514       IntTy.getVectorElementType().getScalarSizeInBits())
16515     return SDValue();
16516 
16517   SDLoc DL(N);
16518   SDValue LHS = DAG.getAnyExtOrTrunc(DAG.getBitcast(IntTy, N->getOperand(0)),
16519                                      DL, ExtIntTy);
16520   SDValue RHS = DAG.getAnyExtOrTrunc(DAG.getBitcast(IntTy, N->getOperand(1)),
16521                                      DL, ExtIntTy);
16522   SDValue Idx = N->getOperand(2);
16523   SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ExtIntTy, LHS, RHS, Idx);
16524   SDValue Trunc = DAG.getAnyExtOrTrunc(Splice, DL, IntTy);
16525   return DAG.getBitcast(Ty, Trunc);
16526 }
16527 
16528 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
16529                                                  DAGCombinerInfo &DCI) const {
16530   SelectionDAG &DAG = DCI.DAG;
16531   switch (N->getOpcode()) {
16532   default:
16533     LLVM_DEBUG(dbgs() << "Custom combining: skipping\n");
16534     break;
16535   case ISD::ADD:
16536   case ISD::SUB:
16537     return performAddSubCombine(N, DCI, DAG);
16538   case ISD::XOR:
16539     return performXorCombine(N, DAG, DCI, Subtarget);
16540   case ISD::MUL:
16541     return performMulCombine(N, DAG, DCI, Subtarget);
16542   case ISD::SINT_TO_FP:
16543   case ISD::UINT_TO_FP:
16544     return performIntToFpCombine(N, DAG, Subtarget);
16545   case ISD::FP_TO_SINT:
16546   case ISD::FP_TO_UINT:
16547     return performFpToIntCombine(N, DAG, DCI, Subtarget);
16548   case ISD::FDIV:
16549     return performFDivCombine(N, DAG, DCI, Subtarget);
16550   case ISD::OR:
16551     return performORCombine(N, DCI, Subtarget);
16552   case ISD::AND:
16553     return performANDCombine(N, DCI);
16554   case ISD::SRL:
16555     return performSRLCombine(N, DCI);
16556   case ISD::INTRINSIC_WO_CHAIN:
16557     return performIntrinsicCombine(N, DCI, Subtarget);
16558   case ISD::ANY_EXTEND:
16559   case ISD::ZERO_EXTEND:
16560   case ISD::SIGN_EXTEND:
16561     return performExtendCombine(N, DCI, DAG);
16562   case ISD::SIGN_EXTEND_INREG:
16563     return performSignExtendInRegCombine(N, DCI, DAG);
16564   case ISD::TRUNCATE:
16565     return performVectorTruncateCombine(N, DCI, DAG);
16566   case ISD::CONCAT_VECTORS:
16567     return performConcatVectorsCombine(N, DCI, DAG);
16568   case ISD::SELECT:
16569     return performSelectCombine(N, DCI);
16570   case ISD::VSELECT:
16571     return performVSelectCombine(N, DCI.DAG);
16572   case ISD::SETCC:
16573     return performSETCCCombine(N, DAG);
16574   case ISD::LOAD:
16575     if (performTBISimplification(N->getOperand(1), DCI, DAG))
16576       return SDValue(N, 0);
16577     break;
16578   case ISD::STORE:
16579     return performSTORECombine(N, DCI, DAG, Subtarget);
16580   case ISD::VECTOR_SPLICE:
16581     return performSVESpliceCombine(N, DAG);
16582   case AArch64ISD::BRCOND:
16583     return performBRCONDCombine(N, DCI, DAG);
16584   case AArch64ISD::TBNZ:
16585   case AArch64ISD::TBZ:
16586     return performTBZCombine(N, DCI, DAG);
16587   case AArch64ISD::CSEL:
16588     return performCSELCombine(N, DCI, DAG);
16589   case AArch64ISD::DUP:
16590     return performPostLD1Combine(N, DCI, false);
16591   case AArch64ISD::NVCAST:
16592     return performNVCASTCombine(N);
16593   case AArch64ISD::SPLICE:
16594     return performSpliceCombine(N, DAG);
16595   case AArch64ISD::UZP1:
16596     return performUzpCombine(N, DAG);
16597   case AArch64ISD::SETCC_MERGE_ZERO:
16598     return performSetccMergeZeroCombine(N, DAG);
16599   case AArch64ISD::GLD1_MERGE_ZERO:
16600   case AArch64ISD::GLD1_SCALED_MERGE_ZERO:
16601   case AArch64ISD::GLD1_UXTW_MERGE_ZERO:
16602   case AArch64ISD::GLD1_SXTW_MERGE_ZERO:
16603   case AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO:
16604   case AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO:
16605   case AArch64ISD::GLD1_IMM_MERGE_ZERO:
16606   case AArch64ISD::GLD1S_MERGE_ZERO:
16607   case AArch64ISD::GLD1S_SCALED_MERGE_ZERO:
16608   case AArch64ISD::GLD1S_UXTW_MERGE_ZERO:
16609   case AArch64ISD::GLD1S_SXTW_MERGE_ZERO:
16610   case AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO:
16611   case AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO:
16612   case AArch64ISD::GLD1S_IMM_MERGE_ZERO:
16613     return performGLD1Combine(N, DAG);
16614   case AArch64ISD::VASHR:
16615   case AArch64ISD::VLSHR:
16616     return performVectorShiftCombine(N, *this, DCI);
16617   case ISD::INSERT_VECTOR_ELT:
16618     return performInsertVectorEltCombine(N, DCI);
16619   case ISD::EXTRACT_VECTOR_ELT:
16620     return performExtractVectorEltCombine(N, DAG);
16621   case ISD::VECREDUCE_ADD:
16622     return performVecReduceAddCombine(N, DCI.DAG, Subtarget);
16623   case ISD::INTRINSIC_VOID:
16624   case ISD::INTRINSIC_W_CHAIN:
16625     switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
16626     case Intrinsic::aarch64_sve_prfb_gather_scalar_offset:
16627       return combineSVEPrefetchVecBaseImmOff(N, DAG, 1 /*=ScalarSizeInBytes*/);
16628     case Intrinsic::aarch64_sve_prfh_gather_scalar_offset:
16629       return combineSVEPrefetchVecBaseImmOff(N, DAG, 2 /*=ScalarSizeInBytes*/);
16630     case Intrinsic::aarch64_sve_prfw_gather_scalar_offset:
16631       return combineSVEPrefetchVecBaseImmOff(N, DAG, 4 /*=ScalarSizeInBytes*/);
16632     case Intrinsic::aarch64_sve_prfd_gather_scalar_offset:
16633       return combineSVEPrefetchVecBaseImmOff(N, DAG, 8 /*=ScalarSizeInBytes*/);
16634     case Intrinsic::aarch64_sve_prfb_gather_uxtw_index:
16635     case Intrinsic::aarch64_sve_prfb_gather_sxtw_index:
16636     case Intrinsic::aarch64_sve_prfh_gather_uxtw_index:
16637     case Intrinsic::aarch64_sve_prfh_gather_sxtw_index:
16638     case Intrinsic::aarch64_sve_prfw_gather_uxtw_index:
16639     case Intrinsic::aarch64_sve_prfw_gather_sxtw_index:
16640     case Intrinsic::aarch64_sve_prfd_gather_uxtw_index:
16641     case Intrinsic::aarch64_sve_prfd_gather_sxtw_index:
16642       return legalizeSVEGatherPrefetchOffsVec(N, DAG);
16643     case Intrinsic::aarch64_neon_ld2:
16644     case Intrinsic::aarch64_neon_ld3:
16645     case Intrinsic::aarch64_neon_ld4:
16646     case Intrinsic::aarch64_neon_ld1x2:
16647     case Intrinsic::aarch64_neon_ld1x3:
16648     case Intrinsic::aarch64_neon_ld1x4:
16649     case Intrinsic::aarch64_neon_ld2lane:
16650     case Intrinsic::aarch64_neon_ld3lane:
16651     case Intrinsic::aarch64_neon_ld4lane:
16652     case Intrinsic::aarch64_neon_ld2r:
16653     case Intrinsic::aarch64_neon_ld3r:
16654     case Intrinsic::aarch64_neon_ld4r:
16655     case Intrinsic::aarch64_neon_st2:
16656     case Intrinsic::aarch64_neon_st3:
16657     case Intrinsic::aarch64_neon_st4:
16658     case Intrinsic::aarch64_neon_st1x2:
16659     case Intrinsic::aarch64_neon_st1x3:
16660     case Intrinsic::aarch64_neon_st1x4:
16661     case Intrinsic::aarch64_neon_st2lane:
16662     case Intrinsic::aarch64_neon_st3lane:
16663     case Intrinsic::aarch64_neon_st4lane:
16664       return performNEONPostLDSTCombine(N, DCI, DAG);
16665     case Intrinsic::aarch64_sve_ldnt1:
16666       return performLDNT1Combine(N, DAG);
16667     case Intrinsic::aarch64_sve_ld1rq:
16668       return performLD1ReplicateCombine<AArch64ISD::LD1RQ_MERGE_ZERO>(N, DAG);
16669     case Intrinsic::aarch64_sve_ld1ro:
16670       return performLD1ReplicateCombine<AArch64ISD::LD1RO_MERGE_ZERO>(N, DAG);
16671     case Intrinsic::aarch64_sve_ldnt1_gather_scalar_offset:
16672       return performGatherLoadCombine(N, DAG, AArch64ISD::GLDNT1_MERGE_ZERO);
16673     case Intrinsic::aarch64_sve_ldnt1_gather:
16674       return performGatherLoadCombine(N, DAG, AArch64ISD::GLDNT1_MERGE_ZERO);
16675     case Intrinsic::aarch64_sve_ldnt1_gather_index:
16676       return performGatherLoadCombine(N, DAG,
16677                                       AArch64ISD::GLDNT1_INDEX_MERGE_ZERO);
16678     case Intrinsic::aarch64_sve_ldnt1_gather_uxtw:
16679       return performGatherLoadCombine(N, DAG, AArch64ISD::GLDNT1_MERGE_ZERO);
16680     case Intrinsic::aarch64_sve_ld1:
16681       return performLD1Combine(N, DAG, AArch64ISD::LD1_MERGE_ZERO);
16682     case Intrinsic::aarch64_sve_ldnf1:
16683       return performLD1Combine(N, DAG, AArch64ISD::LDNF1_MERGE_ZERO);
16684     case Intrinsic::aarch64_sve_ldff1:
16685       return performLD1Combine(N, DAG, AArch64ISD::LDFF1_MERGE_ZERO);
16686     case Intrinsic::aarch64_sve_st1:
16687       return performST1Combine(N, DAG);
16688     case Intrinsic::aarch64_sve_stnt1:
16689       return performSTNT1Combine(N, DAG);
16690     case Intrinsic::aarch64_sve_stnt1_scatter_scalar_offset:
16691       return performScatterStoreCombine(N, DAG, AArch64ISD::SSTNT1_PRED);
16692     case Intrinsic::aarch64_sve_stnt1_scatter_uxtw:
16693       return performScatterStoreCombine(N, DAG, AArch64ISD::SSTNT1_PRED);
16694     case Intrinsic::aarch64_sve_stnt1_scatter:
16695       return performScatterStoreCombine(N, DAG, AArch64ISD::SSTNT1_PRED);
16696     case Intrinsic::aarch64_sve_stnt1_scatter_index:
16697       return performScatterStoreCombine(N, DAG, AArch64ISD::SSTNT1_INDEX_PRED);
16698     case Intrinsic::aarch64_sve_ld1_gather:
16699       return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_MERGE_ZERO);
16700     case Intrinsic::aarch64_sve_ld1_gather_index:
16701       return performGatherLoadCombine(N, DAG,
16702                                       AArch64ISD::GLD1_SCALED_MERGE_ZERO);
16703     case Intrinsic::aarch64_sve_ld1_gather_sxtw:
16704       return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_SXTW_MERGE_ZERO,
16705                                       /*OnlyPackedOffsets=*/false);
16706     case Intrinsic::aarch64_sve_ld1_gather_uxtw:
16707       return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO,
16708                                       /*OnlyPackedOffsets=*/false);
16709     case Intrinsic::aarch64_sve_ld1_gather_sxtw_index:
16710       return performGatherLoadCombine(N, DAG,
16711                                       AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO,
16712                                       /*OnlyPackedOffsets=*/false);
16713     case Intrinsic::aarch64_sve_ld1_gather_uxtw_index:
16714       return performGatherLoadCombine(N, DAG,
16715                                       AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO,
16716                                       /*OnlyPackedOffsets=*/false);
16717     case Intrinsic::aarch64_sve_ld1_gather_scalar_offset:
16718       return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_IMM_MERGE_ZERO);
16719     case Intrinsic::aarch64_sve_ldff1_gather:
16720       return performGatherLoadCombine(N, DAG, AArch64ISD::GLDFF1_MERGE_ZERO);
16721     case Intrinsic::aarch64_sve_ldff1_gather_index:
16722       return performGatherLoadCombine(N, DAG,
16723                                       AArch64ISD::GLDFF1_SCALED_MERGE_ZERO);
16724     case Intrinsic::aarch64_sve_ldff1_gather_sxtw:
16725       return performGatherLoadCombine(N, DAG,
16726                                       AArch64ISD::GLDFF1_SXTW_MERGE_ZERO,
16727                                       /*OnlyPackedOffsets=*/false);
16728     case Intrinsic::aarch64_sve_ldff1_gather_uxtw:
16729       return performGatherLoadCombine(N, DAG,
16730                                       AArch64ISD::GLDFF1_UXTW_MERGE_ZERO,
16731                                       /*OnlyPackedOffsets=*/false);
16732     case Intrinsic::aarch64_sve_ldff1_gather_sxtw_index:
16733       return performGatherLoadCombine(N, DAG,
16734                                       AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO,
16735                                       /*OnlyPackedOffsets=*/false);
16736     case Intrinsic::aarch64_sve_ldff1_gather_uxtw_index:
16737       return performGatherLoadCombine(N, DAG,
16738                                       AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO,
16739                                       /*OnlyPackedOffsets=*/false);
16740     case Intrinsic::aarch64_sve_ldff1_gather_scalar_offset:
16741       return performGatherLoadCombine(N, DAG,
16742                                       AArch64ISD::GLDFF1_IMM_MERGE_ZERO);
16743     case Intrinsic::aarch64_sve_st1_scatter:
16744       return performScatterStoreCombine(N, DAG, AArch64ISD::SST1_PRED);
16745     case Intrinsic::aarch64_sve_st1_scatter_index:
16746       return performScatterStoreCombine(N, DAG, AArch64ISD::SST1_SCALED_PRED);
16747     case Intrinsic::aarch64_sve_st1_scatter_sxtw:
16748       return performScatterStoreCombine(N, DAG, AArch64ISD::SST1_SXTW_PRED,
16749                                         /*OnlyPackedOffsets=*/false);
16750     case Intrinsic::aarch64_sve_st1_scatter_uxtw:
16751       return performScatterStoreCombine(N, DAG, AArch64ISD::SST1_UXTW_PRED,
16752                                         /*OnlyPackedOffsets=*/false);
16753     case Intrinsic::aarch64_sve_st1_scatter_sxtw_index:
16754       return performScatterStoreCombine(N, DAG,
16755                                         AArch64ISD::SST1_SXTW_SCALED_PRED,
16756                                         /*OnlyPackedOffsets=*/false);
16757     case Intrinsic::aarch64_sve_st1_scatter_uxtw_index:
16758       return performScatterStoreCombine(N, DAG,
16759                                         AArch64ISD::SST1_UXTW_SCALED_PRED,
16760                                         /*OnlyPackedOffsets=*/false);
16761     case Intrinsic::aarch64_sve_st1_scatter_scalar_offset:
16762       return performScatterStoreCombine(N, DAG, AArch64ISD::SST1_IMM_PRED);
16763     case Intrinsic::aarch64_sve_tuple_get: {
16764       SDLoc DL(N);
16765       SDValue Chain = N->getOperand(0);
16766       SDValue Src1 = N->getOperand(2);
16767       SDValue Idx = N->getOperand(3);
16768 
16769       uint64_t IdxConst = cast<ConstantSDNode>(Idx)->getZExtValue();
16770       EVT ResVT = N->getValueType(0);
16771       uint64_t NumLanes = ResVT.getVectorElementCount().getKnownMinValue();
16772       SDValue ExtIdx = DAG.getVectorIdxConstant(IdxConst * NumLanes, DL);
16773       SDValue Val =
16774           DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResVT, Src1, ExtIdx);
16775       return DAG.getMergeValues({Val, Chain}, DL);
16776     }
16777     case Intrinsic::aarch64_sve_tuple_set: {
16778       SDLoc DL(N);
16779       SDValue Chain = N->getOperand(0);
16780       SDValue Tuple = N->getOperand(2);
16781       SDValue Idx = N->getOperand(3);
16782       SDValue Vec = N->getOperand(4);
16783 
16784       EVT TupleVT = Tuple.getValueType();
16785       uint64_t TupleLanes = TupleVT.getVectorElementCount().getKnownMinValue();
16786 
16787       uint64_t IdxConst = cast<ConstantSDNode>(Idx)->getZExtValue();
16788       uint64_t NumLanes =
16789           Vec.getValueType().getVectorElementCount().getKnownMinValue();
16790 
16791       if ((TupleLanes % NumLanes) != 0)
16792         report_fatal_error("invalid tuple vector!");
16793 
16794       uint64_t NumVecs = TupleLanes / NumLanes;
16795 
16796       SmallVector<SDValue, 4> Opnds;
16797       for (unsigned I = 0; I < NumVecs; ++I) {
16798         if (I == IdxConst)
16799           Opnds.push_back(Vec);
16800         else {
16801           SDValue ExtIdx = DAG.getVectorIdxConstant(I * NumLanes, DL);
16802           Opnds.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
16803                                       Vec.getValueType(), Tuple, ExtIdx));
16804         }
16805       }
16806       SDValue Concat =
16807           DAG.getNode(ISD::CONCAT_VECTORS, DL, Tuple.getValueType(), Opnds);
16808       return DAG.getMergeValues({Concat, Chain}, DL);
16809     }
16810     case Intrinsic::aarch64_sve_tuple_create2:
16811     case Intrinsic::aarch64_sve_tuple_create3:
16812     case Intrinsic::aarch64_sve_tuple_create4: {
16813       SDLoc DL(N);
16814       SDValue Chain = N->getOperand(0);
16815 
16816       SmallVector<SDValue, 4> Opnds;
16817       for (unsigned I = 2; I < N->getNumOperands(); ++I)
16818         Opnds.push_back(N->getOperand(I));
16819 
16820       EVT VT = Opnds[0].getValueType();
16821       EVT EltVT = VT.getVectorElementType();
16822       EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
16823                                     VT.getVectorElementCount() *
16824                                         (N->getNumOperands() - 2));
16825       SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds);
16826       return DAG.getMergeValues({Concat, Chain}, DL);
16827     }
16828     case Intrinsic::aarch64_sve_ld2:
16829     case Intrinsic::aarch64_sve_ld3:
16830     case Intrinsic::aarch64_sve_ld4: {
16831       SDLoc DL(N);
16832       SDValue Chain = N->getOperand(0);
16833       SDValue Mask = N->getOperand(2);
16834       SDValue BasePtr = N->getOperand(3);
16835       SDValue LoadOps[] = {Chain, Mask, BasePtr};
16836       unsigned IntrinsicID =
16837           cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16838       SDValue Result =
16839           LowerSVEStructLoad(IntrinsicID, LoadOps, N->getValueType(0), DAG, DL);
16840       return DAG.getMergeValues({Result, Chain}, DL);
16841     }
16842     case Intrinsic::aarch64_rndr:
16843     case Intrinsic::aarch64_rndrrs: {
16844       unsigned IntrinsicID =
16845           cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16846       auto Register =
16847           (IntrinsicID == Intrinsic::aarch64_rndr ? AArch64SysReg::RNDR
16848                                                   : AArch64SysReg::RNDRRS);
16849       SDLoc DL(N);
16850       SDValue A = DAG.getNode(
16851           AArch64ISD::MRS, DL, DAG.getVTList(MVT::i64, MVT::Glue, MVT::Other),
16852           N->getOperand(0), DAG.getConstant(Register, DL, MVT::i64));
16853       SDValue B = DAG.getNode(
16854           AArch64ISD::CSINC, DL, MVT::i32, DAG.getConstant(0, DL, MVT::i32),
16855           DAG.getConstant(0, DL, MVT::i32),
16856           DAG.getConstant(AArch64CC::NE, DL, MVT::i32), A.getValue(1));
16857       return DAG.getMergeValues(
16858           {A, DAG.getZExtOrTrunc(B, DL, MVT::i1), A.getValue(2)}, DL);
16859     }
16860     default:
16861       break;
16862     }
16863     break;
16864   case ISD::GlobalAddress:
16865     return performGlobalAddressCombine(N, DAG, Subtarget, getTargetMachine());
16866   }
16867   return SDValue();
16868 }
16869 
16870 // Check if the return value is used as only a return value, as otherwise
16871 // we can't perform a tail-call. In particular, we need to check for
16872 // target ISD nodes that are returns and any other "odd" constructs
16873 // that the generic analysis code won't necessarily catch.
16874 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
16875                                                SDValue &Chain) const {
16876   if (N->getNumValues() != 1)
16877     return false;
16878   if (!N->hasNUsesOfValue(1, 0))
16879     return false;
16880 
16881   SDValue TCChain = Chain;
16882   SDNode *Copy = *N->use_begin();
16883   if (Copy->getOpcode() == ISD::CopyToReg) {
16884     // If the copy has a glue operand, we conservatively assume it isn't safe to
16885     // perform a tail call.
16886     if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
16887         MVT::Glue)
16888       return false;
16889     TCChain = Copy->getOperand(0);
16890   } else if (Copy->getOpcode() != ISD::FP_EXTEND)
16891     return false;
16892 
16893   bool HasRet = false;
16894   for (SDNode *Node : Copy->uses()) {
16895     if (Node->getOpcode() != AArch64ISD::RET_FLAG)
16896       return false;
16897     HasRet = true;
16898   }
16899 
16900   if (!HasRet)
16901     return false;
16902 
16903   Chain = TCChain;
16904   return true;
16905 }
16906 
16907 // Return whether the an instruction can potentially be optimized to a tail
16908 // call. This will cause the optimizers to attempt to move, or duplicate,
16909 // return instructions to help enable tail call optimizations for this
16910 // instruction.
16911 bool AArch64TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
16912   return CI->isTailCall();
16913 }
16914 
16915 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
16916                                                    SDValue &Offset,
16917                                                    ISD::MemIndexedMode &AM,
16918                                                    bool &IsInc,
16919                                                    SelectionDAG &DAG) const {
16920   if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
16921     return false;
16922 
16923   Base = Op->getOperand(0);
16924   // All of the indexed addressing mode instructions take a signed
16925   // 9 bit immediate offset.
16926   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
16927     int64_t RHSC = RHS->getSExtValue();
16928     if (Op->getOpcode() == ISD::SUB)
16929       RHSC = -(uint64_t)RHSC;
16930     if (!isInt<9>(RHSC))
16931       return false;
16932     IsInc = (Op->getOpcode() == ISD::ADD);
16933     Offset = Op->getOperand(1);
16934     return true;
16935   }
16936   return false;
16937 }
16938 
16939 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
16940                                                       SDValue &Offset,
16941                                                       ISD::MemIndexedMode &AM,
16942                                                       SelectionDAG &DAG) const {
16943   EVT VT;
16944   SDValue Ptr;
16945   if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
16946     VT = LD->getMemoryVT();
16947     Ptr = LD->getBasePtr();
16948   } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
16949     VT = ST->getMemoryVT();
16950     Ptr = ST->getBasePtr();
16951   } else
16952     return false;
16953 
16954   bool IsInc;
16955   if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
16956     return false;
16957   AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
16958   return true;
16959 }
16960 
16961 bool AArch64TargetLowering::getPostIndexedAddressParts(
16962     SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
16963     ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
16964   EVT VT;
16965   SDValue Ptr;
16966   if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
16967     VT = LD->getMemoryVT();
16968     Ptr = LD->getBasePtr();
16969   } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
16970     VT = ST->getMemoryVT();
16971     Ptr = ST->getBasePtr();
16972   } else
16973     return false;
16974 
16975   bool IsInc;
16976   if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
16977     return false;
16978   // Post-indexing updates the base, so it's not a valid transform
16979   // if that's not the same as the load's pointer.
16980   if (Ptr != Base)
16981     return false;
16982   AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
16983   return true;
16984 }
16985 
16986 void AArch64TargetLowering::ReplaceBITCASTResults(
16987     SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
16988   SDLoc DL(N);
16989   SDValue Op = N->getOperand(0);
16990   EVT VT = N->getValueType(0);
16991   EVT SrcVT = Op.getValueType();
16992 
16993   if (VT.isScalableVector() && !isTypeLegal(VT) && isTypeLegal(SrcVT)) {
16994     assert(!VT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
16995            "Expected fp->int bitcast!");
16996     SDValue CastResult = getSVESafeBitCast(getSVEContainerType(VT), Op, DAG);
16997     Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, CastResult));
16998     return;
16999   }
17000 
17001   if (VT != MVT::i16 || (SrcVT != MVT::f16 && SrcVT != MVT::bf16))
17002     return;
17003 
17004   Op = SDValue(
17005       DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
17006                          DAG.getUNDEF(MVT::i32), Op,
17007                          DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
17008       0);
17009   Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
17010   Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
17011 }
17012 
17013 static void ReplaceReductionResults(SDNode *N,
17014                                     SmallVectorImpl<SDValue> &Results,
17015                                     SelectionDAG &DAG, unsigned InterOp,
17016                                     unsigned AcrossOp) {
17017   EVT LoVT, HiVT;
17018   SDValue Lo, Hi;
17019   SDLoc dl(N);
17020   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
17021   std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
17022   SDValue InterVal = DAG.getNode(InterOp, dl, LoVT, Lo, Hi);
17023   SDValue SplitVal = DAG.getNode(AcrossOp, dl, LoVT, InterVal);
17024   Results.push_back(SplitVal);
17025 }
17026 
17027 static std::pair<SDValue, SDValue> splitInt128(SDValue N, SelectionDAG &DAG) {
17028   SDLoc DL(N);
17029   SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, N);
17030   SDValue Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64,
17031                            DAG.getNode(ISD::SRL, DL, MVT::i128, N,
17032                                        DAG.getConstant(64, DL, MVT::i64)));
17033   return std::make_pair(Lo, Hi);
17034 }
17035 
17036 void AArch64TargetLowering::ReplaceExtractSubVectorResults(
17037     SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
17038   SDValue In = N->getOperand(0);
17039   EVT InVT = In.getValueType();
17040 
17041   // Common code will handle these just fine.
17042   if (!InVT.isScalableVector() || !InVT.isInteger())
17043     return;
17044 
17045   SDLoc DL(N);
17046   EVT VT = N->getValueType(0);
17047 
17048   // The following checks bail if this is not a halving operation.
17049 
17050   ElementCount ResEC = VT.getVectorElementCount();
17051 
17052   if (InVT.getVectorElementCount() != (ResEC * 2))
17053     return;
17054 
17055   auto *CIndex = dyn_cast<ConstantSDNode>(N->getOperand(1));
17056   if (!CIndex)
17057     return;
17058 
17059   unsigned Index = CIndex->getZExtValue();
17060   if ((Index != 0) && (Index != ResEC.getKnownMinValue()))
17061     return;
17062 
17063   unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI;
17064   EVT ExtendedHalfVT = VT.widenIntegerVectorElementType(*DAG.getContext());
17065 
17066   SDValue Half = DAG.getNode(Opcode, DL, ExtendedHalfVT, N->getOperand(0));
17067   Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Half));
17068 }
17069 
17070 // Create an even/odd pair of X registers holding integer value V.
17071 static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V) {
17072   SDLoc dl(V.getNode());
17073   SDValue VLo = DAG.getAnyExtOrTrunc(V, dl, MVT::i64);
17074   SDValue VHi = DAG.getAnyExtOrTrunc(
17075       DAG.getNode(ISD::SRL, dl, MVT::i128, V, DAG.getConstant(64, dl, MVT::i64)),
17076       dl, MVT::i64);
17077   if (DAG.getDataLayout().isBigEndian())
17078     std::swap (VLo, VHi);
17079   SDValue RegClass =
17080       DAG.getTargetConstant(AArch64::XSeqPairsClassRegClassID, dl, MVT::i32);
17081   SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, dl, MVT::i32);
17082   SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32);
17083   const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
17084   return SDValue(
17085       DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0);
17086 }
17087 
17088 static void ReplaceCMP_SWAP_128Results(SDNode *N,
17089                                        SmallVectorImpl<SDValue> &Results,
17090                                        SelectionDAG &DAG,
17091                                        const AArch64Subtarget *Subtarget) {
17092   assert(N->getValueType(0) == MVT::i128 &&
17093          "AtomicCmpSwap on types less than 128 should be legal");
17094 
17095   MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
17096   if (Subtarget->hasLSE() || Subtarget->outlineAtomics()) {
17097     // LSE has a 128-bit compare and swap (CASP), but i128 is not a legal type,
17098     // so lower it here, wrapped in REG_SEQUENCE and EXTRACT_SUBREG.
17099     SDValue Ops[] = {
17100         createGPRPairNode(DAG, N->getOperand(2)), // Compare value
17101         createGPRPairNode(DAG, N->getOperand(3)), // Store value
17102         N->getOperand(1), // Ptr
17103         N->getOperand(0), // Chain in
17104     };
17105 
17106     unsigned Opcode;
17107     switch (MemOp->getMergedOrdering()) {
17108     case AtomicOrdering::Monotonic:
17109       Opcode = AArch64::CASPX;
17110       break;
17111     case AtomicOrdering::Acquire:
17112       Opcode = AArch64::CASPAX;
17113       break;
17114     case AtomicOrdering::Release:
17115       Opcode = AArch64::CASPLX;
17116       break;
17117     case AtomicOrdering::AcquireRelease:
17118     case AtomicOrdering::SequentiallyConsistent:
17119       Opcode = AArch64::CASPALX;
17120       break;
17121     default:
17122       llvm_unreachable("Unexpected ordering!");
17123     }
17124 
17125     MachineSDNode *CmpSwap = DAG.getMachineNode(
17126         Opcode, SDLoc(N), DAG.getVTList(MVT::Untyped, MVT::Other), Ops);
17127     DAG.setNodeMemRefs(CmpSwap, {MemOp});
17128 
17129     unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64;
17130     if (DAG.getDataLayout().isBigEndian())
17131       std::swap(SubReg1, SubReg2);
17132     SDValue Lo = DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64,
17133                                             SDValue(CmpSwap, 0));
17134     SDValue Hi = DAG.getTargetExtractSubreg(SubReg2, SDLoc(N), MVT::i64,
17135                                             SDValue(CmpSwap, 0));
17136     Results.push_back(
17137         DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Lo, Hi));
17138     Results.push_back(SDValue(CmpSwap, 1)); // Chain out
17139     return;
17140   }
17141 
17142   unsigned Opcode;
17143   switch (MemOp->getMergedOrdering()) {
17144   case AtomicOrdering::Monotonic:
17145     Opcode = AArch64::CMP_SWAP_128_MONOTONIC;
17146     break;
17147   case AtomicOrdering::Acquire:
17148     Opcode = AArch64::CMP_SWAP_128_ACQUIRE;
17149     break;
17150   case AtomicOrdering::Release:
17151     Opcode = AArch64::CMP_SWAP_128_RELEASE;
17152     break;
17153   case AtomicOrdering::AcquireRelease:
17154   case AtomicOrdering::SequentiallyConsistent:
17155     Opcode = AArch64::CMP_SWAP_128;
17156     break;
17157   default:
17158     llvm_unreachable("Unexpected ordering!");
17159   }
17160 
17161   auto Desired = splitInt128(N->getOperand(2), DAG);
17162   auto New = splitInt128(N->getOperand(3), DAG);
17163   SDValue Ops[] = {N->getOperand(1), Desired.first, Desired.second,
17164                    New.first,        New.second,    N->getOperand(0)};
17165   SDNode *CmpSwap = DAG.getMachineNode(
17166       Opcode, SDLoc(N), DAG.getVTList(MVT::i64, MVT::i64, MVT::i32, MVT::Other),
17167       Ops);
17168   DAG.setNodeMemRefs(cast<MachineSDNode>(CmpSwap), {MemOp});
17169 
17170   Results.push_back(DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128,
17171                                 SDValue(CmpSwap, 0), SDValue(CmpSwap, 1)));
17172   Results.push_back(SDValue(CmpSwap, 3));
17173 }
17174 
17175 void AArch64TargetLowering::ReplaceNodeResults(
17176     SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
17177   switch (N->getOpcode()) {
17178   default:
17179     llvm_unreachable("Don't know how to custom expand this");
17180   case ISD::BITCAST:
17181     ReplaceBITCASTResults(N, Results, DAG);
17182     return;
17183   case ISD::VECREDUCE_ADD:
17184   case ISD::VECREDUCE_SMAX:
17185   case ISD::VECREDUCE_SMIN:
17186   case ISD::VECREDUCE_UMAX:
17187   case ISD::VECREDUCE_UMIN:
17188     Results.push_back(LowerVECREDUCE(SDValue(N, 0), DAG));
17189     return;
17190 
17191   case ISD::CTPOP:
17192     if (SDValue Result = LowerCTPOP(SDValue(N, 0), DAG))
17193       Results.push_back(Result);
17194     return;
17195   case AArch64ISD::SADDV:
17196     ReplaceReductionResults(N, Results, DAG, ISD::ADD, AArch64ISD::SADDV);
17197     return;
17198   case AArch64ISD::UADDV:
17199     ReplaceReductionResults(N, Results, DAG, ISD::ADD, AArch64ISD::UADDV);
17200     return;
17201   case AArch64ISD::SMINV:
17202     ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV);
17203     return;
17204   case AArch64ISD::UMINV:
17205     ReplaceReductionResults(N, Results, DAG, ISD::UMIN, AArch64ISD::UMINV);
17206     return;
17207   case AArch64ISD::SMAXV:
17208     ReplaceReductionResults(N, Results, DAG, ISD::SMAX, AArch64ISD::SMAXV);
17209     return;
17210   case AArch64ISD::UMAXV:
17211     ReplaceReductionResults(N, Results, DAG, ISD::UMAX, AArch64ISD::UMAXV);
17212     return;
17213   case ISD::FP_TO_UINT:
17214   case ISD::FP_TO_SINT:
17215     assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
17216     // Let normal code take care of it by not adding anything to Results.
17217     return;
17218   case ISD::ATOMIC_CMP_SWAP:
17219     ReplaceCMP_SWAP_128Results(N, Results, DAG, Subtarget);
17220     return;
17221   case ISD::LOAD: {
17222     assert(SDValue(N, 0).getValueType() == MVT::i128 &&
17223            "unexpected load's value type");
17224     LoadSDNode *LoadNode = cast<LoadSDNode>(N);
17225     if (!LoadNode->isVolatile() || LoadNode->getMemoryVT() != MVT::i128) {
17226       // Non-volatile loads are optimized later in AArch64's load/store
17227       // optimizer.
17228       return;
17229     }
17230 
17231     SDValue Result = DAG.getMemIntrinsicNode(
17232         AArch64ISD::LDP, SDLoc(N),
17233         DAG.getVTList({MVT::i64, MVT::i64, MVT::Other}),
17234         {LoadNode->getChain(), LoadNode->getBasePtr()}, LoadNode->getMemoryVT(),
17235         LoadNode->getMemOperand());
17236 
17237     SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128,
17238                                Result.getValue(0), Result.getValue(1));
17239     Results.append({Pair, Result.getValue(2) /* Chain */});
17240     return;
17241   }
17242   case ISD::EXTRACT_SUBVECTOR:
17243     ReplaceExtractSubVectorResults(N, Results, DAG);
17244     return;
17245   case ISD::INSERT_SUBVECTOR:
17246     // Custom lowering has been requested for INSERT_SUBVECTOR -- but delegate
17247     // to common code for result type legalisation
17248     return;
17249   case ISD::INTRINSIC_WO_CHAIN: {
17250     EVT VT = N->getValueType(0);
17251     assert((VT == MVT::i8 || VT == MVT::i16) &&
17252            "custom lowering for unexpected type");
17253 
17254     ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));
17255     Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
17256     switch (IntID) {
17257     default:
17258       return;
17259     case Intrinsic::aarch64_sve_clasta_n: {
17260       SDLoc DL(N);
17261       auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2));
17262       auto V = DAG.getNode(AArch64ISD::CLASTA_N, DL, MVT::i32,
17263                            N->getOperand(1), Op2, N->getOperand(3));
17264       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
17265       return;
17266     }
17267     case Intrinsic::aarch64_sve_clastb_n: {
17268       SDLoc DL(N);
17269       auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2));
17270       auto V = DAG.getNode(AArch64ISD::CLASTB_N, DL, MVT::i32,
17271                            N->getOperand(1), Op2, N->getOperand(3));
17272       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
17273       return;
17274     }
17275     case Intrinsic::aarch64_sve_lasta: {
17276       SDLoc DL(N);
17277       auto V = DAG.getNode(AArch64ISD::LASTA, DL, MVT::i32,
17278                            N->getOperand(1), N->getOperand(2));
17279       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
17280       return;
17281     }
17282     case Intrinsic::aarch64_sve_lastb: {
17283       SDLoc DL(N);
17284       auto V = DAG.getNode(AArch64ISD::LASTB, DL, MVT::i32,
17285                            N->getOperand(1), N->getOperand(2));
17286       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
17287       return;
17288     }
17289     }
17290   }
17291   }
17292 }
17293 
17294 bool AArch64TargetLowering::useLoadStackGuardNode() const {
17295   if (Subtarget->isTargetAndroid() || Subtarget->isTargetFuchsia())
17296     return TargetLowering::useLoadStackGuardNode();
17297   return true;
17298 }
17299 
17300 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
17301   // Combine multiple FDIVs with the same divisor into multiple FMULs by the
17302   // reciprocal if there are three or more FDIVs.
17303   return 3;
17304 }
17305 
17306 TargetLoweringBase::LegalizeTypeAction
17307 AArch64TargetLowering::getPreferredVectorAction(MVT VT) const {
17308   // During type legalization, we prefer to widen v1i8, v1i16, v1i32  to v8i8,
17309   // v4i16, v2i32 instead of to promote.
17310   if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 ||
17311       VT == MVT::v1f32)
17312     return TypeWidenVector;
17313 
17314   return TargetLoweringBase::getPreferredVectorAction(VT);
17315 }
17316 
17317 // Loads and stores less than 128-bits are already atomic; ones above that
17318 // are doomed anyway, so defer to the default libcall and blame the OS when
17319 // things go wrong.
17320 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17321   unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
17322   return Size == 128;
17323 }
17324 
17325 // Loads and stores less than 128-bits are already atomic; ones above that
17326 // are doomed anyway, so defer to the default libcall and blame the OS when
17327 // things go wrong.
17328 TargetLowering::AtomicExpansionKind
17329 AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17330   unsigned Size = LI->getType()->getPrimitiveSizeInBits();
17331   return Size == 128 ? AtomicExpansionKind::LLSC : AtomicExpansionKind::None;
17332 }
17333 
17334 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
17335 TargetLowering::AtomicExpansionKind
17336 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17337   if (AI->isFloatingPointOperation())
17338     return AtomicExpansionKind::CmpXChg;
17339 
17340   unsigned Size = AI->getType()->getPrimitiveSizeInBits();
17341   if (Size > 128) return AtomicExpansionKind::None;
17342 
17343   // Nand is not supported in LSE.
17344   // Leave 128 bits to LLSC or CmpXChg.
17345   if (AI->getOperation() != AtomicRMWInst::Nand && Size < 128) {
17346     if (Subtarget->hasLSE())
17347       return AtomicExpansionKind::None;
17348     if (Subtarget->outlineAtomics()) {
17349       // [U]Min/[U]Max RWM atomics are used in __sync_fetch_ libcalls so far.
17350       // Don't outline them unless
17351       // (1) high level <atomic> support approved:
17352       //   http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p0493r1.pdf
17353       // (2) low level libgcc and compiler-rt support implemented by:
17354       //   min/max outline atomics helpers
17355       if (AI->getOperation() != AtomicRMWInst::Min &&
17356           AI->getOperation() != AtomicRMWInst::Max &&
17357           AI->getOperation() != AtomicRMWInst::UMin &&
17358           AI->getOperation() != AtomicRMWInst::UMax) {
17359         return AtomicExpansionKind::None;
17360       }
17361     }
17362   }
17363 
17364   // At -O0, fast-regalloc cannot cope with the live vregs necessary to
17365   // implement atomicrmw without spilling. If the target address is also on the
17366   // stack and close enough to the spill slot, this can lead to a situation
17367   // where the monitor always gets cleared and the atomic operation can never
17368   // succeed. So at -O0 lower this operation to a CAS loop.
17369   if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
17370     return AtomicExpansionKind::CmpXChg;
17371 
17372   return AtomicExpansionKind::LLSC;
17373 }
17374 
17375 TargetLowering::AtomicExpansionKind
17376 AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
17377     AtomicCmpXchgInst *AI) const {
17378   // If subtarget has LSE, leave cmpxchg intact for codegen.
17379   if (Subtarget->hasLSE() || Subtarget->outlineAtomics())
17380     return AtomicExpansionKind::None;
17381   // At -O0, fast-regalloc cannot cope with the live vregs necessary to
17382   // implement cmpxchg without spilling. If the address being exchanged is also
17383   // on the stack and close enough to the spill slot, this can lead to a
17384   // situation where the monitor always gets cleared and the atomic operation
17385   // can never succeed. So at -O0 we need a late-expanded pseudo-inst instead.
17386   if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
17387     return AtomicExpansionKind::None;
17388 
17389   // 128-bit atomic cmpxchg is weird; AtomicExpand doesn't know how to expand
17390   // it.
17391   unsigned Size = AI->getCompareOperand()->getType()->getPrimitiveSizeInBits();
17392   if (Size > 64)
17393     return AtomicExpansionKind::None;
17394 
17395   return AtomicExpansionKind::LLSC;
17396 }
17397 
17398 Value *AArch64TargetLowering::emitLoadLinked(IRBuilderBase &Builder,
17399                                              Type *ValueTy, Value *Addr,
17400                                              AtomicOrdering Ord) const {
17401   Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17402   bool IsAcquire = isAcquireOrStronger(Ord);
17403 
17404   // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
17405   // intrinsic must return {i64, i64} and we have to recombine them into a
17406   // single i128 here.
17407   if (ValueTy->getPrimitiveSizeInBits() == 128) {
17408     Intrinsic::ID Int =
17409         IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
17410     Function *Ldxr = Intrinsic::getDeclaration(M, Int);
17411 
17412     Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
17413     Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
17414 
17415     Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
17416     Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
17417     Lo = Builder.CreateZExt(Lo, ValueTy, "lo64");
17418     Hi = Builder.CreateZExt(Hi, ValueTy, "hi64");
17419     return Builder.CreateOr(
17420         Lo, Builder.CreateShl(Hi, ConstantInt::get(ValueTy, 64)), "val64");
17421   }
17422 
17423   Type *Tys[] = { Addr->getType() };
17424   Intrinsic::ID Int =
17425       IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
17426   Function *Ldxr = Intrinsic::getDeclaration(M, Int, Tys);
17427 
17428   const DataLayout &DL = M->getDataLayout();
17429   IntegerType *IntEltTy = Builder.getIntNTy(DL.getTypeSizeInBits(ValueTy));
17430   Value *Trunc = Builder.CreateTrunc(Builder.CreateCall(Ldxr, Addr), IntEltTy);
17431 
17432   return Builder.CreateBitCast(Trunc, ValueTy);
17433 }
17434 
17435 void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
17436     IRBuilderBase &Builder) const {
17437   Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17438   Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::aarch64_clrex));
17439 }
17440 
17441 Value *AArch64TargetLowering::emitStoreConditional(IRBuilderBase &Builder,
17442                                                    Value *Val, Value *Addr,
17443                                                    AtomicOrdering Ord) const {
17444   Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17445   bool IsRelease = isReleaseOrStronger(Ord);
17446 
17447   // Since the intrinsics must have legal type, the i128 intrinsics take two
17448   // parameters: "i64, i64". We must marshal Val into the appropriate form
17449   // before the call.
17450   if (Val->getType()->getPrimitiveSizeInBits() == 128) {
17451     Intrinsic::ID Int =
17452         IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
17453     Function *Stxr = Intrinsic::getDeclaration(M, Int);
17454     Type *Int64Ty = Type::getInt64Ty(M->getContext());
17455 
17456     Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
17457     Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
17458     Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
17459     return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
17460   }
17461 
17462   Intrinsic::ID Int =
17463       IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
17464   Type *Tys[] = { Addr->getType() };
17465   Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
17466 
17467   const DataLayout &DL = M->getDataLayout();
17468   IntegerType *IntValTy = Builder.getIntNTy(DL.getTypeSizeInBits(Val->getType()));
17469   Val = Builder.CreateBitCast(Val, IntValTy);
17470 
17471   return Builder.CreateCall(Stxr,
17472                             {Builder.CreateZExtOrBitCast(
17473                                  Val, Stxr->getFunctionType()->getParamType(0)),
17474                              Addr});
17475 }
17476 
17477 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
17478     Type *Ty, CallingConv::ID CallConv, bool isVarArg,
17479     const DataLayout &DL) const {
17480   if (!Ty->isArrayTy()) {
17481     const TypeSize &TySize = Ty->getPrimitiveSizeInBits();
17482     return TySize.isScalable() && TySize.getKnownMinSize() > 128;
17483   }
17484 
17485   // All non aggregate members of the type must have the same type
17486   SmallVector<EVT> ValueVTs;
17487   ComputeValueVTs(*this, DL, Ty, ValueVTs);
17488   return is_splat(ValueVTs);
17489 }
17490 
17491 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,
17492                                                             EVT) const {
17493   return false;
17494 }
17495 
17496 static Value *UseTlsOffset(IRBuilderBase &IRB, unsigned Offset) {
17497   Module *M = IRB.GetInsertBlock()->getParent()->getParent();
17498   Function *ThreadPointerFunc =
17499       Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
17500   return IRB.CreatePointerCast(
17501       IRB.CreateConstGEP1_32(IRB.getInt8Ty(), IRB.CreateCall(ThreadPointerFunc),
17502                              Offset),
17503       IRB.getInt8PtrTy()->getPointerTo(0));
17504 }
17505 
17506 Value *AArch64TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {
17507   // Android provides a fixed TLS slot for the stack cookie. See the definition
17508   // of TLS_SLOT_STACK_GUARD in
17509   // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
17510   if (Subtarget->isTargetAndroid())
17511     return UseTlsOffset(IRB, 0x28);
17512 
17513   // Fuchsia is similar.
17514   // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
17515   if (Subtarget->isTargetFuchsia())
17516     return UseTlsOffset(IRB, -0x10);
17517 
17518   return TargetLowering::getIRStackGuard(IRB);
17519 }
17520 
17521 void AArch64TargetLowering::insertSSPDeclarations(Module &M) const {
17522   // MSVC CRT provides functionalities for stack protection.
17523   if (Subtarget->getTargetTriple().isWindowsMSVCEnvironment()) {
17524     // MSVC CRT has a global variable holding security cookie.
17525     M.getOrInsertGlobal("__security_cookie",
17526                         Type::getInt8PtrTy(M.getContext()));
17527 
17528     // MSVC CRT has a function to validate security cookie.
17529     FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
17530         "__security_check_cookie", Type::getVoidTy(M.getContext()),
17531         Type::getInt8PtrTy(M.getContext()));
17532     if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
17533       F->setCallingConv(CallingConv::Win64);
17534       F->addAttribute(1, Attribute::AttrKind::InReg);
17535     }
17536     return;
17537   }
17538   TargetLowering::insertSSPDeclarations(M);
17539 }
17540 
17541 Value *AArch64TargetLowering::getSDagStackGuard(const Module &M) const {
17542   // MSVC CRT has a global variable holding security cookie.
17543   if (Subtarget->getTargetTriple().isWindowsMSVCEnvironment())
17544     return M.getGlobalVariable("__security_cookie");
17545   return TargetLowering::getSDagStackGuard(M);
17546 }
17547 
17548 Function *AArch64TargetLowering::getSSPStackGuardCheck(const Module &M) const {
17549   // MSVC CRT has a function to validate security cookie.
17550   if (Subtarget->getTargetTriple().isWindowsMSVCEnvironment())
17551     return M.getFunction("__security_check_cookie");
17552   return TargetLowering::getSSPStackGuardCheck(M);
17553 }
17554 
17555 Value *
17556 AArch64TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
17557   // Android provides a fixed TLS slot for the SafeStack pointer. See the
17558   // definition of TLS_SLOT_SAFESTACK in
17559   // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
17560   if (Subtarget->isTargetAndroid())
17561     return UseTlsOffset(IRB, 0x48);
17562 
17563   // Fuchsia is similar.
17564   // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
17565   if (Subtarget->isTargetFuchsia())
17566     return UseTlsOffset(IRB, -0x8);
17567 
17568   return TargetLowering::getSafeStackPointerLocation(IRB);
17569 }
17570 
17571 bool AArch64TargetLowering::isMaskAndCmp0FoldingBeneficial(
17572     const Instruction &AndI) const {
17573   // Only sink 'and' mask to cmp use block if it is masking a single bit, since
17574   // this is likely to be fold the and/cmp/br into a single tbz instruction.  It
17575   // may be beneficial to sink in other cases, but we would have to check that
17576   // the cmp would not get folded into the br to form a cbz for these to be
17577   // beneficial.
17578   ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
17579   if (!Mask)
17580     return false;
17581   return Mask->getValue().isPowerOf2();
17582 }
17583 
17584 bool AArch64TargetLowering::
17585     shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
17586         SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
17587         unsigned OldShiftOpcode, unsigned NewShiftOpcode,
17588         SelectionDAG &DAG) const {
17589   // Does baseline recommend not to perform the fold by default?
17590   if (!TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
17591           X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG))
17592     return false;
17593   // Else, if this is a vector shift, prefer 'shl'.
17594   return X.getValueType().isScalarInteger() || NewShiftOpcode == ISD::SHL;
17595 }
17596 
17597 bool AArch64TargetLowering::shouldExpandShift(SelectionDAG &DAG,
17598                                               SDNode *N) const {
17599   if (DAG.getMachineFunction().getFunction().hasMinSize() &&
17600       !Subtarget->isTargetWindows() && !Subtarget->isTargetDarwin())
17601     return false;
17602   return true;
17603 }
17604 
17605 void AArch64TargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
17606   // Update IsSplitCSR in AArch64unctionInfo.
17607   AArch64FunctionInfo *AFI = Entry->getParent()->getInfo<AArch64FunctionInfo>();
17608   AFI->setIsSplitCSR(true);
17609 }
17610 
17611 void AArch64TargetLowering::insertCopiesSplitCSR(
17612     MachineBasicBlock *Entry,
17613     const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
17614   const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
17615   const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
17616   if (!IStart)
17617     return;
17618 
17619   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
17620   MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
17621   MachineBasicBlock::iterator MBBI = Entry->begin();
17622   for (const MCPhysReg *I = IStart; *I; ++I) {
17623     const TargetRegisterClass *RC = nullptr;
17624     if (AArch64::GPR64RegClass.contains(*I))
17625       RC = &AArch64::GPR64RegClass;
17626     else if (AArch64::FPR64RegClass.contains(*I))
17627       RC = &AArch64::FPR64RegClass;
17628     else
17629       llvm_unreachable("Unexpected register class in CSRsViaCopy!");
17630 
17631     Register NewVR = MRI->createVirtualRegister(RC);
17632     // Create copy from CSR to a virtual register.
17633     // FIXME: this currently does not emit CFI pseudo-instructions, it works
17634     // fine for CXX_FAST_TLS since the C++-style TLS access functions should be
17635     // nounwind. If we want to generalize this later, we may need to emit
17636     // CFI pseudo-instructions.
17637     assert(Entry->getParent()->getFunction().hasFnAttribute(
17638                Attribute::NoUnwind) &&
17639            "Function should be nounwind in insertCopiesSplitCSR!");
17640     Entry->addLiveIn(*I);
17641     BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
17642         .addReg(*I);
17643 
17644     // Insert the copy-back instructions right before the terminator.
17645     for (auto *Exit : Exits)
17646       BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
17647               TII->get(TargetOpcode::COPY), *I)
17648           .addReg(NewVR);
17649   }
17650 }
17651 
17652 bool AArch64TargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
17653   // Integer division on AArch64 is expensive. However, when aggressively
17654   // optimizing for code size, we prefer to use a div instruction, as it is
17655   // usually smaller than the alternative sequence.
17656   // The exception to this is vector division. Since AArch64 doesn't have vector
17657   // integer division, leaving the division as-is is a loss even in terms of
17658   // size, because it will have to be scalarized, while the alternative code
17659   // sequence can be performed in vector form.
17660   bool OptSize = Attr.hasFnAttribute(Attribute::MinSize);
17661   return OptSize && !VT.isVector();
17662 }
17663 
17664 bool AArch64TargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
17665   // We want inc-of-add for scalars and sub-of-not for vectors.
17666   return VT.isScalarInteger();
17667 }
17668 
17669 bool AArch64TargetLowering::enableAggressiveFMAFusion(EVT VT) const {
17670   return Subtarget->hasAggressiveFMA() && VT.isFloatingPoint();
17671 }
17672 
17673 unsigned
17674 AArch64TargetLowering::getVaListSizeInBits(const DataLayout &DL) const {
17675   if (Subtarget->isTargetDarwin() || Subtarget->isTargetWindows())
17676     return getPointerTy(DL).getSizeInBits();
17677 
17678   return 3 * getPointerTy(DL).getSizeInBits() + 2 * 32;
17679 }
17680 
17681 void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
17682   MF.getFrameInfo().computeMaxCallFrameSize(MF);
17683   TargetLoweringBase::finalizeLowering(MF);
17684 }
17685 
17686 // Unlike X86, we let frame lowering assign offsets to all catch objects.
17687 bool AArch64TargetLowering::needsFixedCatchObjects() const {
17688   return false;
17689 }
17690 
17691 bool AArch64TargetLowering::shouldLocalize(
17692     const MachineInstr &MI, const TargetTransformInfo *TTI) const {
17693   switch (MI.getOpcode()) {
17694   case TargetOpcode::G_GLOBAL_VALUE: {
17695     // On Darwin, TLS global vars get selected into function calls, which
17696     // we don't want localized, as they can get moved into the middle of a
17697     // another call sequence.
17698     const GlobalValue &GV = *MI.getOperand(1).getGlobal();
17699     if (GV.isThreadLocal() && Subtarget->isTargetMachO())
17700       return false;
17701     break;
17702   }
17703   // If we legalized G_GLOBAL_VALUE into ADRP + G_ADD_LOW, mark both as being
17704   // localizable.
17705   case AArch64::ADRP:
17706   case AArch64::G_ADD_LOW:
17707     return true;
17708   default:
17709     break;
17710   }
17711   return TargetLoweringBase::shouldLocalize(MI, TTI);
17712 }
17713 
17714 bool AArch64TargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
17715   if (isa<ScalableVectorType>(Inst.getType()))
17716     return true;
17717 
17718   for (unsigned i = 0; i < Inst.getNumOperands(); ++i)
17719     if (isa<ScalableVectorType>(Inst.getOperand(i)->getType()))
17720       return true;
17721 
17722   if (const AllocaInst *AI = dyn_cast<AllocaInst>(&Inst)) {
17723     if (isa<ScalableVectorType>(AI->getAllocatedType()))
17724       return true;
17725   }
17726 
17727   return false;
17728 }
17729 
17730 // Return the largest legal scalable vector type that matches VT's element type.
17731 static EVT getContainerForFixedLengthVector(SelectionDAG &DAG, EVT VT) {
17732   assert(VT.isFixedLengthVector() &&
17733          DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
17734          "Expected legal fixed length vector!");
17735   switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
17736   default:
17737     llvm_unreachable("unexpected element type for SVE container");
17738   case MVT::i8:
17739     return EVT(MVT::nxv16i8);
17740   case MVT::i16:
17741     return EVT(MVT::nxv8i16);
17742   case MVT::i32:
17743     return EVT(MVT::nxv4i32);
17744   case MVT::i64:
17745     return EVT(MVT::nxv2i64);
17746   case MVT::f16:
17747     return EVT(MVT::nxv8f16);
17748   case MVT::f32:
17749     return EVT(MVT::nxv4f32);
17750   case MVT::f64:
17751     return EVT(MVT::nxv2f64);
17752   }
17753 }
17754 
17755 // Return a PTRUE with active lanes corresponding to the extent of VT.
17756 static SDValue getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL,
17757                                                 EVT VT) {
17758   assert(VT.isFixedLengthVector() &&
17759          DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
17760          "Expected legal fixed length vector!");
17761 
17762   int PgPattern;
17763   switch (VT.getVectorNumElements()) {
17764   default:
17765     llvm_unreachable("unexpected element count for SVE predicate");
17766   case 1:
17767     PgPattern = AArch64SVEPredPattern::vl1;
17768     break;
17769   case 2:
17770     PgPattern = AArch64SVEPredPattern::vl2;
17771     break;
17772   case 4:
17773     PgPattern = AArch64SVEPredPattern::vl4;
17774     break;
17775   case 8:
17776     PgPattern = AArch64SVEPredPattern::vl8;
17777     break;
17778   case 16:
17779     PgPattern = AArch64SVEPredPattern::vl16;
17780     break;
17781   case 32:
17782     PgPattern = AArch64SVEPredPattern::vl32;
17783     break;
17784   case 64:
17785     PgPattern = AArch64SVEPredPattern::vl64;
17786     break;
17787   case 128:
17788     PgPattern = AArch64SVEPredPattern::vl128;
17789     break;
17790   case 256:
17791     PgPattern = AArch64SVEPredPattern::vl256;
17792     break;
17793   }
17794 
17795   // TODO: For vectors that are exactly getMaxSVEVectorSizeInBits big, we can
17796   // use AArch64SVEPredPattern::all, which can enable the use of unpredicated
17797   // variants of instructions when available.
17798 
17799   MVT MaskVT;
17800   switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
17801   default:
17802     llvm_unreachable("unexpected element type for SVE predicate");
17803   case MVT::i8:
17804     MaskVT = MVT::nxv16i1;
17805     break;
17806   case MVT::i16:
17807   case MVT::f16:
17808     MaskVT = MVT::nxv8i1;
17809     break;
17810   case MVT::i32:
17811   case MVT::f32:
17812     MaskVT = MVT::nxv4i1;
17813     break;
17814   case MVT::i64:
17815   case MVT::f64:
17816     MaskVT = MVT::nxv2i1;
17817     break;
17818   }
17819 
17820   return DAG.getNode(AArch64ISD::PTRUE, DL, MaskVT,
17821                      DAG.getTargetConstant(PgPattern, DL, MVT::i64));
17822 }
17823 
17824 static SDValue getPredicateForScalableVector(SelectionDAG &DAG, SDLoc &DL,
17825                                              EVT VT) {
17826   assert(VT.isScalableVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
17827          "Expected legal scalable vector!");
17828   auto PredTy = VT.changeVectorElementType(MVT::i1);
17829   return getPTrue(DAG, DL, PredTy, AArch64SVEPredPattern::all);
17830 }
17831 
17832 static SDValue getPredicateForVector(SelectionDAG &DAG, SDLoc &DL, EVT VT) {
17833   if (VT.isFixedLengthVector())
17834     return getPredicateForFixedLengthVector(DAG, DL, VT);
17835 
17836   return getPredicateForScalableVector(DAG, DL, VT);
17837 }
17838 
17839 // Grow V to consume an entire SVE register.
17840 static SDValue convertToScalableVector(SelectionDAG &DAG, EVT VT, SDValue V) {
17841   assert(VT.isScalableVector() &&
17842          "Expected to convert into a scalable vector!");
17843   assert(V.getValueType().isFixedLengthVector() &&
17844          "Expected a fixed length vector operand!");
17845   SDLoc DL(V);
17846   SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
17847   return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero);
17848 }
17849 
17850 // Shrink V so it's just big enough to maintain a VT's worth of data.
17851 static SDValue convertFromScalableVector(SelectionDAG &DAG, EVT VT, SDValue V) {
17852   assert(VT.isFixedLengthVector() &&
17853          "Expected to convert into a fixed length vector!");
17854   assert(V.getValueType().isScalableVector() &&
17855          "Expected a scalable vector operand!");
17856   SDLoc DL(V);
17857   SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
17858   return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, Zero);
17859 }
17860 
17861 // Convert all fixed length vector loads larger than NEON to masked_loads.
17862 SDValue AArch64TargetLowering::LowerFixedLengthVectorLoadToSVE(
17863     SDValue Op, SelectionDAG &DAG) const {
17864   auto Load = cast<LoadSDNode>(Op);
17865 
17866   SDLoc DL(Op);
17867   EVT VT = Op.getValueType();
17868   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
17869 
17870   auto NewLoad = DAG.getMaskedLoad(
17871       ContainerVT, DL, Load->getChain(), Load->getBasePtr(), Load->getOffset(),
17872       getPredicateForFixedLengthVector(DAG, DL, VT), DAG.getUNDEF(ContainerVT),
17873       Load->getMemoryVT(), Load->getMemOperand(), Load->getAddressingMode(),
17874       Load->getExtensionType());
17875 
17876   auto Result = convertFromScalableVector(DAG, VT, NewLoad);
17877   SDValue MergedValues[2] = {Result, Load->getChain()};
17878   return DAG.getMergeValues(MergedValues, DL);
17879 }
17880 
17881 static SDValue convertFixedMaskToScalableVector(SDValue Mask,
17882                                                 SelectionDAG &DAG) {
17883   SDLoc DL(Mask);
17884   EVT InVT = Mask.getValueType();
17885   EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT);
17886 
17887   auto Op1 = convertToScalableVector(DAG, ContainerVT, Mask);
17888   auto Op2 = DAG.getConstant(0, DL, ContainerVT);
17889   auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
17890 
17891   EVT CmpVT = Pg.getValueType();
17892   return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, CmpVT,
17893                      {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)});
17894 }
17895 
17896 // Convert all fixed length vector loads larger than NEON to masked_loads.
17897 SDValue AArch64TargetLowering::LowerFixedLengthVectorMLoadToSVE(
17898     SDValue Op, SelectionDAG &DAG) const {
17899   auto Load = cast<MaskedLoadSDNode>(Op);
17900 
17901   if (Load->getExtensionType() != ISD::LoadExtType::NON_EXTLOAD)
17902     return SDValue();
17903 
17904   SDLoc DL(Op);
17905   EVT VT = Op.getValueType();
17906   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
17907 
17908   SDValue Mask = convertFixedMaskToScalableVector(Load->getMask(), DAG);
17909 
17910   SDValue PassThru;
17911   bool IsPassThruZeroOrUndef = false;
17912 
17913   if (Load->getPassThru()->isUndef()) {
17914     PassThru = DAG.getUNDEF(ContainerVT);
17915     IsPassThruZeroOrUndef = true;
17916   } else {
17917     if (ContainerVT.isInteger())
17918       PassThru = DAG.getConstant(0, DL, ContainerVT);
17919     else
17920       PassThru = DAG.getConstantFP(0, DL, ContainerVT);
17921     if (isZerosVector(Load->getPassThru().getNode()))
17922       IsPassThruZeroOrUndef = true;
17923   }
17924 
17925   auto NewLoad = DAG.getMaskedLoad(
17926       ContainerVT, DL, Load->getChain(), Load->getBasePtr(), Load->getOffset(),
17927       Mask, PassThru, Load->getMemoryVT(), Load->getMemOperand(),
17928       Load->getAddressingMode(), Load->getExtensionType());
17929 
17930   if (!IsPassThruZeroOrUndef) {
17931     SDValue OldPassThru =
17932         convertToScalableVector(DAG, ContainerVT, Load->getPassThru());
17933     NewLoad = DAG.getSelect(DL, ContainerVT, Mask, NewLoad, OldPassThru);
17934   }
17935 
17936   auto Result = convertFromScalableVector(DAG, VT, NewLoad);
17937   SDValue MergedValues[2] = {Result, Load->getChain()};
17938   return DAG.getMergeValues(MergedValues, DL);
17939 }
17940 
17941 // Convert all fixed length vector stores larger than NEON to masked_stores.
17942 SDValue AArch64TargetLowering::LowerFixedLengthVectorStoreToSVE(
17943     SDValue Op, SelectionDAG &DAG) const {
17944   auto Store = cast<StoreSDNode>(Op);
17945 
17946   SDLoc DL(Op);
17947   EVT VT = Store->getValue().getValueType();
17948   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
17949 
17950   auto NewValue = convertToScalableVector(DAG, ContainerVT, Store->getValue());
17951   return DAG.getMaskedStore(
17952       Store->getChain(), DL, NewValue, Store->getBasePtr(), Store->getOffset(),
17953       getPredicateForFixedLengthVector(DAG, DL, VT), Store->getMemoryVT(),
17954       Store->getMemOperand(), Store->getAddressingMode(),
17955       Store->isTruncatingStore());
17956 }
17957 
17958 SDValue AArch64TargetLowering::LowerFixedLengthVectorMStoreToSVE(
17959     SDValue Op, SelectionDAG &DAG) const {
17960   auto Store = cast<MaskedStoreSDNode>(Op);
17961 
17962   if (Store->isTruncatingStore())
17963     return SDValue();
17964 
17965   SDLoc DL(Op);
17966   EVT VT = Store->getValue().getValueType();
17967   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
17968 
17969   auto NewValue = convertToScalableVector(DAG, ContainerVT, Store->getValue());
17970   SDValue Mask = convertFixedMaskToScalableVector(Store->getMask(), DAG);
17971 
17972   return DAG.getMaskedStore(
17973       Store->getChain(), DL, NewValue, Store->getBasePtr(), Store->getOffset(),
17974       Mask, Store->getMemoryVT(), Store->getMemOperand(),
17975       Store->getAddressingMode(), Store->isTruncatingStore());
17976 }
17977 
17978 SDValue AArch64TargetLowering::LowerFixedLengthVectorIntDivideToSVE(
17979     SDValue Op, SelectionDAG &DAG) const {
17980   SDLoc dl(Op);
17981   EVT VT = Op.getValueType();
17982   EVT EltVT = VT.getVectorElementType();
17983 
17984   bool Signed = Op.getOpcode() == ISD::SDIV;
17985   unsigned PredOpcode = Signed ? AArch64ISD::SDIV_PRED : AArch64ISD::UDIV_PRED;
17986 
17987   // Scalable vector i32/i64 DIV is supported.
17988   if (EltVT == MVT::i32 || EltVT == MVT::i64)
17989     return LowerToPredicatedOp(Op, DAG, PredOpcode, /*OverrideNEON=*/true);
17990 
17991   // Scalable vector i8/i16 DIV is not supported. Promote it to i32.
17992   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
17993   EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
17994   EVT FixedWidenedVT = HalfVT.widenIntegerVectorElementType(*DAG.getContext());
17995   EVT ScalableWidenedVT = getContainerForFixedLengthVector(DAG, FixedWidenedVT);
17996 
17997   // If this is not a full vector, extend, div, and truncate it.
17998   EVT WidenedVT = VT.widenIntegerVectorElementType(*DAG.getContext());
17999   if (DAG.getTargetLoweringInfo().isTypeLegal(WidenedVT)) {
18000     unsigned ExtendOpcode = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18001     SDValue Op0 = DAG.getNode(ExtendOpcode, dl, WidenedVT, Op.getOperand(0));
18002     SDValue Op1 = DAG.getNode(ExtendOpcode, dl, WidenedVT, Op.getOperand(1));
18003     SDValue Div = DAG.getNode(Op.getOpcode(), dl, WidenedVT, Op0, Op1);
18004     return DAG.getNode(ISD::TRUNCATE, dl, VT, Div);
18005   }
18006 
18007   // Convert the operands to scalable vectors.
18008   SDValue Op0 = convertToScalableVector(DAG, ContainerVT, Op.getOperand(0));
18009   SDValue Op1 = convertToScalableVector(DAG, ContainerVT, Op.getOperand(1));
18010 
18011   // Extend the scalable operands.
18012   unsigned UnpkLo = Signed ? AArch64ISD::SUNPKLO : AArch64ISD::UUNPKLO;
18013   unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI;
18014   SDValue Op0Lo = DAG.getNode(UnpkLo, dl, ScalableWidenedVT, Op0);
18015   SDValue Op1Lo = DAG.getNode(UnpkLo, dl, ScalableWidenedVT, Op1);
18016   SDValue Op0Hi = DAG.getNode(UnpkHi, dl, ScalableWidenedVT, Op0);
18017   SDValue Op1Hi = DAG.getNode(UnpkHi, dl, ScalableWidenedVT, Op1);
18018 
18019   // Convert back to fixed vectors so the DIV can be further lowered.
18020   Op0Lo = convertFromScalableVector(DAG, FixedWidenedVT, Op0Lo);
18021   Op1Lo = convertFromScalableVector(DAG, FixedWidenedVT, Op1Lo);
18022   Op0Hi = convertFromScalableVector(DAG, FixedWidenedVT, Op0Hi);
18023   Op1Hi = convertFromScalableVector(DAG, FixedWidenedVT, Op1Hi);
18024   SDValue ResultLo = DAG.getNode(Op.getOpcode(), dl, FixedWidenedVT,
18025                                  Op0Lo, Op1Lo);
18026   SDValue ResultHi = DAG.getNode(Op.getOpcode(), dl, FixedWidenedVT,
18027                                  Op0Hi, Op1Hi);
18028 
18029   // Convert again to scalable vectors to truncate.
18030   ResultLo = convertToScalableVector(DAG, ScalableWidenedVT, ResultLo);
18031   ResultHi = convertToScalableVector(DAG, ScalableWidenedVT, ResultHi);
18032   SDValue ScalableResult = DAG.getNode(AArch64ISD::UZP1, dl, ContainerVT,
18033                                        ResultLo, ResultHi);
18034 
18035   return convertFromScalableVector(DAG, VT, ScalableResult);
18036 }
18037 
18038 SDValue AArch64TargetLowering::LowerFixedLengthVectorIntExtendToSVE(
18039     SDValue Op, SelectionDAG &DAG) const {
18040   EVT VT = Op.getValueType();
18041   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
18042 
18043   SDLoc DL(Op);
18044   SDValue Val = Op.getOperand(0);
18045   EVT ContainerVT = getContainerForFixedLengthVector(DAG, Val.getValueType());
18046   Val = convertToScalableVector(DAG, ContainerVT, Val);
18047 
18048   bool Signed = Op.getOpcode() == ISD::SIGN_EXTEND;
18049   unsigned ExtendOpc = Signed ? AArch64ISD::SUNPKLO : AArch64ISD::UUNPKLO;
18050 
18051   // Repeatedly unpack Val until the result is of the desired element type.
18052   switch (ContainerVT.getSimpleVT().SimpleTy) {
18053   default:
18054     llvm_unreachable("unimplemented container type");
18055   case MVT::nxv16i8:
18056     Val = DAG.getNode(ExtendOpc, DL, MVT::nxv8i16, Val);
18057     if (VT.getVectorElementType() == MVT::i16)
18058       break;
18059     LLVM_FALLTHROUGH;
18060   case MVT::nxv8i16:
18061     Val = DAG.getNode(ExtendOpc, DL, MVT::nxv4i32, Val);
18062     if (VT.getVectorElementType() == MVT::i32)
18063       break;
18064     LLVM_FALLTHROUGH;
18065   case MVT::nxv4i32:
18066     Val = DAG.getNode(ExtendOpc, DL, MVT::nxv2i64, Val);
18067     assert(VT.getVectorElementType() == MVT::i64 && "Unexpected element type!");
18068     break;
18069   }
18070 
18071   return convertFromScalableVector(DAG, VT, Val);
18072 }
18073 
18074 SDValue AArch64TargetLowering::LowerFixedLengthVectorTruncateToSVE(
18075     SDValue Op, SelectionDAG &DAG) const {
18076   EVT VT = Op.getValueType();
18077   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
18078 
18079   SDLoc DL(Op);
18080   SDValue Val = Op.getOperand(0);
18081   EVT ContainerVT = getContainerForFixedLengthVector(DAG, Val.getValueType());
18082   Val = convertToScalableVector(DAG, ContainerVT, Val);
18083 
18084   // Repeatedly truncate Val until the result is of the desired element type.
18085   switch (ContainerVT.getSimpleVT().SimpleTy) {
18086   default:
18087     llvm_unreachable("unimplemented container type");
18088   case MVT::nxv2i64:
18089     Val = DAG.getNode(ISD::BITCAST, DL, MVT::nxv4i32, Val);
18090     Val = DAG.getNode(AArch64ISD::UZP1, DL, MVT::nxv4i32, Val, Val);
18091     if (VT.getVectorElementType() == MVT::i32)
18092       break;
18093     LLVM_FALLTHROUGH;
18094   case MVT::nxv4i32:
18095     Val = DAG.getNode(ISD::BITCAST, DL, MVT::nxv8i16, Val);
18096     Val = DAG.getNode(AArch64ISD::UZP1, DL, MVT::nxv8i16, Val, Val);
18097     if (VT.getVectorElementType() == MVT::i16)
18098       break;
18099     LLVM_FALLTHROUGH;
18100   case MVT::nxv8i16:
18101     Val = DAG.getNode(ISD::BITCAST, DL, MVT::nxv16i8, Val);
18102     Val = DAG.getNode(AArch64ISD::UZP1, DL, MVT::nxv16i8, Val, Val);
18103     assert(VT.getVectorElementType() == MVT::i8 && "Unexpected element type!");
18104     break;
18105   }
18106 
18107   return convertFromScalableVector(DAG, VT, Val);
18108 }
18109 
18110 SDValue AArch64TargetLowering::LowerFixedLengthExtractVectorElt(
18111     SDValue Op, SelectionDAG &DAG) const {
18112   EVT VT = Op.getValueType();
18113   EVT InVT = Op.getOperand(0).getValueType();
18114   assert(InVT.isFixedLengthVector() && "Expected fixed length vector type!");
18115 
18116   SDLoc DL(Op);
18117   EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT);
18118   SDValue Op0 = convertToScalableVector(DAG, ContainerVT, Op->getOperand(0));
18119 
18120   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op0, Op.getOperand(1));
18121 }
18122 
18123 SDValue AArch64TargetLowering::LowerFixedLengthInsertVectorElt(
18124     SDValue Op, SelectionDAG &DAG) const {
18125   EVT VT = Op.getValueType();
18126   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
18127 
18128   SDLoc DL(Op);
18129   EVT InVT = Op.getOperand(0).getValueType();
18130   EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT);
18131   SDValue Op0 = convertToScalableVector(DAG, ContainerVT, Op->getOperand(0));
18132 
18133   auto ScalableRes = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ContainerVT, Op0,
18134                                  Op.getOperand(1), Op.getOperand(2));
18135 
18136   return convertFromScalableVector(DAG, VT, ScalableRes);
18137 }
18138 
18139 // Convert vector operation 'Op' to an equivalent predicated operation whereby
18140 // the original operation's type is used to construct a suitable predicate.
18141 // NOTE: The results for inactive lanes are undefined.
18142 SDValue AArch64TargetLowering::LowerToPredicatedOp(SDValue Op,
18143                                                    SelectionDAG &DAG,
18144                                                    unsigned NewOp,
18145                                                    bool OverrideNEON) const {
18146   EVT VT = Op.getValueType();
18147   SDLoc DL(Op);
18148   auto Pg = getPredicateForVector(DAG, DL, VT);
18149 
18150   if (useSVEForFixedLengthVectorVT(VT, OverrideNEON)) {
18151     EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
18152 
18153     // Create list of operands by converting existing ones to scalable types.
18154     SmallVector<SDValue, 4> Operands = {Pg};
18155     for (const SDValue &V : Op->op_values()) {
18156       if (isa<CondCodeSDNode>(V)) {
18157         Operands.push_back(V);
18158         continue;
18159       }
18160 
18161       if (const VTSDNode *VTNode = dyn_cast<VTSDNode>(V)) {
18162         EVT VTArg = VTNode->getVT().getVectorElementType();
18163         EVT NewVTArg = ContainerVT.changeVectorElementType(VTArg);
18164         Operands.push_back(DAG.getValueType(NewVTArg));
18165         continue;
18166       }
18167 
18168       assert(useSVEForFixedLengthVectorVT(V.getValueType(), OverrideNEON) &&
18169              "Only fixed length vectors are supported!");
18170       Operands.push_back(convertToScalableVector(DAG, ContainerVT, V));
18171     }
18172 
18173     if (isMergePassthruOpcode(NewOp))
18174       Operands.push_back(DAG.getUNDEF(ContainerVT));
18175 
18176     auto ScalableRes = DAG.getNode(NewOp, DL, ContainerVT, Operands);
18177     return convertFromScalableVector(DAG, VT, ScalableRes);
18178   }
18179 
18180   assert(VT.isScalableVector() && "Only expect to lower scalable vector op!");
18181 
18182   SmallVector<SDValue, 4> Operands = {Pg};
18183   for (const SDValue &V : Op->op_values()) {
18184     assert((!V.getValueType().isVector() ||
18185             V.getValueType().isScalableVector()) &&
18186            "Only scalable vectors are supported!");
18187     Operands.push_back(V);
18188   }
18189 
18190   if (isMergePassthruOpcode(NewOp))
18191     Operands.push_back(DAG.getUNDEF(VT));
18192 
18193   return DAG.getNode(NewOp, DL, VT, Operands);
18194 }
18195 
18196 // If a fixed length vector operation has no side effects when applied to
18197 // undefined elements, we can safely use scalable vectors to perform the same
18198 // operation without needing to worry about predication.
18199 SDValue AArch64TargetLowering::LowerToScalableOp(SDValue Op,
18200                                                  SelectionDAG &DAG) const {
18201   EVT VT = Op.getValueType();
18202   assert(useSVEForFixedLengthVectorVT(VT) &&
18203          "Only expected to lower fixed length vector operation!");
18204   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
18205 
18206   // Create list of operands by converting existing ones to scalable types.
18207   SmallVector<SDValue, 4> Ops;
18208   for (const SDValue &V : Op->op_values()) {
18209     assert(!isa<VTSDNode>(V) && "Unexpected VTSDNode node!");
18210 
18211     // Pass through non-vector operands.
18212     if (!V.getValueType().isVector()) {
18213       Ops.push_back(V);
18214       continue;
18215     }
18216 
18217     // "cast" fixed length vector to a scalable vector.
18218     assert(useSVEForFixedLengthVectorVT(V.getValueType()) &&
18219            "Only fixed length vectors are supported!");
18220     Ops.push_back(convertToScalableVector(DAG, ContainerVT, V));
18221   }
18222 
18223   auto ScalableRes = DAG.getNode(Op.getOpcode(), SDLoc(Op), ContainerVT, Ops);
18224   return convertFromScalableVector(DAG, VT, ScalableRes);
18225 }
18226 
18227 SDValue AArch64TargetLowering::LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp,
18228     SelectionDAG &DAG) const {
18229   SDLoc DL(ScalarOp);
18230   SDValue AccOp = ScalarOp.getOperand(0);
18231   SDValue VecOp = ScalarOp.getOperand(1);
18232   EVT SrcVT = VecOp.getValueType();
18233   EVT ResVT = SrcVT.getVectorElementType();
18234 
18235   EVT ContainerVT = SrcVT;
18236   if (SrcVT.isFixedLengthVector()) {
18237     ContainerVT = getContainerForFixedLengthVector(DAG, SrcVT);
18238     VecOp = convertToScalableVector(DAG, ContainerVT, VecOp);
18239   }
18240 
18241   SDValue Pg = getPredicateForVector(DAG, DL, SrcVT);
18242   SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
18243 
18244   // Convert operands to Scalable.
18245   AccOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ContainerVT,
18246                       DAG.getUNDEF(ContainerVT), AccOp, Zero);
18247 
18248   // Perform reduction.
18249   SDValue Rdx = DAG.getNode(AArch64ISD::FADDA_PRED, DL, ContainerVT,
18250                             Pg, AccOp, VecOp);
18251 
18252   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Rdx, Zero);
18253 }
18254 
18255 SDValue AArch64TargetLowering::LowerPredReductionToSVE(SDValue ReduceOp,
18256                                                        SelectionDAG &DAG) const {
18257   SDLoc DL(ReduceOp);
18258   SDValue Op = ReduceOp.getOperand(0);
18259   EVT OpVT = Op.getValueType();
18260   EVT VT = ReduceOp.getValueType();
18261 
18262   if (!OpVT.isScalableVector() || OpVT.getVectorElementType() != MVT::i1)
18263     return SDValue();
18264 
18265   SDValue Pg = getPredicateForVector(DAG, DL, OpVT);
18266 
18267   switch (ReduceOp.getOpcode()) {
18268   default:
18269     return SDValue();
18270   case ISD::VECREDUCE_OR:
18271     return getPTest(DAG, VT, Pg, Op, AArch64CC::ANY_ACTIVE);
18272   case ISD::VECREDUCE_AND: {
18273     Op = DAG.getNode(ISD::XOR, DL, OpVT, Op, Pg);
18274     return getPTest(DAG, VT, Pg, Op, AArch64CC::NONE_ACTIVE);
18275   }
18276   case ISD::VECREDUCE_XOR: {
18277     SDValue ID =
18278         DAG.getTargetConstant(Intrinsic::aarch64_sve_cntp, DL, MVT::i64);
18279     SDValue Cntp =
18280         DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i64, ID, Pg, Op);
18281     return DAG.getAnyExtOrTrunc(Cntp, DL, VT);
18282   }
18283   }
18284 
18285   return SDValue();
18286 }
18287 
18288 SDValue AArch64TargetLowering::LowerReductionToSVE(unsigned Opcode,
18289                                                    SDValue ScalarOp,
18290                                                    SelectionDAG &DAG) const {
18291   SDLoc DL(ScalarOp);
18292   SDValue VecOp = ScalarOp.getOperand(0);
18293   EVT SrcVT = VecOp.getValueType();
18294 
18295   if (useSVEForFixedLengthVectorVT(SrcVT, true)) {
18296     EVT ContainerVT = getContainerForFixedLengthVector(DAG, SrcVT);
18297     VecOp = convertToScalableVector(DAG, ContainerVT, VecOp);
18298   }
18299 
18300   // UADDV always returns an i64 result.
18301   EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 :
18302                                                    SrcVT.getVectorElementType();
18303   EVT RdxVT = SrcVT;
18304   if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED)
18305     RdxVT = getPackedSVEVectorVT(ResVT);
18306 
18307   SDValue Pg = getPredicateForVector(DAG, DL, SrcVT);
18308   SDValue Rdx = DAG.getNode(Opcode, DL, RdxVT, Pg, VecOp);
18309   SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT,
18310                             Rdx, DAG.getConstant(0, DL, MVT::i64));
18311 
18312   // The VEC_REDUCE nodes expect an element size result.
18313   if (ResVT != ScalarOp.getValueType())
18314     Res = DAG.getAnyExtOrTrunc(Res, DL, ScalarOp.getValueType());
18315 
18316   return Res;
18317 }
18318 
18319 SDValue
18320 AArch64TargetLowering::LowerFixedLengthVectorSelectToSVE(SDValue Op,
18321     SelectionDAG &DAG) const {
18322   EVT VT = Op.getValueType();
18323   SDLoc DL(Op);
18324 
18325   EVT InVT = Op.getOperand(1).getValueType();
18326   EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT);
18327   SDValue Op1 = convertToScalableVector(DAG, ContainerVT, Op->getOperand(1));
18328   SDValue Op2 = convertToScalableVector(DAG, ContainerVT, Op->getOperand(2));
18329 
18330   // Convert the mask to a predicated (NOTE: We don't need to worry about
18331   // inactive lanes since VSELECT is safe when given undefined elements).
18332   EVT MaskVT = Op.getOperand(0).getValueType();
18333   EVT MaskContainerVT = getContainerForFixedLengthVector(DAG, MaskVT);
18334   auto Mask = convertToScalableVector(DAG, MaskContainerVT, Op.getOperand(0));
18335   Mask = DAG.getNode(ISD::TRUNCATE, DL,
18336                      MaskContainerVT.changeVectorElementType(MVT::i1), Mask);
18337 
18338   auto ScalableRes = DAG.getNode(ISD::VSELECT, DL, ContainerVT,
18339                                 Mask, Op1, Op2);
18340 
18341   return convertFromScalableVector(DAG, VT, ScalableRes);
18342 }
18343 
18344 SDValue AArch64TargetLowering::LowerFixedLengthVectorSetccToSVE(
18345     SDValue Op, SelectionDAG &DAG) const {
18346   SDLoc DL(Op);
18347   EVT InVT = Op.getOperand(0).getValueType();
18348   EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT);
18349 
18350   assert(useSVEForFixedLengthVectorVT(InVT) &&
18351          "Only expected to lower fixed length vector operation!");
18352   assert(Op.getValueType() == InVT.changeTypeToInteger() &&
18353          "Expected integer result of the same bit length as the inputs!");
18354 
18355   auto Op1 = convertToScalableVector(DAG, ContainerVT, Op.getOperand(0));
18356   auto Op2 = convertToScalableVector(DAG, ContainerVT, Op.getOperand(1));
18357   auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
18358 
18359   EVT CmpVT = Pg.getValueType();
18360   auto Cmp = DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, CmpVT,
18361                          {Pg, Op1, Op2, Op.getOperand(2)});
18362 
18363   EVT PromoteVT = ContainerVT.changeTypeToInteger();
18364   auto Promote = DAG.getBoolExtOrTrunc(Cmp, DL, PromoteVT, InVT);
18365   return convertFromScalableVector(DAG, Op.getValueType(), Promote);
18366 }
18367 
18368 SDValue
18369 AArch64TargetLowering::LowerFixedLengthBitcastToSVE(SDValue Op,
18370                                                     SelectionDAG &DAG) const {
18371   SDLoc DL(Op);
18372   auto SrcOp = Op.getOperand(0);
18373   EVT VT = Op.getValueType();
18374   EVT ContainerDstVT = getContainerForFixedLengthVector(DAG, VT);
18375   EVT ContainerSrcVT =
18376       getContainerForFixedLengthVector(DAG, SrcOp.getValueType());
18377 
18378   SrcOp = convertToScalableVector(DAG, ContainerSrcVT, SrcOp);
18379   Op = DAG.getNode(ISD::BITCAST, DL, ContainerDstVT, SrcOp);
18380   return convertFromScalableVector(DAG, VT, Op);
18381 }
18382 
18383 SDValue AArch64TargetLowering::LowerFixedLengthConcatVectorsToSVE(
18384     SDValue Op, SelectionDAG &DAG) const {
18385   SDLoc DL(Op);
18386   unsigned NumOperands = Op->getNumOperands();
18387 
18388   assert(NumOperands > 1 && isPowerOf2_32(NumOperands) &&
18389          "Unexpected number of operands in CONCAT_VECTORS");
18390 
18391   auto SrcOp1 = Op.getOperand(0);
18392   auto SrcOp2 = Op.getOperand(1);
18393   EVT VT = Op.getValueType();
18394   EVT SrcVT = SrcOp1.getValueType();
18395 
18396   if (NumOperands > 2) {
18397     SmallVector<SDValue, 4> Ops;
18398     EVT PairVT = SrcVT.getDoubleNumVectorElementsVT(*DAG.getContext());
18399     for (unsigned I = 0; I < NumOperands; I += 2)
18400       Ops.push_back(DAG.getNode(ISD::CONCAT_VECTORS, DL, PairVT,
18401                                 Op->getOperand(I), Op->getOperand(I + 1)));
18402 
18403     return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Ops);
18404   }
18405 
18406   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
18407 
18408   SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT);
18409   SrcOp1 = convertToScalableVector(DAG, ContainerVT, SrcOp1);
18410   SrcOp2 = convertToScalableVector(DAG, ContainerVT, SrcOp2);
18411 
18412   Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2);
18413 
18414   return convertFromScalableVector(DAG, VT, Op);
18415 }
18416 
18417 SDValue
18418 AArch64TargetLowering::LowerFixedLengthFPExtendToSVE(SDValue Op,
18419                                                      SelectionDAG &DAG) const {
18420   EVT VT = Op.getValueType();
18421   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
18422 
18423   SDLoc DL(Op);
18424   SDValue Val = Op.getOperand(0);
18425   SDValue Pg = getPredicateForVector(DAG, DL, VT);
18426   EVT SrcVT = Val.getValueType();
18427   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
18428   EVT ExtendVT = ContainerVT.changeVectorElementType(
18429       SrcVT.getVectorElementType());
18430 
18431   Val = DAG.getNode(ISD::BITCAST, DL, SrcVT.changeTypeToInteger(), Val);
18432   Val = DAG.getNode(ISD::ANY_EXTEND, DL, VT.changeTypeToInteger(), Val);
18433 
18434   Val = convertToScalableVector(DAG, ContainerVT.changeTypeToInteger(), Val);
18435   Val = getSVESafeBitCast(ExtendVT, Val, DAG);
18436   Val = DAG.getNode(AArch64ISD::FP_EXTEND_MERGE_PASSTHRU, DL, ContainerVT,
18437                     Pg, Val, DAG.getUNDEF(ContainerVT));
18438 
18439   return convertFromScalableVector(DAG, VT, Val);
18440 }
18441 
18442 SDValue
18443 AArch64TargetLowering::LowerFixedLengthFPRoundToSVE(SDValue Op,
18444                                                     SelectionDAG &DAG) const {
18445   EVT VT = Op.getValueType();
18446   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
18447 
18448   SDLoc DL(Op);
18449   SDValue Val = Op.getOperand(0);
18450   EVT SrcVT = Val.getValueType();
18451   EVT ContainerSrcVT = getContainerForFixedLengthVector(DAG, SrcVT);
18452   EVT RoundVT = ContainerSrcVT.changeVectorElementType(
18453       VT.getVectorElementType());
18454   SDValue Pg = getPredicateForVector(DAG, DL, RoundVT);
18455 
18456   Val = convertToScalableVector(DAG, ContainerSrcVT, Val);
18457   Val = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, RoundVT, Pg, Val,
18458                     Op.getOperand(1), DAG.getUNDEF(RoundVT));
18459   Val = getSVESafeBitCast(ContainerSrcVT.changeTypeToInteger(), Val, DAG);
18460   Val = convertFromScalableVector(DAG, SrcVT.changeTypeToInteger(), Val);
18461 
18462   Val = DAG.getNode(ISD::TRUNCATE, DL, VT.changeTypeToInteger(), Val);
18463   return DAG.getNode(ISD::BITCAST, DL, VT, Val);
18464 }
18465 
18466 SDValue
18467 AArch64TargetLowering::LowerFixedLengthIntToFPToSVE(SDValue Op,
18468                                                     SelectionDAG &DAG) const {
18469   EVT VT = Op.getValueType();
18470   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
18471 
18472   bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP;
18473   unsigned Opcode = IsSigned ? AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU
18474                              : AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU;
18475 
18476   SDLoc DL(Op);
18477   SDValue Val = Op.getOperand(0);
18478   EVT SrcVT = Val.getValueType();
18479   EVT ContainerDstVT = getContainerForFixedLengthVector(DAG, VT);
18480   EVT ContainerSrcVT = getContainerForFixedLengthVector(DAG, SrcVT);
18481 
18482   if (ContainerSrcVT.getVectorElementType().getSizeInBits() <=
18483       ContainerDstVT.getVectorElementType().getSizeInBits()) {
18484     SDValue Pg = getPredicateForVector(DAG, DL, VT);
18485 
18486     Val = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL,
18487                       VT.changeTypeToInteger(), Val);
18488 
18489     Val = convertToScalableVector(DAG, ContainerSrcVT, Val);
18490     Val = getSVESafeBitCast(ContainerDstVT.changeTypeToInteger(), Val, DAG);
18491     // Safe to use a larger than specified operand since we just unpacked the
18492     // data, hence the upper bits are zero.
18493     Val = DAG.getNode(Opcode, DL, ContainerDstVT, Pg, Val,
18494                       DAG.getUNDEF(ContainerDstVT));
18495     return convertFromScalableVector(DAG, VT, Val);
18496   } else {
18497     EVT CvtVT = ContainerSrcVT.changeVectorElementType(
18498         ContainerDstVT.getVectorElementType());
18499     SDValue Pg = getPredicateForVector(DAG, DL, CvtVT);
18500 
18501     Val = convertToScalableVector(DAG, ContainerSrcVT, Val);
18502     Val = DAG.getNode(Opcode, DL, CvtVT, Pg, Val, DAG.getUNDEF(CvtVT));
18503     Val = getSVESafeBitCast(ContainerSrcVT, Val, DAG);
18504     Val = convertFromScalableVector(DAG, SrcVT, Val);
18505 
18506     Val = DAG.getNode(ISD::TRUNCATE, DL, VT.changeTypeToInteger(), Val);
18507     return DAG.getNode(ISD::BITCAST, DL, VT, Val);
18508   }
18509 }
18510 
18511 SDValue
18512 AArch64TargetLowering::LowerFixedLengthFPToIntToSVE(SDValue Op,
18513                                                     SelectionDAG &DAG) const {
18514   EVT VT = Op.getValueType();
18515   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
18516 
18517   bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT;
18518   unsigned Opcode = IsSigned ? AArch64ISD::FCVTZS_MERGE_PASSTHRU
18519                              : AArch64ISD::FCVTZU_MERGE_PASSTHRU;
18520 
18521   SDLoc DL(Op);
18522   SDValue Val = Op.getOperand(0);
18523   EVT SrcVT = Val.getValueType();
18524   EVT ContainerDstVT = getContainerForFixedLengthVector(DAG, VT);
18525   EVT ContainerSrcVT = getContainerForFixedLengthVector(DAG, SrcVT);
18526 
18527   if (ContainerSrcVT.getVectorElementType().getSizeInBits() <=
18528       ContainerDstVT.getVectorElementType().getSizeInBits()) {
18529     EVT CvtVT = ContainerDstVT.changeVectorElementType(
18530       ContainerSrcVT.getVectorElementType());
18531     SDValue Pg = getPredicateForVector(DAG, DL, VT);
18532 
18533     Val = DAG.getNode(ISD::BITCAST, DL, SrcVT.changeTypeToInteger(), Val);
18534     Val = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Val);
18535 
18536     Val = convertToScalableVector(DAG, ContainerSrcVT, Val);
18537     Val = getSVESafeBitCast(CvtVT, Val, DAG);
18538     Val = DAG.getNode(Opcode, DL, ContainerDstVT, Pg, Val,
18539                       DAG.getUNDEF(ContainerDstVT));
18540     return convertFromScalableVector(DAG, VT, Val);
18541   } else {
18542     EVT CvtVT = ContainerSrcVT.changeTypeToInteger();
18543     SDValue Pg = getPredicateForVector(DAG, DL, CvtVT);
18544 
18545     // Safe to use a larger than specified result since an fp_to_int where the
18546     // result doesn't fit into the destination is undefined.
18547     Val = convertToScalableVector(DAG, ContainerSrcVT, Val);
18548     Val = DAG.getNode(Opcode, DL, CvtVT, Pg, Val, DAG.getUNDEF(CvtVT));
18549     Val = convertFromScalableVector(DAG, SrcVT.changeTypeToInteger(), Val);
18550 
18551     return DAG.getNode(ISD::TRUNCATE, DL, VT, Val);
18552   }
18553 }
18554 
18555 SDValue AArch64TargetLowering::LowerFixedLengthVECTOR_SHUFFLEToSVE(
18556     SDValue Op, SelectionDAG &DAG) const {
18557   EVT VT = Op.getValueType();
18558   assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
18559 
18560   auto *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
18561   auto ShuffleMask = SVN->getMask();
18562 
18563   SDLoc DL(Op);
18564   SDValue Op1 = Op.getOperand(0);
18565   SDValue Op2 = Op.getOperand(1);
18566 
18567   EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
18568   Op1 = convertToScalableVector(DAG, ContainerVT, Op1);
18569   Op2 = convertToScalableVector(DAG, ContainerVT, Op2);
18570 
18571   bool ReverseEXT = false;
18572   unsigned Imm;
18573   if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm) &&
18574       Imm == VT.getVectorNumElements() - 1) {
18575     if (ReverseEXT)
18576       std::swap(Op1, Op2);
18577 
18578     EVT ScalarTy = VT.getVectorElementType();
18579     if ((ScalarTy == MVT::i8) || (ScalarTy == MVT::i16))
18580       ScalarTy = MVT::i32;
18581     SDValue Scalar = DAG.getNode(
18582         ISD::EXTRACT_VECTOR_ELT, DL, ScalarTy, Op1,
18583         DAG.getConstant(VT.getVectorNumElements() - 1, DL, MVT::i64));
18584     Op = DAG.getNode(AArch64ISD::INSR, DL, ContainerVT, Op2, Scalar);
18585     return convertFromScalableVector(DAG, VT, Op);
18586   }
18587 
18588   return SDValue();
18589 }
18590 
18591 SDValue AArch64TargetLowering::getSVESafeBitCast(EVT VT, SDValue Op,
18592                                                  SelectionDAG &DAG) const {
18593   SDLoc DL(Op);
18594   EVT InVT = Op.getValueType();
18595   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18596   (void)TLI;
18597 
18598   assert(VT.isScalableVector() && TLI.isTypeLegal(VT) &&
18599          InVT.isScalableVector() && TLI.isTypeLegal(InVT) &&
18600          "Only expect to cast between legal scalable vector types!");
18601   assert((VT.getVectorElementType() == MVT::i1) ==
18602              (InVT.getVectorElementType() == MVT::i1) &&
18603          "Cannot cast between data and predicate scalable vector types!");
18604 
18605   if (InVT == VT)
18606     return Op;
18607 
18608   if (VT.getVectorElementType() == MVT::i1)
18609     return DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, VT, Op);
18610 
18611   EVT PackedVT = getPackedSVEVectorVT(VT.getVectorElementType());
18612   EVT PackedInVT = getPackedSVEVectorVT(InVT.getVectorElementType());
18613 
18614   // Pack input if required.
18615   if (InVT != PackedInVT)
18616     Op = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, PackedInVT, Op);
18617 
18618   Op = DAG.getNode(ISD::BITCAST, DL, PackedVT, Op);
18619 
18620   // Unpack result if required.
18621   if (VT != PackedVT)
18622     Op = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, VT, Op);
18623 
18624   return Op;
18625 }
18626 
18627 bool AArch64TargetLowering::isAllActivePredicate(SDValue N) const {
18628   return ::isAllActivePredicate(N);
18629 }
18630 
18631 EVT AArch64TargetLowering::getPromotedVTForPredicate(EVT VT) const {
18632   return ::getPromotedVTForPredicate(VT);
18633 }
18634 
18635 bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
18636     SDValue Op, const APInt &OriginalDemandedBits,
18637     const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO,
18638     unsigned Depth) const {
18639 
18640   unsigned Opc = Op.getOpcode();
18641   switch (Opc) {
18642   case AArch64ISD::VSHL: {
18643     // Match (VSHL (VLSHR Val X) X)
18644     SDValue ShiftL = Op;
18645     SDValue ShiftR = Op->getOperand(0);
18646     if (ShiftR->getOpcode() != AArch64ISD::VLSHR)
18647       return false;
18648 
18649     if (!ShiftL.hasOneUse() || !ShiftR.hasOneUse())
18650       return false;
18651 
18652     unsigned ShiftLBits = ShiftL->getConstantOperandVal(1);
18653     unsigned ShiftRBits = ShiftR->getConstantOperandVal(1);
18654 
18655     // Other cases can be handled as well, but this is not
18656     // implemented.
18657     if (ShiftRBits != ShiftLBits)
18658       return false;
18659 
18660     unsigned ScalarSize = Op.getScalarValueSizeInBits();
18661     assert(ScalarSize > ShiftLBits && "Invalid shift imm");
18662 
18663     APInt ZeroBits = APInt::getLowBitsSet(ScalarSize, ShiftLBits);
18664     APInt UnusedBits = ~OriginalDemandedBits;
18665 
18666     if ((ZeroBits & UnusedBits) != ZeroBits)
18667       return false;
18668 
18669     // All bits that are zeroed by (VSHL (VLSHR Val X) X) are not
18670     // used - simplify to just Val.
18671     return TLO.CombineTo(Op, ShiftR->getOperand(0));
18672   }
18673   }
18674 
18675   return TargetLowering::SimplifyDemandedBitsForTargetNode(
18676       Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
18677 }
18678 
18679 bool AArch64TargetLowering::isConstantUnsignedBitfieldExtactLegal(
18680     unsigned Opc, LLT Ty1, LLT Ty2) const {
18681   return Ty1 == Ty2 && (Ty1 == LLT::scalar(32) || Ty1 == LLT::scalar(64));
18682 }
18683