1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file When allowed by the instruction, replace a dead definition of a GPR
10 /// with the zero register. This makes the code a bit friendlier towards the
11 /// hardware's register renamer.
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64.h"
15 #include "AArch64RegisterInfo.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "aarch64-dead-defs"
26 
27 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28 
29 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
30 
31 namespace {
32 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
33 private:
34   const TargetRegisterInfo *TRI;
35   bool Changed;
36   bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
37   void processMachineBasicBlock(MachineBasicBlock &MBB);
38 public:
39   static char ID; // Pass identification, replacement for typeid.
40   AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
41     initializeAArch64DeadRegisterDefinitionsPass(
42         *PassRegistry::getPassRegistry());
43   }
44 
45   bool runOnMachineFunction(MachineFunction &F) override;
46 
47   MachineFunctionProperties getRequiredProperties() const override {
48     return MachineFunctionProperties().set(
49         MachineFunctionProperties::Property::NoVRegs);
50   }
51 
52   StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
53 
54   void getAnalysisUsage(AnalysisUsage &AU) const override {
55     AU.setPreservesCFG();
56     MachineFunctionPass::getAnalysisUsage(AU);
57   }
58 };
59 char AArch64DeadRegisterDefinitions::ID = 0;
60 } // end anonymous namespace
61 
62 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
63                 AARCH64_DEAD_REG_DEF_NAME, false, false)
64 
65 bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
66     unsigned Reg, const MachineInstr &MI) {
67   for (const MachineOperand &MO : MI.implicit_operands())
68     if (MO.isReg() && MO.isDef())
69       if (TRI->regsOverlap(Reg, MO.getReg()))
70         return true;
71   return false;
72 }
73 
74 static bool usesFrameIndex(const MachineInstr &MI) {
75   for (const MachineOperand &MO : MI.uses())
76     if (MO.isFI())
77       return true;
78   return false;
79 }
80 
81 void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
82     MachineBasicBlock &MBB) {
83   for (MachineInstr &MI : MBB) {
84     if (usesFrameIndex(MI)) {
85       // We need to skip this instruction because while it appears to have a
86       // dead def it uses a frame index which might expand into a multi
87       // instruction sequence during EPI.
88       DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
89       continue;
90     }
91     if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
92       // It is not allowed to write to the same register (not even the zero
93       // register) twice in a single instruction.
94       DEBUG(dbgs() << "    Ignoring, XZR or WZR already used by the instruction\n");
95       continue;
96     }
97     const MCInstrDesc &Desc = MI.getDesc();
98     for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
99       MachineOperand &MO = MI.getOperand(I);
100       if (!MO.isReg() || !MO.isDead() || !MO.isDef())
101         continue;
102       assert(!MO.isImplicit() && "Unexpected implicit def!");
103       DEBUG(dbgs() << "  Dead def operand #" << I << " in:\n    ";
104             MI.print(dbgs()));
105       // Be careful not to change the register if it's a tied operand.
106       if (MI.isRegTiedToUseOperand(I)) {
107         DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
108         continue;
109       }
110       // Don't change the register if there's an implicit def of a subreg or
111       // superreg.
112       if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
113         DEBUG(dbgs() << "    Ignoring, implicitly defines overlap reg.\n");
114         continue;
115       }
116       // Make sure the instruction take a register class that contains
117       // the zero register and replace it if so.
118       unsigned NewReg;
119       switch (Desc.OpInfo[I].RegClass) {
120       default:
121         DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
122         continue;
123       case AArch64::GPR32RegClassID:
124         NewReg = AArch64::WZR;
125         break;
126       case AArch64::GPR64RegClassID:
127         NewReg = AArch64::XZR;
128         break;
129       }
130       DEBUG(dbgs() << "    Replacing with zero register. New:\n      ");
131       MO.setReg(NewReg);
132       DEBUG(MI.print(dbgs()));
133       ++NumDeadDefsReplaced;
134       Changed = true;
135       // Only replace one dead register, see check for zero register above.
136       break;
137     }
138   }
139 }
140 
141 // Scan the function for instructions that have a dead definition of a
142 // register. Replace that register with the zero register when possible.
143 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
144   if (skipFunction(*MF.getFunction()))
145     return false;
146 
147   TRI = MF.getSubtarget().getRegisterInfo();
148   DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
149   Changed = false;
150   for (auto &MBB : MF)
151     processMachineBasicBlock(MBB);
152   return Changed;
153 }
154 
155 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
156   return new AArch64DeadRegisterDefinitions();
157 }
158