1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // When allowed by the instruction, replace a dead definition of a GPR with
10 // the zero register. This makes the code a bit friendlier towards the
11 // hardware's register renamer.
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64.h"
15 #include "AArch64RegisterInfo.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "aarch64-dead-defs"
26 
27 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28 
29 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
30 
31 namespace {
32 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
33 private:
34   const TargetRegisterInfo *TRI;
35   bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
36   bool processMachineBasicBlock(MachineBasicBlock &MBB);
37   bool usesFrameIndex(const MachineInstr &MI);
38 public:
39   static char ID; // Pass identification, replacement for typeid.
40   explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
41     initializeAArch64DeadRegisterDefinitionsPass(
42         *PassRegistry::getPassRegistry());
43   }
44 
45   bool runOnMachineFunction(MachineFunction &F) override;
46 
47   MachineFunctionProperties getRequiredProperties() const override {
48     return MachineFunctionProperties().set(
49         MachineFunctionProperties::Property::NoVRegs);
50   }
51 
52   StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
53 
54   void getAnalysisUsage(AnalysisUsage &AU) const override {
55     AU.setPreservesCFG();
56     MachineFunctionPass::getAnalysisUsage(AU);
57   }
58 };
59 char AArch64DeadRegisterDefinitions::ID = 0;
60 } // end anonymous namespace
61 
62 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
63                 AARCH64_DEAD_REG_DEF_NAME, false, false)
64 
65 bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
66     unsigned Reg, const MachineInstr &MI) {
67   for (const MachineOperand &MO : MI.implicit_operands())
68     if (MO.isReg() && MO.isDef())
69       if (TRI->regsOverlap(Reg, MO.getReg()))
70         return true;
71   return false;
72 }
73 
74 bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
75   for (const MachineOperand &Op : MI.uses())
76     if (Op.isFI())
77       return true;
78   return false;
79 }
80 
81 bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
82     MachineBasicBlock &MBB) {
83   bool Changed = false;
84   for (MachineInstr &MI : MBB) {
85     if (usesFrameIndex(MI)) {
86       // We need to skip this instruction because while it appears to have a
87       // dead def it uses a frame index which might expand into a multi
88       // instruction sequence during EPI.
89       DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
90       continue;
91     }
92     if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
93       // It is not allowed to write to the same register (not even the zero
94       // register) twice in a single instruction.
95       DEBUG(dbgs() << "    Ignoring, XZR or WZR already used by the instruction\n");
96       continue;
97     }
98     for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
99       MachineOperand &MO = MI.getOperand(i);
100       if (MO.isReg() && MO.isDead() && MO.isDef()) {
101         assert(!MO.isImplicit() && "Unexpected implicit def!");
102         DEBUG(dbgs() << "  Dead def operand #" << i << " in:\n    ";
103               MI.print(dbgs()));
104         // Be careful not to change the register if it's a tied operand.
105         if (MI.isRegTiedToUseOperand(i)) {
106           DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
107           continue;
108         }
109         // Don't change the register if there's an implicit def of a subreg or
110         // superreg.
111         if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
112           DEBUG(dbgs() << "    Ignoring, implicitly defines overlap reg.\n");
113           continue;
114         }
115         // Make sure the instruction take a register class that contains
116         // the zero register and replace it if so.
117         unsigned NewReg;
118         switch (MI.getDesc().OpInfo[i].RegClass) {
119         default:
120           DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
121           continue;
122         case AArch64::GPR32RegClassID:
123           NewReg = AArch64::WZR;
124           break;
125         case AArch64::GPR64RegClassID:
126           NewReg = AArch64::XZR;
127           break;
128         }
129         DEBUG(dbgs() << "    Replacing with zero register. New:\n      ");
130         MO.setReg(NewReg);
131         DEBUG(MI.print(dbgs()));
132         ++NumDeadDefsReplaced;
133         // Only replace one dead register, see check for zero register above.
134         break;
135       }
136     }
137   }
138   return Changed;
139 }
140 
141 // Scan the function for instructions that have a dead definition of a
142 // register. Replace that register with the zero register when possible.
143 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
144   TRI = MF.getSubtarget().getRegisterInfo();
145   bool Changed = false;
146   DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
147 
148   if (skipFunction(*MF.getFunction()))
149     return false;
150 
151   for (auto &MBB : MF)
152     if (processMachineBasicBlock(MBB))
153       Changed = true;
154   return Changed;
155 }
156 
157 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
158   return new AArch64DeadRegisterDefinitions();
159 }
160