1 //===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains a printer that converts from our internal representation 11 // of machine-dependent LLVM code to the AArch64 assembly language. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MCTargetDesc/AArch64AddressingModes.h" 16 #include "AArch64.h" 17 #include "AArch64MCInstLower.h" 18 #include "AArch64MachineFunctionInfo.h" 19 #include "AArch64RegisterInfo.h" 20 #include "AArch64Subtarget.h" 21 #include "InstPrinter/AArch64InstPrinter.h" 22 #include "MCTargetDesc/AArch64MCExpr.h" 23 #include "llvm/ADT/SmallString.h" 24 #include "llvm/ADT/StringSwitch.h" 25 #include "llvm/ADT/Twine.h" 26 #include "llvm/CodeGen/AsmPrinter.h" 27 #include "llvm/CodeGen/MachineInstr.h" 28 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 29 #include "llvm/CodeGen/StackMaps.h" 30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 31 #include "llvm/IR/DataLayout.h" 32 #include "llvm/IR/DebugInfo.h" 33 #include "llvm/MC/MCAsmInfo.h" 34 #include "llvm/MC/MCContext.h" 35 #include "llvm/MC/MCInst.h" 36 #include "llvm/MC/MCInstBuilder.h" 37 #include "llvm/MC/MCLinkerOptimizationHint.h" 38 #include "llvm/MC/MCStreamer.h" 39 #include "llvm/MC/MCSymbol.h" 40 #include "llvm/Support/Debug.h" 41 #include "llvm/Support/TargetRegistry.h" 42 #include "llvm/Support/raw_ostream.h" 43 using namespace llvm; 44 45 #define DEBUG_TYPE "asm-printer" 46 47 namespace { 48 49 class AArch64AsmPrinter : public AsmPrinter { 50 AArch64MCInstLower MCInstLowering; 51 StackMaps SM; 52 53 public: 54 AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer) 55 : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this), 56 SM(*this), AArch64FI(nullptr) {} 57 58 const char *getPassName() const override { 59 return "AArch64 Assembly Printer"; 60 } 61 62 /// \brief Wrapper for MCInstLowering.lowerOperand() for the 63 /// tblgen'erated pseudo lowering. 64 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const { 65 return MCInstLowering.lowerOperand(MO, MCOp); 66 } 67 68 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, 69 const MachineInstr &MI); 70 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, 71 const MachineInstr &MI); 72 /// \brief tblgen'erated driver function for lowering simple MI->MC 73 /// pseudo instructions. 74 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, 75 const MachineInstr *MI); 76 77 void EmitInstruction(const MachineInstr *MI) override; 78 79 void getAnalysisUsage(AnalysisUsage &AU) const override { 80 AsmPrinter::getAnalysisUsage(AU); 81 AU.setPreservesAll(); 82 } 83 84 bool runOnMachineFunction(MachineFunction &F) override { 85 AArch64FI = F.getInfo<AArch64FunctionInfo>(); 86 return AsmPrinter::runOnMachineFunction(F); 87 } 88 89 private: 90 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O); 91 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O); 92 bool printAsmRegInClass(const MachineOperand &MO, 93 const TargetRegisterClass *RC, bool isVector, 94 raw_ostream &O); 95 96 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 97 unsigned AsmVariant, const char *ExtraCode, 98 raw_ostream &O) override; 99 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, 100 unsigned AsmVariant, const char *ExtraCode, 101 raw_ostream &O) override; 102 103 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); 104 105 void EmitFunctionBodyEnd() override; 106 107 MCSymbol *GetCPISymbol(unsigned CPID) const override; 108 void EmitEndOfAsmFile(Module &M) override; 109 AArch64FunctionInfo *AArch64FI; 110 111 /// \brief Emit the LOHs contained in AArch64FI. 112 void EmitLOHs(); 113 114 typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol; 115 MInstToMCSymbol LOHInstToLabel; 116 }; 117 118 } // end of anonymous namespace 119 120 //===----------------------------------------------------------------------===// 121 122 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) { 123 const Triple &TT = TM.getTargetTriple(); 124 if (TT.isOSBinFormatMachO()) { 125 // Funny Darwin hack: This flag tells the linker that no global symbols 126 // contain code that falls through to other global symbols (e.g. the obvious 127 // implementation of multiple entry points). If this doesn't occur, the 128 // linker can safely perform dead code stripping. Since LLVM never 129 // generates code that does this, it is always safe to set. 130 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); 131 SM.serializeToStackMapSection(); 132 } 133 } 134 135 void AArch64AsmPrinter::EmitLOHs() { 136 SmallVector<MCSymbol *, 3> MCArgs; 137 138 for (const auto &D : AArch64FI->getLOHContainer()) { 139 for (const MachineInstr *MI : D.getArgs()) { 140 MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI); 141 assert(LabelIt != LOHInstToLabel.end() && 142 "Label hasn't been inserted for LOH related instruction"); 143 MCArgs.push_back(LabelIt->second); 144 } 145 OutStreamer->EmitLOHDirective(D.getKind(), MCArgs); 146 MCArgs.clear(); 147 } 148 } 149 150 void AArch64AsmPrinter::EmitFunctionBodyEnd() { 151 if (!AArch64FI->getLOHRelated().empty()) 152 EmitLOHs(); 153 } 154 155 /// GetCPISymbol - Return the symbol for the specified constant pool entry. 156 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const { 157 // Darwin uses a linker-private symbol name for constant-pools (to 158 // avoid addends on the relocation?), ELF has no such concept and 159 // uses a normal private symbol. 160 if (getDataLayout().getLinkerPrivateGlobalPrefix()[0]) 161 return OutContext.getOrCreateSymbol( 162 Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" + 163 Twine(getFunctionNumber()) + "_" + Twine(CPID)); 164 165 return OutContext.getOrCreateSymbol( 166 Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" + 167 Twine(getFunctionNumber()) + "_" + Twine(CPID)); 168 } 169 170 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum, 171 raw_ostream &O) { 172 const MachineOperand &MO = MI->getOperand(OpNum); 173 switch (MO.getType()) { 174 default: 175 llvm_unreachable("<unknown operand type>"); 176 case MachineOperand::MO_Register: { 177 unsigned Reg = MO.getReg(); 178 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 179 assert(!MO.getSubReg() && "Subregs should be eliminated!"); 180 O << AArch64InstPrinter::getRegisterName(Reg); 181 break; 182 } 183 case MachineOperand::MO_Immediate: { 184 int64_t Imm = MO.getImm(); 185 O << '#' << Imm; 186 break; 187 } 188 case MachineOperand::MO_GlobalAddress: { 189 const GlobalValue *GV = MO.getGlobal(); 190 MCSymbol *Sym = getSymbol(GV); 191 192 // FIXME: Can we get anything other than a plain symbol here? 193 assert(!MO.getTargetFlags() && "Unknown operand target flag!"); 194 195 Sym->print(O, MAI); 196 printOffset(MO.getOffset(), O); 197 break; 198 } 199 } 200 } 201 202 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode, 203 raw_ostream &O) { 204 unsigned Reg = MO.getReg(); 205 switch (Mode) { 206 default: 207 return true; // Unknown mode. 208 case 'w': 209 Reg = getWRegFromXReg(Reg); 210 break; 211 case 'x': 212 Reg = getXRegFromWReg(Reg); 213 break; 214 } 215 216 O << AArch64InstPrinter::getRegisterName(Reg); 217 return false; 218 } 219 220 // Prints the register in MO using class RC using the offset in the 221 // new register class. This should not be used for cross class 222 // printing. 223 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO, 224 const TargetRegisterClass *RC, 225 bool isVector, raw_ostream &O) { 226 assert(MO.isReg() && "Should only get here with a register!"); 227 const AArch64RegisterInfo *RI = 228 MF->getSubtarget<AArch64Subtarget>().getRegisterInfo(); 229 unsigned Reg = MO.getReg(); 230 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg)); 231 assert(RI->regsOverlap(RegToPrint, Reg)); 232 O << AArch64InstPrinter::getRegisterName( 233 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName); 234 return false; 235 } 236 237 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 238 unsigned AsmVariant, 239 const char *ExtraCode, raw_ostream &O) { 240 const MachineOperand &MO = MI->getOperand(OpNum); 241 242 // First try the generic code, which knows about modifiers like 'c' and 'n'. 243 if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O)) 244 return false; 245 246 // Does this asm operand have a single letter operand modifier? 247 if (ExtraCode && ExtraCode[0]) { 248 if (ExtraCode[1] != 0) 249 return true; // Unknown modifier. 250 251 switch (ExtraCode[0]) { 252 default: 253 return true; // Unknown modifier. 254 case 'w': // Print W register 255 case 'x': // Print X register 256 if (MO.isReg()) 257 return printAsmMRegister(MO, ExtraCode[0], O); 258 if (MO.isImm() && MO.getImm() == 0) { 259 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR; 260 O << AArch64InstPrinter::getRegisterName(Reg); 261 return false; 262 } 263 printOperand(MI, OpNum, O); 264 return false; 265 case 'b': // Print B register. 266 case 'h': // Print H register. 267 case 's': // Print S register. 268 case 'd': // Print D register. 269 case 'q': // Print Q register. 270 if (MO.isReg()) { 271 const TargetRegisterClass *RC; 272 switch (ExtraCode[0]) { 273 case 'b': 274 RC = &AArch64::FPR8RegClass; 275 break; 276 case 'h': 277 RC = &AArch64::FPR16RegClass; 278 break; 279 case 's': 280 RC = &AArch64::FPR32RegClass; 281 break; 282 case 'd': 283 RC = &AArch64::FPR64RegClass; 284 break; 285 case 'q': 286 RC = &AArch64::FPR128RegClass; 287 break; 288 default: 289 return true; 290 } 291 return printAsmRegInClass(MO, RC, false /* vector */, O); 292 } 293 printOperand(MI, OpNum, O); 294 return false; 295 } 296 } 297 298 // According to ARM, we should emit x and v registers unless we have a 299 // modifier. 300 if (MO.isReg()) { 301 unsigned Reg = MO.getReg(); 302 303 // If this is a w or x register, print an x register. 304 if (AArch64::GPR32allRegClass.contains(Reg) || 305 AArch64::GPR64allRegClass.contains(Reg)) 306 return printAsmMRegister(MO, 'x', O); 307 308 // If this is a b, h, s, d, or q register, print it as a v register. 309 return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */, 310 O); 311 } 312 313 printOperand(MI, OpNum, O); 314 return false; 315 } 316 317 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 318 unsigned OpNum, 319 unsigned AsmVariant, 320 const char *ExtraCode, 321 raw_ostream &O) { 322 if (ExtraCode && ExtraCode[0]) 323 return true; // Unknown modifier. 324 325 const MachineOperand &MO = MI->getOperand(OpNum); 326 assert(MO.isReg() && "unexpected inline asm memory operand"); 327 O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]"; 328 return false; 329 } 330 331 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI, 332 raw_ostream &OS) { 333 unsigned NOps = MI->getNumOperands(); 334 assert(NOps == 4); 335 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: "; 336 // cast away const; DIetc do not take const operands for some reason. 337 OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata()) 338 ->getName(); 339 OS << " <- "; 340 // Frame address. Currently handles register +- offset only. 341 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); 342 OS << '['; 343 printOperand(MI, 0, OS); 344 OS << '+'; 345 printOperand(MI, 1, OS); 346 OS << ']'; 347 OS << "+"; 348 printOperand(MI, NOps - 2, OS); 349 } 350 351 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, 352 const MachineInstr &MI) { 353 unsigned NumNOPBytes = MI.getOperand(1).getImm(); 354 355 SM.recordStackMap(MI); 356 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!"); 357 358 // Scan ahead to trim the shadow. 359 const MachineBasicBlock &MBB = *MI.getParent(); 360 MachineBasicBlock::const_iterator MII(MI); 361 ++MII; 362 while (NumNOPBytes > 0) { 363 if (MII == MBB.end() || MII->isCall() || 364 MII->getOpcode() == AArch64::DBG_VALUE || 365 MII->getOpcode() == TargetOpcode::PATCHPOINT || 366 MII->getOpcode() == TargetOpcode::STACKMAP) 367 break; 368 ++MII; 369 NumNOPBytes -= 4; 370 } 371 372 // Emit nops. 373 for (unsigned i = 0; i < NumNOPBytes; i += 4) 374 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); 375 } 376 377 // Lower a patchpoint of the form: 378 // [<def>], <id>, <numBytes>, <target>, <numArgs> 379 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, 380 const MachineInstr &MI) { 381 SM.recordPatchPoint(MI); 382 383 PatchPointOpers Opers(&MI); 384 385 int64_t CallTarget = Opers.getMetaOper(PatchPointOpers::TargetPos).getImm(); 386 unsigned EncodedBytes = 0; 387 if (CallTarget) { 388 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget && 389 "High 16 bits of call target should be zero."); 390 unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg(); 391 EncodedBytes = 16; 392 // Materialize the jump address: 393 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi) 394 .addReg(ScratchReg) 395 .addImm((CallTarget >> 32) & 0xFFFF) 396 .addImm(32)); 397 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi) 398 .addReg(ScratchReg) 399 .addReg(ScratchReg) 400 .addImm((CallTarget >> 16) & 0xFFFF) 401 .addImm(16)); 402 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi) 403 .addReg(ScratchReg) 404 .addReg(ScratchReg) 405 .addImm(CallTarget & 0xFFFF) 406 .addImm(0)); 407 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); 408 } 409 // Emit padding. 410 unsigned NumBytes = Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm(); 411 assert(NumBytes >= EncodedBytes && 412 "Patchpoint can't request size less than the length of a call."); 413 assert((NumBytes - EncodedBytes) % 4 == 0 && 414 "Invalid number of NOP bytes requested!"); 415 for (unsigned i = EncodedBytes; i < NumBytes; i += 4) 416 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); 417 } 418 419 // Simple pseudo-instructions have their lowering (with expansion to real 420 // instructions) auto-generated. 421 #include "AArch64GenMCPseudoLowering.inc" 422 423 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) { 424 // Do any auto-generated pseudo lowerings. 425 if (emitPseudoExpansionLowering(*OutStreamer, MI)) 426 return; 427 428 if (AArch64FI->getLOHRelated().count(MI)) { 429 // Generate a label for LOH related instruction 430 MCSymbol *LOHLabel = createTempSymbol("loh"); 431 // Associate the instruction with the label 432 LOHInstToLabel[MI] = LOHLabel; 433 OutStreamer->EmitLabel(LOHLabel); 434 } 435 436 // Do any manual lowerings. 437 switch (MI->getOpcode()) { 438 default: 439 break; 440 case AArch64::DBG_VALUE: { 441 if (isVerbose() && OutStreamer->hasRawTextSupport()) { 442 SmallString<128> TmpStr; 443 raw_svector_ostream OS(TmpStr); 444 PrintDebugValueComment(MI, OS); 445 OutStreamer->EmitRawText(StringRef(OS.str())); 446 } 447 return; 448 } 449 450 // Tail calls use pseudo instructions so they have the proper code-gen 451 // attributes (isCall, isReturn, etc.). We lower them to the real 452 // instruction here. 453 case AArch64::TCRETURNri: { 454 MCInst TmpInst; 455 TmpInst.setOpcode(AArch64::BR); 456 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 457 EmitToStreamer(*OutStreamer, TmpInst); 458 return; 459 } 460 case AArch64::TCRETURNdi: { 461 MCOperand Dest; 462 MCInstLowering.lowerOperand(MI->getOperand(0), Dest); 463 MCInst TmpInst; 464 TmpInst.setOpcode(AArch64::B); 465 TmpInst.addOperand(Dest); 466 EmitToStreamer(*OutStreamer, TmpInst); 467 return; 468 } 469 case AArch64::TLSDESC_CALLSEQ: { 470 /// lower this to: 471 /// adrp x0, :tlsdesc:var 472 /// ldr x1, [x0, #:tlsdesc_lo12:var] 473 /// add x0, x0, #:tlsdesc_lo12:var 474 /// .tlsdesccall var 475 /// blr x1 476 /// (TPIDR_EL0 offset now in x0) 477 const MachineOperand &MO_Sym = MI->getOperand(0); 478 MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym); 479 MCOperand Sym, SymTLSDescLo12, SymTLSDesc; 480 MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | 481 AArch64II::MO_NC); 482 MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE); 483 MCInstLowering.lowerOperand(MO_Sym, Sym); 484 MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12); 485 MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc); 486 487 MCInst Adrp; 488 Adrp.setOpcode(AArch64::ADRP); 489 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); 490 Adrp.addOperand(SymTLSDesc); 491 EmitToStreamer(*OutStreamer, Adrp); 492 493 MCInst Ldr; 494 Ldr.setOpcode(AArch64::LDRXui); 495 Ldr.addOperand(MCOperand::createReg(AArch64::X1)); 496 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); 497 Ldr.addOperand(SymTLSDescLo12); 498 Ldr.addOperand(MCOperand::createImm(0)); 499 EmitToStreamer(*OutStreamer, Ldr); 500 501 MCInst Add; 502 Add.setOpcode(AArch64::ADDXri); 503 Add.addOperand(MCOperand::createReg(AArch64::X0)); 504 Add.addOperand(MCOperand::createReg(AArch64::X0)); 505 Add.addOperand(SymTLSDescLo12); 506 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0))); 507 EmitToStreamer(*OutStreamer, Add); 508 509 // Emit a relocation-annotation. This expands to no code, but requests 510 // the following instruction gets an R_AARCH64_TLSDESC_CALL. 511 MCInst TLSDescCall; 512 TLSDescCall.setOpcode(AArch64::TLSDESCCALL); 513 TLSDescCall.addOperand(Sym); 514 EmitToStreamer(*OutStreamer, TLSDescCall); 515 516 MCInst Blr; 517 Blr.setOpcode(AArch64::BLR); 518 Blr.addOperand(MCOperand::createReg(AArch64::X1)); 519 EmitToStreamer(*OutStreamer, Blr); 520 521 return; 522 } 523 524 case TargetOpcode::STACKMAP: 525 return LowerSTACKMAP(*OutStreamer, SM, *MI); 526 527 case TargetOpcode::PATCHPOINT: 528 return LowerPATCHPOINT(*OutStreamer, SM, *MI); 529 } 530 531 // Finally, do the automated lowerings for everything else. 532 MCInst TmpInst; 533 MCInstLowering.Lower(MI, TmpInst); 534 EmitToStreamer(*OutStreamer, TmpInst); 535 } 536 537 // Force static initialization. 538 extern "C" void LLVMInitializeAArch64AsmPrinter() { 539 RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64leTarget); 540 RegisterAsmPrinter<AArch64AsmPrinter> Y(TheAArch64beTarget); 541 RegisterAsmPrinter<AArch64AsmPrinter> Z(TheARM64Target); 542 } 543