1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to the AArch64 assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64.h"
15 #include "AArch64MCInstLower.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64RegisterInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "MCTargetDesc/AArch64InstPrinter.h"
22 #include "MCTargetDesc/AArch64MCExpr.h"
23 #include "MCTargetDesc/AArch64MCTargetDesc.h"
24 #include "MCTargetDesc/AArch64TargetStreamer.h"
25 #include "TargetInfo/AArch64TargetInfo.h"
26 #include "Utils/AArch64BaseInfo.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/ADT/Twine.h"
32 #include "llvm/BinaryFormat/COFF.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/AsmPrinter.h"
35 #include "llvm/CodeGen/FaultMaps.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineInstr.h"
39 #include "llvm/CodeGen/MachineJumpTableInfo.h"
40 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
41 #include "llvm/CodeGen/MachineOperand.h"
42 #include "llvm/CodeGen/StackMaps.h"
43 #include "llvm/CodeGen/TargetRegisterInfo.h"
44 #include "llvm/IR/DataLayout.h"
45 #include "llvm/IR/DebugInfoMetadata.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCInst.h"
49 #include "llvm/MC/MCInstBuilder.h"
50 #include "llvm/MC/MCSectionELF.h"
51 #include "llvm/MC/MCStreamer.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/Casting.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/TargetRegistry.h"
56 #include "llvm/Support/raw_ostream.h"
57 #include "llvm/Target/TargetMachine.h"
58 #include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
59 #include <algorithm>
60 #include <cassert>
61 #include <cstdint>
62 #include <map>
63 #include <memory>
64 
65 using namespace llvm;
66 
67 #define DEBUG_TYPE "asm-printer"
68 
69 namespace {
70 
71 class AArch64AsmPrinter : public AsmPrinter {
72   AArch64MCInstLower MCInstLowering;
73   StackMaps SM;
74   FaultMaps FM;
75   const AArch64Subtarget *STI;
76 
77 public:
78   AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
79       : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
80         SM(*this), FM(*this) {}
81 
82   StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
83 
84   /// Wrapper for MCInstLowering.lowerOperand() for the
85   /// tblgen'erated pseudo lowering.
86   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
87     return MCInstLowering.lowerOperand(MO, MCOp);
88   }
89 
90   void emitStartOfAsmFile(Module &M) override;
91   void emitJumpTableInfo() override;
92 
93   void emitFunctionEntryLabel() override;
94 
95   void LowerJumpTableDest(MCStreamer &OutStreamer, const MachineInstr &MI);
96 
97   void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
98                      const MachineInstr &MI);
99   void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
100                        const MachineInstr &MI);
101   void LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
102                        const MachineInstr &MI);
103   void LowerFAULTING_OP(const MachineInstr &MI);
104 
105   void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
106   void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
107   void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
108 
109   typedef std::tuple<unsigned, bool, uint32_t> HwasanMemaccessTuple;
110   std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
111   void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
112   void emitHwasanMemaccessSymbols(Module &M);
113 
114   void emitSled(const MachineInstr &MI, SledKind Kind);
115 
116   /// tblgen'erated driver function for lowering simple MI->MC
117   /// pseudo instructions.
118   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
119                                    const MachineInstr *MI);
120 
121   void emitInstruction(const MachineInstr *MI) override;
122 
123   void emitFunctionHeaderComment() override;
124 
125   void getAnalysisUsage(AnalysisUsage &AU) const override {
126     AsmPrinter::getAnalysisUsage(AU);
127     AU.setPreservesAll();
128   }
129 
130   bool runOnMachineFunction(MachineFunction &MF) override {
131     AArch64FI = MF.getInfo<AArch64FunctionInfo>();
132     STI = static_cast<const AArch64Subtarget*>(&MF.getSubtarget());
133 
134     SetupMachineFunction(MF);
135 
136     if (STI->isTargetCOFF()) {
137       bool Internal = MF.getFunction().hasInternalLinkage();
138       COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
139                                               : COFF::IMAGE_SYM_CLASS_EXTERNAL;
140       int Type =
141         COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
142 
143       OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
144       OutStreamer->EmitCOFFSymbolStorageClass(Scl);
145       OutStreamer->EmitCOFFSymbolType(Type);
146       OutStreamer->EndCOFFSymbolDef();
147     }
148 
149     // Emit the rest of the function body.
150     emitFunctionBody();
151 
152     // Emit the XRay table for this function.
153     emitXRayTable();
154 
155     // We didn't modify anything.
156     return false;
157   }
158 
159 private:
160   void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
161   bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
162   bool printAsmRegInClass(const MachineOperand &MO,
163                           const TargetRegisterClass *RC, unsigned AltName,
164                           raw_ostream &O);
165 
166   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
167                        const char *ExtraCode, raw_ostream &O) override;
168   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
169                              const char *ExtraCode, raw_ostream &O) override;
170 
171   void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
172 
173   void emitFunctionBodyEnd() override;
174 
175   MCSymbol *GetCPISymbol(unsigned CPID) const override;
176   void emitEndOfAsmFile(Module &M) override;
177 
178   AArch64FunctionInfo *AArch64FI = nullptr;
179 
180   /// Emit the LOHs contained in AArch64FI.
181   void emitLOHs();
182 
183   /// Emit instruction to set float register to zero.
184   void emitFMov0(const MachineInstr &MI);
185 
186   using MInstToMCSymbol = std::map<const MachineInstr *, MCSymbol *>;
187 
188   MInstToMCSymbol LOHInstToLabel;
189 };
190 
191 } // end anonymous namespace
192 
193 void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) {
194   const Triple &TT = TM.getTargetTriple();
195 
196   if (TT.isOSBinFormatCOFF()) {
197     // Emit an absolute @feat.00 symbol.  This appears to be some kind of
198     // compiler features bitfield read by link.exe.
199     MCSymbol *S = MMI->getContext().getOrCreateSymbol(StringRef("@feat.00"));
200     OutStreamer->BeginCOFFSymbolDef(S);
201     OutStreamer->EmitCOFFSymbolStorageClass(COFF::IMAGE_SYM_CLASS_STATIC);
202     OutStreamer->EmitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_NULL);
203     OutStreamer->EndCOFFSymbolDef();
204     int64_t Feat00Flags = 0;
205 
206     if (M.getModuleFlag("cfguard")) {
207       Feat00Flags |= 0x800; // Object is CFG-aware.
208     }
209 
210     if (M.getModuleFlag("ehcontguard")) {
211       Feat00Flags |= 0x4000; // Object also has EHCont.
212     }
213 
214     OutStreamer->emitSymbolAttribute(S, MCSA_Global);
215     OutStreamer->emitAssignment(
216         S, MCConstantExpr::create(Feat00Flags, MMI->getContext()));
217   }
218 
219   if (!TT.isOSBinFormatELF())
220     return;
221 
222   // Assemble feature flags that may require creation of a note section.
223   unsigned Flags = 0;
224   if (const auto *BTE = mdconst::extract_or_null<ConstantInt>(
225           M.getModuleFlag("branch-target-enforcement")))
226     if (BTE->getZExtValue())
227       Flags |= ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI;
228 
229   if (const auto *Sign = mdconst::extract_or_null<ConstantInt>(
230           M.getModuleFlag("sign-return-address")))
231     if (Sign->getZExtValue())
232       Flags |= ELF::GNU_PROPERTY_AARCH64_FEATURE_1_PAC;
233 
234   if (Flags == 0)
235     return;
236 
237   // Emit a .note.gnu.property section with the flags.
238   if (auto *TS = static_cast<AArch64TargetStreamer *>(
239           OutStreamer->getTargetStreamer()))
240     TS->emitNoteSection(Flags);
241 }
242 
243 void AArch64AsmPrinter::emitFunctionHeaderComment() {
244   const AArch64FunctionInfo *FI = MF->getInfo<AArch64FunctionInfo>();
245   Optional<std::string> OutlinerString = FI->getOutliningStyle();
246   if (OutlinerString != None)
247     OutStreamer->GetCommentOS() << ' ' << OutlinerString;
248 }
249 
250 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
251 {
252   const Function &F = MF->getFunction();
253   if (F.hasFnAttribute("patchable-function-entry")) {
254     unsigned Num;
255     if (F.getFnAttribute("patchable-function-entry")
256             .getValueAsString()
257             .getAsInteger(10, Num))
258       return;
259     emitNops(Num);
260     return;
261   }
262 
263   emitSled(MI, SledKind::FUNCTION_ENTER);
264 }
265 
266 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
267   emitSled(MI, SledKind::FUNCTION_EXIT);
268 }
269 
270 void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
271   emitSled(MI, SledKind::TAIL_CALL);
272 }
273 
274 void AArch64AsmPrinter::emitSled(const MachineInstr &MI, SledKind Kind) {
275   static const int8_t NoopsInSledCount = 7;
276   // We want to emit the following pattern:
277   //
278   // .Lxray_sled_N:
279   //   ALIGN
280   //   B #32
281   //   ; 7 NOP instructions (28 bytes)
282   // .tmpN
283   //
284   // We need the 28 bytes (7 instructions) because at runtime, we'd be patching
285   // over the full 32 bytes (8 instructions) with the following pattern:
286   //
287   //   STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
288   //   LDR W0, #12 ; W0 := function ID
289   //   LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
290   //   BLR X16 ; call the tracing trampoline
291   //   ;DATA: 32 bits of function ID
292   //   ;DATA: lower 32 bits of the address of the trampoline
293   //   ;DATA: higher 32 bits of the address of the trampoline
294   //   LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
295   //
296   OutStreamer->emitCodeAlignment(4);
297   auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
298   OutStreamer->emitLabel(CurSled);
299   auto Target = OutContext.createTempSymbol();
300 
301   // Emit "B #32" instruction, which jumps over the next 28 bytes.
302   // The operand has to be the number of 4-byte instructions to jump over,
303   // including the current instruction.
304   EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
305 
306   for (int8_t I = 0; I < NoopsInSledCount; I++)
307     EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
308 
309   OutStreamer->emitLabel(Target);
310   recordSled(CurSled, MI, Kind, 2);
311 }
312 
313 void AArch64AsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
314   Register Reg = MI.getOperand(0).getReg();
315   bool IsShort =
316       MI.getOpcode() == AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES;
317   uint32_t AccessInfo = MI.getOperand(1).getImm();
318   MCSymbol *&Sym =
319       HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, IsShort, AccessInfo)];
320   if (!Sym) {
321     // FIXME: Make this work on non-ELF.
322     if (!TM.getTargetTriple().isOSBinFormatELF())
323       report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF");
324 
325     std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
326                           utostr(AccessInfo);
327     if (IsShort)
328       SymName += "_short_v2";
329     Sym = OutContext.getOrCreateSymbol(SymName);
330   }
331 
332   EmitToStreamer(*OutStreamer,
333                  MCInstBuilder(AArch64::BL)
334                      .addExpr(MCSymbolRefExpr::create(Sym, OutContext)));
335 }
336 
337 void AArch64AsmPrinter::emitHwasanMemaccessSymbols(Module &M) {
338   if (HwasanMemaccessSymbols.empty())
339     return;
340 
341   const Triple &TT = TM.getTargetTriple();
342   assert(TT.isOSBinFormatELF());
343   std::unique_ptr<MCSubtargetInfo> STI(
344       TM.getTarget().createMCSubtargetInfo(TT.str(), "", ""));
345   assert(STI && "Unable to create subtarget info");
346 
347   MCSymbol *HwasanTagMismatchV1Sym =
348       OutContext.getOrCreateSymbol("__hwasan_tag_mismatch");
349   MCSymbol *HwasanTagMismatchV2Sym =
350       OutContext.getOrCreateSymbol("__hwasan_tag_mismatch_v2");
351 
352   const MCSymbolRefExpr *HwasanTagMismatchV1Ref =
353       MCSymbolRefExpr::create(HwasanTagMismatchV1Sym, OutContext);
354   const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
355       MCSymbolRefExpr::create(HwasanTagMismatchV2Sym, OutContext);
356 
357   for (auto &P : HwasanMemaccessSymbols) {
358     unsigned Reg = std::get<0>(P.first);
359     bool IsShort = std::get<1>(P.first);
360     uint32_t AccessInfo = std::get<2>(P.first);
361     const MCSymbolRefExpr *HwasanTagMismatchRef =
362         IsShort ? HwasanTagMismatchV2Ref : HwasanTagMismatchV1Ref;
363     MCSymbol *Sym = P.second;
364 
365     bool HasMatchAllTag =
366         (AccessInfo >> HWASanAccessInfo::HasMatchAllShift) & 1;
367     uint8_t MatchAllTag =
368         (AccessInfo >> HWASanAccessInfo::MatchAllShift) & 0xff;
369     unsigned Size =
370         1 << ((AccessInfo >> HWASanAccessInfo::AccessSizeShift) & 0xf);
371     bool CompileKernel =
372         (AccessInfo >> HWASanAccessInfo::CompileKernelShift) & 1;
373 
374     OutStreamer->SwitchSection(OutContext.getELFSection(
375         ".text.hot", ELF::SHT_PROGBITS,
376         ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0,
377         Sym->getName(), /*IsComdat=*/true));
378 
379     OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
380     OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
381     OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
382     OutStreamer->emitLabel(Sym);
383 
384     OutStreamer->emitInstruction(MCInstBuilder(AArch64::SBFMXri)
385                                      .addReg(AArch64::X16)
386                                      .addReg(Reg)
387                                      .addImm(4)
388                                      .addImm(55),
389                                  *STI);
390     OutStreamer->emitInstruction(
391         MCInstBuilder(AArch64::LDRBBroX)
392             .addReg(AArch64::W16)
393             .addReg(IsShort ? AArch64::X20 : AArch64::X9)
394             .addReg(AArch64::X16)
395             .addImm(0)
396             .addImm(0),
397         *STI);
398     OutStreamer->emitInstruction(
399         MCInstBuilder(AArch64::SUBSXrs)
400             .addReg(AArch64::XZR)
401             .addReg(AArch64::X16)
402             .addReg(Reg)
403             .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
404         *STI);
405     MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
406     OutStreamer->emitInstruction(
407         MCInstBuilder(AArch64::Bcc)
408             .addImm(AArch64CC::NE)
409             .addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym,
410                                              OutContext)),
411         *STI);
412     MCSymbol *ReturnSym = OutContext.createTempSymbol();
413     OutStreamer->emitLabel(ReturnSym);
414     OutStreamer->emitInstruction(
415         MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
416     OutStreamer->emitLabel(HandleMismatchOrPartialSym);
417 
418     if (HasMatchAllTag) {
419       OutStreamer->emitInstruction(MCInstBuilder(AArch64::UBFMXri)
420                                        .addReg(AArch64::X16)
421                                        .addReg(Reg)
422                                        .addImm(56)
423                                        .addImm(63),
424                                    *STI);
425       OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSXri)
426                                        .addReg(AArch64::XZR)
427                                        .addReg(AArch64::X16)
428                                        .addImm(MatchAllTag)
429                                        .addImm(0),
430                                    *STI);
431       OutStreamer->emitInstruction(
432           MCInstBuilder(AArch64::Bcc)
433               .addImm(AArch64CC::EQ)
434               .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
435           *STI);
436     }
437 
438     if (IsShort) {
439       OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSWri)
440                                        .addReg(AArch64::WZR)
441                                        .addReg(AArch64::W16)
442                                        .addImm(15)
443                                        .addImm(0),
444                                    *STI);
445       MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
446       OutStreamer->emitInstruction(
447           MCInstBuilder(AArch64::Bcc)
448               .addImm(AArch64CC::HI)
449               .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
450           *STI);
451 
452       OutStreamer->emitInstruction(
453           MCInstBuilder(AArch64::ANDXri)
454               .addReg(AArch64::X17)
455               .addReg(Reg)
456               .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
457           *STI);
458       if (Size != 1)
459         OutStreamer->emitInstruction(MCInstBuilder(AArch64::ADDXri)
460                                          .addReg(AArch64::X17)
461                                          .addReg(AArch64::X17)
462                                          .addImm(Size - 1)
463                                          .addImm(0),
464                                      *STI);
465       OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSWrs)
466                                        .addReg(AArch64::WZR)
467                                        .addReg(AArch64::W16)
468                                        .addReg(AArch64::W17)
469                                        .addImm(0),
470                                    *STI);
471       OutStreamer->emitInstruction(
472           MCInstBuilder(AArch64::Bcc)
473               .addImm(AArch64CC::LS)
474               .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
475           *STI);
476 
477       OutStreamer->emitInstruction(
478           MCInstBuilder(AArch64::ORRXri)
479               .addReg(AArch64::X16)
480               .addReg(Reg)
481               .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
482           *STI);
483       OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRBBui)
484                                        .addReg(AArch64::W16)
485                                        .addReg(AArch64::X16)
486                                        .addImm(0),
487                                    *STI);
488       OutStreamer->emitInstruction(
489           MCInstBuilder(AArch64::SUBSXrs)
490               .addReg(AArch64::XZR)
491               .addReg(AArch64::X16)
492               .addReg(Reg)
493               .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
494           *STI);
495       OutStreamer->emitInstruction(
496           MCInstBuilder(AArch64::Bcc)
497               .addImm(AArch64CC::EQ)
498               .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
499           *STI);
500 
501       OutStreamer->emitLabel(HandleMismatchSym);
502     }
503 
504     OutStreamer->emitInstruction(MCInstBuilder(AArch64::STPXpre)
505                                      .addReg(AArch64::SP)
506                                      .addReg(AArch64::X0)
507                                      .addReg(AArch64::X1)
508                                      .addReg(AArch64::SP)
509                                      .addImm(-32),
510                                  *STI);
511     OutStreamer->emitInstruction(MCInstBuilder(AArch64::STPXi)
512                                      .addReg(AArch64::FP)
513                                      .addReg(AArch64::LR)
514                                      .addReg(AArch64::SP)
515                                      .addImm(29),
516                                  *STI);
517 
518     if (Reg != AArch64::X0)
519       OutStreamer->emitInstruction(MCInstBuilder(AArch64::ORRXrs)
520                                        .addReg(AArch64::X0)
521                                        .addReg(AArch64::XZR)
522                                        .addReg(Reg)
523                                        .addImm(0),
524                                    *STI);
525     OutStreamer->emitInstruction(
526         MCInstBuilder(AArch64::MOVZXi)
527             .addReg(AArch64::X1)
528             .addImm(AccessInfo & HWASanAccessInfo::RuntimeMask)
529             .addImm(0),
530         *STI);
531 
532     if (CompileKernel) {
533       // The Linux kernel's dynamic loader doesn't support GOT relative
534       // relocations, but it doesn't support late binding either, so just call
535       // the function directly.
536       OutStreamer->emitInstruction(
537           MCInstBuilder(AArch64::B).addExpr(HwasanTagMismatchRef), *STI);
538     } else {
539       // Intentionally load the GOT entry and branch to it, rather than possibly
540       // late binding the function, which may clobber the registers before we
541       // have a chance to save them.
542       OutStreamer->emitInstruction(
543           MCInstBuilder(AArch64::ADRP)
544               .addReg(AArch64::X16)
545               .addExpr(AArch64MCExpr::create(
546                   HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_PAGE,
547                   OutContext)),
548           *STI);
549       OutStreamer->emitInstruction(
550           MCInstBuilder(AArch64::LDRXui)
551               .addReg(AArch64::X16)
552               .addReg(AArch64::X16)
553               .addExpr(AArch64MCExpr::create(
554                   HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_LO12,
555                   OutContext)),
556           *STI);
557       OutStreamer->emitInstruction(
558           MCInstBuilder(AArch64::BR).addReg(AArch64::X16), *STI);
559     }
560   }
561 }
562 
563 void AArch64AsmPrinter::emitEndOfAsmFile(Module &M) {
564   emitHwasanMemaccessSymbols(M);
565 
566   const Triple &TT = TM.getTargetTriple();
567   if (TT.isOSBinFormatMachO()) {
568     // Funny Darwin hack: This flag tells the linker that no global symbols
569     // contain code that falls through to other global symbols (e.g. the obvious
570     // implementation of multiple entry points).  If this doesn't occur, the
571     // linker can safely perform dead code stripping.  Since LLVM never
572     // generates code that does this, it is always safe to set.
573     OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
574   }
575 
576   // Emit stack and fault map information.
577   emitStackMaps(SM);
578   FM.serializeToFaultMapSection();
579 
580 }
581 
582 void AArch64AsmPrinter::emitLOHs() {
583   SmallVector<MCSymbol *, 3> MCArgs;
584 
585   for (const auto &D : AArch64FI->getLOHContainer()) {
586     for (const MachineInstr *MI : D.getArgs()) {
587       MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
588       assert(LabelIt != LOHInstToLabel.end() &&
589              "Label hasn't been inserted for LOH related instruction");
590       MCArgs.push_back(LabelIt->second);
591     }
592     OutStreamer->emitLOHDirective(D.getKind(), MCArgs);
593     MCArgs.clear();
594   }
595 }
596 
597 void AArch64AsmPrinter::emitFunctionBodyEnd() {
598   if (!AArch64FI->getLOHRelated().empty())
599     emitLOHs();
600 }
601 
602 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
603 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
604   // Darwin uses a linker-private symbol name for constant-pools (to
605   // avoid addends on the relocation?), ELF has no such concept and
606   // uses a normal private symbol.
607   if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty())
608     return OutContext.getOrCreateSymbol(
609         Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
610         Twine(getFunctionNumber()) + "_" + Twine(CPID));
611 
612   return AsmPrinter::GetCPISymbol(CPID);
613 }
614 
615 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
616                                      raw_ostream &O) {
617   const MachineOperand &MO = MI->getOperand(OpNum);
618   switch (MO.getType()) {
619   default:
620     llvm_unreachable("<unknown operand type>");
621   case MachineOperand::MO_Register: {
622     Register Reg = MO.getReg();
623     assert(Register::isPhysicalRegister(Reg));
624     assert(!MO.getSubReg() && "Subregs should be eliminated!");
625     O << AArch64InstPrinter::getRegisterName(Reg);
626     break;
627   }
628   case MachineOperand::MO_Immediate: {
629     O << MO.getImm();
630     break;
631   }
632   case MachineOperand::MO_GlobalAddress: {
633     PrintSymbolOperand(MO, O);
634     break;
635   }
636   case MachineOperand::MO_BlockAddress: {
637     MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
638     Sym->print(O, MAI);
639     break;
640   }
641   }
642 }
643 
644 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
645                                           raw_ostream &O) {
646   Register Reg = MO.getReg();
647   switch (Mode) {
648   default:
649     return true; // Unknown mode.
650   case 'w':
651     Reg = getWRegFromXReg(Reg);
652     break;
653   case 'x':
654     Reg = getXRegFromWReg(Reg);
655     break;
656   }
657 
658   O << AArch64InstPrinter::getRegisterName(Reg);
659   return false;
660 }
661 
662 // Prints the register in MO using class RC using the offset in the
663 // new register class. This should not be used for cross class
664 // printing.
665 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
666                                            const TargetRegisterClass *RC,
667                                            unsigned AltName, raw_ostream &O) {
668   assert(MO.isReg() && "Should only get here with a register!");
669   const TargetRegisterInfo *RI = STI->getRegisterInfo();
670   Register Reg = MO.getReg();
671   unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
672   if (!RI->regsOverlap(RegToPrint, Reg))
673     return true;
674   O << AArch64InstPrinter::getRegisterName(RegToPrint, AltName);
675   return false;
676 }
677 
678 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
679                                         const char *ExtraCode, raw_ostream &O) {
680   const MachineOperand &MO = MI->getOperand(OpNum);
681 
682   // First try the generic code, which knows about modifiers like 'c' and 'n'.
683   if (!AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O))
684     return false;
685 
686   // Does this asm operand have a single letter operand modifier?
687   if (ExtraCode && ExtraCode[0]) {
688     if (ExtraCode[1] != 0)
689       return true; // Unknown modifier.
690 
691     switch (ExtraCode[0]) {
692     default:
693       return true; // Unknown modifier.
694     case 'w':      // Print W register
695     case 'x':      // Print X register
696       if (MO.isReg())
697         return printAsmMRegister(MO, ExtraCode[0], O);
698       if (MO.isImm() && MO.getImm() == 0) {
699         unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
700         O << AArch64InstPrinter::getRegisterName(Reg);
701         return false;
702       }
703       printOperand(MI, OpNum, O);
704       return false;
705     case 'b': // Print B register.
706     case 'h': // Print H register.
707     case 's': // Print S register.
708     case 'd': // Print D register.
709     case 'q': // Print Q register.
710     case 'z': // Print Z register.
711       if (MO.isReg()) {
712         const TargetRegisterClass *RC;
713         switch (ExtraCode[0]) {
714         case 'b':
715           RC = &AArch64::FPR8RegClass;
716           break;
717         case 'h':
718           RC = &AArch64::FPR16RegClass;
719           break;
720         case 's':
721           RC = &AArch64::FPR32RegClass;
722           break;
723         case 'd':
724           RC = &AArch64::FPR64RegClass;
725           break;
726         case 'q':
727           RC = &AArch64::FPR128RegClass;
728           break;
729         case 'z':
730           RC = &AArch64::ZPRRegClass;
731           break;
732         default:
733           return true;
734         }
735         return printAsmRegInClass(MO, RC, AArch64::NoRegAltName, O);
736       }
737       printOperand(MI, OpNum, O);
738       return false;
739     }
740   }
741 
742   // According to ARM, we should emit x and v registers unless we have a
743   // modifier.
744   if (MO.isReg()) {
745     Register Reg = MO.getReg();
746 
747     // If this is a w or x register, print an x register.
748     if (AArch64::GPR32allRegClass.contains(Reg) ||
749         AArch64::GPR64allRegClass.contains(Reg))
750       return printAsmMRegister(MO, 'x', O);
751 
752     unsigned AltName = AArch64::NoRegAltName;
753     const TargetRegisterClass *RegClass;
754     if (AArch64::ZPRRegClass.contains(Reg)) {
755       RegClass = &AArch64::ZPRRegClass;
756     } else if (AArch64::PPRRegClass.contains(Reg)) {
757       RegClass = &AArch64::PPRRegClass;
758     } else {
759       RegClass = &AArch64::FPR128RegClass;
760       AltName = AArch64::vreg;
761     }
762 
763     // If this is a b, h, s, d, or q register, print it as a v register.
764     return printAsmRegInClass(MO, RegClass, AltName, O);
765   }
766 
767   printOperand(MI, OpNum, O);
768   return false;
769 }
770 
771 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
772                                               unsigned OpNum,
773                                               const char *ExtraCode,
774                                               raw_ostream &O) {
775   if (ExtraCode && ExtraCode[0] && ExtraCode[0] != 'a')
776     return true; // Unknown modifier.
777 
778   const MachineOperand &MO = MI->getOperand(OpNum);
779   assert(MO.isReg() && "unexpected inline asm memory operand");
780   O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
781   return false;
782 }
783 
784 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
785                                                raw_ostream &OS) {
786   unsigned NOps = MI->getNumOperands();
787   assert(NOps == 4);
788   OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
789   // cast away const; DIetc do not take const operands for some reason.
790   OS << MI->getDebugVariable()->getName();
791   OS << " <- ";
792   // Frame address.  Currently handles register +- offset only.
793   assert(MI->isIndirectDebugValue());
794   OS << '[';
795   for (unsigned I = 0, E = std::distance(MI->debug_operands().begin(),
796                                          MI->debug_operands().end());
797        I < E; ++I) {
798     if (I != 0)
799       OS << ", ";
800     printOperand(MI, I, OS);
801   }
802   OS << ']';
803   OS << "+";
804   printOperand(MI, NOps - 2, OS);
805 }
806 
807 void AArch64AsmPrinter::emitJumpTableInfo() {
808   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
809   if (!MJTI) return;
810 
811   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
812   if (JT.empty()) return;
813 
814   const Function &F = MF->getFunction();
815   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
816   bool JTInDiffSection =
817       !STI->isTargetCOFF() ||
818       !TLOF.shouldPutJumpTableInFunctionSection(
819           MJTI->getEntryKind() == MachineJumpTableInfo::EK_LabelDifference32,
820           F);
821   if (JTInDiffSection) {
822       // Drop it in the readonly section.
823       MCSection *ReadOnlySec = TLOF.getSectionForJumpTable(F, TM);
824       OutStreamer->SwitchSection(ReadOnlySec);
825   }
826 
827   auto AFI = MF->getInfo<AArch64FunctionInfo>();
828   for (unsigned JTI = 0, e = JT.size(); JTI != e; ++JTI) {
829     const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
830 
831     // If this jump table was deleted, ignore it.
832     if (JTBBs.empty()) continue;
833 
834     unsigned Size = AFI->getJumpTableEntrySize(JTI);
835     emitAlignment(Align(Size));
836     OutStreamer->emitLabel(GetJTISymbol(JTI));
837 
838     const MCSymbol *BaseSym = AArch64FI->getJumpTableEntryPCRelSymbol(JTI);
839     const MCExpr *Base = MCSymbolRefExpr::create(BaseSym, OutContext);
840 
841     for (auto *JTBB : JTBBs) {
842       const MCExpr *Value =
843           MCSymbolRefExpr::create(JTBB->getSymbol(), OutContext);
844 
845       // Each entry is:
846       //     .byte/.hword (LBB - Lbase)>>2
847       // or plain:
848       //     .word LBB - Lbase
849       Value = MCBinaryExpr::createSub(Value, Base, OutContext);
850       if (Size != 4)
851         Value = MCBinaryExpr::createLShr(
852             Value, MCConstantExpr::create(2, OutContext), OutContext);
853 
854       OutStreamer->emitValue(Value, Size);
855     }
856   }
857 }
858 
859 void AArch64AsmPrinter::emitFunctionEntryLabel() {
860   if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall ||
861       MF->getFunction().getCallingConv() ==
862           CallingConv::AArch64_SVE_VectorCall ||
863       STI->getRegisterInfo()->hasSVEArgsOrReturn(MF)) {
864     auto *TS =
865         static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
866     TS->emitDirectiveVariantPCS(CurrentFnSym);
867   }
868 
869   return AsmPrinter::emitFunctionEntryLabel();
870 }
871 
872 /// Small jump tables contain an unsigned byte or half, representing the offset
873 /// from the lowest-addressed possible destination to the desired basic
874 /// block. Since all instructions are 4-byte aligned, this is further compressed
875 /// by counting in instructions rather than bytes (i.e. divided by 4). So, to
876 /// materialize the correct destination we need:
877 ///
878 ///             adr xDest, .LBB0_0
879 ///             ldrb wScratch, [xTable, xEntry]   (with "lsl #1" for ldrh).
880 ///             add xDest, xDest, xScratch (with "lsl #2" for smaller entries)
881 void AArch64AsmPrinter::LowerJumpTableDest(llvm::MCStreamer &OutStreamer,
882                                            const llvm::MachineInstr &MI) {
883   Register DestReg = MI.getOperand(0).getReg();
884   Register ScratchReg = MI.getOperand(1).getReg();
885   Register ScratchRegW =
886       STI->getRegisterInfo()->getSubReg(ScratchReg, AArch64::sub_32);
887   Register TableReg = MI.getOperand(2).getReg();
888   Register EntryReg = MI.getOperand(3).getReg();
889   int JTIdx = MI.getOperand(4).getIndex();
890   int Size = AArch64FI->getJumpTableEntrySize(JTIdx);
891 
892   // This has to be first because the compression pass based its reachability
893   // calculations on the start of the JumpTableDest instruction.
894   auto Label =
895       MF->getInfo<AArch64FunctionInfo>()->getJumpTableEntryPCRelSymbol(JTIdx);
896 
897   // If we don't already have a symbol to use as the base, use the ADR
898   // instruction itself.
899   if (!Label) {
900     Label = MF->getContext().createTempSymbol();
901     AArch64FI->setJumpTableEntryInfo(JTIdx, Size, Label);
902     OutStreamer.emitLabel(Label);
903   }
904 
905   auto LabelExpr = MCSymbolRefExpr::create(Label, MF->getContext());
906   EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADR)
907                                   .addReg(DestReg)
908                                   .addExpr(LabelExpr));
909 
910   // Load the number of instruction-steps to offset from the label.
911   unsigned LdrOpcode;
912   switch (Size) {
913   case 1: LdrOpcode = AArch64::LDRBBroX; break;
914   case 2: LdrOpcode = AArch64::LDRHHroX; break;
915   case 4: LdrOpcode = AArch64::LDRSWroX; break;
916   default:
917     llvm_unreachable("Unknown jump table size");
918   }
919 
920   EmitToStreamer(OutStreamer, MCInstBuilder(LdrOpcode)
921                                   .addReg(Size == 4 ? ScratchReg : ScratchRegW)
922                                   .addReg(TableReg)
923                                   .addReg(EntryReg)
924                                   .addImm(0)
925                                   .addImm(Size == 1 ? 0 : 1));
926 
927   // Add to the already materialized base label address, multiplying by 4 if
928   // compressed.
929   EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADDXrs)
930                                   .addReg(DestReg)
931                                   .addReg(DestReg)
932                                   .addReg(ScratchReg)
933                                   .addImm(Size == 4 ? 0 : 2));
934 }
935 
936 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
937                                       const MachineInstr &MI) {
938   unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
939 
940   auto &Ctx = OutStreamer.getContext();
941   MCSymbol *MILabel = Ctx.createTempSymbol();
942   OutStreamer.emitLabel(MILabel);
943 
944   SM.recordStackMap(*MILabel, MI);
945   assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
946 
947   // Scan ahead to trim the shadow.
948   const MachineBasicBlock &MBB = *MI.getParent();
949   MachineBasicBlock::const_iterator MII(MI);
950   ++MII;
951   while (NumNOPBytes > 0) {
952     if (MII == MBB.end() || MII->isCall() ||
953         MII->getOpcode() == AArch64::DBG_VALUE ||
954         MII->getOpcode() == TargetOpcode::PATCHPOINT ||
955         MII->getOpcode() == TargetOpcode::STACKMAP)
956       break;
957     ++MII;
958     NumNOPBytes -= 4;
959   }
960 
961   // Emit nops.
962   for (unsigned i = 0; i < NumNOPBytes; i += 4)
963     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
964 }
965 
966 // Lower a patchpoint of the form:
967 // [<def>], <id>, <numBytes>, <target>, <numArgs>
968 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
969                                         const MachineInstr &MI) {
970   auto &Ctx = OutStreamer.getContext();
971   MCSymbol *MILabel = Ctx.createTempSymbol();
972   OutStreamer.emitLabel(MILabel);
973   SM.recordPatchPoint(*MILabel, MI);
974 
975   PatchPointOpers Opers(&MI);
976 
977   int64_t CallTarget = Opers.getCallTarget().getImm();
978   unsigned EncodedBytes = 0;
979   if (CallTarget) {
980     assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
981            "High 16 bits of call target should be zero.");
982     Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
983     EncodedBytes = 16;
984     // Materialize the jump address:
985     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
986                                     .addReg(ScratchReg)
987                                     .addImm((CallTarget >> 32) & 0xFFFF)
988                                     .addImm(32));
989     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
990                                     .addReg(ScratchReg)
991                                     .addReg(ScratchReg)
992                                     .addImm((CallTarget >> 16) & 0xFFFF)
993                                     .addImm(16));
994     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
995                                     .addReg(ScratchReg)
996                                     .addReg(ScratchReg)
997                                     .addImm(CallTarget & 0xFFFF)
998                                     .addImm(0));
999     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
1000   }
1001   // Emit padding.
1002   unsigned NumBytes = Opers.getNumPatchBytes();
1003   assert(NumBytes >= EncodedBytes &&
1004          "Patchpoint can't request size less than the length of a call.");
1005   assert((NumBytes - EncodedBytes) % 4 == 0 &&
1006          "Invalid number of NOP bytes requested!");
1007   for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
1008     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
1009 }
1010 
1011 void AArch64AsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
1012                                         const MachineInstr &MI) {
1013   StatepointOpers SOpers(&MI);
1014   if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
1015     assert(PatchBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
1016     for (unsigned i = 0; i < PatchBytes; i += 4)
1017       EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
1018   } else {
1019     // Lower call target and choose correct opcode
1020     const MachineOperand &CallTarget = SOpers.getCallTarget();
1021     MCOperand CallTargetMCOp;
1022     unsigned CallOpcode;
1023     switch (CallTarget.getType()) {
1024     case MachineOperand::MO_GlobalAddress:
1025     case MachineOperand::MO_ExternalSymbol:
1026       MCInstLowering.lowerOperand(CallTarget, CallTargetMCOp);
1027       CallOpcode = AArch64::BL;
1028       break;
1029     case MachineOperand::MO_Immediate:
1030       CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
1031       CallOpcode = AArch64::BL;
1032       break;
1033     case MachineOperand::MO_Register:
1034       CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
1035       CallOpcode = AArch64::BLR;
1036       break;
1037     default:
1038       llvm_unreachable("Unsupported operand type in statepoint call target");
1039       break;
1040     }
1041 
1042     EmitToStreamer(OutStreamer,
1043                    MCInstBuilder(CallOpcode).addOperand(CallTargetMCOp));
1044   }
1045 
1046   auto &Ctx = OutStreamer.getContext();
1047   MCSymbol *MILabel = Ctx.createTempSymbol();
1048   OutStreamer.emitLabel(MILabel);
1049   SM.recordStatepoint(*MILabel, MI);
1050 }
1051 
1052 void AArch64AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI) {
1053   // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
1054   //                  <opcode>, <operands>
1055 
1056   Register DefRegister = FaultingMI.getOperand(0).getReg();
1057   FaultMaps::FaultKind FK =
1058       static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
1059   MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
1060   unsigned Opcode = FaultingMI.getOperand(3).getImm();
1061   unsigned OperandsBeginIdx = 4;
1062 
1063   auto &Ctx = OutStreamer->getContext();
1064   MCSymbol *FaultingLabel = Ctx.createTempSymbol();
1065   OutStreamer->emitLabel(FaultingLabel);
1066 
1067   assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
1068   FM.recordFaultingOp(FK, FaultingLabel, HandlerLabel);
1069 
1070   MCInst MI;
1071   MI.setOpcode(Opcode);
1072 
1073   if (DefRegister != (Register)0)
1074     MI.addOperand(MCOperand::createReg(DefRegister));
1075 
1076   for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
1077             E = FaultingMI.operands_end();
1078        I != E; ++I) {
1079     MCOperand Dest;
1080     lowerOperand(*I, Dest);
1081     MI.addOperand(Dest);
1082   }
1083 
1084   OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
1085   OutStreamer->emitInstruction(MI, getSubtargetInfo());
1086 }
1087 
1088 void AArch64AsmPrinter::emitFMov0(const MachineInstr &MI) {
1089   Register DestReg = MI.getOperand(0).getReg();
1090   if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround()) {
1091     // Convert H/S register to corresponding D register
1092     if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
1093       DestReg = AArch64::D0 + (DestReg - AArch64::H0);
1094     else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
1095       DestReg = AArch64::D0 + (DestReg - AArch64::S0);
1096     else
1097       assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
1098 
1099     MCInst MOVI;
1100     MOVI.setOpcode(AArch64::MOVID);
1101     MOVI.addOperand(MCOperand::createReg(DestReg));
1102     MOVI.addOperand(MCOperand::createImm(0));
1103     EmitToStreamer(*OutStreamer, MOVI);
1104   } else {
1105     MCInst FMov;
1106     switch (MI.getOpcode()) {
1107     default: llvm_unreachable("Unexpected opcode");
1108     case AArch64::FMOVH0:
1109       FMov.setOpcode(AArch64::FMOVWHr);
1110       FMov.addOperand(MCOperand::createReg(DestReg));
1111       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
1112       break;
1113     case AArch64::FMOVS0:
1114       FMov.setOpcode(AArch64::FMOVWSr);
1115       FMov.addOperand(MCOperand::createReg(DestReg));
1116       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
1117       break;
1118     case AArch64::FMOVD0:
1119       FMov.setOpcode(AArch64::FMOVXDr);
1120       FMov.addOperand(MCOperand::createReg(DestReg));
1121       FMov.addOperand(MCOperand::createReg(AArch64::XZR));
1122       break;
1123     }
1124     EmitToStreamer(*OutStreamer, FMov);
1125   }
1126 }
1127 
1128 // Simple pseudo-instructions have their lowering (with expansion to real
1129 // instructions) auto-generated.
1130 #include "AArch64GenMCPseudoLowering.inc"
1131 
1132 void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
1133   // Do any auto-generated pseudo lowerings.
1134   if (emitPseudoExpansionLowering(*OutStreamer, MI))
1135     return;
1136 
1137   if (AArch64FI->getLOHRelated().count(MI)) {
1138     // Generate a label for LOH related instruction
1139     MCSymbol *LOHLabel = createTempSymbol("loh");
1140     // Associate the instruction with the label
1141     LOHInstToLabel[MI] = LOHLabel;
1142     OutStreamer->emitLabel(LOHLabel);
1143   }
1144 
1145   AArch64TargetStreamer *TS =
1146     static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
1147   // Do any manual lowerings.
1148   switch (MI->getOpcode()) {
1149   default:
1150     break;
1151   case AArch64::HINT: {
1152     // CurrentPatchableFunctionEntrySym can be CurrentFnBegin only for
1153     // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be
1154     // non-empty. If MI is the initial BTI, place the
1155     // __patchable_function_entries label after BTI.
1156     if (CurrentPatchableFunctionEntrySym &&
1157         CurrentPatchableFunctionEntrySym == CurrentFnBegin &&
1158         MI == &MF->front().front()) {
1159       int64_t Imm = MI->getOperand(0).getImm();
1160       if ((Imm & 32) && (Imm & 6)) {
1161         MCInst Inst;
1162         MCInstLowering.Lower(MI, Inst);
1163         EmitToStreamer(*OutStreamer, Inst);
1164         CurrentPatchableFunctionEntrySym = createTempSymbol("patch");
1165         OutStreamer->emitLabel(CurrentPatchableFunctionEntrySym);
1166         return;
1167       }
1168     }
1169     break;
1170   }
1171     case AArch64::MOVMCSym: {
1172       Register DestReg = MI->getOperand(0).getReg();
1173       const MachineOperand &MO_Sym = MI->getOperand(1);
1174       MachineOperand Hi_MOSym(MO_Sym), Lo_MOSym(MO_Sym);
1175       MCOperand Hi_MCSym, Lo_MCSym;
1176 
1177       Hi_MOSym.setTargetFlags(AArch64II::MO_G1 | AArch64II::MO_S);
1178       Lo_MOSym.setTargetFlags(AArch64II::MO_G0 | AArch64II::MO_NC);
1179 
1180       MCInstLowering.lowerOperand(Hi_MOSym, Hi_MCSym);
1181       MCInstLowering.lowerOperand(Lo_MOSym, Lo_MCSym);
1182 
1183       MCInst MovZ;
1184       MovZ.setOpcode(AArch64::MOVZXi);
1185       MovZ.addOperand(MCOperand::createReg(DestReg));
1186       MovZ.addOperand(Hi_MCSym);
1187       MovZ.addOperand(MCOperand::createImm(16));
1188       EmitToStreamer(*OutStreamer, MovZ);
1189 
1190       MCInst MovK;
1191       MovK.setOpcode(AArch64::MOVKXi);
1192       MovK.addOperand(MCOperand::createReg(DestReg));
1193       MovK.addOperand(MCOperand::createReg(DestReg));
1194       MovK.addOperand(Lo_MCSym);
1195       MovK.addOperand(MCOperand::createImm(0));
1196       EmitToStreamer(*OutStreamer, MovK);
1197       return;
1198   }
1199   case AArch64::MOVIv2d_ns:
1200     // If the target has <rdar://problem/16473581>, lower this
1201     // instruction to movi.16b instead.
1202     if (STI->hasZeroCycleZeroingFPWorkaround() &&
1203         MI->getOperand(1).getImm() == 0) {
1204       MCInst TmpInst;
1205       TmpInst.setOpcode(AArch64::MOVIv16b_ns);
1206       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1207       TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
1208       EmitToStreamer(*OutStreamer, TmpInst);
1209       return;
1210     }
1211     break;
1212 
1213   case AArch64::DBG_VALUE:
1214   case AArch64::DBG_VALUE_LIST: {
1215     if (isVerbose() && OutStreamer->hasRawTextSupport()) {
1216       SmallString<128> TmpStr;
1217       raw_svector_ostream OS(TmpStr);
1218       PrintDebugValueComment(MI, OS);
1219       OutStreamer->emitRawText(StringRef(OS.str()));
1220     }
1221     return;
1222 
1223   case AArch64::EMITBKEY: {
1224       ExceptionHandling ExceptionHandlingType = MAI->getExceptionHandlingType();
1225       if (ExceptionHandlingType != ExceptionHandling::DwarfCFI &&
1226           ExceptionHandlingType != ExceptionHandling::ARM)
1227         return;
1228 
1229       if (getFunctionCFISectionType(*MF) == CFISection::None)
1230         return;
1231 
1232       OutStreamer->emitCFIBKeyFrame();
1233       return;
1234     }
1235     }
1236 
1237   // Tail calls use pseudo instructions so they have the proper code-gen
1238   // attributes (isCall, isReturn, etc.). We lower them to the real
1239   // instruction here.
1240   case AArch64::TCRETURNri:
1241   case AArch64::TCRETURNriBTI:
1242   case AArch64::TCRETURNriALL: {
1243     MCInst TmpInst;
1244     TmpInst.setOpcode(AArch64::BR);
1245     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1246     EmitToStreamer(*OutStreamer, TmpInst);
1247     return;
1248   }
1249   case AArch64::TCRETURNdi: {
1250     MCOperand Dest;
1251     MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
1252     MCInst TmpInst;
1253     TmpInst.setOpcode(AArch64::B);
1254     TmpInst.addOperand(Dest);
1255     EmitToStreamer(*OutStreamer, TmpInst);
1256     return;
1257   }
1258   case AArch64::SpeculationBarrierISBDSBEndBB: {
1259     // Print DSB SYS + ISB
1260     MCInst TmpInstDSB;
1261     TmpInstDSB.setOpcode(AArch64::DSB);
1262     TmpInstDSB.addOperand(MCOperand::createImm(0xf));
1263     EmitToStreamer(*OutStreamer, TmpInstDSB);
1264     MCInst TmpInstISB;
1265     TmpInstISB.setOpcode(AArch64::ISB);
1266     TmpInstISB.addOperand(MCOperand::createImm(0xf));
1267     EmitToStreamer(*OutStreamer, TmpInstISB);
1268     return;
1269   }
1270   case AArch64::SpeculationBarrierSBEndBB: {
1271     // Print SB
1272     MCInst TmpInstSB;
1273     TmpInstSB.setOpcode(AArch64::SB);
1274     EmitToStreamer(*OutStreamer, TmpInstSB);
1275     return;
1276   }
1277   case AArch64::TLSDESC_CALLSEQ: {
1278     /// lower this to:
1279     ///    adrp  x0, :tlsdesc:var
1280     ///    ldr   x1, [x0, #:tlsdesc_lo12:var]
1281     ///    add   x0, x0, #:tlsdesc_lo12:var
1282     ///    .tlsdesccall var
1283     ///    blr   x1
1284     ///    (TPIDR_EL0 offset now in x0)
1285     const MachineOperand &MO_Sym = MI->getOperand(0);
1286     MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
1287     MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
1288     MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
1289     MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
1290     MCInstLowering.lowerOperand(MO_Sym, Sym);
1291     MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
1292     MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
1293 
1294     MCInst Adrp;
1295     Adrp.setOpcode(AArch64::ADRP);
1296     Adrp.addOperand(MCOperand::createReg(AArch64::X0));
1297     Adrp.addOperand(SymTLSDesc);
1298     EmitToStreamer(*OutStreamer, Adrp);
1299 
1300     MCInst Ldr;
1301     if (STI->isTargetILP32()) {
1302       Ldr.setOpcode(AArch64::LDRWui);
1303       Ldr.addOperand(MCOperand::createReg(AArch64::W1));
1304     } else {
1305       Ldr.setOpcode(AArch64::LDRXui);
1306       Ldr.addOperand(MCOperand::createReg(AArch64::X1));
1307     }
1308     Ldr.addOperand(MCOperand::createReg(AArch64::X0));
1309     Ldr.addOperand(SymTLSDescLo12);
1310     Ldr.addOperand(MCOperand::createImm(0));
1311     EmitToStreamer(*OutStreamer, Ldr);
1312 
1313     MCInst Add;
1314     if (STI->isTargetILP32()) {
1315       Add.setOpcode(AArch64::ADDWri);
1316       Add.addOperand(MCOperand::createReg(AArch64::W0));
1317       Add.addOperand(MCOperand::createReg(AArch64::W0));
1318     } else {
1319       Add.setOpcode(AArch64::ADDXri);
1320       Add.addOperand(MCOperand::createReg(AArch64::X0));
1321       Add.addOperand(MCOperand::createReg(AArch64::X0));
1322     }
1323     Add.addOperand(SymTLSDescLo12);
1324     Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
1325     EmitToStreamer(*OutStreamer, Add);
1326 
1327     // Emit a relocation-annotation. This expands to no code, but requests
1328     // the following instruction gets an R_AARCH64_TLSDESC_CALL.
1329     MCInst TLSDescCall;
1330     TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
1331     TLSDescCall.addOperand(Sym);
1332     EmitToStreamer(*OutStreamer, TLSDescCall);
1333 
1334     MCInst Blr;
1335     Blr.setOpcode(AArch64::BLR);
1336     Blr.addOperand(MCOperand::createReg(AArch64::X1));
1337     EmitToStreamer(*OutStreamer, Blr);
1338 
1339     return;
1340   }
1341 
1342   case AArch64::JumpTableDest32:
1343   case AArch64::JumpTableDest16:
1344   case AArch64::JumpTableDest8:
1345     LowerJumpTableDest(*OutStreamer, *MI);
1346     return;
1347 
1348   case AArch64::FMOVH0:
1349   case AArch64::FMOVS0:
1350   case AArch64::FMOVD0:
1351     emitFMov0(*MI);
1352     return;
1353 
1354   case TargetOpcode::STACKMAP:
1355     return LowerSTACKMAP(*OutStreamer, SM, *MI);
1356 
1357   case TargetOpcode::PATCHPOINT:
1358     return LowerPATCHPOINT(*OutStreamer, SM, *MI);
1359 
1360   case TargetOpcode::STATEPOINT:
1361     return LowerSTATEPOINT(*OutStreamer, SM, *MI);
1362 
1363   case TargetOpcode::FAULTING_OP:
1364     return LowerFAULTING_OP(*MI);
1365 
1366   case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1367     LowerPATCHABLE_FUNCTION_ENTER(*MI);
1368     return;
1369 
1370   case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
1371     LowerPATCHABLE_FUNCTION_EXIT(*MI);
1372     return;
1373 
1374   case TargetOpcode::PATCHABLE_TAIL_CALL:
1375     LowerPATCHABLE_TAIL_CALL(*MI);
1376     return;
1377 
1378   case AArch64::HWASAN_CHECK_MEMACCESS:
1379   case AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
1380     LowerHWASAN_CHECK_MEMACCESS(*MI);
1381     return;
1382 
1383   case AArch64::SEH_StackAlloc:
1384     TS->emitARM64WinCFIAllocStack(MI->getOperand(0).getImm());
1385     return;
1386 
1387   case AArch64::SEH_SaveFPLR:
1388     TS->emitARM64WinCFISaveFPLR(MI->getOperand(0).getImm());
1389     return;
1390 
1391   case AArch64::SEH_SaveFPLR_X:
1392     assert(MI->getOperand(0).getImm() < 0 &&
1393            "Pre increment SEH opcode must have a negative offset");
1394     TS->emitARM64WinCFISaveFPLRX(-MI->getOperand(0).getImm());
1395     return;
1396 
1397   case AArch64::SEH_SaveReg:
1398     TS->emitARM64WinCFISaveReg(MI->getOperand(0).getImm(),
1399                                MI->getOperand(1).getImm());
1400     return;
1401 
1402   case AArch64::SEH_SaveReg_X:
1403     assert(MI->getOperand(1).getImm() < 0 &&
1404            "Pre increment SEH opcode must have a negative offset");
1405     TS->emitARM64WinCFISaveRegX(MI->getOperand(0).getImm(),
1406                                 -MI->getOperand(1).getImm());
1407     return;
1408 
1409   case AArch64::SEH_SaveRegP:
1410     if (MI->getOperand(1).getImm() == 30 && MI->getOperand(0).getImm() >= 19 &&
1411         MI->getOperand(0).getImm() <= 28) {
1412       assert((MI->getOperand(0).getImm() - 19) % 2 == 0 &&
1413              "Register paired with LR must be odd");
1414       TS->emitARM64WinCFISaveLRPair(MI->getOperand(0).getImm(),
1415                                     MI->getOperand(2).getImm());
1416       return;
1417     }
1418     assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1419             "Non-consecutive registers not allowed for save_regp");
1420     TS->emitARM64WinCFISaveRegP(MI->getOperand(0).getImm(),
1421                                 MI->getOperand(2).getImm());
1422     return;
1423 
1424   case AArch64::SEH_SaveRegP_X:
1425     assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1426             "Non-consecutive registers not allowed for save_regp_x");
1427     assert(MI->getOperand(2).getImm() < 0 &&
1428            "Pre increment SEH opcode must have a negative offset");
1429     TS->emitARM64WinCFISaveRegPX(MI->getOperand(0).getImm(),
1430                                  -MI->getOperand(2).getImm());
1431     return;
1432 
1433   case AArch64::SEH_SaveFReg:
1434     TS->emitARM64WinCFISaveFReg(MI->getOperand(0).getImm(),
1435                                 MI->getOperand(1).getImm());
1436     return;
1437 
1438   case AArch64::SEH_SaveFReg_X:
1439     assert(MI->getOperand(1).getImm() < 0 &&
1440            "Pre increment SEH opcode must have a negative offset");
1441     TS->emitARM64WinCFISaveFRegX(MI->getOperand(0).getImm(),
1442                                  -MI->getOperand(1).getImm());
1443     return;
1444 
1445   case AArch64::SEH_SaveFRegP:
1446     assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1447             "Non-consecutive registers not allowed for save_regp");
1448     TS->emitARM64WinCFISaveFRegP(MI->getOperand(0).getImm(),
1449                                  MI->getOperand(2).getImm());
1450     return;
1451 
1452   case AArch64::SEH_SaveFRegP_X:
1453     assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1454             "Non-consecutive registers not allowed for save_regp_x");
1455     assert(MI->getOperand(2).getImm() < 0 &&
1456            "Pre increment SEH opcode must have a negative offset");
1457     TS->emitARM64WinCFISaveFRegPX(MI->getOperand(0).getImm(),
1458                                   -MI->getOperand(2).getImm());
1459     return;
1460 
1461   case AArch64::SEH_SetFP:
1462     TS->emitARM64WinCFISetFP();
1463     return;
1464 
1465   case AArch64::SEH_AddFP:
1466     TS->emitARM64WinCFIAddFP(MI->getOperand(0).getImm());
1467     return;
1468 
1469   case AArch64::SEH_Nop:
1470     TS->emitARM64WinCFINop();
1471     return;
1472 
1473   case AArch64::SEH_PrologEnd:
1474     TS->emitARM64WinCFIPrologEnd();
1475     return;
1476 
1477   case AArch64::SEH_EpilogStart:
1478     TS->emitARM64WinCFIEpilogStart();
1479     return;
1480 
1481   case AArch64::SEH_EpilogEnd:
1482     TS->emitARM64WinCFIEpilogEnd();
1483     return;
1484   }
1485 
1486   // Finally, do the automated lowerings for everything else.
1487   MCInst TmpInst;
1488   MCInstLowering.Lower(MI, TmpInst);
1489   EmitToStreamer(*OutStreamer, TmpInst);
1490 }
1491 
1492 // Force static initialization.
1493 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64AsmPrinter() {
1494   RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget());
1495   RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget());
1496   RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target());
1497   RegisterAsmPrinter<AArch64AsmPrinter> W(getTheARM64_32Target());
1498   RegisterAsmPrinter<AArch64AsmPrinter> V(getTheAArch64_32Target());
1499 }
1500