1 //===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains a printer that converts from our internal representation 11 // of machine-dependent LLVM code to the AArch64 assembly language. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MCTargetDesc/AArch64AddressingModes.h" 16 #include "AArch64.h" 17 #include "AArch64MCInstLower.h" 18 #include "AArch64MachineFunctionInfo.h" 19 #include "AArch64RegisterInfo.h" 20 #include "AArch64Subtarget.h" 21 #include "InstPrinter/AArch64InstPrinter.h" 22 #include "MCTargetDesc/AArch64MCExpr.h" 23 #include "llvm/ADT/SmallString.h" 24 #include "llvm/ADT/StringSwitch.h" 25 #include "llvm/ADT/Twine.h" 26 #include "llvm/CodeGen/AsmPrinter.h" 27 #include "llvm/CodeGen/MachineInstr.h" 28 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 29 #include "llvm/CodeGen/StackMaps.h" 30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 31 #include "llvm/IR/DataLayout.h" 32 #include "llvm/IR/DebugInfo.h" 33 #include "llvm/MC/MCAsmInfo.h" 34 #include "llvm/MC/MCContext.h" 35 #include "llvm/MC/MCInst.h" 36 #include "llvm/MC/MCInstBuilder.h" 37 #include "llvm/MC/MCLinkerOptimizationHint.h" 38 #include "llvm/MC/MCStreamer.h" 39 #include "llvm/MC/MCSymbol.h" 40 #include "llvm/MC/MCSymbolELF.h" 41 #include "llvm/MC/MCSectionELF.h" 42 #include "llvm/MC/MCSectionMachO.h" 43 #include "llvm/Support/Debug.h" 44 #include "llvm/Support/TargetRegistry.h" 45 #include "llvm/Support/raw_ostream.h" 46 using namespace llvm; 47 48 #define DEBUG_TYPE "asm-printer" 49 50 namespace { 51 52 class AArch64AsmPrinter : public AsmPrinter { 53 AArch64MCInstLower MCInstLowering; 54 StackMaps SM; 55 const AArch64Subtarget *STI; 56 57 public: 58 AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer) 59 : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this), 60 SM(*this), AArch64FI(nullptr) {} 61 62 StringRef getPassName() const override { return "AArch64 Assembly Printer"; } 63 64 /// \brief Wrapper for MCInstLowering.lowerOperand() for the 65 /// tblgen'erated pseudo lowering. 66 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const { 67 return MCInstLowering.lowerOperand(MO, MCOp); 68 } 69 70 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, 71 const MachineInstr &MI); 72 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, 73 const MachineInstr &MI); 74 75 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI); 76 void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI); 77 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI); 78 79 void EmitSled(const MachineInstr &MI, SledKind Kind); 80 81 /// \brief tblgen'erated driver function for lowering simple MI->MC 82 /// pseudo instructions. 83 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, 84 const MachineInstr *MI); 85 86 void EmitInstruction(const MachineInstr *MI) override; 87 88 void getAnalysisUsage(AnalysisUsage &AU) const override { 89 AsmPrinter::getAnalysisUsage(AU); 90 AU.setPreservesAll(); 91 } 92 93 bool runOnMachineFunction(MachineFunction &F) override { 94 AArch64FI = F.getInfo<AArch64FunctionInfo>(); 95 STI = static_cast<const AArch64Subtarget*>(&F.getSubtarget()); 96 bool Result = AsmPrinter::runOnMachineFunction(F); 97 emitXRayTable(); 98 return Result; 99 } 100 101 private: 102 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O); 103 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O); 104 bool printAsmRegInClass(const MachineOperand &MO, 105 const TargetRegisterClass *RC, bool isVector, 106 raw_ostream &O); 107 108 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 109 unsigned AsmVariant, const char *ExtraCode, 110 raw_ostream &O) override; 111 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, 112 unsigned AsmVariant, const char *ExtraCode, 113 raw_ostream &O) override; 114 115 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); 116 117 void EmitFunctionBodyEnd() override; 118 119 MCSymbol *GetCPISymbol(unsigned CPID) const override; 120 void EmitEndOfAsmFile(Module &M) override; 121 AArch64FunctionInfo *AArch64FI; 122 123 /// \brief Emit the LOHs contained in AArch64FI. 124 void EmitLOHs(); 125 126 /// Emit instruction to set float register to zero. 127 void EmitFMov0(const MachineInstr &MI); 128 129 typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol; 130 MInstToMCSymbol LOHInstToLabel; 131 }; 132 133 } // end of anonymous namespace 134 135 //===----------------------------------------------------------------------===// 136 137 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) 138 { 139 EmitSled(MI, SledKind::FUNCTION_ENTER); 140 } 141 142 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) 143 { 144 EmitSled(MI, SledKind::FUNCTION_EXIT); 145 } 146 147 void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) 148 { 149 EmitSled(MI, SledKind::TAIL_CALL); 150 } 151 152 void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) 153 { 154 static const int8_t NoopsInSledCount = 7; 155 // We want to emit the following pattern: 156 // 157 // .Lxray_sled_N: 158 // ALIGN 159 // B #32 160 // ; 7 NOP instructions (28 bytes) 161 // .tmpN 162 // 163 // We need the 28 bytes (7 instructions) because at runtime, we'd be patching 164 // over the full 32 bytes (8 instructions) with the following pattern: 165 // 166 // STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack 167 // LDR W0, #12 ; W0 := function ID 168 // LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit 169 // BLR X16 ; call the tracing trampoline 170 // ;DATA: 32 bits of function ID 171 // ;DATA: lower 32 bits of the address of the trampoline 172 // ;DATA: higher 32 bits of the address of the trampoline 173 // LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack 174 // 175 OutStreamer->EmitCodeAlignment(4); 176 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 177 OutStreamer->EmitLabel(CurSled); 178 auto Target = OutContext.createTempSymbol(); 179 180 // Emit "B #32" instruction, which jumps over the next 28 bytes. 181 // The operand has to be the number of 4-byte instructions to jump over, 182 // including the current instruction. 183 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8)); 184 185 for (int8_t I = 0; I < NoopsInSledCount; I++) 186 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); 187 188 OutStreamer->EmitLabel(Target); 189 recordSled(CurSled, MI, Kind); 190 } 191 192 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) { 193 const Triple &TT = TM.getTargetTriple(); 194 if (TT.isOSBinFormatMachO()) { 195 // Funny Darwin hack: This flag tells the linker that no global symbols 196 // contain code that falls through to other global symbols (e.g. the obvious 197 // implementation of multiple entry points). If this doesn't occur, the 198 // linker can safely perform dead code stripping. Since LLVM never 199 // generates code that does this, it is always safe to set. 200 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); 201 SM.serializeToStackMapSection(); 202 } 203 } 204 205 void AArch64AsmPrinter::EmitLOHs() { 206 SmallVector<MCSymbol *, 3> MCArgs; 207 208 for (const auto &D : AArch64FI->getLOHContainer()) { 209 for (const MachineInstr *MI : D.getArgs()) { 210 MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI); 211 assert(LabelIt != LOHInstToLabel.end() && 212 "Label hasn't been inserted for LOH related instruction"); 213 MCArgs.push_back(LabelIt->second); 214 } 215 OutStreamer->EmitLOHDirective(D.getKind(), MCArgs); 216 MCArgs.clear(); 217 } 218 } 219 220 void AArch64AsmPrinter::EmitFunctionBodyEnd() { 221 if (!AArch64FI->getLOHRelated().empty()) 222 EmitLOHs(); 223 } 224 225 /// GetCPISymbol - Return the symbol for the specified constant pool entry. 226 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const { 227 // Darwin uses a linker-private symbol name for constant-pools (to 228 // avoid addends on the relocation?), ELF has no such concept and 229 // uses a normal private symbol. 230 if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty()) 231 return OutContext.getOrCreateSymbol( 232 Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" + 233 Twine(getFunctionNumber()) + "_" + Twine(CPID)); 234 235 return OutContext.getOrCreateSymbol( 236 Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" + 237 Twine(getFunctionNumber()) + "_" + Twine(CPID)); 238 } 239 240 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum, 241 raw_ostream &O) { 242 const MachineOperand &MO = MI->getOperand(OpNum); 243 switch (MO.getType()) { 244 default: 245 llvm_unreachable("<unknown operand type>"); 246 case MachineOperand::MO_Register: { 247 unsigned Reg = MO.getReg(); 248 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 249 assert(!MO.getSubReg() && "Subregs should be eliminated!"); 250 O << AArch64InstPrinter::getRegisterName(Reg); 251 break; 252 } 253 case MachineOperand::MO_Immediate: { 254 int64_t Imm = MO.getImm(); 255 O << '#' << Imm; 256 break; 257 } 258 case MachineOperand::MO_GlobalAddress: { 259 const GlobalValue *GV = MO.getGlobal(); 260 MCSymbol *Sym = getSymbol(GV); 261 262 // FIXME: Can we get anything other than a plain symbol here? 263 assert(!MO.getTargetFlags() && "Unknown operand target flag!"); 264 265 Sym->print(O, MAI); 266 printOffset(MO.getOffset(), O); 267 break; 268 } 269 } 270 } 271 272 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode, 273 raw_ostream &O) { 274 unsigned Reg = MO.getReg(); 275 switch (Mode) { 276 default: 277 return true; // Unknown mode. 278 case 'w': 279 Reg = getWRegFromXReg(Reg); 280 break; 281 case 'x': 282 Reg = getXRegFromWReg(Reg); 283 break; 284 } 285 286 O << AArch64InstPrinter::getRegisterName(Reg); 287 return false; 288 } 289 290 // Prints the register in MO using class RC using the offset in the 291 // new register class. This should not be used for cross class 292 // printing. 293 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO, 294 const TargetRegisterClass *RC, 295 bool isVector, raw_ostream &O) { 296 assert(MO.isReg() && "Should only get here with a register!"); 297 const TargetRegisterInfo *RI = STI->getRegisterInfo(); 298 unsigned Reg = MO.getReg(); 299 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg)); 300 assert(RI->regsOverlap(RegToPrint, Reg)); 301 O << AArch64InstPrinter::getRegisterName( 302 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName); 303 return false; 304 } 305 306 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 307 unsigned AsmVariant, 308 const char *ExtraCode, raw_ostream &O) { 309 const MachineOperand &MO = MI->getOperand(OpNum); 310 311 // First try the generic code, which knows about modifiers like 'c' and 'n'. 312 if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O)) 313 return false; 314 315 // Does this asm operand have a single letter operand modifier? 316 if (ExtraCode && ExtraCode[0]) { 317 if (ExtraCode[1] != 0) 318 return true; // Unknown modifier. 319 320 switch (ExtraCode[0]) { 321 default: 322 return true; // Unknown modifier. 323 case 'w': // Print W register 324 case 'x': // Print X register 325 if (MO.isReg()) 326 return printAsmMRegister(MO, ExtraCode[0], O); 327 if (MO.isImm() && MO.getImm() == 0) { 328 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR; 329 O << AArch64InstPrinter::getRegisterName(Reg); 330 return false; 331 } 332 printOperand(MI, OpNum, O); 333 return false; 334 case 'b': // Print B register. 335 case 'h': // Print H register. 336 case 's': // Print S register. 337 case 'd': // Print D register. 338 case 'q': // Print Q register. 339 if (MO.isReg()) { 340 const TargetRegisterClass *RC; 341 switch (ExtraCode[0]) { 342 case 'b': 343 RC = &AArch64::FPR8RegClass; 344 break; 345 case 'h': 346 RC = &AArch64::FPR16RegClass; 347 break; 348 case 's': 349 RC = &AArch64::FPR32RegClass; 350 break; 351 case 'd': 352 RC = &AArch64::FPR64RegClass; 353 break; 354 case 'q': 355 RC = &AArch64::FPR128RegClass; 356 break; 357 default: 358 return true; 359 } 360 return printAsmRegInClass(MO, RC, false /* vector */, O); 361 } 362 printOperand(MI, OpNum, O); 363 return false; 364 } 365 } 366 367 // According to ARM, we should emit x and v registers unless we have a 368 // modifier. 369 if (MO.isReg()) { 370 unsigned Reg = MO.getReg(); 371 372 // If this is a w or x register, print an x register. 373 if (AArch64::GPR32allRegClass.contains(Reg) || 374 AArch64::GPR64allRegClass.contains(Reg)) 375 return printAsmMRegister(MO, 'x', O); 376 377 // If this is a b, h, s, d, or q register, print it as a v register. 378 return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */, 379 O); 380 } 381 382 printOperand(MI, OpNum, O); 383 return false; 384 } 385 386 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 387 unsigned OpNum, 388 unsigned AsmVariant, 389 const char *ExtraCode, 390 raw_ostream &O) { 391 if (ExtraCode && ExtraCode[0]) 392 return true; // Unknown modifier. 393 394 const MachineOperand &MO = MI->getOperand(OpNum); 395 assert(MO.isReg() && "unexpected inline asm memory operand"); 396 O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]"; 397 return false; 398 } 399 400 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI, 401 raw_ostream &OS) { 402 unsigned NOps = MI->getNumOperands(); 403 assert(NOps == 4); 404 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: "; 405 // cast away const; DIetc do not take const operands for some reason. 406 OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata()) 407 ->getName(); 408 OS << " <- "; 409 // Frame address. Currently handles register +- offset only. 410 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); 411 OS << '['; 412 printOperand(MI, 0, OS); 413 OS << '+'; 414 printOperand(MI, 1, OS); 415 OS << ']'; 416 OS << "+"; 417 printOperand(MI, NOps - 2, OS); 418 } 419 420 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, 421 const MachineInstr &MI) { 422 unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes(); 423 424 SM.recordStackMap(MI); 425 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!"); 426 427 // Scan ahead to trim the shadow. 428 const MachineBasicBlock &MBB = *MI.getParent(); 429 MachineBasicBlock::const_iterator MII(MI); 430 ++MII; 431 while (NumNOPBytes > 0) { 432 if (MII == MBB.end() || MII->isCall() || 433 MII->getOpcode() == AArch64::DBG_VALUE || 434 MII->getOpcode() == TargetOpcode::PATCHPOINT || 435 MII->getOpcode() == TargetOpcode::STACKMAP) 436 break; 437 ++MII; 438 NumNOPBytes -= 4; 439 } 440 441 // Emit nops. 442 for (unsigned i = 0; i < NumNOPBytes; i += 4) 443 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); 444 } 445 446 // Lower a patchpoint of the form: 447 // [<def>], <id>, <numBytes>, <target>, <numArgs> 448 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, 449 const MachineInstr &MI) { 450 SM.recordPatchPoint(MI); 451 452 PatchPointOpers Opers(&MI); 453 454 int64_t CallTarget = Opers.getCallTarget().getImm(); 455 unsigned EncodedBytes = 0; 456 if (CallTarget) { 457 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget && 458 "High 16 bits of call target should be zero."); 459 unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg(); 460 EncodedBytes = 16; 461 // Materialize the jump address: 462 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi) 463 .addReg(ScratchReg) 464 .addImm((CallTarget >> 32) & 0xFFFF) 465 .addImm(32)); 466 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi) 467 .addReg(ScratchReg) 468 .addReg(ScratchReg) 469 .addImm((CallTarget >> 16) & 0xFFFF) 470 .addImm(16)); 471 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi) 472 .addReg(ScratchReg) 473 .addReg(ScratchReg) 474 .addImm(CallTarget & 0xFFFF) 475 .addImm(0)); 476 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); 477 } 478 // Emit padding. 479 unsigned NumBytes = Opers.getNumPatchBytes(); 480 assert(NumBytes >= EncodedBytes && 481 "Patchpoint can't request size less than the length of a call."); 482 assert((NumBytes - EncodedBytes) % 4 == 0 && 483 "Invalid number of NOP bytes requested!"); 484 for (unsigned i = EncodedBytes; i < NumBytes; i += 4) 485 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); 486 } 487 488 void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) { 489 unsigned DestReg = MI.getOperand(0).getReg(); 490 if (STI->hasZeroCycleZeroing()) { 491 // Convert S/D register to corresponding Q register 492 if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) { 493 DestReg = AArch64::Q0 + (DestReg - AArch64::S0); 494 } else { 495 assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31); 496 DestReg = AArch64::Q0 + (DestReg - AArch64::D0); 497 } 498 MCInst MOVI; 499 MOVI.setOpcode(AArch64::MOVIv2d_ns); 500 MOVI.addOperand(MCOperand::createReg(DestReg)); 501 MOVI.addOperand(MCOperand::createImm(0)); 502 EmitToStreamer(*OutStreamer, MOVI); 503 } else { 504 MCInst FMov; 505 switch (MI.getOpcode()) { 506 default: llvm_unreachable("Unexpected opcode"); 507 case AArch64::FMOVS0: 508 FMov.setOpcode(AArch64::FMOVWSr); 509 FMov.addOperand(MCOperand::createReg(DestReg)); 510 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); 511 break; 512 case AArch64::FMOVD0: 513 FMov.setOpcode(AArch64::FMOVXDr); 514 FMov.addOperand(MCOperand::createReg(DestReg)); 515 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); 516 break; 517 } 518 EmitToStreamer(*OutStreamer, FMov); 519 } 520 } 521 522 // Simple pseudo-instructions have their lowering (with expansion to real 523 // instructions) auto-generated. 524 #include "AArch64GenMCPseudoLowering.inc" 525 526 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) { 527 // Do any auto-generated pseudo lowerings. 528 if (emitPseudoExpansionLowering(*OutStreamer, MI)) 529 return; 530 531 if (AArch64FI->getLOHRelated().count(MI)) { 532 // Generate a label for LOH related instruction 533 MCSymbol *LOHLabel = createTempSymbol("loh"); 534 // Associate the instruction with the label 535 LOHInstToLabel[MI] = LOHLabel; 536 OutStreamer->EmitLabel(LOHLabel); 537 } 538 539 // Do any manual lowerings. 540 switch (MI->getOpcode()) { 541 default: 542 break; 543 case AArch64::DBG_VALUE: { 544 if (isVerbose() && OutStreamer->hasRawTextSupport()) { 545 SmallString<128> TmpStr; 546 raw_svector_ostream OS(TmpStr); 547 PrintDebugValueComment(MI, OS); 548 OutStreamer->EmitRawText(StringRef(OS.str())); 549 } 550 return; 551 } 552 553 // Tail calls use pseudo instructions so they have the proper code-gen 554 // attributes (isCall, isReturn, etc.). We lower them to the real 555 // instruction here. 556 case AArch64::TCRETURNri: { 557 MCInst TmpInst; 558 TmpInst.setOpcode(AArch64::BR); 559 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 560 EmitToStreamer(*OutStreamer, TmpInst); 561 return; 562 } 563 case AArch64::TCRETURNdi: { 564 MCOperand Dest; 565 MCInstLowering.lowerOperand(MI->getOperand(0), Dest); 566 MCInst TmpInst; 567 TmpInst.setOpcode(AArch64::B); 568 TmpInst.addOperand(Dest); 569 EmitToStreamer(*OutStreamer, TmpInst); 570 return; 571 } 572 case AArch64::TLSDESC_CALLSEQ: { 573 /// lower this to: 574 /// adrp x0, :tlsdesc:var 575 /// ldr x1, [x0, #:tlsdesc_lo12:var] 576 /// add x0, x0, #:tlsdesc_lo12:var 577 /// .tlsdesccall var 578 /// blr x1 579 /// (TPIDR_EL0 offset now in x0) 580 const MachineOperand &MO_Sym = MI->getOperand(0); 581 MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym); 582 MCOperand Sym, SymTLSDescLo12, SymTLSDesc; 583 MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | 584 AArch64II::MO_NC); 585 MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE); 586 MCInstLowering.lowerOperand(MO_Sym, Sym); 587 MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12); 588 MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc); 589 590 MCInst Adrp; 591 Adrp.setOpcode(AArch64::ADRP); 592 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); 593 Adrp.addOperand(SymTLSDesc); 594 EmitToStreamer(*OutStreamer, Adrp); 595 596 MCInst Ldr; 597 Ldr.setOpcode(AArch64::LDRXui); 598 Ldr.addOperand(MCOperand::createReg(AArch64::X1)); 599 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); 600 Ldr.addOperand(SymTLSDescLo12); 601 Ldr.addOperand(MCOperand::createImm(0)); 602 EmitToStreamer(*OutStreamer, Ldr); 603 604 MCInst Add; 605 Add.setOpcode(AArch64::ADDXri); 606 Add.addOperand(MCOperand::createReg(AArch64::X0)); 607 Add.addOperand(MCOperand::createReg(AArch64::X0)); 608 Add.addOperand(SymTLSDescLo12); 609 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0))); 610 EmitToStreamer(*OutStreamer, Add); 611 612 // Emit a relocation-annotation. This expands to no code, but requests 613 // the following instruction gets an R_AARCH64_TLSDESC_CALL. 614 MCInst TLSDescCall; 615 TLSDescCall.setOpcode(AArch64::TLSDESCCALL); 616 TLSDescCall.addOperand(Sym); 617 EmitToStreamer(*OutStreamer, TLSDescCall); 618 619 MCInst Blr; 620 Blr.setOpcode(AArch64::BLR); 621 Blr.addOperand(MCOperand::createReg(AArch64::X1)); 622 EmitToStreamer(*OutStreamer, Blr); 623 624 return; 625 } 626 627 case AArch64::FMOVS0: 628 case AArch64::FMOVD0: 629 EmitFMov0(*MI); 630 return; 631 632 case TargetOpcode::STACKMAP: 633 return LowerSTACKMAP(*OutStreamer, SM, *MI); 634 635 case TargetOpcode::PATCHPOINT: 636 return LowerPATCHPOINT(*OutStreamer, SM, *MI); 637 638 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: 639 LowerPATCHABLE_FUNCTION_ENTER(*MI); 640 return; 641 642 case TargetOpcode::PATCHABLE_FUNCTION_EXIT: 643 LowerPATCHABLE_FUNCTION_EXIT(*MI); 644 return; 645 646 case TargetOpcode::PATCHABLE_TAIL_CALL: 647 LowerPATCHABLE_TAIL_CALL(*MI); 648 return; 649 } 650 651 // Finally, do the automated lowerings for everything else. 652 MCInst TmpInst; 653 MCInstLowering.Lower(MI, TmpInst); 654 EmitToStreamer(*OutStreamer, TmpInst); 655 } 656 657 // Force static initialization. 658 extern "C" void LLVMInitializeAArch64AsmPrinter() { 659 RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget()); 660 RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget()); 661 RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target()); 662 } 663