1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 #include <numeric> 17 18 using namespace llvm; 19 using namespace llvm::X86; 20 21 namespace { 22 23 /// Container class for CPU features. 24 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 25 /// nice to use std::bitset directly, but it doesn't support constant 26 /// initialization. 27 class FeatureBitset { 28 static constexpr unsigned NUM_FEATURE_WORDS = 29 (X86::CPU_FEATURE_MAX + 31) / 32; 30 31 // This cannot be a std::array, operator[] is not constexpr until C++17. 32 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 33 34 public: 35 constexpr FeatureBitset() = default; 36 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 37 for (auto I : Init) 38 set(I); 39 } 40 41 bool any() const { 42 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; }); 43 } 44 45 constexpr FeatureBitset &set(unsigned I) { 46 // GCC <6.2 crashes if this is written in a single statement. 47 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 48 Bits[I / 32] = NewBits; 49 return *this; 50 } 51 52 constexpr bool operator[](unsigned I) const { 53 uint32_t Mask = uint32_t(1) << (I % 32); 54 return (Bits[I / 32] & Mask) != 0; 55 } 56 57 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { 58 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 59 // GCC <6.2 crashes if this is written in a single statement. 60 uint32_t NewBits = Bits[I] & RHS.Bits[I]; 61 Bits[I] = NewBits; 62 } 63 return *this; 64 } 65 66 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { 67 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 68 // GCC <6.2 crashes if this is written in a single statement. 69 uint32_t NewBits = Bits[I] | RHS.Bits[I]; 70 Bits[I] = NewBits; 71 } 72 return *this; 73 } 74 75 // gcc 5.3 miscompiles this if we try to write this using operator&=. 76 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 77 FeatureBitset Result; 78 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 79 Result.Bits[I] = Bits[I] & RHS.Bits[I]; 80 return Result; 81 } 82 83 // gcc 5.3 miscompiles this if we try to write this using operator&=. 84 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 85 FeatureBitset Result; 86 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 87 Result.Bits[I] = Bits[I] | RHS.Bits[I]; 88 return Result; 89 } 90 91 constexpr FeatureBitset operator~() const { 92 FeatureBitset Result; 93 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 94 Result.Bits[I] = ~Bits[I]; 95 return Result; 96 } 97 98 constexpr bool operator!=(const FeatureBitset &RHS) const { 99 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 100 if (Bits[I] != RHS.Bits[I]) 101 return true; 102 return false; 103 } 104 }; 105 106 struct ProcInfo { 107 StringLiteral Name; 108 X86::CPUKind Kind; 109 unsigned KeyFeature; 110 FeatureBitset Features; 111 }; 112 113 struct FeatureInfo { 114 StringLiteral Name; 115 FeatureBitset ImpliedFeatures; 116 }; 117 118 } // end anonymous namespace 119 120 #define X86_FEATURE(ENUM, STRING) \ 121 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 122 #include "llvm/Support/X86TargetParser.def" 123 124 // Pentium with MMX. 125 constexpr FeatureBitset FeaturesPentiumMMX = 126 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 127 128 // Pentium 2 and 3. 129 constexpr FeatureBitset FeaturesPentium2 = 130 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 131 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 132 133 // Pentium 4 CPUs 134 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2; 135 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3; 136 constexpr FeatureBitset FeaturesNocona = 137 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; 138 139 // Basic 64-bit capable CPU. 140 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; 141 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF | 142 FeaturePOPCNT | FeatureSSE4_2 | 143 FeatureCMPXCHG16B; 144 constexpr FeatureBitset FeaturesX86_64_V3 = 145 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C | 146 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE; 147 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | 148 FeatureAVX512BW | FeatureAVX512CD | 149 FeatureAVX512DQ | FeatureAVX512VL; 150 151 // Intel Core CPUs 152 constexpr FeatureBitset FeaturesCore2 = 153 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 154 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 155 constexpr FeatureBitset FeaturesNehalem = 156 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; 157 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL; 158 constexpr FeatureBitset FeaturesSandyBridge = 159 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 160 constexpr FeatureBitset FeaturesIvyBridge = 161 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 162 constexpr FeatureBitset FeaturesHaswell = 163 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 164 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 165 constexpr FeatureBitset FeaturesBroadwell = 166 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 167 168 // Intel Knights Landing and Knights Mill 169 // Knights Landing has feature parity with Broadwell. 170 constexpr FeatureBitset FeaturesKNL = 171 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 172 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 173 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ; 174 175 // Intel Skylake processors. 176 constexpr FeatureBitset FeaturesSkylakeClient = 177 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 178 FeatureXSAVES | FeatureSGX; 179 // SkylakeServer inherits all SkylakeClient features except SGX. 180 // FIXME: That doesn't match gcc. 181 constexpr FeatureBitset FeaturesSkylakeServer = 182 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 183 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 184 FeaturePKU; 185 constexpr FeatureBitset FeaturesCascadeLake = 186 FeaturesSkylakeServer | FeatureAVX512VNNI; 187 constexpr FeatureBitset FeaturesCooperLake = 188 FeaturesCascadeLake | FeatureAVX512BF16; 189 190 // Intel 10nm processors. 191 constexpr FeatureBitset FeaturesCannonlake = 192 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 193 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 194 FeaturePKU | FeatureSHA; 195 constexpr FeatureBitset FeaturesICLClient = 196 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 197 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID | 198 FeatureVAES | FeatureVPCLMULQDQ; 199 constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX; 200 constexpr FeatureBitset FeaturesICLServer = 201 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD; 202 constexpr FeatureBitset FeaturesTigerlake = 203 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 204 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; 205 constexpr FeatureBitset FeaturesSapphireRapids = 206 FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE | 207 FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVX512VP2INTERSECT | 208 FeatureAVXVNNI | FeatureCLDEMOTE | FeatureENQCMD | FeatureMOVDIR64B | 209 FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | FeatureSHSTK | 210 FeatureTSXLDTRK | FeatureUINTR | FeatureWAITPKG; 211 212 // Intel Atom processors. 213 // Bonnell has feature parity with Core2 and adds MOVBE. 214 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 215 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 216 constexpr FeatureBitset FeaturesSilvermont = 217 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 218 constexpr FeatureBitset FeaturesGoldmont = 219 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 220 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 221 FeatureXSAVEOPT | FeatureXSAVES; 222 constexpr FeatureBitset FeaturesGoldmontPlus = 223 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 224 constexpr FeatureBitset FeaturesTremont = 225 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 226 constexpr FeatureBitset FeaturesAlderlake = 227 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C | 228 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU | 229 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ | 230 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG | 231 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL; 232 233 // Geode Processor. 234 constexpr FeatureBitset FeaturesGeode = 235 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 236 237 // K6 processor. 238 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 239 240 // K7 and K8 architecture processors. 241 constexpr FeatureBitset FeaturesAthlon = 242 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 243 constexpr FeatureBitset FeaturesAthlonXP = 244 FeaturesAthlon | FeatureFXSR | FeatureSSE; 245 constexpr FeatureBitset FeaturesK8 = 246 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; 247 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 248 constexpr FeatureBitset FeaturesAMDFAM10 = 249 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 250 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 251 252 // Bobcat architecture processors. 253 constexpr FeatureBitset FeaturesBTVER1 = 254 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | 255 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 256 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 257 FeatureSAHF; 258 constexpr FeatureBitset FeaturesBTVER2 = 259 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | 260 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 261 262 // AMD Bulldozer architecture processors. 263 constexpr FeatureBitset FeaturesBDVER1 = 264 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 265 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP | 266 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | 267 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | 268 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; 269 constexpr FeatureBitset FeaturesBDVER2 = 270 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 271 constexpr FeatureBitset FeaturesBDVER3 = 272 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 273 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 | 274 FeatureBMI2 | FeatureMOVBE | 275 FeatureMWAITX | FeatureRDRND; 276 277 // AMD Zen architecture processors. 278 constexpr FeatureBitset FeaturesZNVER1 = 279 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 280 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 281 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C | 282 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | 283 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 284 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 285 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 286 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 287 FeatureXSAVEOPT | FeatureXSAVES; 288 constexpr FeatureBitset FeaturesZNVER2 = 289 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD; 290 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 | 291 FeatureINVPCID | FeaturePKU | 292 FeatureVAES | FeatureVPCLMULQDQ; 293 294 constexpr ProcInfo Processors[] = { 295 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 296 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 297 // i386-generation processors. 298 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 299 // i486-generation processors. 300 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 301 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 302 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 303 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 304 // i586-generation processors, P5 microarchitecture based. 305 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 306 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 307 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 308 // i686-generation processors, P6 / Pentium M microarchitecture based. 309 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 310 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 311 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 312 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 313 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 314 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 315 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 316 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 317 // Netburst microarchitecture based processors. 318 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 319 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 320 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 321 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 322 // Core microarchitecture based processors. 323 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, 324 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 325 // Atom processors 326 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 327 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 328 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 329 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 330 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 331 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 332 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 333 // Nehalem microarchitecture based processors. 334 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 335 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 336 // Westmere microarchitecture based processors. 337 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 338 // Sandy Bridge microarchitecture based processors. 339 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 340 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 341 // Ivy Bridge microarchitecture based processors. 342 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 343 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 344 // Haswell microarchitecture based processors. 345 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 346 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 347 // Broadwell microarchitecture based processors. 348 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 349 // Skylake client microarchitecture based processors. 350 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 351 // Skylake server microarchitecture based processors. 352 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 353 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 354 // Cascadelake Server microarchitecture based processors. 355 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 356 // Cooperlake Server microarchitecture based processors. 357 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 358 // Cannonlake client microarchitecture based processors. 359 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 360 // Icelake client microarchitecture based processors. 361 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 362 // Rocketlake microarchitecture based processors. 363 { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake }, 364 // Icelake server microarchitecture based processors. 365 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 366 // Tigerlake microarchitecture based processors. 367 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 368 // Sapphire Rapids microarchitecture based processors. 369 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids }, 370 // Alderlake microarchitecture based processors. 371 { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake }, 372 // Knights Landing processor. 373 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 374 // Knights Mill processor. 375 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 376 // Lakemont microarchitecture based processors. 377 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 378 // K6 architecture processors. 379 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 380 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 381 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 382 // K7 architecture processors. 383 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 384 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 385 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 386 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 387 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 388 // K8 architecture processors. 389 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 390 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 391 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 392 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 393 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 394 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 395 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 396 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 397 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 398 // Bobcat architecture processors. 399 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 400 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 401 // Bulldozer architecture processors. 402 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 403 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 404 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 405 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 406 // Zen architecture processors. 407 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 408 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 409 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 }, 410 // Generic 64-bit processor. 411 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 412 { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 }, 413 { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 }, 414 { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 }, 415 // Geode processors. 416 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 417 }; 418 419 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"}; 420 421 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 422 for (const auto &P : Processors) 423 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) 424 return P.Kind; 425 426 return CK_None; 427 } 428 429 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) { 430 if (llvm::is_contained(NoTuneList, CPU)) 431 return CK_None; 432 return parseArchX86(CPU, Only64Bit); 433 } 434 435 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 436 bool Only64Bit) { 437 for (const auto &P : Processors) 438 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit)) 439 Values.emplace_back(P.Name); 440 } 441 442 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values, 443 bool Only64Bit) { 444 for (const ProcInfo &P : Processors) 445 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) && 446 !llvm::is_contained(NoTuneList, P.Name)) 447 Values.emplace_back(P.Name); 448 } 449 450 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 451 // FIXME: Can we avoid a linear search here? The table might be sorted by 452 // CPUKind so we could binary search? 453 for (const auto &P : Processors) { 454 if (P.Kind == Kind) { 455 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 456 return static_cast<ProcessorFeatures>(P.KeyFeature); 457 } 458 } 459 460 llvm_unreachable("Unable to find CPU kind!"); 461 } 462 463 // Features with no dependencies. 464 constexpr FeatureBitset ImpliedFeatures64BIT = {}; 465 constexpr FeatureBitset ImpliedFeaturesADX = {}; 466 constexpr FeatureBitset ImpliedFeaturesBMI = {}; 467 constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 468 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 469 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 470 constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 471 constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 472 constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 473 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 474 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 475 constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 476 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 477 constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 478 constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 479 constexpr FeatureBitset ImpliedFeaturesLWP = {}; 480 constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 481 constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 482 constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 483 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 484 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 485 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 486 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 487 constexpr FeatureBitset ImpliedFeaturesPKU = {}; 488 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 489 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 490 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 491 constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 492 constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 493 constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 494 constexpr FeatureBitset ImpliedFeaturesRTM = {}; 495 constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 496 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 497 constexpr FeatureBitset ImpliedFeaturesSGX = {}; 498 constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 499 constexpr FeatureBitset ImpliedFeaturesTBM = {}; 500 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 501 constexpr FeatureBitset ImpliedFeaturesUINTR = {}; 502 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 503 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 504 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 505 constexpr FeatureBitset ImpliedFeaturesX87 = {}; 506 constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 507 508 // Not really CPU features, but need to be in the table because clang uses 509 // target features to communicate them to the backend. 510 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 511 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 512 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 513 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 514 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 515 516 // XSAVE features are dependent on basic XSAVE. 517 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 518 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 519 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 520 521 // MMX->3DNOW->3DNOWA chain. 522 constexpr FeatureBitset ImpliedFeaturesMMX = {}; 523 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 524 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 525 526 // SSE/AVX/AVX512F chain. 527 constexpr FeatureBitset ImpliedFeaturesSSE = {}; 528 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 529 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 530 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 531 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 532 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 533 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 534 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 535 constexpr FeatureBitset ImpliedFeaturesAVX512F = 536 FeatureAVX2 | FeatureF16C | FeatureFMA; 537 538 // Vector extensions that build on SSE or AVX. 539 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 540 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 541 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 542 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 543 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 544 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 545 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; 546 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL; 547 548 // AVX512 features. 549 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 550 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 551 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 552 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 553 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 554 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 555 556 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 557 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 558 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 559 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 560 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 561 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 562 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 563 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F; 564 565 // FIXME: These two aren't really implemented and just exist in the feature 566 // list for __builtin_cpu_supports. So omit their dependencies. 567 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 568 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 569 570 // SSE4_A->FMA4->XOP chain. 571 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3; 572 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 573 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 574 575 // AMX Features 576 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 577 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 578 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 579 constexpr FeatureBitset ImpliedFeaturesHRESET = {}; 580 581 static constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = 582 FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL; 583 // Key Locker Features 584 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2; 585 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL; 586 587 // AVXVNNI Features 588 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2; 589 590 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 591 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM}, 592 #include "llvm/Support/X86TargetParser.def" 593 }; 594 595 void llvm::X86::getFeaturesForCPU(StringRef CPU, 596 SmallVectorImpl<StringRef> &EnabledFeatures) { 597 auto I = llvm::find_if(Processors, 598 [&](const ProcInfo &P) { return P.Name == CPU; }); 599 assert(I != std::end(Processors) && "Processor not found!"); 600 601 FeatureBitset Bits = I->Features; 602 603 // Remove the 64-bit feature which we only use to validate if a CPU can 604 // be used with 64-bit mode. 605 Bits &= ~Feature64BIT; 606 607 // Add the string version of all set bits. 608 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 609 if (Bits[i] && !FeatureInfos[i].Name.empty()) 610 EnabledFeatures.push_back(FeatureInfos[i].Name); 611 } 612 613 // For each feature that is (transitively) implied by this feature, set it. 614 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 615 const FeatureBitset &Implies) { 616 // Fast path: Implies is often empty. 617 if (!Implies.any()) 618 return; 619 FeatureBitset Prev; 620 Bits |= Implies; 621 do { 622 Prev = Bits; 623 for (unsigned i = CPU_FEATURE_MAX; i;) 624 if (Bits[--i]) 625 Bits |= FeatureInfos[i].ImpliedFeatures; 626 } while (Prev != Bits); 627 } 628 629 /// Create bit vector of features that are implied disabled if the feature 630 /// passed in Value is disabled. 631 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 632 // Check all features looking for any dependent on this feature. If we find 633 // one, mark it and recursively find any feature that depend on it. 634 FeatureBitset Prev; 635 Bits.set(Value); 636 do { 637 Prev = Bits; 638 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 639 if ((FeatureInfos[i].ImpliedFeatures & Bits).any()) 640 Bits.set(i); 641 } while (Prev != Bits); 642 } 643 644 void llvm::X86::updateImpliedFeatures( 645 StringRef Feature, bool Enabled, 646 StringMap<bool> &Features) { 647 auto I = llvm::find_if( 648 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; }); 649 if (I == std::end(FeatureInfos)) { 650 // FIXME: This shouldn't happen, but may not have all features in the table 651 // yet. 652 return; 653 } 654 655 FeatureBitset ImpliedBits; 656 if (Enabled) 657 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 658 else 659 getImpliedDisabledFeatures(ImpliedBits, 660 std::distance(std::begin(FeatureInfos), I)); 661 662 // Update the map entry for all implied features. 663 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 664 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty()) 665 Features[FeatureInfos[i].Name] = Enabled; 666 } 667 668 uint64_t llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) { 669 // Processor features and mapping to processor feature value. 670 uint64_t FeaturesMask = 0; 671 for (const StringRef &FeatureStr : FeatureStrs) { 672 unsigned Feature = StringSwitch<unsigned>(FeatureStr) 673 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 674 .Case(STR, llvm::X86::FEATURE_##ENUM) 675 #include "llvm/Support/X86TargetParser.def" 676 ; 677 FeaturesMask |= (1ULL << Feature); 678 } 679 return FeaturesMask; 680 } 681 682 unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) { 683 #ifndef NDEBUG 684 // Check that priorities are set properly in the .def file. We expect that 685 // "compat" features are assigned non-duplicate consecutive priorities 686 // starting from zero (0, 1, ..., num_features - 1). 687 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY, 688 unsigned Priorities[] = { 689 #include "llvm/Support/X86TargetParser.def" 690 std::numeric_limits<unsigned>::max() // Need to consume last comma. 691 }; 692 std::array<unsigned, array_lengthof(Priorities) - 1> HelperList; 693 std::iota(HelperList.begin(), HelperList.end(), 0); 694 assert(std::is_permutation(HelperList.begin(), HelperList.end(), 695 std::begin(Priorities), 696 std::prev(std::end(Priorities))) && 697 "Priorities don't form consecutive range!"); 698 #endif 699 700 switch (Feat) { 701 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 702 case X86::FEATURE_##ENUM: \ 703 return PRIORITY; 704 #include "llvm/Support/X86TargetParser.def" 705 default: 706 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 707 } 708 } 709