1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 /// Container class for CPU features. 23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 24 /// nice to use std::bitset directly, but it doesn't support constant 25 /// initialization. 26 class FeatureBitset { 27 static constexpr unsigned NUM_FEATURE_WORDS = 28 (X86::CPU_FEATURE_MAX + 31) / 32; 29 30 // This cannot be a std::array, operator[] is not constexpr until C++17. 31 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 32 33 public: 34 constexpr FeatureBitset() = default; 35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 36 for (auto I : Init) 37 set(I); 38 } 39 40 constexpr FeatureBitset &set(unsigned I) { 41 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 42 Bits[I / 32] = NewBits; 43 return *this; 44 } 45 46 constexpr bool operator[](unsigned I) const { 47 uint32_t Mask = uint32_t(1) << (I % 32); 48 return (Bits[I / 32] & Mask) != 0; 49 } 50 51 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { 52 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 53 uint32_t NewBits = Bits[I] | RHS.Bits[I]; 54 Bits[I] = NewBits; 55 } 56 return *this; 57 } 58 59 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 60 FeatureBitset Result; 61 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 62 Result.Bits[I] = Bits[I] & RHS.Bits[I]; 63 return Result; 64 } 65 66 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 67 FeatureBitset Result; 68 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 69 Result.Bits[I] = Bits[I] | RHS.Bits[I]; 70 return Result; 71 } 72 73 constexpr FeatureBitset operator~() const { 74 FeatureBitset Result; 75 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 76 Result.Bits[I] = ~Bits[I]; 77 return Result; 78 } 79 }; 80 81 struct ProcInfo { 82 StringLiteral Name; 83 X86::CPUKind Kind; 84 unsigned KeyFeature; 85 FeatureBitset Features; 86 }; 87 88 struct FeatureInfo { 89 StringLiteral Name; 90 FeatureBitset ImpliedFeatures; 91 }; 92 93 } // end anonymous namespace 94 95 #define X86_FEATURE(ENUM, STRING) \ 96 static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 97 #include "llvm/Support/X86TargetParser.def" 98 99 // Pentium with MMX. 100 static constexpr FeatureBitset FeaturesPentiumMMX = 101 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 102 103 // Pentium 2 and 3. 104 static constexpr FeatureBitset FeaturesPentium2 = 105 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 106 static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 107 108 // Pentium 4 CPUs 109 static constexpr FeatureBitset FeaturesPentium4 = 110 FeaturesPentium3 | FeatureSSE2; 111 static constexpr FeatureBitset FeaturesPrescott = 112 FeaturesPentium4 | FeatureSSE3; 113 static constexpr FeatureBitset FeaturesNocona = 114 FeaturesPrescott | FeatureEM64T | FeatureCMPXCHG16B; 115 116 // Basic 64-bit capable CPU. 117 static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | FeatureEM64T; 118 119 // Intel Core CPUs 120 static constexpr FeatureBitset FeaturesCore2 = 121 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 122 static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 123 static constexpr FeatureBitset FeaturesNehalem = 124 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; 125 static constexpr FeatureBitset FeaturesWestmere = 126 FeaturesNehalem | FeaturePCLMUL; 127 static constexpr FeatureBitset FeaturesSandyBridge = 128 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 129 static constexpr FeatureBitset FeaturesIvyBridge = 130 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 131 static constexpr FeatureBitset FeaturesHaswell = 132 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 133 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 134 static constexpr FeatureBitset FeaturesBroadwell = 135 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 136 137 // Intel Knights Landing and Knights Mill 138 // Knights Landing has feature parity with Broadwell. 139 static constexpr FeatureBitset FeaturesKNL = 140 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 141 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 142 static constexpr FeatureBitset FeaturesKNM = 143 FeaturesKNL | FeatureAVX512VPOPCNTDQ; 144 145 // Intel Skylake processors. 146 static constexpr FeatureBitset FeaturesSkylakeClient = 147 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 148 FeatureXSAVES | FeatureSGX; 149 // SkylakeServer inherits all SkylakeClient features except SGX. 150 // FIXME: That doesn't match gcc. 151 static constexpr FeatureBitset FeaturesSkylakeServer = 152 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 153 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 154 FeaturePKU; 155 static constexpr FeatureBitset FeaturesCascadeLake = 156 FeaturesSkylakeServer | FeatureAVX512VNNI; 157 static constexpr FeatureBitset FeaturesCooperLake = 158 FeaturesCascadeLake | FeatureAVX512BF16; 159 160 // Intel 10nm processors. 161 static constexpr FeatureBitset FeaturesCannonlake = 162 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 163 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 164 FeaturePKU | FeatureSHA; 165 static constexpr FeatureBitset FeaturesICLClient = 166 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 167 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI | 168 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ; 169 static constexpr FeatureBitset FeaturesICLServer = 170 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD; 171 static constexpr FeatureBitset FeaturesTigerlake = 172 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 173 FeatureMOVDIRI | FeatureSHSTK; 174 175 // Intel Atom processors. 176 // Bonnell has feature parity with Core2 and adds MOVBE. 177 static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 178 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 179 static constexpr FeatureBitset FeaturesSilvermont = 180 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 181 static constexpr FeatureBitset FeaturesGoldmont = 182 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 183 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 184 FeatureXSAVEOPT | FeatureXSAVES; 185 static constexpr FeatureBitset FeaturesGoldmontPlus = 186 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 187 static constexpr FeatureBitset FeaturesTremont = 188 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 189 190 // Geode Processor. 191 static constexpr FeatureBitset FeaturesGeode = 192 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 193 194 // K6 processor. 195 static constexpr FeatureBitset FeaturesK6 = 196 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 197 198 // K7 and K8 architecture processors. 199 static constexpr FeatureBitset FeaturesAthlon = 200 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 201 static constexpr FeatureBitset FeaturesAthlonXP = 202 FeaturesAthlon | FeatureFXSR | FeatureSSE; 203 static constexpr FeatureBitset FeaturesK8 = 204 FeaturesAthlonXP | FeatureSSE2 | FeatureEM64T; 205 static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 206 static constexpr FeatureBitset FeaturesAMDFAM10 = 207 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 208 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 209 210 // Bobcat architecture processors. 211 static constexpr FeatureBitset FeaturesBTVER1 = 212 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | 213 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 214 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 215 FeatureSAHF; 216 static constexpr FeatureBitset FeaturesBTVER2 = 217 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | 218 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 219 220 // AMD Bulldozer architecture processors. 221 static constexpr FeatureBitset FeaturesBDVER1 = 222 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 223 FeatureCMPXCHG16B | FeatureEM64T | FeatureFMA4 | FeatureFXSR | FeatureLWP | 224 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | 225 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | 226 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; 227 static constexpr FeatureBitset FeaturesBDVER2 = 228 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 229 static constexpr FeatureBitset FeaturesBDVER3 = 230 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 231 static constexpr FeatureBitset FeaturesBDVER4 = 232 FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX | 233 FeatureRDRND; 234 235 // AMD Zen architecture processors. 236 static constexpr FeatureBitset FeaturesZNVER1 = 237 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 238 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 239 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | FeatureF16C | 240 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | 241 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 242 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 243 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 244 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 245 FeatureXSAVEOPT | FeatureXSAVES; 246 static constexpr FeatureBitset FeaturesZNVER2 = 247 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD; 248 249 static constexpr ProcInfo Processors[] = { 250 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 251 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 252 // i386-generation processors. 253 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 254 // i486-generation processors. 255 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 256 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 257 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 258 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 259 // i586-generation processors, P5 microarchitecture based. 260 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 261 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 262 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 263 // i686-generation processors, P6 / Pentium M microarchitecture based. 264 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 265 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 266 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 267 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 268 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 269 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 270 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 271 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 272 // Netburst microarchitecture based processors. 273 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 274 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 275 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 276 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 277 // Core microarchitecture based processors. 278 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, 279 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 280 // Atom processors 281 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 282 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 283 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 284 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 285 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 286 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 287 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 288 // Nehalem microarchitecture based processors. 289 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 290 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 291 // Westmere microarchitecture based processors. 292 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 293 // Sandy Bridge microarchitecture based processors. 294 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 295 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 296 // Ivy Bridge microarchitecture based processors. 297 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 298 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 299 // Haswell microarchitecture based processors. 300 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 301 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 302 // Broadwell microarchitecture based processors. 303 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 304 // Skylake client microarchitecture based processors. 305 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 306 // Skylake server microarchitecture based processors. 307 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 308 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 309 // Cascadelake Server microarchitecture based processors. 310 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 311 // Cooperlake Server microarchitecture based processors. 312 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 313 // Cannonlake client microarchitecture based processors. 314 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 315 // Icelake client microarchitecture based processors. 316 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 317 // Icelake server microarchitecture based processors. 318 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 319 // Tigerlake microarchitecture based processors. 320 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 321 // Knights Landing processor. 322 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 323 // Knights Mill processor. 324 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 325 // Lakemont microarchitecture based processors. 326 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 327 // K6 architecture processors. 328 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 329 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 330 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 331 // K7 architecture processors. 332 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 333 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 334 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 335 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 336 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 337 // K8 architecture processors. 338 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 339 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 340 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 341 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 342 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 343 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 344 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 345 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 346 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 347 // Bobcat architecture processors. 348 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 349 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 350 // Bulldozer architecture processors. 351 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 352 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 353 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 354 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 355 // Zen architecture processors. 356 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 357 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 358 // Generic 64-bit processor. 359 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 360 // Geode processors. 361 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 362 }; 363 364 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 365 for (const auto &P : Processors) 366 if (P.Name == CPU && (P.Features[FEATURE_EM64T] || !Only64Bit)) 367 return P.Kind; 368 369 return CK_None; 370 } 371 372 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 373 bool Only64Bit) { 374 for (const auto &P : Processors) 375 if (!P.Name.empty() && (P.Features[FEATURE_EM64T] || !Only64Bit)) 376 Values.emplace_back(P.Name); 377 } 378 379 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 380 // FIXME: Can we avoid a linear search here? The table might be sorted by 381 // CPUKind so we could binary search? 382 for (const auto &P : Processors) { 383 if (P.Kind == Kind) { 384 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 385 return static_cast<ProcessorFeatures>(P.KeyFeature); 386 } 387 } 388 389 llvm_unreachable("Unable to find CPU kind!"); 390 } 391 392 // Features with no dependencies. 393 static constexpr FeatureBitset ImpliedFeatures64BIT = {}; 394 static constexpr FeatureBitset ImpliedFeaturesADX = {}; 395 static constexpr FeatureBitset ImpliedFeaturesBMI = {}; 396 static constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 397 static constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 398 static constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 399 static constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 400 static constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 401 static constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 402 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 403 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 404 static constexpr FeatureBitset ImpliedFeaturesEM64T = {}; 405 static constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 406 static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 407 static constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 408 static constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 409 static constexpr FeatureBitset ImpliedFeaturesLWP = {}; 410 static constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 411 static constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 412 static constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 413 static constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 414 static constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 415 static constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 416 static constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 417 static constexpr FeatureBitset ImpliedFeaturesPKU = {}; 418 static constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 419 static constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 420 static constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 421 static constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 422 static constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 423 static constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 424 static constexpr FeatureBitset ImpliedFeaturesRTM = {}; 425 static constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 426 static constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 427 static constexpr FeatureBitset ImpliedFeaturesSGX = {}; 428 static constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 429 static constexpr FeatureBitset ImpliedFeaturesTBM = {}; 430 static constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 431 static constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 432 static constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 433 static constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 434 static constexpr FeatureBitset ImpliedFeaturesX87 = {}; 435 static constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 436 437 // Not really CPU features, but need to be in the table because clang uses 438 // target features to communicate them to the backend. 439 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 440 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 441 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 442 static constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 443 static constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 444 445 // XSAVE features are dependent on basic XSAVE. 446 static constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 447 static constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 448 static constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 449 450 // MMX->3DNOW->3DNOWA chain. 451 static constexpr FeatureBitset ImpliedFeaturesMMX = {}; 452 static constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 453 static constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 454 455 // SSE/AVX/AVX512F chain. 456 static constexpr FeatureBitset ImpliedFeaturesSSE = {}; 457 static constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 458 static constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 459 static constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 460 static constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 461 static constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 462 static constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 463 static constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 464 static constexpr FeatureBitset ImpliedFeaturesAVX512F = 465 FeatureAVX2 | FeatureF16C | FeatureFMA; 466 467 // Vector extensions that build on SSE or AVX. 468 static constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 469 static constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 470 static constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 471 static constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 472 static constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 473 static constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 474 static constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; 475 static constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = 476 FeatureAVX | FeaturePCLMUL; 477 478 // AVX512 features. 479 static constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 480 static constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 481 static constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 482 static constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 483 static constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 484 static constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 485 486 static constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 487 static constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 488 static constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 489 static constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 490 static constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 491 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 492 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 493 static constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = 494 FeatureAVX512F; 495 496 // FIXME: These two aren't really implemented and just exist in the feature 497 // list for __builtin_cpu_supports. So omit their dependencies. 498 static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 499 static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 500 501 // SSE4_A->FMA4->XOP chain. 502 static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSSE3; 503 static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 504 static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 505 506 // AMX Features 507 static constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 508 static constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 509 static constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 510 511 static constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 512 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM}, 513 #include "llvm/Support/X86TargetParser.def" 514 }; 515 516 // Convert the set bits in FeatureBitset to a list of strings. 517 static void getFeatureBitsAsStrings(const FeatureBitset &Bits, 518 SmallVectorImpl<StringRef> &Features) { 519 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 520 if (Bits[i] && !FeatureInfos[i].Name.empty()) 521 Features.push_back(FeatureInfos[i].Name); 522 } 523 524 void llvm::X86::getFeaturesForCPU(StringRef CPU, 525 SmallVectorImpl<StringRef> &EnabledFeatures) { 526 auto I = llvm::find_if(Processors, 527 [&](const ProcInfo &P) { return P.Name == CPU; }); 528 assert(I != std::end(Processors) && "Processor not found!"); 529 530 // Add the string version of all set bits. 531 getFeatureBitsAsStrings(I->Features, EnabledFeatures); 532 } 533 534 // For each feature that is (transitively) implied by this feature, set it. 535 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 536 const FeatureBitset &Implies) { 537 Bits |= Implies; 538 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) { 539 if (Implies[i]) 540 getImpliedEnabledFeatures(Bits, FeatureInfos[i].ImpliedFeatures); 541 } 542 } 543 544 /// Create bit vector of features that are implied disabled if the feature 545 /// passed in Value is disabled. 546 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 547 // Check all features looking for any dependent on this feature. If we find 548 // one, mark it and recursively find any feature that depend on it. 549 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) { 550 if (FeatureInfos[i].ImpliedFeatures[Value]) { 551 Bits.set(i); 552 getImpliedDisabledFeatures(Bits, i); 553 } 554 } 555 } 556 557 void llvm::X86::getImpliedFeatures( 558 StringRef Feature, bool Enabled, 559 SmallVectorImpl<StringRef> &ImpliedFeatures) { 560 auto I = llvm::find_if( 561 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; }); 562 if (I == std::end(FeatureInfos)) { 563 // FIXME: This shouldn't happen, but may not have all features in the table 564 // yet. 565 return; 566 } 567 568 FeatureBitset ImpliedBits; 569 if (Enabled) 570 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 571 else 572 getImpliedDisabledFeatures(ImpliedBits, 573 std::distance(std::begin(FeatureInfos), I)); 574 575 // Convert all the found bits into strings. 576 getFeatureBitsAsStrings(ImpliedBits, ImpliedFeatures); 577 } 578