1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 /// Container class for CPU features. 23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 24 /// nice to use std::bitset directly, but it doesn't support constant 25 /// initialization. 26 class FeatureBitset { 27 static constexpr unsigned NUM_FEATURE_WORDS = 28 (X86::CPU_FEATURE_MAX + 31) / 32; 29 30 // This cannot be a std::array, operator[] is not constexpr until C++17. 31 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 32 33 public: 34 constexpr FeatureBitset() = default; 35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 36 for (auto I : Init) 37 set(I); 38 } 39 40 bool any() const { 41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; }); 42 } 43 44 constexpr FeatureBitset &set(unsigned I) { 45 // GCC <6.2 crashes if this is written in a single statement. 46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 47 Bits[I / 32] = NewBits; 48 return *this; 49 } 50 51 constexpr bool operator[](unsigned I) const { 52 uint32_t Mask = uint32_t(1) << (I % 32); 53 return (Bits[I / 32] & Mask) != 0; 54 } 55 56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { 57 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 58 // GCC <6.2 crashes if this is written in a single statement. 59 uint32_t NewBits = Bits[I] & RHS.Bits[I]; 60 Bits[I] = NewBits; 61 } 62 return *this; 63 } 64 65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { 66 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 67 // GCC <6.2 crashes if this is written in a single statement. 68 uint32_t NewBits = Bits[I] | RHS.Bits[I]; 69 Bits[I] = NewBits; 70 } 71 return *this; 72 } 73 74 // gcc 5.3 miscompiles this if we try to write this using operator&=. 75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 76 FeatureBitset Result; 77 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 78 Result.Bits[I] = Bits[I] & RHS.Bits[I]; 79 return Result; 80 } 81 82 // gcc 5.3 miscompiles this if we try to write this using operator&=. 83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 84 FeatureBitset Result; 85 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 86 Result.Bits[I] = Bits[I] | RHS.Bits[I]; 87 return Result; 88 } 89 90 constexpr FeatureBitset operator~() const { 91 FeatureBitset Result; 92 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 93 Result.Bits[I] = ~Bits[I]; 94 return Result; 95 } 96 97 constexpr bool operator!=(const FeatureBitset &RHS) const { 98 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 99 if (Bits[I] != RHS.Bits[I]) 100 return true; 101 return false; 102 } 103 }; 104 105 struct ProcInfo { 106 StringLiteral Name; 107 X86::CPUKind Kind; 108 unsigned KeyFeature; 109 FeatureBitset Features; 110 }; 111 112 struct FeatureInfo { 113 StringLiteral Name; 114 FeatureBitset ImpliedFeatures; 115 }; 116 117 } // end anonymous namespace 118 119 #define X86_FEATURE(ENUM, STRING) \ 120 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 121 #include "llvm/Support/X86TargetParser.def" 122 123 // Pentium with MMX. 124 constexpr FeatureBitset FeaturesPentiumMMX = 125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 126 127 // Pentium 2 and 3. 128 constexpr FeatureBitset FeaturesPentium2 = 129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 130 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 131 132 // Pentium 4 CPUs 133 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2; 134 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3; 135 constexpr FeatureBitset FeaturesNocona = 136 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; 137 138 // Basic 64-bit capable CPU. 139 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; 140 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF | 141 FeaturePOPCNT | FeatureSSE4_2 | 142 FeatureCMPXCHG16B; 143 constexpr FeatureBitset FeaturesX86_64_V3 = 144 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C | 145 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE; 146 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | 147 FeatureAVX512BW | FeatureAVX512CD | 148 FeatureAVX512DQ | FeatureAVX512VL; 149 150 // Intel Core CPUs 151 constexpr FeatureBitset FeaturesCore2 = 152 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 153 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 154 constexpr FeatureBitset FeaturesNehalem = 155 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; 156 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL; 157 constexpr FeatureBitset FeaturesSandyBridge = 158 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 159 constexpr FeatureBitset FeaturesIvyBridge = 160 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 161 constexpr FeatureBitset FeaturesHaswell = 162 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 163 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 164 constexpr FeatureBitset FeaturesBroadwell = 165 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 166 167 // Intel Knights Landing and Knights Mill 168 // Knights Landing has feature parity with Broadwell. 169 constexpr FeatureBitset FeaturesKNL = 170 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 171 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 172 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ; 173 174 // Intel Skylake processors. 175 constexpr FeatureBitset FeaturesSkylakeClient = 176 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 177 FeatureXSAVES | FeatureSGX; 178 // SkylakeServer inherits all SkylakeClient features except SGX. 179 // FIXME: That doesn't match gcc. 180 constexpr FeatureBitset FeaturesSkylakeServer = 181 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 182 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 183 FeaturePKU; 184 constexpr FeatureBitset FeaturesCascadeLake = 185 FeaturesSkylakeServer | FeatureAVX512VNNI; 186 constexpr FeatureBitset FeaturesCooperLake = 187 FeaturesCascadeLake | FeatureAVX512BF16; 188 189 // Intel 10nm processors. 190 constexpr FeatureBitset FeaturesCannonlake = 191 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 192 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 193 FeaturePKU | FeatureSHA; 194 constexpr FeatureBitset FeaturesICLClient = 195 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 196 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI | 197 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ; 198 constexpr FeatureBitset FeaturesICLServer = 199 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD; 200 constexpr FeatureBitset FeaturesTigerlake = 201 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 202 FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; 203 constexpr FeatureBitset FeaturesSapphireRapids = 204 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 | 205 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE | 206 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | 207 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR | 208 FeatureWAITPKG; 209 210 // Intel Atom processors. 211 // Bonnell has feature parity with Core2 and adds MOVBE. 212 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 213 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 214 constexpr FeatureBitset FeaturesSilvermont = 215 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 216 constexpr FeatureBitset FeaturesGoldmont = 217 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 218 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 219 FeatureXSAVEOPT | FeatureXSAVES; 220 constexpr FeatureBitset FeaturesGoldmontPlus = 221 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 222 constexpr FeatureBitset FeaturesTremont = 223 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 224 225 // Geode Processor. 226 constexpr FeatureBitset FeaturesGeode = 227 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 228 229 // K6 processor. 230 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 231 232 // K7 and K8 architecture processors. 233 constexpr FeatureBitset FeaturesAthlon = 234 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 235 constexpr FeatureBitset FeaturesAthlonXP = 236 FeaturesAthlon | FeatureFXSR | FeatureSSE; 237 constexpr FeatureBitset FeaturesK8 = 238 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; 239 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 240 constexpr FeatureBitset FeaturesAMDFAM10 = 241 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 242 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 243 244 // Bobcat architecture processors. 245 constexpr FeatureBitset FeaturesBTVER1 = 246 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | 247 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 248 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 249 FeatureSAHF; 250 constexpr FeatureBitset FeaturesBTVER2 = 251 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | 252 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 253 254 // AMD Bulldozer architecture processors. 255 constexpr FeatureBitset FeaturesBDVER1 = 256 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 257 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP | 258 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | 259 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | 260 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; 261 constexpr FeatureBitset FeaturesBDVER2 = 262 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 263 constexpr FeatureBitset FeaturesBDVER3 = 264 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 265 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 | 266 FeatureBMI2 | FeatureMOVBE | 267 FeatureMWAITX | FeatureRDRND; 268 269 // AMD Zen architecture processors. 270 constexpr FeatureBitset FeaturesZNVER1 = 271 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 272 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 273 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C | 274 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | 275 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 276 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 277 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 278 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 279 FeatureXSAVEOPT | FeatureXSAVES; 280 constexpr FeatureBitset FeaturesZNVER2 = 281 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD; 282 283 constexpr ProcInfo Processors[] = { 284 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 285 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 286 // i386-generation processors. 287 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 288 // i486-generation processors. 289 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 290 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 291 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 292 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 293 // i586-generation processors, P5 microarchitecture based. 294 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 295 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 296 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 297 // i686-generation processors, P6 / Pentium M microarchitecture based. 298 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 299 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 300 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 301 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 302 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 303 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 304 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 305 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 306 // Netburst microarchitecture based processors. 307 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 308 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 309 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 310 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 311 // Core microarchitecture based processors. 312 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, 313 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 314 // Atom processors 315 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 316 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 317 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 318 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 319 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 320 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 321 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 322 // Nehalem microarchitecture based processors. 323 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 324 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 325 // Westmere microarchitecture based processors. 326 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 327 // Sandy Bridge microarchitecture based processors. 328 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 329 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 330 // Ivy Bridge microarchitecture based processors. 331 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 332 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 333 // Haswell microarchitecture based processors. 334 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 335 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 336 // Broadwell microarchitecture based processors. 337 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 338 // Skylake client microarchitecture based processors. 339 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 340 // Skylake server microarchitecture based processors. 341 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 342 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 343 // Cascadelake Server microarchitecture based processors. 344 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 345 // Cooperlake Server microarchitecture based processors. 346 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 347 // Cannonlake client microarchitecture based processors. 348 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 349 // Icelake client microarchitecture based processors. 350 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 351 // Icelake server microarchitecture based processors. 352 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 353 // Tigerlake microarchitecture based processors. 354 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 355 // Sapphire Rapids microarchitecture based processors. 356 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids }, 357 // Knights Landing processor. 358 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 359 // Knights Mill processor. 360 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 361 // Lakemont microarchitecture based processors. 362 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 363 // K6 architecture processors. 364 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 365 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 366 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 367 // K7 architecture processors. 368 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 369 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 370 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 371 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 372 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 373 // K8 architecture processors. 374 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 375 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 376 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 377 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 378 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 379 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 380 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 381 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 382 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 383 // Bobcat architecture processors. 384 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 385 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 386 // Bulldozer architecture processors. 387 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 388 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 389 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 390 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 391 // Zen architecture processors. 392 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 393 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 394 // Generic 64-bit processor. 395 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 396 { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 }, 397 { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 }, 398 { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 }, 399 // Geode processors. 400 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 401 }; 402 403 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"}; 404 405 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 406 for (const auto &P : Processors) 407 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) 408 return P.Kind; 409 410 return CK_None; 411 } 412 413 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) { 414 if (llvm::is_contained(NoTuneList, CPU)) 415 return CK_None; 416 return parseArchX86(CPU, Only64Bit); 417 } 418 419 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 420 bool Only64Bit) { 421 for (const auto &P : Processors) 422 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit)) 423 Values.emplace_back(P.Name); 424 } 425 426 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values, 427 bool Only64Bit) { 428 for (const ProcInfo &P : Processors) 429 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) && 430 !llvm::is_contained(NoTuneList, P.Name)) 431 Values.emplace_back(P.Name); 432 } 433 434 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 435 // FIXME: Can we avoid a linear search here? The table might be sorted by 436 // CPUKind so we could binary search? 437 for (const auto &P : Processors) { 438 if (P.Kind == Kind) { 439 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 440 return static_cast<ProcessorFeatures>(P.KeyFeature); 441 } 442 } 443 444 llvm_unreachable("Unable to find CPU kind!"); 445 } 446 447 // Features with no dependencies. 448 constexpr FeatureBitset ImpliedFeatures64BIT = {}; 449 constexpr FeatureBitset ImpliedFeaturesADX = {}; 450 constexpr FeatureBitset ImpliedFeaturesBMI = {}; 451 constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 452 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 453 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 454 constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 455 constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 456 constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 457 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 458 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 459 constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 460 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 461 constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 462 constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 463 constexpr FeatureBitset ImpliedFeaturesLWP = {}; 464 constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 465 constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 466 constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 467 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 468 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 469 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 470 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 471 constexpr FeatureBitset ImpliedFeaturesPKU = {}; 472 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 473 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 474 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 475 constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 476 constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 477 constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 478 constexpr FeatureBitset ImpliedFeaturesRTM = {}; 479 constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 480 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 481 constexpr FeatureBitset ImpliedFeaturesSGX = {}; 482 constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 483 constexpr FeatureBitset ImpliedFeaturesTBM = {}; 484 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 485 constexpr FeatureBitset ImpliedFeaturesUINTR = {}; 486 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 487 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 488 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 489 constexpr FeatureBitset ImpliedFeaturesX87 = {}; 490 constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 491 492 // Not really CPU features, but need to be in the table because clang uses 493 // target features to communicate them to the backend. 494 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 495 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 496 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 497 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 498 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 499 500 // XSAVE features are dependent on basic XSAVE. 501 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 502 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 503 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 504 505 // MMX->3DNOW->3DNOWA chain. 506 constexpr FeatureBitset ImpliedFeaturesMMX = {}; 507 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 508 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 509 510 // SSE/AVX/AVX512F chain. 511 constexpr FeatureBitset ImpliedFeaturesSSE = {}; 512 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 513 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 514 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 515 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 516 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 517 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 518 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 519 constexpr FeatureBitset ImpliedFeaturesAVX512F = 520 FeatureAVX2 | FeatureF16C | FeatureFMA; 521 522 // Vector extensions that build on SSE or AVX. 523 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 524 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 525 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 526 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 527 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 528 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 529 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; 530 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL; 531 532 // AVX512 features. 533 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 534 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 535 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 536 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 537 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 538 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 539 540 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 541 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 542 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 543 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 544 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 545 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 546 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 547 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F; 548 549 // FIXME: These two aren't really implemented and just exist in the feature 550 // list for __builtin_cpu_supports. So omit their dependencies. 551 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 552 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 553 554 // SSE4_A->FMA4->XOP chain. 555 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3; 556 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 557 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 558 559 // AMX Features 560 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 561 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 562 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 563 constexpr FeatureBitset ImpliedFeaturesHRESET = {}; 564 565 // Key Locker Features 566 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2; 567 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL; 568 569 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 570 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM}, 571 #include "llvm/Support/X86TargetParser.def" 572 }; 573 574 void llvm::X86::getFeaturesForCPU(StringRef CPU, 575 SmallVectorImpl<StringRef> &EnabledFeatures) { 576 auto I = llvm::find_if(Processors, 577 [&](const ProcInfo &P) { return P.Name == CPU; }); 578 assert(I != std::end(Processors) && "Processor not found!"); 579 580 FeatureBitset Bits = I->Features; 581 582 // Remove the 64-bit feature which we only use to validate if a CPU can 583 // be used with 64-bit mode. 584 Bits &= ~Feature64BIT; 585 586 // Add the string version of all set bits. 587 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 588 if (Bits[i] && !FeatureInfos[i].Name.empty()) 589 EnabledFeatures.push_back(FeatureInfos[i].Name); 590 } 591 592 // For each feature that is (transitively) implied by this feature, set it. 593 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 594 const FeatureBitset &Implies) { 595 // Fast path: Implies is often empty. 596 if (!Implies.any()) 597 return; 598 FeatureBitset Prev; 599 Bits |= Implies; 600 do { 601 Prev = Bits; 602 for (unsigned i = CPU_FEATURE_MAX; i;) 603 if (Bits[--i]) 604 Bits |= FeatureInfos[i].ImpliedFeatures; 605 } while (Prev != Bits); 606 } 607 608 /// Create bit vector of features that are implied disabled if the feature 609 /// passed in Value is disabled. 610 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 611 // Check all features looking for any dependent on this feature. If we find 612 // one, mark it and recursively find any feature that depend on it. 613 FeatureBitset Prev; 614 Bits.set(Value); 615 do { 616 Prev = Bits; 617 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 618 if ((FeatureInfos[i].ImpliedFeatures & Bits).any()) 619 Bits.set(i); 620 } while (Prev != Bits); 621 } 622 623 void llvm::X86::updateImpliedFeatures( 624 StringRef Feature, bool Enabled, 625 StringMap<bool> &Features) { 626 auto I = llvm::find_if( 627 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; }); 628 if (I == std::end(FeatureInfos)) { 629 // FIXME: This shouldn't happen, but may not have all features in the table 630 // yet. 631 return; 632 } 633 634 FeatureBitset ImpliedBits; 635 if (Enabled) 636 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 637 else 638 getImpliedDisabledFeatures(ImpliedBits, 639 std::distance(std::begin(FeatureInfos), I)); 640 641 // Update the map entry for all implied features. 642 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 643 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty()) 644 Features[FeatureInfos[i].Name] = Enabled; 645 } 646