1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 /// Container class for CPU features. 23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 24 /// nice to use std::bitset directly, but it doesn't support constant 25 /// initialization. 26 class FeatureBitset { 27 static constexpr unsigned NUM_FEATURE_WORDS = 28 (X86::CPU_FEATURE_MAX + 31) / 32; 29 30 // This cannot be a std::array, operator[] is not constexpr until C++17. 31 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 32 33 public: 34 constexpr FeatureBitset() = default; 35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 36 for (auto I : Init) 37 set(I); 38 } 39 40 bool any() const { 41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; }); 42 } 43 44 constexpr FeatureBitset &set(unsigned I) { 45 // GCC <6.2 crashes if this is written in a single statement. 46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 47 Bits[I / 32] = NewBits; 48 return *this; 49 } 50 51 constexpr bool operator[](unsigned I) const { 52 uint32_t Mask = uint32_t(1) << (I % 32); 53 return (Bits[I / 32] & Mask) != 0; 54 } 55 56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { 57 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 58 // GCC <6.2 crashes if this is written in a single statement. 59 uint32_t NewBits = Bits[I] & RHS.Bits[I]; 60 Bits[I] = NewBits; 61 } 62 return *this; 63 } 64 65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { 66 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 67 // GCC <6.2 crashes if this is written in a single statement. 68 uint32_t NewBits = Bits[I] | RHS.Bits[I]; 69 Bits[I] = NewBits; 70 } 71 return *this; 72 } 73 74 // gcc 5.3 miscompiles this if we try to write this using operator&=. 75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 76 FeatureBitset Result; 77 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 78 Result.Bits[I] = Bits[I] & RHS.Bits[I]; 79 return Result; 80 } 81 82 // gcc 5.3 miscompiles this if we try to write this using operator&=. 83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 84 FeatureBitset Result; 85 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 86 Result.Bits[I] = Bits[I] | RHS.Bits[I]; 87 return Result; 88 } 89 90 constexpr FeatureBitset operator~() const { 91 FeatureBitset Result; 92 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 93 Result.Bits[I] = ~Bits[I]; 94 return Result; 95 } 96 97 constexpr bool operator!=(const FeatureBitset &RHS) const { 98 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 99 if (Bits[I] != RHS.Bits[I]) 100 return true; 101 return false; 102 } 103 }; 104 105 struct ProcInfo { 106 StringLiteral Name; 107 X86::CPUKind Kind; 108 unsigned KeyFeature; 109 FeatureBitset Features; 110 }; 111 112 struct FeatureInfo { 113 StringLiteral Name; 114 FeatureBitset ImpliedFeatures; 115 }; 116 117 } // end anonymous namespace 118 119 #define X86_FEATURE(ENUM, STRING) \ 120 static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 121 #include "llvm/Support/X86TargetParser.def" 122 123 // Pentium with MMX. 124 static constexpr FeatureBitset FeaturesPentiumMMX = 125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 126 127 // Pentium 2 and 3. 128 static constexpr FeatureBitset FeaturesPentium2 = 129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 130 static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 131 132 // Pentium 4 CPUs 133 static constexpr FeatureBitset FeaturesPentium4 = 134 FeaturesPentium3 | FeatureSSE2; 135 static constexpr FeatureBitset FeaturesPrescott = 136 FeaturesPentium4 | FeatureSSE3; 137 static constexpr FeatureBitset FeaturesNocona = 138 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; 139 140 // Basic 64-bit capable CPU. 141 static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; 142 143 // Intel Core CPUs 144 static constexpr FeatureBitset FeaturesCore2 = 145 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 146 static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 147 static constexpr FeatureBitset FeaturesNehalem = 148 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; 149 static constexpr FeatureBitset FeaturesWestmere = 150 FeaturesNehalem | FeaturePCLMUL; 151 static constexpr FeatureBitset FeaturesSandyBridge = 152 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 153 static constexpr FeatureBitset FeaturesIvyBridge = 154 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 155 static constexpr FeatureBitset FeaturesHaswell = 156 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 157 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 158 static constexpr FeatureBitset FeaturesBroadwell = 159 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 160 161 // Intel Knights Landing and Knights Mill 162 // Knights Landing has feature parity with Broadwell. 163 static constexpr FeatureBitset FeaturesKNL = 164 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 165 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 166 static constexpr FeatureBitset FeaturesKNM = 167 FeaturesKNL | FeatureAVX512VPOPCNTDQ; 168 169 // Intel Skylake processors. 170 static constexpr FeatureBitset FeaturesSkylakeClient = 171 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 172 FeatureXSAVES | FeatureSGX; 173 // SkylakeServer inherits all SkylakeClient features except SGX. 174 // FIXME: That doesn't match gcc. 175 static constexpr FeatureBitset FeaturesSkylakeServer = 176 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 177 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 178 FeaturePKU; 179 static constexpr FeatureBitset FeaturesCascadeLake = 180 FeaturesSkylakeServer | FeatureAVX512VNNI; 181 static constexpr FeatureBitset FeaturesCooperLake = 182 FeaturesCascadeLake | FeatureAVX512BF16; 183 184 // Intel 10nm processors. 185 static constexpr FeatureBitset FeaturesCannonlake = 186 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 187 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 188 FeaturePKU | FeatureSHA; 189 static constexpr FeatureBitset FeaturesICLClient = 190 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 191 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI | 192 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ; 193 static constexpr FeatureBitset FeaturesICLServer = 194 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD; 195 static constexpr FeatureBitset FeaturesTigerlake = 196 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 197 FeatureMOVDIRI | FeatureSHSTK; 198 static constexpr FeatureBitset FeaturesSapphireRapids = 199 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 | 200 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE | FeatureENQCMD | 201 FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | 202 FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG; 203 204 // Intel Atom processors. 205 // Bonnell has feature parity with Core2 and adds MOVBE. 206 static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 207 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 208 static constexpr FeatureBitset FeaturesSilvermont = 209 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 210 static constexpr FeatureBitset FeaturesGoldmont = 211 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 212 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 213 FeatureXSAVEOPT | FeatureXSAVES; 214 static constexpr FeatureBitset FeaturesGoldmontPlus = 215 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 216 static constexpr FeatureBitset FeaturesTremont = 217 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 218 219 // Geode Processor. 220 static constexpr FeatureBitset FeaturesGeode = 221 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 222 223 // K6 processor. 224 static constexpr FeatureBitset FeaturesK6 = 225 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 226 227 // K7 and K8 architecture processors. 228 static constexpr FeatureBitset FeaturesAthlon = 229 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 230 static constexpr FeatureBitset FeaturesAthlonXP = 231 FeaturesAthlon | FeatureFXSR | FeatureSSE; 232 static constexpr FeatureBitset FeaturesK8 = 233 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; 234 static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 235 static constexpr FeatureBitset FeaturesAMDFAM10 = 236 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 237 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 238 239 // Bobcat architecture processors. 240 static constexpr FeatureBitset FeaturesBTVER1 = 241 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | 242 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 243 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 244 FeatureSAHF; 245 static constexpr FeatureBitset FeaturesBTVER2 = 246 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | 247 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 248 249 // AMD Bulldozer architecture processors. 250 static constexpr FeatureBitset FeaturesBDVER1 = 251 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 252 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP | 253 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | 254 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | 255 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; 256 static constexpr FeatureBitset FeaturesBDVER2 = 257 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 258 static constexpr FeatureBitset FeaturesBDVER3 = 259 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 260 static constexpr FeatureBitset FeaturesBDVER4 = 261 FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX | 262 FeatureRDRND; 263 264 // AMD Zen architecture processors. 265 static constexpr FeatureBitset FeaturesZNVER1 = 266 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 267 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 268 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C | 269 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | 270 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 271 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 272 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 273 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 274 FeatureXSAVEOPT | FeatureXSAVES; 275 static constexpr FeatureBitset FeaturesZNVER2 = 276 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD; 277 278 static constexpr ProcInfo Processors[] = { 279 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 280 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 281 // i386-generation processors. 282 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 283 // i486-generation processors. 284 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 285 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 286 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 287 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 288 // i586-generation processors, P5 microarchitecture based. 289 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 290 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 291 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 292 // i686-generation processors, P6 / Pentium M microarchitecture based. 293 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 294 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 295 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 296 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 297 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 298 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 299 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 300 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 301 // Netburst microarchitecture based processors. 302 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 303 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 304 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 305 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 306 // Core microarchitecture based processors. 307 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, 308 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 309 // Atom processors 310 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 311 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 312 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 313 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 314 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 315 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 316 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 317 // Nehalem microarchitecture based processors. 318 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 319 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 320 // Westmere microarchitecture based processors. 321 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 322 // Sandy Bridge microarchitecture based processors. 323 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 324 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 325 // Ivy Bridge microarchitecture based processors. 326 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 327 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 328 // Haswell microarchitecture based processors. 329 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 330 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 331 // Broadwell microarchitecture based processors. 332 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 333 // Skylake client microarchitecture based processors. 334 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 335 // Skylake server microarchitecture based processors. 336 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 337 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 338 // Cascadelake Server microarchitecture based processors. 339 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 340 // Cooperlake Server microarchitecture based processors. 341 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 342 // Cannonlake client microarchitecture based processors. 343 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 344 // Icelake client microarchitecture based processors. 345 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 346 // Icelake server microarchitecture based processors. 347 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 348 // Tigerlake microarchitecture based processors. 349 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 350 // Sapphire Rapids microarchitecture based processors. 351 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids }, 352 // Knights Landing processor. 353 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 354 // Knights Mill processor. 355 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 356 // Lakemont microarchitecture based processors. 357 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 358 // K6 architecture processors. 359 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 360 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 361 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 362 // K7 architecture processors. 363 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 364 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 365 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 366 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 367 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 368 // K8 architecture processors. 369 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 370 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 371 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 372 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 373 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 374 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 375 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 376 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 377 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 378 // Bobcat architecture processors. 379 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 380 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 381 // Bulldozer architecture processors. 382 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 383 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 384 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 385 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 386 // Zen architecture processors. 387 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 388 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 389 // Generic 64-bit processor. 390 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 391 // Geode processors. 392 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 393 }; 394 395 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 396 for (const auto &P : Processors) 397 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) 398 return P.Kind; 399 400 return CK_None; 401 } 402 403 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 404 bool Only64Bit) { 405 for (const auto &P : Processors) 406 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit)) 407 Values.emplace_back(P.Name); 408 } 409 410 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 411 // FIXME: Can we avoid a linear search here? The table might be sorted by 412 // CPUKind so we could binary search? 413 for (const auto &P : Processors) { 414 if (P.Kind == Kind) { 415 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 416 return static_cast<ProcessorFeatures>(P.KeyFeature); 417 } 418 } 419 420 llvm_unreachable("Unable to find CPU kind!"); 421 } 422 423 // Features with no dependencies. 424 static constexpr FeatureBitset ImpliedFeatures64BIT = {}; 425 static constexpr FeatureBitset ImpliedFeaturesADX = {}; 426 static constexpr FeatureBitset ImpliedFeaturesBMI = {}; 427 static constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 428 static constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 429 static constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 430 static constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 431 static constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 432 static constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 433 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 434 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 435 static constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 436 static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 437 static constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 438 static constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 439 static constexpr FeatureBitset ImpliedFeaturesLWP = {}; 440 static constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 441 static constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 442 static constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 443 static constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 444 static constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 445 static constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 446 static constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 447 static constexpr FeatureBitset ImpliedFeaturesPKU = {}; 448 static constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 449 static constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 450 static constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 451 static constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 452 static constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 453 static constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 454 static constexpr FeatureBitset ImpliedFeaturesRTM = {}; 455 static constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 456 static constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 457 static constexpr FeatureBitset ImpliedFeaturesSGX = {}; 458 static constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 459 static constexpr FeatureBitset ImpliedFeaturesTBM = {}; 460 static constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 461 static constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 462 static constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 463 static constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 464 static constexpr FeatureBitset ImpliedFeaturesX87 = {}; 465 static constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 466 467 // Not really CPU features, but need to be in the table because clang uses 468 // target features to communicate them to the backend. 469 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 470 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 471 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 472 static constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 473 static constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 474 475 // XSAVE features are dependent on basic XSAVE. 476 static constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 477 static constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 478 static constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 479 480 // MMX->3DNOW->3DNOWA chain. 481 static constexpr FeatureBitset ImpliedFeaturesMMX = {}; 482 static constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 483 static constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 484 485 // SSE/AVX/AVX512F chain. 486 static constexpr FeatureBitset ImpliedFeaturesSSE = {}; 487 static constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 488 static constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 489 static constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 490 static constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 491 static constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 492 static constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 493 static constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 494 static constexpr FeatureBitset ImpliedFeaturesAVX512F = 495 FeatureAVX2 | FeatureF16C | FeatureFMA; 496 497 // Vector extensions that build on SSE or AVX. 498 static constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 499 static constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 500 static constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 501 static constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 502 static constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 503 static constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 504 static constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; 505 static constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = 506 FeatureAVX | FeaturePCLMUL; 507 508 // AVX512 features. 509 static constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 510 static constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 511 static constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 512 static constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 513 static constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 514 static constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 515 516 static constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 517 static constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 518 static constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 519 static constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 520 static constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 521 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 522 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 523 static constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = 524 FeatureAVX512F; 525 526 // FIXME: These two aren't really implemented and just exist in the feature 527 // list for __builtin_cpu_supports. So omit their dependencies. 528 static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 529 static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 530 531 // SSE4_A->FMA4->XOP chain. 532 static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3; 533 static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 534 static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 535 536 // AMX Features 537 static constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 538 static constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 539 static constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 540 541 static constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 542 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM}, 543 #include "llvm/Support/X86TargetParser.def" 544 }; 545 546 void llvm::X86::getFeaturesForCPU(StringRef CPU, 547 SmallVectorImpl<StringRef> &EnabledFeatures) { 548 auto I = llvm::find_if(Processors, 549 [&](const ProcInfo &P) { return P.Name == CPU; }); 550 assert(I != std::end(Processors) && "Processor not found!"); 551 552 FeatureBitset Bits = I->Features; 553 554 // Remove the 64-bit feature which we only use to validate if a CPU can 555 // be used with 64-bit mode. 556 Bits &= ~Feature64BIT; 557 558 // Add the string version of all set bits. 559 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 560 if (Bits[i] && !FeatureInfos[i].Name.empty()) 561 EnabledFeatures.push_back(FeatureInfos[i].Name); 562 } 563 564 // For each feature that is (transitively) implied by this feature, set it. 565 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 566 const FeatureBitset &Implies) { 567 // Fast path: Implies is often empty. 568 if (!Implies.any()) 569 return; 570 FeatureBitset Prev; 571 Bits |= Implies; 572 do { 573 Prev = Bits; 574 for (unsigned i = CPU_FEATURE_MAX; i;) 575 if (Bits[--i]) 576 Bits |= FeatureInfos[i].ImpliedFeatures; 577 } while (Prev != Bits); 578 } 579 580 /// Create bit vector of features that are implied disabled if the feature 581 /// passed in Value is disabled. 582 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 583 // Check all features looking for any dependent on this feature. If we find 584 // one, mark it and recursively find any feature that depend on it. 585 FeatureBitset Prev; 586 Bits.set(Value); 587 do { 588 Prev = Bits; 589 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 590 if ((FeatureInfos[i].ImpliedFeatures & Bits).any()) 591 Bits.set(i); 592 } while (Prev != Bits); 593 } 594 595 void llvm::X86::updateImpliedFeatures( 596 StringRef Feature, bool Enabled, 597 StringMap<bool> &Features) { 598 auto I = llvm::find_if( 599 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; }); 600 if (I == std::end(FeatureInfos)) { 601 // FIXME: This shouldn't happen, but may not have all features in the table 602 // yet. 603 return; 604 } 605 606 FeatureBitset ImpliedBits; 607 if (Enabled) 608 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 609 else 610 getImpliedDisabledFeatures(ImpliedBits, 611 std::distance(std::begin(FeatureInfos), I)); 612 613 // Update the map entry for all implied features. 614 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 615 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty()) 616 Features[FeatureInfos[i].Name] = Enabled; 617 } 618