1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 struct ProcInfo { 23 StringLiteral Name; 24 X86::CPUKind Kind; 25 unsigned KeyFeature; 26 bool Is64Bit; 27 }; 28 29 } // end anonymous namespace 30 31 #define PROC_64_BIT true 32 #define PROC_32_BIT false 33 34 static constexpr ProcInfo Processors[] = { 35 // i386-generation processors. 36 { {"i386"}, CK_i386, ~0U, PROC_32_BIT }, 37 // i486-generation processors. 38 { {"i486"}, CK_i486, ~0U, PROC_32_BIT }, 39 { {"winchip-c6"}, CK_WinChipC6, ~0U, PROC_32_BIT }, 40 { {"winchip2"}, CK_WinChip2, ~0U, PROC_32_BIT }, 41 { {"c3"}, CK_C3, ~0U, PROC_32_BIT }, 42 // i586-generation processors, P5 microarchitecture based. 43 { {"i586"}, CK_i586, ~0U, PROC_32_BIT }, 44 { {"pentium"}, CK_Pentium, ~0U, PROC_32_BIT }, 45 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, PROC_32_BIT }, 46 { {"pentiumpro"}, CK_PentiumPro, ~0U, PROC_32_BIT }, 47 // i686-generation processors, P6 / Pentium M microarchitecture based. 48 { {"i686"}, CK_i686, ~0U, PROC_32_BIT }, 49 { {"pentium2"}, CK_Pentium2, ~0U, PROC_32_BIT }, 50 { {"pentium3"}, CK_Pentium3, ~0U, PROC_32_BIT }, 51 { {"pentium3m"}, CK_Pentium3, ~0U, PROC_32_BIT }, 52 { {"pentium-m"}, CK_PentiumM, ~0U, PROC_32_BIT }, 53 { {"c3-2"}, CK_C3_2, ~0U, PROC_32_BIT }, 54 { {"yonah"}, CK_Yonah, ~0U, PROC_32_BIT }, 55 // Netburst microarchitecture based processors. 56 { {"pentium4"}, CK_Pentium4, ~0U, PROC_32_BIT }, 57 { {"pentium4m"}, CK_Pentium4, ~0U, PROC_32_BIT }, 58 { {"prescott"}, CK_Prescott, ~0U, PROC_32_BIT }, 59 { {"nocona"}, CK_Nocona, ~0U, PROC_64_BIT }, 60 // Core microarchitecture based processors. 61 { {"core2"}, CK_Core2, ~0U, PROC_64_BIT }, 62 { {"penryn"}, CK_Penryn, ~0U, PROC_64_BIT }, 63 // Atom processors 64 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, PROC_64_BIT }, 65 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, PROC_64_BIT }, 66 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, PROC_64_BIT }, 67 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, PROC_64_BIT }, 68 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, PROC_64_BIT }, 69 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, PROC_64_BIT }, 70 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, PROC_64_BIT }, 71 // Nehalem microarchitecture based processors. 72 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, PROC_64_BIT }, 73 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, PROC_64_BIT }, 74 // Westmere microarchitecture based processors. 75 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, PROC_64_BIT }, 76 // Sandy Bridge microarchitecture based processors. 77 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, PROC_64_BIT }, 78 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, PROC_64_BIT }, 79 // Ivy Bridge microarchitecture based processors. 80 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, PROC_64_BIT }, 81 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, PROC_64_BIT }, 82 // Haswell microarchitecture based processors. 83 { {"haswell"}, CK_Haswell, FEATURE_AVX2, PROC_64_BIT }, 84 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, PROC_64_BIT }, 85 // Broadwell microarchitecture based processors. 86 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, PROC_64_BIT }, 87 // Skylake client microarchitecture based processors. 88 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, PROC_64_BIT }, 89 // Skylake server microarchitecture based processors. 90 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, PROC_64_BIT }, 91 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, PROC_64_BIT }, 92 // Cascadelake Server microarchitecture based processors. 93 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, PROC_64_BIT }, 94 // Cooperlake Server microarchitecture based processors. 95 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, PROC_64_BIT }, 96 // Cannonlake client microarchitecture based processors. 97 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, PROC_64_BIT }, 98 // Icelake client microarchitecture based processors. 99 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, PROC_64_BIT }, 100 // Icelake server microarchitecture based processors. 101 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, PROC_64_BIT }, 102 // Tigerlake microarchitecture based processors. 103 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, PROC_64_BIT }, 104 // Knights Landing processor. 105 { {"knl"}, CK_KNL, FEATURE_AVX512F, PROC_64_BIT }, 106 // Knights Mill processor. 107 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, PROC_64_BIT }, 108 // Lakemont microarchitecture based processors. 109 { {"lakemont"}, CK_Lakemont, ~0U, PROC_32_BIT }, 110 // K6 architecture processors. 111 { {"k6"}, CK_K6, ~0U, PROC_32_BIT }, 112 { {"k6-2"}, CK_K6_2, ~0U, PROC_32_BIT }, 113 { {"k6-3"}, CK_K6_3, ~0U, PROC_32_BIT }, 114 // K7 architecture processors. 115 { {"athlon"}, CK_Athlon, ~0U, PROC_32_BIT }, 116 { {"athlon-tbird"}, CK_Athlon, ~0U, PROC_32_BIT }, 117 { {"athlon-xp"}, CK_AthlonXP, ~0U, PROC_32_BIT }, 118 { {"athlon-mp"}, CK_AthlonXP, ~0U, PROC_32_BIT }, 119 { {"athlon-4"}, CK_AthlonXP, ~0U, PROC_32_BIT }, 120 // K8 architecture processors. 121 { {"k8"}, CK_K8, ~0U, PROC_64_BIT }, 122 { {"athlon64"}, CK_K8, ~0U, PROC_64_BIT }, 123 { {"athlon-fx"}, CK_K8, ~0U, PROC_64_BIT }, 124 { {"opteron"}, CK_K8, ~0U, PROC_64_BIT }, 125 { {"k8-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT }, 126 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT }, 127 { {"opteron-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT }, 128 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, PROC_64_BIT }, 129 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, PROC_64_BIT }, 130 // Bobcat architecture processors. 131 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, PROC_64_BIT }, 132 { {"btver2"}, CK_BTVER2, FEATURE_BMI, PROC_64_BIT }, 133 // Bulldozer architecture processors. 134 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, PROC_64_BIT }, 135 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, PROC_64_BIT }, 136 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, PROC_64_BIT }, 137 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, PROC_64_BIT }, 138 // Zen architecture processors. 139 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, PROC_64_BIT }, 140 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, PROC_64_BIT }, 141 // Generic 64-bit processor. 142 { {"x86-64"}, CK_x86_64, ~0U, PROC_64_BIT }, 143 // Geode processors. 144 { {"geode"}, CK_Geode, ~0U, PROC_32_BIT }, 145 }; 146 147 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 148 for (const auto &P : Processors) 149 if (P.Name == CPU && (P.Is64Bit || !Only64Bit)) 150 return P.Kind; 151 152 return CK_None; 153 } 154 155 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 156 bool Only64Bit) { 157 for (const auto &P : Processors) 158 if (P.Is64Bit || !Only64Bit) 159 Values.emplace_back(P.Name); 160 } 161 162 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 163 // FIXME: Can we avoid a linear search here? The table might be sorted by 164 // CPUKind so we could binary search? 165 for (const auto &P : Processors) { 166 if (P.Kind == Kind) { 167 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 168 return static_cast<ProcessorFeatures>(P.KeyFeature); 169 } 170 } 171 172 llvm_unreachable("Unable to find CPU kind!"); 173 } 174