1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 /// Container class for CPU features. 23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 24 /// nice to use std::bitset directly, but it doesn't support constant 25 /// initialization. 26 class FeatureBitset { 27 static constexpr unsigned NUM_FEATURE_WORDS = 28 (X86::CPU_FEATURE_MAX + 31) / 32; 29 30 // This cannot be a std::array, operator[] is not constexpr until C++17. 31 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 32 33 public: 34 constexpr FeatureBitset() = default; 35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 36 for (auto I : Init) 37 set(I); 38 } 39 40 bool any() const { 41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; }); 42 } 43 44 constexpr FeatureBitset &set(unsigned I) { 45 // GCC <6.2 crashes if this is written in a single statement. 46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 47 Bits[I / 32] = NewBits; 48 return *this; 49 } 50 51 constexpr bool operator[](unsigned I) const { 52 uint32_t Mask = uint32_t(1) << (I % 32); 53 return (Bits[I / 32] & Mask) != 0; 54 } 55 56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { 57 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 58 // GCC <6.2 crashes if this is written in a single statement. 59 uint32_t NewBits = Bits[I] & RHS.Bits[I]; 60 Bits[I] = NewBits; 61 } 62 return *this; 63 } 64 65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { 66 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 67 // GCC <6.2 crashes if this is written in a single statement. 68 uint32_t NewBits = Bits[I] | RHS.Bits[I]; 69 Bits[I] = NewBits; 70 } 71 return *this; 72 } 73 74 // gcc 5.3 miscompiles this if we try to write this using operator&=. 75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 76 FeatureBitset Result; 77 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 78 Result.Bits[I] = Bits[I] & RHS.Bits[I]; 79 return Result; 80 } 81 82 // gcc 5.3 miscompiles this if we try to write this using operator&=. 83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 84 FeatureBitset Result; 85 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 86 Result.Bits[I] = Bits[I] | RHS.Bits[I]; 87 return Result; 88 } 89 90 constexpr FeatureBitset operator~() const { 91 FeatureBitset Result; 92 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 93 Result.Bits[I] = ~Bits[I]; 94 return Result; 95 } 96 97 constexpr bool operator!=(const FeatureBitset &RHS) const { 98 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 99 if (Bits[I] != RHS.Bits[I]) 100 return true; 101 return false; 102 } 103 }; 104 105 struct ProcInfo { 106 StringLiteral Name; 107 X86::CPUKind Kind; 108 unsigned KeyFeature; 109 FeatureBitset Features; 110 }; 111 112 struct FeatureInfo { 113 StringLiteral Name; 114 FeatureBitset ImpliedFeatures; 115 }; 116 117 } // end anonymous namespace 118 119 #define X86_FEATURE(ENUM, STRING) \ 120 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 121 #include "llvm/Support/X86TargetParser.def" 122 123 // Pentium with MMX. 124 constexpr FeatureBitset FeaturesPentiumMMX = 125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 126 127 // Pentium 2 and 3. 128 constexpr FeatureBitset FeaturesPentium2 = 129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 130 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 131 132 // Pentium 4 CPUs 133 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2; 134 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3; 135 constexpr FeatureBitset FeaturesNocona = 136 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; 137 138 // Basic 64-bit capable CPU. 139 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; 140 141 // Intel Core CPUs 142 constexpr FeatureBitset FeaturesCore2 = 143 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 144 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 145 constexpr FeatureBitset FeaturesNehalem = 146 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; 147 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL; 148 constexpr FeatureBitset FeaturesSandyBridge = 149 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 150 constexpr FeatureBitset FeaturesIvyBridge = 151 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 152 constexpr FeatureBitset FeaturesHaswell = 153 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 154 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 155 constexpr FeatureBitset FeaturesBroadwell = 156 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 157 158 // Intel Knights Landing and Knights Mill 159 // Knights Landing has feature parity with Broadwell. 160 constexpr FeatureBitset FeaturesKNL = 161 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 162 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 163 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ; 164 165 // Intel Skylake processors. 166 constexpr FeatureBitset FeaturesSkylakeClient = 167 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 168 FeatureXSAVES | FeatureSGX; 169 // SkylakeServer inherits all SkylakeClient features except SGX. 170 // FIXME: That doesn't match gcc. 171 constexpr FeatureBitset FeaturesSkylakeServer = 172 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 173 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 174 FeaturePKU; 175 constexpr FeatureBitset FeaturesCascadeLake = 176 FeaturesSkylakeServer | FeatureAVX512VNNI; 177 constexpr FeatureBitset FeaturesCooperLake = 178 FeaturesCascadeLake | FeatureAVX512BF16; 179 180 // Intel 10nm processors. 181 constexpr FeatureBitset FeaturesCannonlake = 182 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 183 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 184 FeaturePKU | FeatureSHA; 185 constexpr FeatureBitset FeaturesICLClient = 186 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 187 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI | 188 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ; 189 constexpr FeatureBitset FeaturesICLServer = 190 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD; 191 constexpr FeatureBitset FeaturesTigerlake = 192 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 193 FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; 194 constexpr FeatureBitset FeaturesSapphireRapids = 195 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 | 196 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE | 197 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | 198 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG; 199 200 // Intel Atom processors. 201 // Bonnell has feature parity with Core2 and adds MOVBE. 202 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 203 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 204 constexpr FeatureBitset FeaturesSilvermont = 205 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 206 constexpr FeatureBitset FeaturesGoldmont = 207 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 208 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 209 FeatureXSAVEOPT | FeatureXSAVES; 210 constexpr FeatureBitset FeaturesGoldmontPlus = 211 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 212 constexpr FeatureBitset FeaturesTremont = 213 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 214 215 // Geode Processor. 216 constexpr FeatureBitset FeaturesGeode = 217 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 218 219 // K6 processor. 220 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 221 222 // K7 and K8 architecture processors. 223 constexpr FeatureBitset FeaturesAthlon = 224 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 225 constexpr FeatureBitset FeaturesAthlonXP = 226 FeaturesAthlon | FeatureFXSR | FeatureSSE; 227 constexpr FeatureBitset FeaturesK8 = 228 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; 229 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 230 constexpr FeatureBitset FeaturesAMDFAM10 = 231 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 232 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 233 234 // Bobcat architecture processors. 235 constexpr FeatureBitset FeaturesBTVER1 = 236 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | 237 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 238 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 239 FeatureSAHF; 240 constexpr FeatureBitset FeaturesBTVER2 = 241 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | 242 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 243 244 // AMD Bulldozer architecture processors. 245 constexpr FeatureBitset FeaturesBDVER1 = 246 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 247 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP | 248 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | 249 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | 250 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; 251 constexpr FeatureBitset FeaturesBDVER2 = 252 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 253 constexpr FeatureBitset FeaturesBDVER3 = 254 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 255 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 | 256 FeatureBMI2 | FeatureMOVBE | 257 FeatureMWAITX | FeatureRDRND; 258 259 // AMD Zen architecture processors. 260 constexpr FeatureBitset FeaturesZNVER1 = 261 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 262 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 263 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C | 264 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | 265 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 266 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 267 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 268 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 269 FeatureXSAVEOPT | FeatureXSAVES; 270 constexpr FeatureBitset FeaturesZNVER2 = 271 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD; 272 273 constexpr ProcInfo Processors[] = { 274 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 275 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 276 // i386-generation processors. 277 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 278 // i486-generation processors. 279 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 280 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 281 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 282 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 283 // i586-generation processors, P5 microarchitecture based. 284 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 285 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 286 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 287 // i686-generation processors, P6 / Pentium M microarchitecture based. 288 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 289 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 290 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 291 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 292 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 293 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 294 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 295 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 296 // Netburst microarchitecture based processors. 297 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 298 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 299 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 300 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 301 // Core microarchitecture based processors. 302 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, 303 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 304 // Atom processors 305 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 306 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 307 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 308 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 309 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 310 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 311 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 312 // Nehalem microarchitecture based processors. 313 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 314 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 315 // Westmere microarchitecture based processors. 316 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 317 // Sandy Bridge microarchitecture based processors. 318 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 319 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 320 // Ivy Bridge microarchitecture based processors. 321 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 322 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 323 // Haswell microarchitecture based processors. 324 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 325 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 326 // Broadwell microarchitecture based processors. 327 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 328 // Skylake client microarchitecture based processors. 329 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 330 // Skylake server microarchitecture based processors. 331 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 332 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 333 // Cascadelake Server microarchitecture based processors. 334 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 335 // Cooperlake Server microarchitecture based processors. 336 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 337 // Cannonlake client microarchitecture based processors. 338 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 339 // Icelake client microarchitecture based processors. 340 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 341 // Icelake server microarchitecture based processors. 342 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 343 // Tigerlake microarchitecture based processors. 344 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 345 // Sapphire Rapids microarchitecture based processors. 346 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids }, 347 // Knights Landing processor. 348 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 349 // Knights Mill processor. 350 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 351 // Lakemont microarchitecture based processors. 352 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 353 // K6 architecture processors. 354 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 355 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 356 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 357 // K7 architecture processors. 358 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 359 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 360 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 361 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 362 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 363 // K8 architecture processors. 364 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 365 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 366 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 367 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 368 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 369 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 370 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 371 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 372 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 373 // Bobcat architecture processors. 374 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 375 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 376 // Bulldozer architecture processors. 377 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 378 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 379 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 380 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 381 // Zen architecture processors. 382 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 383 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 384 // Generic 64-bit processor. 385 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 386 // Geode processors. 387 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 388 }; 389 390 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 391 for (const auto &P : Processors) 392 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) 393 return P.Kind; 394 395 return CK_None; 396 } 397 398 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 399 bool Only64Bit) { 400 for (const auto &P : Processors) 401 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit)) 402 Values.emplace_back(P.Name); 403 } 404 405 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 406 // FIXME: Can we avoid a linear search here? The table might be sorted by 407 // CPUKind so we could binary search? 408 for (const auto &P : Processors) { 409 if (P.Kind == Kind) { 410 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 411 return static_cast<ProcessorFeatures>(P.KeyFeature); 412 } 413 } 414 415 llvm_unreachable("Unable to find CPU kind!"); 416 } 417 418 // Features with no dependencies. 419 constexpr FeatureBitset ImpliedFeatures64BIT = {}; 420 constexpr FeatureBitset ImpliedFeaturesADX = {}; 421 constexpr FeatureBitset ImpliedFeaturesBMI = {}; 422 constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 423 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 424 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 425 constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 426 constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 427 constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 428 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 429 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 430 constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 431 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 432 constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 433 constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 434 constexpr FeatureBitset ImpliedFeaturesLWP = {}; 435 constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 436 constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 437 constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 438 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 439 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 440 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 441 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 442 constexpr FeatureBitset ImpliedFeaturesPKU = {}; 443 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 444 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 445 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 446 constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 447 constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 448 constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 449 constexpr FeatureBitset ImpliedFeaturesRTM = {}; 450 constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 451 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 452 constexpr FeatureBitset ImpliedFeaturesSGX = {}; 453 constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 454 constexpr FeatureBitset ImpliedFeaturesTBM = {}; 455 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 456 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 457 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 458 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 459 constexpr FeatureBitset ImpliedFeaturesX87 = {}; 460 constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 461 462 // Not really CPU features, but need to be in the table because clang uses 463 // target features to communicate them to the backend. 464 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 465 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 466 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 467 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 468 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 469 470 // XSAVE features are dependent on basic XSAVE. 471 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 472 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 473 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 474 475 // MMX->3DNOW->3DNOWA chain. 476 constexpr FeatureBitset ImpliedFeaturesMMX = {}; 477 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 478 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 479 480 // SSE/AVX/AVX512F chain. 481 constexpr FeatureBitset ImpliedFeaturesSSE = {}; 482 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 483 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 484 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 485 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 486 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 487 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 488 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 489 constexpr FeatureBitset ImpliedFeaturesAVX512F = 490 FeatureAVX2 | FeatureF16C | FeatureFMA; 491 492 // Vector extensions that build on SSE or AVX. 493 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 494 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 495 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 496 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 497 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 498 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 499 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; 500 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL; 501 502 // AVX512 features. 503 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 504 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 505 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 506 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 507 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 508 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 509 510 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 511 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 512 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 513 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 514 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 515 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 516 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 517 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F; 518 519 // FIXME: These two aren't really implemented and just exist in the feature 520 // list for __builtin_cpu_supports. So omit their dependencies. 521 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 522 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 523 524 // SSE4_A->FMA4->XOP chain. 525 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3; 526 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 527 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 528 529 // AMX Features 530 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 531 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 532 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 533 534 // Key Locker Features 535 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2; 536 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL; 537 538 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 539 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM}, 540 #include "llvm/Support/X86TargetParser.def" 541 }; 542 543 void llvm::X86::getFeaturesForCPU(StringRef CPU, 544 SmallVectorImpl<StringRef> &EnabledFeatures) { 545 auto I = llvm::find_if(Processors, 546 [&](const ProcInfo &P) { return P.Name == CPU; }); 547 assert(I != std::end(Processors) && "Processor not found!"); 548 549 FeatureBitset Bits = I->Features; 550 551 // Remove the 64-bit feature which we only use to validate if a CPU can 552 // be used with 64-bit mode. 553 Bits &= ~Feature64BIT; 554 555 // Add the string version of all set bits. 556 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 557 if (Bits[i] && !FeatureInfos[i].Name.empty()) 558 EnabledFeatures.push_back(FeatureInfos[i].Name); 559 } 560 561 // For each feature that is (transitively) implied by this feature, set it. 562 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 563 const FeatureBitset &Implies) { 564 // Fast path: Implies is often empty. 565 if (!Implies.any()) 566 return; 567 FeatureBitset Prev; 568 Bits |= Implies; 569 do { 570 Prev = Bits; 571 for (unsigned i = CPU_FEATURE_MAX; i;) 572 if (Bits[--i]) 573 Bits |= FeatureInfos[i].ImpliedFeatures; 574 } while (Prev != Bits); 575 } 576 577 /// Create bit vector of features that are implied disabled if the feature 578 /// passed in Value is disabled. 579 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 580 // Check all features looking for any dependent on this feature. If we find 581 // one, mark it and recursively find any feature that depend on it. 582 FeatureBitset Prev; 583 Bits.set(Value); 584 do { 585 Prev = Bits; 586 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 587 if ((FeatureInfos[i].ImpliedFeatures & Bits).any()) 588 Bits.set(i); 589 } while (Prev != Bits); 590 } 591 592 void llvm::X86::updateImpliedFeatures( 593 StringRef Feature, bool Enabled, 594 StringMap<bool> &Features) { 595 auto I = llvm::find_if( 596 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; }); 597 if (I == std::end(FeatureInfos)) { 598 // FIXME: This shouldn't happen, but may not have all features in the table 599 // yet. 600 return; 601 } 602 603 FeatureBitset ImpliedBits; 604 if (Enabled) 605 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 606 else 607 getImpliedDisabledFeatures(ImpliedBits, 608 std::distance(std::begin(FeatureInfos), I)); 609 610 // Update the map entry for all implied features. 611 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 612 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty()) 613 Features[FeatureInfos[i].Name] = Enabled; 614 } 615