1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 /// Container class for CPU features. 23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 24 /// nice to use std::bitset directly, but it doesn't support constant 25 /// initialization. 26 class FeatureBitset { 27 static constexpr unsigned NUM_FEATURE_WORDS = 28 (X86::CPU_FEATURE_MAX + 31) / 32; 29 30 // This cannot be a std::array, operator[] is not constexpr until C++17. 31 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 32 33 public: 34 constexpr FeatureBitset() = default; 35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 36 for (auto I : Init) 37 set(I); 38 } 39 40 constexpr FeatureBitset &set(unsigned I) { 41 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 42 Bits[I / 32] = NewBits; 43 return *this; 44 } 45 46 constexpr bool operator[](unsigned I) const { 47 uint32_t Mask = uint32_t(1) << (I % 32); 48 return (Bits[I / 32] & Mask) != 0; 49 } 50 51 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 52 FeatureBitset Result; 53 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 54 Result.Bits[I] = Bits[I] & RHS.Bits[I]; 55 return Result; 56 } 57 58 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 59 FeatureBitset Result; 60 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 61 Result.Bits[I] = Bits[I] | RHS.Bits[I]; 62 return Result; 63 } 64 65 constexpr FeatureBitset operator~() const { 66 FeatureBitset Result; 67 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 68 Result.Bits[I] = ~Bits[I]; 69 return Result; 70 } 71 }; 72 73 struct ProcInfo { 74 StringLiteral Name; 75 X86::CPUKind Kind; 76 unsigned KeyFeature; 77 FeatureBitset Features; 78 }; 79 80 } // end anonymous namespace 81 82 #define X86_FEATURE(ENUM, STRING) \ 83 static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 84 #include "llvm/Support/X86TargetParser.def" 85 86 // Pentium with MMX. 87 static constexpr FeatureBitset FeaturesPentiumMMX = 88 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 89 90 // Pentium 2 and 3. 91 static constexpr FeatureBitset FeaturesPentium2 = 92 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 93 static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 94 95 // Pentium 4 CPUs 96 static constexpr FeatureBitset FeaturesPentium4 = 97 FeaturesPentium3 | FeatureSSE2; 98 static constexpr FeatureBitset FeaturesPrescott = 99 FeaturesPentium4 | FeatureSSE3; 100 static constexpr FeatureBitset FeaturesNocona = 101 FeaturesPrescott | FeatureEM64T | FeatureCMPXCHG16B; 102 103 // Basic 64-bit capable CPU. 104 static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | FeatureEM64T; 105 106 // Intel Core CPUs 107 static constexpr FeatureBitset FeaturesCore2 = 108 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 109 static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 110 static constexpr FeatureBitset FeaturesNehalem = 111 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; 112 static constexpr FeatureBitset FeaturesWestmere = 113 FeaturesNehalem | FeaturePCLMUL; 114 static constexpr FeatureBitset FeaturesSandyBridge = 115 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 116 static constexpr FeatureBitset FeaturesIvyBridge = 117 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 118 static constexpr FeatureBitset FeaturesHaswell = 119 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 120 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 121 static constexpr FeatureBitset FeaturesBroadwell = 122 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 123 124 // Intel Knights Landing and Knights Mill 125 // Knights Landing has feature parity with Broadwell. 126 static constexpr FeatureBitset FeaturesKNL = 127 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 128 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 129 static constexpr FeatureBitset FeaturesKNM = 130 FeaturesKNL | FeatureAVX512VPOPCNTDQ; 131 132 // Intel Skylake processors. 133 static constexpr FeatureBitset FeaturesSkylakeClient = 134 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 135 FeatureXSAVES | FeatureSGX; 136 // SkylakeServer inherits all SkylakeClient features except SGX. 137 // FIXME: That doesn't match gcc. 138 static constexpr FeatureBitset FeaturesSkylakeServer = 139 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 140 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 141 FeaturePKU; 142 static constexpr FeatureBitset FeaturesCascadeLake = 143 FeaturesSkylakeServer | FeatureAVX512VNNI; 144 static constexpr FeatureBitset FeaturesCooperLake = 145 FeaturesCascadeLake | FeatureAVX512BF16; 146 147 // Intel 10nm processors. 148 static constexpr FeatureBitset FeaturesCannonlake = 149 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 150 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 151 FeaturePKU | FeatureSHA; 152 static constexpr FeatureBitset FeaturesICLClient = 153 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 154 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI | 155 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ; 156 static constexpr FeatureBitset FeaturesICLServer = 157 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD; 158 static constexpr FeatureBitset FeaturesTigerlake = 159 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 160 FeatureMOVDIRI | FeatureSHSTK; 161 162 // Intel Atom processors. 163 // Bonnell has feature parity with Core2 and adds MOVBE. 164 static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 165 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 166 static constexpr FeatureBitset FeaturesSilvermont = 167 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 168 static constexpr FeatureBitset FeaturesGoldmont = 169 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 170 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 171 FeatureXSAVEOPT | FeatureXSAVES; 172 static constexpr FeatureBitset FeaturesGoldmontPlus = 173 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 174 static constexpr FeatureBitset FeaturesTremont = 175 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 176 177 // Geode Processor. 178 static constexpr FeatureBitset FeaturesGeode = 179 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 180 181 // K6 processor. 182 static constexpr FeatureBitset FeaturesK6 = 183 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 184 185 // K7 and K8 architecture processors. 186 static constexpr FeatureBitset FeaturesAthlon = 187 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 188 static constexpr FeatureBitset FeaturesAthlonXP = 189 FeaturesAthlon | FeatureFXSR | FeatureSSE; 190 static constexpr FeatureBitset FeaturesK8 = 191 FeaturesAthlonXP | FeatureSSE2 | FeatureEM64T; 192 static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 193 static constexpr FeatureBitset FeaturesAMDFAM10 = 194 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 195 FeaturePRFCHW | FeatureSAHF | FeatureSSE4A; 196 197 // Bobcat architecture processors. 198 static constexpr FeatureBitset FeaturesBTVER1 = 199 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | 200 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 201 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4A | 202 FeatureSAHF; 203 static constexpr FeatureBitset FeaturesBTVER2 = 204 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | 205 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 206 207 // AMD Bulldozer architecture processors. 208 static constexpr FeatureBitset FeaturesBDVER1 = 209 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 210 FeatureCMPXCHG16B | FeatureEM64T | FeatureFMA4 | FeatureFXSR | 211 FeatureLZCNT | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL | 212 FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 | 213 FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4A | 214 FeatureXOP | FeatureXSAVE; 215 static constexpr FeatureBitset FeaturesBDVER2 = 216 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 217 static constexpr FeatureBitset FeaturesBDVER3 = 218 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 219 static constexpr FeatureBitset FeaturesBDVER4 = 220 FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX | 221 FeatureRDRND; 222 223 // AMD Zen architecture processors. 224 static constexpr FeatureBitset FeaturesZNVER1 = 225 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 226 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 227 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | FeatureF16C | 228 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureLWP | 229 FeatureLZCNT | FeatureMOVBE | FeatureMMX | FeatureMWAITX | FeaturePCLMUL | 230 FeaturePOPCNT | FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | 231 FeatureSHA | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | 232 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4A | FeatureXSAVE | 233 FeatureXSAVEC | FeatureXSAVEOPT | FeatureXSAVES; 234 static constexpr FeatureBitset FeaturesZNVER2 = 235 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD; 236 237 static constexpr ProcInfo Processors[] = { 238 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 239 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 240 // i386-generation processors. 241 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 242 // i486-generation processors. 243 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 244 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 245 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 246 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 247 // i586-generation processors, P5 microarchitecture based. 248 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 249 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 250 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 251 // i686-generation processors, P6 / Pentium M microarchitecture based. 252 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 253 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 254 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 255 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 256 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 257 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 258 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 259 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 260 // Netburst microarchitecture based processors. 261 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 262 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 263 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 264 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 265 // Core microarchitecture based processors. 266 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, 267 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 268 // Atom processors 269 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 270 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 271 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 272 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 273 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 274 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 275 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 276 // Nehalem microarchitecture based processors. 277 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 278 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 279 // Westmere microarchitecture based processors. 280 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 281 // Sandy Bridge microarchitecture based processors. 282 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 283 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 284 // Ivy Bridge microarchitecture based processors. 285 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 286 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 287 // Haswell microarchitecture based processors. 288 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 289 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 290 // Broadwell microarchitecture based processors. 291 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 292 // Skylake client microarchitecture based processors. 293 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 294 // Skylake server microarchitecture based processors. 295 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 296 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 297 // Cascadelake Server microarchitecture based processors. 298 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 299 // Cooperlake Server microarchitecture based processors. 300 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 301 // Cannonlake client microarchitecture based processors. 302 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 303 // Icelake client microarchitecture based processors. 304 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 305 // Icelake server microarchitecture based processors. 306 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 307 // Tigerlake microarchitecture based processors. 308 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 309 // Knights Landing processor. 310 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 311 // Knights Mill processor. 312 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 313 // Lakemont microarchitecture based processors. 314 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 315 // K6 architecture processors. 316 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 317 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 318 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 319 // K7 architecture processors. 320 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 321 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 322 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 323 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 324 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 325 // K8 architecture processors. 326 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 327 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 328 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 329 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 330 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 331 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 332 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 333 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 334 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 335 // Bobcat architecture processors. 336 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 337 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 338 // Bulldozer architecture processors. 339 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 340 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 341 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 342 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 343 // Zen architecture processors. 344 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 345 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 346 // Generic 64-bit processor. 347 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 348 // Geode processors. 349 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 350 }; 351 352 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 353 for (const auto &P : Processors) 354 if (P.Name == CPU && (P.Features[FEATURE_EM64T] || !Only64Bit)) 355 return P.Kind; 356 357 return CK_None; 358 } 359 360 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 361 bool Only64Bit) { 362 for (const auto &P : Processors) 363 if (!P.Name.empty() && (P.Features[FEATURE_EM64T] || !Only64Bit)) 364 Values.emplace_back(P.Name); 365 } 366 367 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 368 // FIXME: Can we avoid a linear search here? The table might be sorted by 369 // CPUKind so we could binary search? 370 for (const auto &P : Processors) { 371 if (P.Kind == Kind) { 372 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 373 return static_cast<ProcessorFeatures>(P.KeyFeature); 374 } 375 } 376 377 llvm_unreachable("Unable to find CPU kind!"); 378 } 379 380 static const char *FeatureStrings[X86::CPU_FEATURE_MAX] = { 381 #define X86_FEATURE(ENUM, STR) STR, 382 #include "llvm/Support/X86TargetParser.def" 383 }; 384 385 void llvm::X86::getFeaturesForCPU(StringRef CPU, 386 SmallVectorImpl<StringRef> &Features) { 387 auto I = llvm::find_if(Processors, 388 [&](const ProcInfo &P) { return P.Name == CPU; }); 389 assert(I != std::end(Processors) && "Processor not found!"); 390 391 // Add the string version of all set bits. 392 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 393 if (FeatureStrings[i] && I->Features[i]) 394 Features.push_back(FeatureStrings[i]); 395 } 396