1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 /// Container class for CPU features. 23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 24 /// nice to use std::bitset directly, but it doesn't support constant 25 /// initialization. 26 class FeatureBitset { 27 static constexpr unsigned NUM_FEATURE_WORDS = 28 (X86::CPU_FEATURE_MAX + 31) / 32; 29 30 // This cannot be a std::array, operator[] is not constexpr until C++17. 31 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 32 33 public: 34 constexpr FeatureBitset() = default; 35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 36 for (auto I : Init) 37 set(I); 38 } 39 40 constexpr FeatureBitset &set(unsigned I) { 41 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 42 Bits[I / 32] = NewBits; 43 return *this; 44 } 45 46 constexpr bool operator[](unsigned I) const { 47 uint32_t Mask = uint32_t(1) << (I % 32); 48 return (Bits[I / 32] & Mask) != 0; 49 } 50 51 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { 52 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 53 uint32_t NewBits = Bits[I] & RHS.Bits[I]; 54 Bits[I] = NewBits; 55 } 56 return *this; 57 } 58 59 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { 60 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 61 uint32_t NewBits = Bits[I] | RHS.Bits[I]; 62 Bits[I] = NewBits; 63 } 64 return *this; 65 } 66 67 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 68 FeatureBitset Result = *this; 69 Result &= RHS; 70 return Result; 71 } 72 73 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 74 FeatureBitset Result = *this; 75 Result |= RHS; 76 return Result; 77 } 78 79 constexpr FeatureBitset operator~() const { 80 FeatureBitset Result; 81 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 82 Result.Bits[I] = ~Bits[I]; 83 return Result; 84 } 85 }; 86 87 struct ProcInfo { 88 StringLiteral Name; 89 X86::CPUKind Kind; 90 unsigned KeyFeature; 91 FeatureBitset Features; 92 }; 93 94 struct FeatureInfo { 95 StringLiteral Name; 96 FeatureBitset ImpliedFeatures; 97 }; 98 99 } // end anonymous namespace 100 101 #define X86_FEATURE(ENUM, STRING) \ 102 static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 103 #include "llvm/Support/X86TargetParser.def" 104 105 // Pentium with MMX. 106 static constexpr FeatureBitset FeaturesPentiumMMX = 107 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 108 109 // Pentium 2 and 3. 110 static constexpr FeatureBitset FeaturesPentium2 = 111 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 112 static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 113 114 // Pentium 4 CPUs 115 static constexpr FeatureBitset FeaturesPentium4 = 116 FeaturesPentium3 | FeatureSSE2; 117 static constexpr FeatureBitset FeaturesPrescott = 118 FeaturesPentium4 | FeatureSSE3; 119 static constexpr FeatureBitset FeaturesNocona = 120 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; 121 122 // Basic 64-bit capable CPU. 123 static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; 124 125 // Intel Core CPUs 126 static constexpr FeatureBitset FeaturesCore2 = 127 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 128 static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 129 static constexpr FeatureBitset FeaturesNehalem = 130 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; 131 static constexpr FeatureBitset FeaturesWestmere = 132 FeaturesNehalem | FeaturePCLMUL; 133 static constexpr FeatureBitset FeaturesSandyBridge = 134 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 135 static constexpr FeatureBitset FeaturesIvyBridge = 136 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 137 static constexpr FeatureBitset FeaturesHaswell = 138 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 139 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 140 static constexpr FeatureBitset FeaturesBroadwell = 141 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 142 143 // Intel Knights Landing and Knights Mill 144 // Knights Landing has feature parity with Broadwell. 145 static constexpr FeatureBitset FeaturesKNL = 146 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 147 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 148 static constexpr FeatureBitset FeaturesKNM = 149 FeaturesKNL | FeatureAVX512VPOPCNTDQ; 150 151 // Intel Skylake processors. 152 static constexpr FeatureBitset FeaturesSkylakeClient = 153 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 154 FeatureXSAVES | FeatureSGX; 155 // SkylakeServer inherits all SkylakeClient features except SGX. 156 // FIXME: That doesn't match gcc. 157 static constexpr FeatureBitset FeaturesSkylakeServer = 158 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 159 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 160 FeaturePKU; 161 static constexpr FeatureBitset FeaturesCascadeLake = 162 FeaturesSkylakeServer | FeatureAVX512VNNI; 163 static constexpr FeatureBitset FeaturesCooperLake = 164 FeaturesCascadeLake | FeatureAVX512BF16; 165 166 // Intel 10nm processors. 167 static constexpr FeatureBitset FeaturesCannonlake = 168 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 169 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 170 FeaturePKU | FeatureSHA; 171 static constexpr FeatureBitset FeaturesICLClient = 172 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 173 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI | 174 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ; 175 static constexpr FeatureBitset FeaturesICLServer = 176 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD; 177 static constexpr FeatureBitset FeaturesTigerlake = 178 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 179 FeatureMOVDIRI | FeatureSHSTK; 180 181 // Intel Atom processors. 182 // Bonnell has feature parity with Core2 and adds MOVBE. 183 static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 184 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 185 static constexpr FeatureBitset FeaturesSilvermont = 186 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 187 static constexpr FeatureBitset FeaturesGoldmont = 188 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 189 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 190 FeatureXSAVEOPT | FeatureXSAVES; 191 static constexpr FeatureBitset FeaturesGoldmontPlus = 192 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 193 static constexpr FeatureBitset FeaturesTremont = 194 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 195 196 // Geode Processor. 197 static constexpr FeatureBitset FeaturesGeode = 198 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 199 200 // K6 processor. 201 static constexpr FeatureBitset FeaturesK6 = 202 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 203 204 // K7 and K8 architecture processors. 205 static constexpr FeatureBitset FeaturesAthlon = 206 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 207 static constexpr FeatureBitset FeaturesAthlonXP = 208 FeaturesAthlon | FeatureFXSR | FeatureSSE; 209 static constexpr FeatureBitset FeaturesK8 = 210 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; 211 static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 212 static constexpr FeatureBitset FeaturesAMDFAM10 = 213 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 214 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 215 216 // Bobcat architecture processors. 217 static constexpr FeatureBitset FeaturesBTVER1 = 218 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | 219 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 220 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 221 FeatureSAHF; 222 static constexpr FeatureBitset FeaturesBTVER2 = 223 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | 224 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 225 226 // AMD Bulldozer architecture processors. 227 static constexpr FeatureBitset FeaturesBDVER1 = 228 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 229 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP | 230 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | 231 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | 232 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; 233 static constexpr FeatureBitset FeaturesBDVER2 = 234 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 235 static constexpr FeatureBitset FeaturesBDVER3 = 236 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 237 static constexpr FeatureBitset FeaturesBDVER4 = 238 FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX | 239 FeatureRDRND; 240 241 // AMD Zen architecture processors. 242 static constexpr FeatureBitset FeaturesZNVER1 = 243 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 244 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 245 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C | 246 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | 247 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 248 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 249 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 250 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 251 FeatureXSAVEOPT | FeatureXSAVES; 252 static constexpr FeatureBitset FeaturesZNVER2 = 253 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD; 254 255 static constexpr ProcInfo Processors[] = { 256 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 257 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 258 // i386-generation processors. 259 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 260 // i486-generation processors. 261 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 262 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 263 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 264 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 265 // i586-generation processors, P5 microarchitecture based. 266 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 267 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 268 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 269 // i686-generation processors, P6 / Pentium M microarchitecture based. 270 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 271 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 272 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 273 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 274 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 275 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 276 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 277 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 278 // Netburst microarchitecture based processors. 279 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 280 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 281 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 282 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 283 // Core microarchitecture based processors. 284 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, 285 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 286 // Atom processors 287 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 288 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 289 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 290 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 291 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 292 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 293 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 294 // Nehalem microarchitecture based processors. 295 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 296 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 297 // Westmere microarchitecture based processors. 298 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 299 // Sandy Bridge microarchitecture based processors. 300 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 301 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 302 // Ivy Bridge microarchitecture based processors. 303 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 304 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 305 // Haswell microarchitecture based processors. 306 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 307 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 308 // Broadwell microarchitecture based processors. 309 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 310 // Skylake client microarchitecture based processors. 311 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 312 // Skylake server microarchitecture based processors. 313 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 314 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 315 // Cascadelake Server microarchitecture based processors. 316 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 317 // Cooperlake Server microarchitecture based processors. 318 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 319 // Cannonlake client microarchitecture based processors. 320 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 321 // Icelake client microarchitecture based processors. 322 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 323 // Icelake server microarchitecture based processors. 324 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 325 // Tigerlake microarchitecture based processors. 326 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 327 // Knights Landing processor. 328 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 329 // Knights Mill processor. 330 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 331 // Lakemont microarchitecture based processors. 332 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 333 // K6 architecture processors. 334 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 335 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 336 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 337 // K7 architecture processors. 338 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 339 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 340 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 341 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 342 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 343 // K8 architecture processors. 344 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 345 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 346 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 347 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 348 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 349 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 350 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 351 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 352 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 353 // Bobcat architecture processors. 354 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 355 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 356 // Bulldozer architecture processors. 357 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 358 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 359 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 360 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 361 // Zen architecture processors. 362 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 363 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 364 // Generic 64-bit processor. 365 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 366 // Geode processors. 367 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 368 }; 369 370 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 371 for (const auto &P : Processors) 372 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) 373 return P.Kind; 374 375 return CK_None; 376 } 377 378 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 379 bool Only64Bit) { 380 for (const auto &P : Processors) 381 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit)) 382 Values.emplace_back(P.Name); 383 } 384 385 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 386 // FIXME: Can we avoid a linear search here? The table might be sorted by 387 // CPUKind so we could binary search? 388 for (const auto &P : Processors) { 389 if (P.Kind == Kind) { 390 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 391 return static_cast<ProcessorFeatures>(P.KeyFeature); 392 } 393 } 394 395 llvm_unreachable("Unable to find CPU kind!"); 396 } 397 398 // Features with no dependencies. 399 static constexpr FeatureBitset ImpliedFeatures64BIT = {}; 400 static constexpr FeatureBitset ImpliedFeaturesADX = {}; 401 static constexpr FeatureBitset ImpliedFeaturesBMI = {}; 402 static constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 403 static constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 404 static constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 405 static constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 406 static constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 407 static constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 408 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 409 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 410 static constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 411 static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 412 static constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 413 static constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 414 static constexpr FeatureBitset ImpliedFeaturesLWP = {}; 415 static constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 416 static constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 417 static constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 418 static constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 419 static constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 420 static constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 421 static constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 422 static constexpr FeatureBitset ImpliedFeaturesPKU = {}; 423 static constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 424 static constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 425 static constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 426 static constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 427 static constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 428 static constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 429 static constexpr FeatureBitset ImpliedFeaturesRTM = {}; 430 static constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 431 static constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 432 static constexpr FeatureBitset ImpliedFeaturesSGX = {}; 433 static constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 434 static constexpr FeatureBitset ImpliedFeaturesTBM = {}; 435 static constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 436 static constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 437 static constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 438 static constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 439 static constexpr FeatureBitset ImpliedFeaturesX87 = {}; 440 static constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 441 442 // Not really CPU features, but need to be in the table because clang uses 443 // target features to communicate them to the backend. 444 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 445 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 446 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 447 static constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 448 static constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 449 450 // XSAVE features are dependent on basic XSAVE. 451 static constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 452 static constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 453 static constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 454 455 // MMX->3DNOW->3DNOWA chain. 456 static constexpr FeatureBitset ImpliedFeaturesMMX = {}; 457 static constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 458 static constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 459 460 // SSE/AVX/AVX512F chain. 461 static constexpr FeatureBitset ImpliedFeaturesSSE = {}; 462 static constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 463 static constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 464 static constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 465 static constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 466 static constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 467 static constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 468 static constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 469 static constexpr FeatureBitset ImpliedFeaturesAVX512F = 470 FeatureAVX2 | FeatureF16C | FeatureFMA; 471 472 // Vector extensions that build on SSE or AVX. 473 static constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 474 static constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 475 static constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 476 static constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 477 static constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 478 static constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 479 static constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; 480 static constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = 481 FeatureAVX | FeaturePCLMUL; 482 483 // AVX512 features. 484 static constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 485 static constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 486 static constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 487 static constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 488 static constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 489 static constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 490 491 static constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 492 static constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 493 static constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 494 static constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 495 static constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 496 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 497 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 498 static constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = 499 FeatureAVX512F; 500 501 // FIXME: These two aren't really implemented and just exist in the feature 502 // list for __builtin_cpu_supports. So omit their dependencies. 503 static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 504 static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 505 506 // SSE4_A->FMA4->XOP chain. 507 static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSSE3; 508 static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 509 static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 510 511 // AMX Features 512 static constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 513 static constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 514 static constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 515 516 static constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 517 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM}, 518 #include "llvm/Support/X86TargetParser.def" 519 }; 520 521 // Convert the set bits in FeatureBitset to a list of strings. 522 static void getFeatureBitsAsStrings(const FeatureBitset &Bits, 523 SmallVectorImpl<StringRef> &Features) { 524 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 525 if (Bits[i] && !FeatureInfos[i].Name.empty()) 526 Features.push_back(FeatureInfos[i].Name); 527 } 528 529 void llvm::X86::getFeaturesForCPU(StringRef CPU, 530 SmallVectorImpl<StringRef> &EnabledFeatures) { 531 auto I = llvm::find_if(Processors, 532 [&](const ProcInfo &P) { return P.Name == CPU; }); 533 assert(I != std::end(Processors) && "Processor not found!"); 534 535 FeatureBitset Bits = I->Features; 536 537 // Remove the 64-bit feature which we only use to validate if a CPU can 538 // be used with 64-bit mode. 539 Bits &= ~Feature64BIT; 540 541 // Add the string version of all set bits. 542 getFeatureBitsAsStrings(Bits, EnabledFeatures); 543 } 544 545 // For each feature that is (transitively) implied by this feature, set it. 546 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 547 const FeatureBitset &Implies) { 548 Bits |= Implies; 549 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) { 550 if (Implies[i]) 551 getImpliedEnabledFeatures(Bits, FeatureInfos[i].ImpliedFeatures); 552 } 553 } 554 555 /// Create bit vector of features that are implied disabled if the feature 556 /// passed in Value is disabled. 557 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 558 // Check all features looking for any dependent on this feature. If we find 559 // one, mark it and recursively find any feature that depend on it. 560 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) { 561 if (FeatureInfos[i].ImpliedFeatures[Value]) { 562 Bits.set(i); 563 getImpliedDisabledFeatures(Bits, i); 564 } 565 } 566 } 567 568 void llvm::X86::getImpliedFeatures( 569 StringRef Feature, bool Enabled, 570 SmallVectorImpl<StringRef> &ImpliedFeatures) { 571 auto I = llvm::find_if( 572 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; }); 573 if (I == std::end(FeatureInfos)) { 574 // FIXME: This shouldn't happen, but may not have all features in the table 575 // yet. 576 return; 577 } 578 579 FeatureBitset ImpliedBits; 580 if (Enabled) 581 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 582 else 583 getImpliedDisabledFeatures(ImpliedBits, 584 std::distance(std::begin(FeatureInfos), I)); 585 586 // Convert all the found bits into strings. 587 getFeatureBitsAsStrings(ImpliedBits, ImpliedFeatures); 588 } 589