1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Triple.h" 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 /// Container class for CPU features. 23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 24 /// nice to use std::bitset directly, but it doesn't support constant 25 /// initialization. 26 class FeatureBitset { 27 static constexpr unsigned NUM_FEATURE_WORDS = 28 (X86::CPU_FEATURE_MAX + 31) / 32; 29 30 // This cannot be a std::array, operator[] is not constexpr until C++17. 31 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 32 33 public: 34 constexpr FeatureBitset() = default; 35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 36 for (auto I : Init) 37 set(I); 38 } 39 40 constexpr FeatureBitset &set(unsigned I) { 41 // GCC <6.2 crashes if this is written in a single statement. 42 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 43 Bits[I / 32] = NewBits; 44 return *this; 45 } 46 47 constexpr bool operator[](unsigned I) const { 48 uint32_t Mask = uint32_t(1) << (I % 32); 49 return (Bits[I / 32] & Mask) != 0; 50 } 51 52 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { 53 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 54 // GCC <6.2 crashes if this is written in a single statement. 55 uint32_t NewBits = Bits[I] & RHS.Bits[I]; 56 Bits[I] = NewBits; 57 } 58 return *this; 59 } 60 61 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { 62 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { 63 // GCC <6.2 crashes if this is written in a single statement. 64 uint32_t NewBits = Bits[I] | RHS.Bits[I]; 65 Bits[I] = NewBits; 66 } 67 return *this; 68 } 69 70 // gcc 5.3 miscompiles this if we try to write this using operator&=. 71 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 72 FeatureBitset Result; 73 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 74 Result.Bits[I] = Bits[I] & RHS.Bits[I]; 75 return Result; 76 } 77 78 // gcc 5.3 miscompiles this if we try to write this using operator&=. 79 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 80 FeatureBitset Result; 81 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 82 Result.Bits[I] = Bits[I] | RHS.Bits[I]; 83 return Result; 84 } 85 86 constexpr FeatureBitset operator~() const { 87 FeatureBitset Result; 88 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) 89 Result.Bits[I] = ~Bits[I]; 90 return Result; 91 } 92 }; 93 94 struct ProcInfo { 95 StringLiteral Name; 96 X86::CPUKind Kind; 97 unsigned KeyFeature; 98 FeatureBitset Features; 99 }; 100 101 struct FeatureInfo { 102 StringLiteral Name; 103 FeatureBitset ImpliedFeatures; 104 }; 105 106 } // end anonymous namespace 107 108 #define X86_FEATURE(ENUM, STRING) \ 109 static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 110 #include "llvm/Support/X86TargetParser.def" 111 112 // Pentium with MMX. 113 static constexpr FeatureBitset FeaturesPentiumMMX = 114 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 115 116 // Pentium 2 and 3. 117 static constexpr FeatureBitset FeaturesPentium2 = 118 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 119 static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 120 121 // Pentium 4 CPUs 122 static constexpr FeatureBitset FeaturesPentium4 = 123 FeaturesPentium3 | FeatureSSE2; 124 static constexpr FeatureBitset FeaturesPrescott = 125 FeaturesPentium4 | FeatureSSE3; 126 static constexpr FeatureBitset FeaturesNocona = 127 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; 128 129 // Basic 64-bit capable CPU. 130 static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; 131 132 // Intel Core CPUs 133 static constexpr FeatureBitset FeaturesCore2 = 134 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 135 static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 136 static constexpr FeatureBitset FeaturesNehalem = 137 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; 138 static constexpr FeatureBitset FeaturesWestmere = 139 FeaturesNehalem | FeaturePCLMUL; 140 static constexpr FeatureBitset FeaturesSandyBridge = 141 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 142 static constexpr FeatureBitset FeaturesIvyBridge = 143 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 144 static constexpr FeatureBitset FeaturesHaswell = 145 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 146 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 147 static constexpr FeatureBitset FeaturesBroadwell = 148 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 149 150 // Intel Knights Landing and Knights Mill 151 // Knights Landing has feature parity with Broadwell. 152 static constexpr FeatureBitset FeaturesKNL = 153 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 154 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 155 static constexpr FeatureBitset FeaturesKNM = 156 FeaturesKNL | FeatureAVX512VPOPCNTDQ; 157 158 // Intel Skylake processors. 159 static constexpr FeatureBitset FeaturesSkylakeClient = 160 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 161 FeatureXSAVES | FeatureSGX; 162 // SkylakeServer inherits all SkylakeClient features except SGX. 163 // FIXME: That doesn't match gcc. 164 static constexpr FeatureBitset FeaturesSkylakeServer = 165 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 166 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 167 FeaturePKU; 168 static constexpr FeatureBitset FeaturesCascadeLake = 169 FeaturesSkylakeServer | FeatureAVX512VNNI; 170 static constexpr FeatureBitset FeaturesCooperLake = 171 FeaturesCascadeLake | FeatureAVX512BF16; 172 173 // Intel 10nm processors. 174 static constexpr FeatureBitset FeaturesCannonlake = 175 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 176 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 177 FeaturePKU | FeatureSHA; 178 static constexpr FeatureBitset FeaturesICLClient = 179 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 180 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI | 181 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ; 182 static constexpr FeatureBitset FeaturesICLServer = 183 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD; 184 static constexpr FeatureBitset FeaturesTigerlake = 185 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 186 FeatureMOVDIRI | FeatureSHSTK; 187 188 // Intel Atom processors. 189 // Bonnell has feature parity with Core2 and adds MOVBE. 190 static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 191 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 192 static constexpr FeatureBitset FeaturesSilvermont = 193 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 194 static constexpr FeatureBitset FeaturesGoldmont = 195 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 196 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 197 FeatureXSAVEOPT | FeatureXSAVES; 198 static constexpr FeatureBitset FeaturesGoldmontPlus = 199 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 200 static constexpr FeatureBitset FeaturesTremont = 201 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 202 203 // Geode Processor. 204 static constexpr FeatureBitset FeaturesGeode = 205 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 206 207 // K6 processor. 208 static constexpr FeatureBitset FeaturesK6 = 209 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 210 211 // K7 and K8 architecture processors. 212 static constexpr FeatureBitset FeaturesAthlon = 213 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 214 static constexpr FeatureBitset FeaturesAthlonXP = 215 FeaturesAthlon | FeatureFXSR | FeatureSSE; 216 static constexpr FeatureBitset FeaturesK8 = 217 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; 218 static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 219 static constexpr FeatureBitset FeaturesAMDFAM10 = 220 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 221 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 222 223 // Bobcat architecture processors. 224 static constexpr FeatureBitset FeaturesBTVER1 = 225 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | 226 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 227 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 228 FeatureSAHF; 229 static constexpr FeatureBitset FeaturesBTVER2 = 230 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | 231 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 232 233 // AMD Bulldozer architecture processors. 234 static constexpr FeatureBitset FeaturesBDVER1 = 235 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 236 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP | 237 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | 238 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | 239 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; 240 static constexpr FeatureBitset FeaturesBDVER2 = 241 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 242 static constexpr FeatureBitset FeaturesBDVER3 = 243 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 244 static constexpr FeatureBitset FeaturesBDVER4 = 245 FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX | 246 FeatureRDRND; 247 248 // AMD Zen architecture processors. 249 static constexpr FeatureBitset FeaturesZNVER1 = 250 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 251 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 252 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C | 253 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | 254 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 255 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 256 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 257 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 258 FeatureXSAVEOPT | FeatureXSAVES; 259 static constexpr FeatureBitset FeaturesZNVER2 = 260 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD; 261 262 static constexpr ProcInfo Processors[] = { 263 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 264 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 265 // i386-generation processors. 266 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 267 // i486-generation processors. 268 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 269 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 270 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 271 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 272 // i586-generation processors, P5 microarchitecture based. 273 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 274 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 275 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 276 // i686-generation processors, P6 / Pentium M microarchitecture based. 277 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 278 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 279 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 280 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 281 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 282 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 283 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 284 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 285 // Netburst microarchitecture based processors. 286 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 287 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 288 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 289 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 290 // Core microarchitecture based processors. 291 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, 292 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 293 // Atom processors 294 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 295 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 296 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 297 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 298 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 299 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 300 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 301 // Nehalem microarchitecture based processors. 302 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 303 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 304 // Westmere microarchitecture based processors. 305 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 306 // Sandy Bridge microarchitecture based processors. 307 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 308 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 309 // Ivy Bridge microarchitecture based processors. 310 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 311 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 312 // Haswell microarchitecture based processors. 313 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 314 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 315 // Broadwell microarchitecture based processors. 316 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 317 // Skylake client microarchitecture based processors. 318 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 319 // Skylake server microarchitecture based processors. 320 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 321 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 322 // Cascadelake Server microarchitecture based processors. 323 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 324 // Cooperlake Server microarchitecture based processors. 325 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 326 // Cannonlake client microarchitecture based processors. 327 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 328 // Icelake client microarchitecture based processors. 329 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 330 // Icelake server microarchitecture based processors. 331 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 332 // Tigerlake microarchitecture based processors. 333 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 334 // Knights Landing processor. 335 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 336 // Knights Mill processor. 337 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 338 // Lakemont microarchitecture based processors. 339 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 340 // K6 architecture processors. 341 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 342 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 343 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 344 // K7 architecture processors. 345 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 346 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 347 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 348 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 349 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 350 // K8 architecture processors. 351 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 352 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 353 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 354 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 355 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 356 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 357 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 358 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 359 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 360 // Bobcat architecture processors. 361 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 362 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 363 // Bulldozer architecture processors. 364 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 365 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 366 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 367 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 368 // Zen architecture processors. 369 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 370 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 371 // Generic 64-bit processor. 372 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 373 // Geode processors. 374 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 375 }; 376 377 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 378 for (const auto &P : Processors) 379 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) 380 return P.Kind; 381 382 return CK_None; 383 } 384 385 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 386 bool Only64Bit) { 387 for (const auto &P : Processors) 388 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit)) 389 Values.emplace_back(P.Name); 390 } 391 392 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 393 // FIXME: Can we avoid a linear search here? The table might be sorted by 394 // CPUKind so we could binary search? 395 for (const auto &P : Processors) { 396 if (P.Kind == Kind) { 397 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 398 return static_cast<ProcessorFeatures>(P.KeyFeature); 399 } 400 } 401 402 llvm_unreachable("Unable to find CPU kind!"); 403 } 404 405 // Features with no dependencies. 406 static constexpr FeatureBitset ImpliedFeatures64BIT = {}; 407 static constexpr FeatureBitset ImpliedFeaturesADX = {}; 408 static constexpr FeatureBitset ImpliedFeaturesBMI = {}; 409 static constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 410 static constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 411 static constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 412 static constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 413 static constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 414 static constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 415 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 416 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 417 static constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 418 static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 419 static constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 420 static constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 421 static constexpr FeatureBitset ImpliedFeaturesLWP = {}; 422 static constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 423 static constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 424 static constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 425 static constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 426 static constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 427 static constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 428 static constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 429 static constexpr FeatureBitset ImpliedFeaturesPKU = {}; 430 static constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 431 static constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 432 static constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 433 static constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 434 static constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 435 static constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 436 static constexpr FeatureBitset ImpliedFeaturesRTM = {}; 437 static constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 438 static constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 439 static constexpr FeatureBitset ImpliedFeaturesSGX = {}; 440 static constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 441 static constexpr FeatureBitset ImpliedFeaturesTBM = {}; 442 static constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 443 static constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 444 static constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 445 static constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 446 static constexpr FeatureBitset ImpliedFeaturesX87 = {}; 447 static constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 448 449 // Not really CPU features, but need to be in the table because clang uses 450 // target features to communicate them to the backend. 451 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 452 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 453 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 454 static constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 455 static constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 456 457 // XSAVE features are dependent on basic XSAVE. 458 static constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 459 static constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 460 static constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 461 462 // MMX->3DNOW->3DNOWA chain. 463 static constexpr FeatureBitset ImpliedFeaturesMMX = {}; 464 static constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 465 static constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 466 467 // SSE/AVX/AVX512F chain. 468 static constexpr FeatureBitset ImpliedFeaturesSSE = {}; 469 static constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 470 static constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 471 static constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 472 static constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 473 static constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 474 static constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 475 static constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 476 static constexpr FeatureBitset ImpliedFeaturesAVX512F = 477 FeatureAVX2 | FeatureF16C | FeatureFMA; 478 479 // Vector extensions that build on SSE or AVX. 480 static constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 481 static constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 482 static constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 483 static constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 484 static constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 485 static constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 486 static constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; 487 static constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = 488 FeatureAVX | FeaturePCLMUL; 489 490 // AVX512 features. 491 static constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 492 static constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 493 static constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 494 static constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 495 static constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 496 static constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 497 498 static constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 499 static constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 500 static constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 501 static constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 502 static constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 503 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 504 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 505 static constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = 506 FeatureAVX512F; 507 508 // FIXME: These two aren't really implemented and just exist in the feature 509 // list for __builtin_cpu_supports. So omit their dependencies. 510 static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 511 static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 512 513 // SSE4_A->FMA4->XOP chain. 514 static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSSE3; 515 static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 516 static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 517 518 // AMX Features 519 static constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 520 static constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 521 static constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 522 523 static constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 524 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM}, 525 #include "llvm/Support/X86TargetParser.def" 526 }; 527 528 // Convert the set bits in FeatureBitset to a list of strings. 529 static void getFeatureBitsAsStrings(const FeatureBitset &Bits, 530 SmallVectorImpl<StringRef> &Features) { 531 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 532 if (Bits[i] && !FeatureInfos[i].Name.empty()) 533 Features.push_back(FeatureInfos[i].Name); 534 } 535 536 void llvm::X86::getFeaturesForCPU(StringRef CPU, 537 SmallVectorImpl<StringRef> &EnabledFeatures) { 538 auto I = llvm::find_if(Processors, 539 [&](const ProcInfo &P) { return P.Name == CPU; }); 540 assert(I != std::end(Processors) && "Processor not found!"); 541 542 FeatureBitset Bits = I->Features; 543 544 // Remove the 64-bit feature which we only use to validate if a CPU can 545 // be used with 64-bit mode. 546 Bits &= ~Feature64BIT; 547 548 // Add the string version of all set bits. 549 getFeatureBitsAsStrings(Bits, EnabledFeatures); 550 } 551 552 // For each feature that is (transitively) implied by this feature, set it. 553 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 554 const FeatureBitset &Implies) { 555 Bits |= Implies; 556 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) { 557 if (Implies[i]) 558 getImpliedEnabledFeatures(Bits, FeatureInfos[i].ImpliedFeatures); 559 } 560 } 561 562 /// Create bit vector of features that are implied disabled if the feature 563 /// passed in Value is disabled. 564 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 565 // Check all features looking for any dependent on this feature. If we find 566 // one, mark it and recursively find any feature that depend on it. 567 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) { 568 if (FeatureInfos[i].ImpliedFeatures[Value]) { 569 Bits.set(i); 570 getImpliedDisabledFeatures(Bits, i); 571 } 572 } 573 } 574 575 void llvm::X86::getImpliedFeatures( 576 StringRef Feature, bool Enabled, 577 SmallVectorImpl<StringRef> &ImpliedFeatures) { 578 auto I = llvm::find_if( 579 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; }); 580 if (I == std::end(FeatureInfos)) { 581 // FIXME: This shouldn't happen, but may not have all features in the table 582 // yet. 583 return; 584 } 585 586 FeatureBitset ImpliedBits; 587 if (Enabled) 588 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 589 else 590 getImpliedDisabledFeatures(ImpliedBits, 591 std::distance(std::begin(FeatureInfos), I)); 592 593 // Convert all the found bits into strings. 594 getFeatureBitsAsStrings(ImpliedBits, ImpliedFeatures); 595 } 596