1f5f373fcSRenato Golin //===-- TargetParser - Parser for target features ---------------*- C++ -*-===// 2f5f373fcSRenato Golin // 3f5f373fcSRenato Golin // The LLVM Compiler Infrastructure 4f5f373fcSRenato Golin // 5f5f373fcSRenato Golin // This file is distributed under the University of Illinois Open Source 6f5f373fcSRenato Golin // License. See LICENSE.TXT for details. 7f5f373fcSRenato Golin // 8f5f373fcSRenato Golin //===----------------------------------------------------------------------===// 9f5f373fcSRenato Golin // 10f5f373fcSRenato Golin // This file implements a target parser to recognise hardware features such as 11f5f373fcSRenato Golin // FPU/CPU/ARCH names as well as specific support such as HDIV, etc. 12f5f373fcSRenato Golin // 13f5f373fcSRenato Golin //===----------------------------------------------------------------------===// 14f5f373fcSRenato Golin 15f5f373fcSRenato Golin #include "llvm/Support/ARMBuildAttributes.h" 16f5f373fcSRenato Golin #include "llvm/Support/TargetParser.h" 17f5f373fcSRenato Golin #include "llvm/ADT/StringExtras.h" 18f5f373fcSRenato Golin #include "llvm/ADT/StringSwitch.h" 19f5f373fcSRenato Golin 20f5f373fcSRenato Golin using namespace llvm; 21f5f373fcSRenato Golin 22f5f373fcSRenato Golin namespace { 23f5f373fcSRenato Golin 24f5f373fcSRenato Golin // List of canonical FPU names (use getFPUSynonym) 25f5f373fcSRenato Golin // FIXME: TableGen this. 26f5f373fcSRenato Golin struct { 27f5f373fcSRenato Golin const char * Name; 28f5f373fcSRenato Golin ARM::FPUKind ID; 29f5f373fcSRenato Golin } FPUNames[] = { 30*35de35d0SRenato Golin { "invalid", ARM::FK_INVALID }, 31*35de35d0SRenato Golin { "vfp", ARM::FK_VFP }, 32*35de35d0SRenato Golin { "vfpv2", ARM::FK_VFPV2 }, 33*35de35d0SRenato Golin { "vfpv3", ARM::FK_VFPV3 }, 34*35de35d0SRenato Golin { "vfpv3-d16", ARM::FK_VFPV3_D16 }, 35*35de35d0SRenato Golin { "vfpv4", ARM::FK_VFPV4 }, 36*35de35d0SRenato Golin { "vfpv4-d16", ARM::FK_VFPV4_D16 }, 37*35de35d0SRenato Golin { "fpv5-d16", ARM::FK_FPV5_D16 }, 38*35de35d0SRenato Golin { "fp-armv8", ARM::FK_FP_ARMV8 }, 39*35de35d0SRenato Golin { "neon", ARM::FK_NEON }, 40*35de35d0SRenato Golin { "neon-vfpv4", ARM::FK_NEON_VFPV4 }, 41*35de35d0SRenato Golin { "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8 }, 42*35de35d0SRenato Golin { "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 }, 43*35de35d0SRenato Golin { "softvfp", ARM::FK_SOFTVFP } 44f5f373fcSRenato Golin }; 45f5f373fcSRenato Golin // List of canonical arch names (use getArchSynonym) 46f5f373fcSRenato Golin // FIXME: TableGen this. 47f5f373fcSRenato Golin struct { 48f5f373fcSRenato Golin const char *Name; 49f5f373fcSRenato Golin ARM::ArchKind ID; 50f5f373fcSRenato Golin const char *DefaultCPU; 51f5f373fcSRenato Golin ARMBuildAttrs::CPUArch DefaultArch; 52f5f373fcSRenato Golin } ARCHNames[] = { 53*35de35d0SRenato Golin { "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 }, 54*35de35d0SRenato Golin { "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 }, 55*35de35d0SRenato Golin { "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 }, 56*35de35d0SRenato Golin { "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 }, 57*35de35d0SRenato Golin { "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 }, 58*35de35d0SRenato Golin { "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 }, 59*35de35d0SRenato Golin { "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T }, 60*35de35d0SRenato Golin { "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T }, 61*35de35d0SRenato Golin { "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T }, 62*35de35d0SRenato Golin { "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE }, 63*35de35d0SRenato Golin { "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 }, 64*35de35d0SRenato Golin { "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 }, 65*35de35d0SRenato Golin { "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K }, 66*35de35d0SRenato Golin { "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 }, 67*35de35d0SRenato Golin { "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ }, 68*35de35d0SRenato Golin { "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ }, 69*35de35d0SRenato Golin { "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M }, 70*35de35d0SRenato Golin { "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 }, 71*35de35d0SRenato Golin { "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 }, 72*35de35d0SRenato Golin { "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 }, 73*35de35d0SRenato Golin { "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 }, 74*35de35d0SRenato Golin { "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 }, 75*35de35d0SRenato Golin { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 }, 76*35de35d0SRenato Golin { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE }, 77*35de35d0SRenato Golin { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE } 78f5f373fcSRenato Golin }; 79f5f373fcSRenato Golin // List of canonical ARCH names (use getARCHSynonym) 80f5f373fcSRenato Golin // FIXME: TableGen this. 81f5f373fcSRenato Golin struct { 82f5f373fcSRenato Golin const char *Name; 83f5f373fcSRenato Golin ARM::ArchExtKind ID; 84f5f373fcSRenato Golin } ARCHExtNames[] = { 85*35de35d0SRenato Golin { "invalid", ARM::AEK_INVALID }, 86*35de35d0SRenato Golin { "crc", ARM::AEK_CRC }, 87*35de35d0SRenato Golin { "crypto", ARM::AEK_CRYPTO }, 88*35de35d0SRenato Golin { "fp", ARM::AEK_FP }, 89*35de35d0SRenato Golin { "idiv", ARM::AEK_HWDIV }, 90*35de35d0SRenato Golin { "mp", ARM::AEK_MP }, 91*35de35d0SRenato Golin { "sec", ARM::AEK_SEC }, 92*35de35d0SRenato Golin { "virt", ARM::AEK_VIRT } 93f5f373fcSRenato Golin }; 94f5f373fcSRenato Golin 95f5f373fcSRenato Golin } // namespace 96f5f373fcSRenato Golin 97f5f373fcSRenato Golin namespace llvm { 98f5f373fcSRenato Golin 99f5f373fcSRenato Golin // ======================================================= // 100f5f373fcSRenato Golin // Information by ID 101f5f373fcSRenato Golin // ======================================================= // 102f5f373fcSRenato Golin 103f5f373fcSRenato Golin const char *ARMTargetParser::getFPUName(unsigned ID) { 104*35de35d0SRenato Golin if (ID >= ARM::FK_LAST) 105f5f373fcSRenato Golin return nullptr; 106f5f373fcSRenato Golin return FPUNames[ID].Name; 107f5f373fcSRenato Golin } 108f5f373fcSRenato Golin 109f5f373fcSRenato Golin const char *ARMTargetParser::getArchName(unsigned ID) { 110*35de35d0SRenato Golin if (ID >= ARM::AK_LAST) 111f5f373fcSRenato Golin return nullptr; 112f5f373fcSRenato Golin return ARCHNames[ID].Name; 113f5f373fcSRenato Golin } 114f5f373fcSRenato Golin 115f5f373fcSRenato Golin const char *ARMTargetParser::getArchDefaultCPUName(unsigned ID) { 116*35de35d0SRenato Golin if (ID >= ARM::AK_LAST) 117f5f373fcSRenato Golin return nullptr; 118f5f373fcSRenato Golin return ARCHNames[ID].DefaultCPU; 119f5f373fcSRenato Golin } 120f5f373fcSRenato Golin 121f5f373fcSRenato Golin unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ID) { 122*35de35d0SRenato Golin if (ID >= ARM::AK_LAST) 123f5f373fcSRenato Golin return 0; 124f5f373fcSRenato Golin return ARCHNames[ID].DefaultArch; 125f5f373fcSRenato Golin } 126f5f373fcSRenato Golin 127f5f373fcSRenato Golin const char *ARMTargetParser::getArchExtName(unsigned ID) { 128*35de35d0SRenato Golin if (ID >= ARM::AEK_LAST) 129f5f373fcSRenato Golin return nullptr; 130f5f373fcSRenato Golin return ARCHExtNames[ID].Name; 131f5f373fcSRenato Golin } 132f5f373fcSRenato Golin 133f5f373fcSRenato Golin // ======================================================= // 134f5f373fcSRenato Golin // Parsers 135f5f373fcSRenato Golin // ======================================================= // 136f5f373fcSRenato Golin 137f5f373fcSRenato Golin StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) { 138f5f373fcSRenato Golin return StringSwitch<StringRef>(FPU) 139f5f373fcSRenato Golin .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported 140f5f373fcSRenato Golin .Case("vfp2", "vfpv2") 141f5f373fcSRenato Golin .Case("vfp3", "vfpv3") 142f5f373fcSRenato Golin .Case("vfp4", "vfpv4") 143f5f373fcSRenato Golin .Case("vfp3-d16", "vfpv3-d16") 144f5f373fcSRenato Golin .Case("vfp4-d16", "vfpv4-d16") 145f5f373fcSRenato Golin // FIXME: sp-16 is NOT the same as d16 146f5f373fcSRenato Golin .Cases("fp4-sp-d16", "fpv4-sp-d16", "vfpv4-d16") 147f5f373fcSRenato Golin .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16") 148f5f373fcSRenato Golin .Cases("fp5-sp-d16", "fpv5-sp-d16", "fpv5-d16") 149f5f373fcSRenato Golin .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16") 150f5f373fcSRenato Golin // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3. 151f5f373fcSRenato Golin .Case("neon-vfpv3", "neon") 152f5f373fcSRenato Golin .Default(FPU); 153f5f373fcSRenato Golin } 154f5f373fcSRenato Golin 155f5f373fcSRenato Golin StringRef ARMTargetParser::getArchSynonym(StringRef Arch) { 156f5f373fcSRenato Golin return StringSwitch<StringRef>(Arch) 157f5f373fcSRenato Golin .Case("armv5tej", "armv5te") 158f5f373fcSRenato Golin .Case("armv6m", "armv6-m") 159f5f373fcSRenato Golin .Case("armv7a", "armv7-a") 160f5f373fcSRenato Golin .Case("armv7r", "armv7-r") 161f5f373fcSRenato Golin .Case("armv7m", "armv7-m") 162f5f373fcSRenato Golin .Case("armv8a", "armv8-a") 163f5f373fcSRenato Golin .Case("armv8.1a", "armv8.1-a") 164f5f373fcSRenato Golin .Default(Arch); 165f5f373fcSRenato Golin } 166f5f373fcSRenato Golin 167f5f373fcSRenato Golin unsigned ARMTargetParser::parseFPU(StringRef FPU) { 168f5f373fcSRenato Golin StringRef Syn = getFPUSynonym(FPU); 169f5f373fcSRenato Golin for (const auto F : FPUNames) { 170f5f373fcSRenato Golin if (Syn == F.Name) 171f5f373fcSRenato Golin return F.ID; 172f5f373fcSRenato Golin } 173*35de35d0SRenato Golin return ARM::FK_INVALID; 174f5f373fcSRenato Golin } 175f5f373fcSRenato Golin 176f5f373fcSRenato Golin unsigned ARMTargetParser::parseArch(StringRef Arch) { 177f5f373fcSRenato Golin StringRef Syn = getArchSynonym(Arch); 178f5f373fcSRenato Golin for (const auto A : ARCHNames) { 179f5f373fcSRenato Golin if (Syn == A.Name) 180f5f373fcSRenato Golin return A.ID; 181f5f373fcSRenato Golin } 182*35de35d0SRenato Golin return ARM::AK_INVALID; 183f5f373fcSRenato Golin } 184f5f373fcSRenato Golin 185f5f373fcSRenato Golin unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) { 186f5f373fcSRenato Golin for (const auto A : ARCHExtNames) { 187f5f373fcSRenato Golin if (ArchExt == A.Name) 188f5f373fcSRenato Golin return A.ID; 189f5f373fcSRenato Golin } 190*35de35d0SRenato Golin return ARM::AEK_INVALID; 191f5f373fcSRenato Golin } 192f5f373fcSRenato Golin 193f5f373fcSRenato Golin } // namespace llvm 194