1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise ARM hardware features 10 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/ARMTargetParser.h" 15 #include "llvm/ADT/StringSwitch.h" 16 #include <cctype> 17 18 using namespace llvm; 19 20 static StringRef getHWDivSynonym(StringRef HWDiv) { 21 return StringSwitch<StringRef>(HWDiv) 22 .Case("thumb,arm", "arm,thumb") 23 .Default(HWDiv); 24 } 25 26 // Allows partial match, ex. "v7a" matches "armv7a". 27 ARM::ArchKind ARM::parseArch(StringRef Arch) { 28 Arch = getCanonicalArchName(Arch); 29 StringRef Syn = getArchSynonym(Arch); 30 for (const auto A : ARCHNames) { 31 if (A.getName().endswith(Syn)) 32 return A.ID; 33 } 34 return ArchKind::INVALID; 35 } 36 37 // Version number (ex. v7 = 7). 38 unsigned ARM::parseArchVersion(StringRef Arch) { 39 Arch = getCanonicalArchName(Arch); 40 switch (parseArch(Arch)) { 41 case ArchKind::ARMV2: 42 case ArchKind::ARMV2A: 43 return 2; 44 case ArchKind::ARMV3: 45 case ArchKind::ARMV3M: 46 return 3; 47 case ArchKind::ARMV4: 48 case ArchKind::ARMV4T: 49 return 4; 50 case ArchKind::ARMV5T: 51 case ArchKind::ARMV5TE: 52 case ArchKind::IWMMXT: 53 case ArchKind::IWMMXT2: 54 case ArchKind::XSCALE: 55 case ArchKind::ARMV5TEJ: 56 return 5; 57 case ArchKind::ARMV6: 58 case ArchKind::ARMV6K: 59 case ArchKind::ARMV6T2: 60 case ArchKind::ARMV6KZ: 61 case ArchKind::ARMV6M: 62 return 6; 63 case ArchKind::ARMV7A: 64 case ArchKind::ARMV7VE: 65 case ArchKind::ARMV7R: 66 case ArchKind::ARMV7M: 67 case ArchKind::ARMV7S: 68 case ArchKind::ARMV7EM: 69 case ArchKind::ARMV7K: 70 return 7; 71 case ArchKind::ARMV8A: 72 case ArchKind::ARMV8_1A: 73 case ArchKind::ARMV8_2A: 74 case ArchKind::ARMV8_3A: 75 case ArchKind::ARMV8_4A: 76 case ArchKind::ARMV8_5A: 77 case ArchKind::ARMV8R: 78 case ArchKind::ARMV8MBaseline: 79 case ArchKind::ARMV8MMainline: 80 case ArchKind::ARMV8_1MMainline: 81 return 8; 82 case ArchKind::INVALID: 83 return 0; 84 } 85 llvm_unreachable("Unhandled architecture"); 86 } 87 88 // Profile A/R/M 89 ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) { 90 Arch = getCanonicalArchName(Arch); 91 switch (parseArch(Arch)) { 92 case ArchKind::ARMV6M: 93 case ArchKind::ARMV7M: 94 case ArchKind::ARMV7EM: 95 case ArchKind::ARMV8MMainline: 96 case ArchKind::ARMV8MBaseline: 97 case ArchKind::ARMV8_1MMainline: 98 return ProfileKind::M; 99 case ArchKind::ARMV7R: 100 case ArchKind::ARMV8R: 101 return ProfileKind::R; 102 case ArchKind::ARMV7A: 103 case ArchKind::ARMV7VE: 104 case ArchKind::ARMV7K: 105 case ArchKind::ARMV8A: 106 case ArchKind::ARMV8_1A: 107 case ArchKind::ARMV8_2A: 108 case ArchKind::ARMV8_3A: 109 case ArchKind::ARMV8_4A: 110 case ArchKind::ARMV8_5A: 111 return ProfileKind::A; 112 case ArchKind::ARMV2: 113 case ArchKind::ARMV2A: 114 case ArchKind::ARMV3: 115 case ArchKind::ARMV3M: 116 case ArchKind::ARMV4: 117 case ArchKind::ARMV4T: 118 case ArchKind::ARMV5T: 119 case ArchKind::ARMV5TE: 120 case ArchKind::ARMV5TEJ: 121 case ArchKind::ARMV6: 122 case ArchKind::ARMV6K: 123 case ArchKind::ARMV6T2: 124 case ArchKind::ARMV6KZ: 125 case ArchKind::ARMV7S: 126 case ArchKind::IWMMXT: 127 case ArchKind::IWMMXT2: 128 case ArchKind::XSCALE: 129 case ArchKind::INVALID: 130 return ProfileKind::INVALID; 131 } 132 llvm_unreachable("Unhandled architecture"); 133 } 134 135 StringRef ARM::getArchSynonym(StringRef Arch) { 136 return StringSwitch<StringRef>(Arch) 137 .Case("v5", "v5t") 138 .Case("v5e", "v5te") 139 .Case("v6j", "v6") 140 .Case("v6hl", "v6k") 141 .Cases("v6m", "v6sm", "v6s-m", "v6-m") 142 .Cases("v6z", "v6zk", "v6kz") 143 .Cases("v7", "v7a", "v7hl", "v7l", "v7-a") 144 .Case("v7r", "v7-r") 145 .Case("v7m", "v7-m") 146 .Case("v7em", "v7e-m") 147 .Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a") 148 .Case("v8.1a", "v8.1-a") 149 .Case("v8.2a", "v8.2-a") 150 .Case("v8.3a", "v8.3-a") 151 .Case("v8.4a", "v8.4-a") 152 .Case("v8.5a", "v8.5-a") 153 .Case("v8r", "v8-r") 154 .Case("v8m.base", "v8-m.base") 155 .Case("v8m.main", "v8-m.main") 156 .Case("v8.1m.main", "v8.1-m.main") 157 .Default(Arch); 158 } 159 160 bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) { 161 162 if (FPUKind >= FK_LAST || FPUKind == FK_INVALID) 163 return false; 164 165 static const struct FPUFeatureNameInfo { 166 const char *PlusName, *MinusName; 167 FPUVersion MinVersion; 168 FPURestriction MaxRestriction; 169 } FPUFeatureInfoList[] = { 170 // We have to specify the + and - versions of the name in full so 171 // that we can return them as static StringRefs. 172 // 173 // Also, the SubtargetFeatures ending in just "sp" are listed here 174 // under FPURestriction::None, which is the only FPURestriction in 175 // which they would be valid (since FPURestriction::SP doesn't 176 // exist). 177 178 {"+fpregs", "-fpregs", FPUVersion::VFPV2, FPURestriction::SP_D16}, 179 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::None}, 180 {"+vfp2d16", "-vfp2d16", FPUVersion::VFPV2, FPURestriction::D16}, 181 {"+vfp2d16sp", "-vfp2d16sp", FPUVersion::VFPV2, FPURestriction::SP_D16}, 182 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::None}, 183 {"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None}, 184 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16}, 185 {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16}, 186 {"+vfp3sp", "-vfp3sp", FPUVersion::VFPV3, FPURestriction::None}, 187 {"+fp16", "-fp16", FPUVersion::VFPV3_FP16, FPURestriction::SP_D16}, 188 {"+vfp4", "-vfp4", FPUVersion::VFPV4, FPURestriction::None}, 189 {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16}, 190 {"+vfp4d16sp", "-vfp4d16sp", FPUVersion::VFPV4, FPURestriction::SP_D16}, 191 {"+vfp4sp", "-vfp4sp", FPUVersion::VFPV4, FPURestriction::None}, 192 {"+fp-armv8", "-fp-armv8", FPUVersion::VFPV5, FPURestriction::None}, 193 {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16}, 194 {"+fp-armv8d16sp", "-fp-armv8d16sp", FPUVersion::VFPV5, FPURestriction::SP_D16}, 195 {"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None}, 196 {"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16}, 197 {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16}, 198 {"+d32", "-d32", FPUVersion::VFPV2, FPURestriction::None}, 199 }; 200 201 for (const auto &Info: FPUFeatureInfoList) { 202 if (FPUNames[FPUKind].FPUVer >= Info.MinVersion && 203 FPUNames[FPUKind].Restriction <= Info.MaxRestriction) 204 Features.push_back(Info.PlusName); 205 else 206 Features.push_back(Info.MinusName); 207 } 208 209 static const struct NeonFeatureNameInfo { 210 const char *PlusName, *MinusName; 211 NeonSupportLevel MinSupportLevel; 212 } NeonFeatureInfoList[] = { 213 {"+neon", "-neon", NeonSupportLevel::Neon}, 214 {"+crypto", "-crypto", NeonSupportLevel::Crypto}, 215 }; 216 217 for (const auto &Info: NeonFeatureInfoList) { 218 if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel) 219 Features.push_back(Info.PlusName); 220 else 221 Features.push_back(Info.MinusName); 222 } 223 224 return true; 225 } 226 227 // Little/Big endian 228 ARM::EndianKind ARM::parseArchEndian(StringRef Arch) { 229 if (Arch.startswith("armeb") || Arch.startswith("thumbeb") || 230 Arch.startswith("aarch64_be")) 231 return EndianKind::BIG; 232 233 if (Arch.startswith("arm") || Arch.startswith("thumb")) { 234 if (Arch.endswith("eb")) 235 return EndianKind::BIG; 236 else 237 return EndianKind::LITTLE; 238 } 239 240 if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32")) 241 return EndianKind::LITTLE; 242 243 return EndianKind::INVALID; 244 } 245 246 // ARM, Thumb, AArch64 247 ARM::ISAKind ARM::parseArchISA(StringRef Arch) { 248 return StringSwitch<ISAKind>(Arch) 249 .StartsWith("aarch64", ISAKind::AARCH64) 250 .StartsWith("arm64", ISAKind::AARCH64) 251 .StartsWith("thumb", ISAKind::THUMB) 252 .StartsWith("arm", ISAKind::ARM) 253 .Default(ISAKind::INVALID); 254 } 255 256 unsigned ARM::parseFPU(StringRef FPU) { 257 StringRef Syn = getFPUSynonym(FPU); 258 for (const auto F : FPUNames) { 259 if (Syn == F.getName()) 260 return F.ID; 261 } 262 return FK_INVALID; 263 } 264 265 ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) { 266 if (FPUKind >= FK_LAST) 267 return NeonSupportLevel::None; 268 return FPUNames[FPUKind].NeonSupport; 269 } 270 271 // MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but 272 // (iwmmxt|xscale)(eb)? is also permitted. If the former, return 273 // "v.+", if the latter, return unmodified string, minus 'eb'. 274 // If invalid, return empty string. 275 StringRef ARM::getCanonicalArchName(StringRef Arch) { 276 size_t offset = StringRef::npos; 277 StringRef A = Arch; 278 StringRef Error = ""; 279 280 // Begins with "arm" / "thumb", move past it. 281 if (A.startswith("arm64_32")) 282 offset = 8; 283 else if (A.startswith("arm64")) 284 offset = 5; 285 else if (A.startswith("aarch64_32")) 286 offset = 10; 287 else if (A.startswith("arm")) 288 offset = 3; 289 else if (A.startswith("thumb")) 290 offset = 5; 291 else if (A.startswith("aarch64")) { 292 offset = 7; 293 // AArch64 uses "_be", not "eb" suffix. 294 if (A.find("eb") != StringRef::npos) 295 return Error; 296 if (A.substr(offset, 3) == "_be") 297 offset += 3; 298 } 299 300 // Ex. "armebv7", move past the "eb". 301 if (offset != StringRef::npos && A.substr(offset, 2) == "eb") 302 offset += 2; 303 // Or, if it ends with eb ("armv7eb"), chop it off. 304 else if (A.endswith("eb")) 305 A = A.substr(0, A.size() - 2); 306 // Trim the head 307 if (offset != StringRef::npos) 308 A = A.substr(offset); 309 310 // Empty string means offset reached the end, which means it's valid. 311 if (A.empty()) 312 return Arch; 313 314 // Only match non-marketing names 315 if (offset != StringRef::npos) { 316 // Must start with 'vN'. 317 if (A.size() >= 2 && (A[0] != 'v' || !std::isdigit(A[1]))) 318 return Error; 319 // Can't have an extra 'eb'. 320 if (A.find("eb") != StringRef::npos) 321 return Error; 322 } 323 324 // Arch will either be a 'v' name (v7a) or a marketing name (xscale). 325 return A; 326 } 327 328 StringRef ARM::getFPUSynonym(StringRef FPU) { 329 return StringSwitch<StringRef>(FPU) 330 .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported 331 .Case("vfp2", "vfpv2") 332 .Case("vfp3", "vfpv3") 333 .Case("vfp4", "vfpv4") 334 .Case("vfp3-d16", "vfpv3-d16") 335 .Case("vfp4-d16", "vfpv4-d16") 336 .Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16") 337 .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16") 338 .Case("fp5-sp-d16", "fpv5-sp-d16") 339 .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16") 340 // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3. 341 .Case("neon-vfpv3", "neon") 342 .Default(FPU); 343 } 344 345 StringRef ARM::getFPUName(unsigned FPUKind) { 346 if (FPUKind >= FK_LAST) 347 return StringRef(); 348 return FPUNames[FPUKind].getName(); 349 } 350 351 ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) { 352 if (FPUKind >= FK_LAST) 353 return FPUVersion::NONE; 354 return FPUNames[FPUKind].FPUVer; 355 } 356 357 ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) { 358 if (FPUKind >= FK_LAST) 359 return FPURestriction::None; 360 return FPUNames[FPUKind].Restriction; 361 } 362 363 unsigned ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) { 364 if (CPU == "generic") 365 return ARM::ARCHNames[static_cast<unsigned>(AK)].DefaultFPU; 366 367 return StringSwitch<unsigned>(CPU) 368 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ 369 .Case(NAME, DEFAULT_FPU) 370 #include "llvm/Support/ARMTargetParser.def" 371 .Default(ARM::FK_INVALID); 372 } 373 374 unsigned ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) { 375 if (CPU == "generic") 376 return ARM::ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions; 377 378 return StringSwitch<unsigned>(CPU) 379 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ 380 .Case(NAME, \ 381 ARCHNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \ 382 DEFAULT_EXT) 383 #include "llvm/Support/ARMTargetParser.def" 384 .Default(ARM::AEK_INVALID); 385 } 386 387 bool ARM::getHWDivFeatures(unsigned HWDivKind, 388 std::vector<StringRef> &Features) { 389 390 if (HWDivKind == AEK_INVALID) 391 return false; 392 393 if (HWDivKind & AEK_HWDIVARM) 394 Features.push_back("+hwdiv-arm"); 395 else 396 Features.push_back("-hwdiv-arm"); 397 398 if (HWDivKind & AEK_HWDIVTHUMB) 399 Features.push_back("+hwdiv"); 400 else 401 Features.push_back("-hwdiv"); 402 403 return true; 404 } 405 406 bool ARM::getExtensionFeatures(unsigned Extensions, 407 std::vector<StringRef> &Features) { 408 409 if (Extensions == AEK_INVALID) 410 return false; 411 412 for (const auto AE : ARCHExtNames) { 413 if ((Extensions & AE.ID) == AE.ID && AE.Feature) 414 Features.push_back(AE.Feature); 415 else if (AE.NegFeature) 416 Features.push_back(AE.NegFeature); 417 } 418 419 return getHWDivFeatures(Extensions, Features); 420 } 421 422 StringRef ARM::getArchName(ARM::ArchKind AK) { 423 return ARCHNames[static_cast<unsigned>(AK)].getName(); 424 } 425 426 StringRef ARM::getCPUAttr(ARM::ArchKind AK) { 427 return ARCHNames[static_cast<unsigned>(AK)].getCPUAttr(); 428 } 429 430 StringRef ARM::getSubArch(ARM::ArchKind AK) { 431 return ARCHNames[static_cast<unsigned>(AK)].getSubArch(); 432 } 433 434 unsigned ARM::getArchAttr(ARM::ArchKind AK) { 435 return ARCHNames[static_cast<unsigned>(AK)].ArchAttr; 436 } 437 438 StringRef ARM::getArchExtName(unsigned ArchExtKind) { 439 for (const auto AE : ARCHExtNames) { 440 if (ArchExtKind == AE.ID) 441 return AE.getName(); 442 } 443 return StringRef(); 444 } 445 446 static bool stripNegationPrefix(StringRef &Name) { 447 if (Name.startswith("no")) { 448 Name = Name.substr(2); 449 return true; 450 } 451 return false; 452 } 453 454 StringRef ARM::getArchExtFeature(StringRef ArchExt) { 455 bool Negated = stripNegationPrefix(ArchExt); 456 for (const auto AE : ARCHExtNames) { 457 if (AE.Feature && ArchExt == AE.getName()) 458 return StringRef(Negated ? AE.NegFeature : AE.Feature); 459 } 460 461 return StringRef(); 462 } 463 464 static unsigned findDoublePrecisionFPU(unsigned InputFPUKind) { 465 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind]; 466 467 // If the input FPU already supports double-precision, then there 468 // isn't any different FPU we can return here. 469 // 470 // The current available FPURestriction values are None (no 471 // restriction), D16 (only 16 d-regs) and SP_D16 (16 d-regs 472 // and single precision only); there's no value representing 473 // SP restriction without D16. So this test just means 'is it 474 // SP only?'. 475 if (InputFPU.Restriction != ARM::FPURestriction::SP_D16) 476 return ARM::FK_INVALID; 477 478 // Otherwise, look for an FPU entry with all the same fields, except 479 // that SP_D16 has been replaced with just D16, representing adding 480 // double precision and not changing anything else. 481 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) { 482 if (CandidateFPU.FPUVer == InputFPU.FPUVer && 483 CandidateFPU.NeonSupport == InputFPU.NeonSupport && 484 CandidateFPU.Restriction == ARM::FPURestriction::D16) { 485 return CandidateFPU.ID; 486 } 487 } 488 489 // nothing found 490 return ARM::FK_INVALID; 491 } 492 493 static unsigned getAEKID(StringRef ArchExtName) { 494 for (const auto AE : ARM::ARCHExtNames) 495 if (AE.getName() == ArchExtName) 496 return AE.ID; 497 return ARM::AEK_INVALID; 498 } 499 500 bool ARM::appendArchExtFeatures( 501 StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, 502 std::vector<StringRef> &Features) { 503 504 size_t StartingNumFeatures = Features.size(); 505 const bool Negated = stripNegationPrefix(ArchExt); 506 unsigned ID = getAEKID(ArchExt); 507 508 if (ID == AEK_INVALID) 509 return false; 510 511 for (const auto AE : ARCHExtNames) { 512 if (Negated && (AE.ID & ID) == ID && AE.NegFeature) 513 Features.push_back(AE.NegFeature); 514 else if (AE.ID == ID && AE.Feature) 515 Features.push_back(AE.Feature); 516 } 517 518 if (CPU == "") 519 CPU = "generic"; 520 521 if (ArchExt == "fp" || ArchExt == "fp.dp") { 522 unsigned FPUKind; 523 if (ArchExt == "fp.dp") { 524 if (Negated) { 525 Features.push_back("-fp64"); 526 return true; 527 } 528 FPUKind = findDoublePrecisionFPU(getDefaultFPU(CPU, AK)); 529 } else if (Negated) { 530 FPUKind = ARM::FK_NONE; 531 } else { 532 FPUKind = getDefaultFPU(CPU, AK); 533 } 534 return ARM::getFPUFeatures(FPUKind, Features); 535 } 536 return StartingNumFeatures != Features.size(); 537 } 538 539 StringRef ARM::getHWDivName(unsigned HWDivKind) { 540 for (const auto D : HWDivNames) { 541 if (HWDivKind == D.ID) 542 return D.getName(); 543 } 544 return StringRef(); 545 } 546 547 StringRef ARM::getDefaultCPU(StringRef Arch) { 548 ArchKind AK = parseArch(Arch); 549 if (AK == ArchKind::INVALID) 550 return StringRef(); 551 552 // Look for multiple AKs to find the default for pair AK+Name. 553 for (const auto CPU : CPUNames) { 554 if (CPU.ArchID == AK && CPU.Default) 555 return CPU.getName(); 556 } 557 558 // If we can't find a default then target the architecture instead 559 return "generic"; 560 } 561 562 unsigned ARM::parseHWDiv(StringRef HWDiv) { 563 StringRef Syn = getHWDivSynonym(HWDiv); 564 for (const auto D : HWDivNames) { 565 if (Syn == D.getName()) 566 return D.ID; 567 } 568 return AEK_INVALID; 569 } 570 571 unsigned ARM::parseArchExt(StringRef ArchExt) { 572 for (const auto A : ARCHExtNames) { 573 if (ArchExt == A.getName()) 574 return A.ID; 575 } 576 return AEK_INVALID; 577 } 578 579 ARM::ArchKind ARM::parseCPUArch(StringRef CPU) { 580 for (const auto C : CPUNames) { 581 if (CPU == C.getName()) 582 return C.ArchID; 583 } 584 return ArchKind::INVALID; 585 } 586 587 void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) { 588 for (const CpuNames<ArchKind> &Arch : CPUNames) { 589 if (Arch.ArchID != ArchKind::INVALID) 590 Values.push_back(Arch.getName()); 591 } 592 } 593 594 StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) { 595 StringRef ArchName = 596 CPU.empty() ? TT.getArchName() : getArchName(parseCPUArch(CPU)); 597 598 if (TT.isOSBinFormatMachO()) { 599 if (TT.getEnvironment() == Triple::EABI || 600 TT.getOS() == Triple::UnknownOS || 601 parseArchProfile(ArchName) == ProfileKind::M) 602 return "aapcs"; 603 if (TT.isWatchABI()) 604 return "aapcs16"; 605 return "apcs-gnu"; 606 } else if (TT.isOSWindows()) 607 // FIXME: this is invalid for WindowsCE. 608 return "aapcs"; 609 610 // Select the default based on the platform. 611 switch (TT.getEnvironment()) { 612 case Triple::Android: 613 case Triple::GNUEABI: 614 case Triple::GNUEABIHF: 615 case Triple::MuslEABI: 616 case Triple::MuslEABIHF: 617 return "aapcs-linux"; 618 case Triple::EABIHF: 619 case Triple::EABI: 620 return "aapcs"; 621 default: 622 if (TT.isOSNetBSD()) 623 return "apcs-gnu"; 624 if (TT.isOSOpenBSD()) 625 return "aapcs-linux"; 626 return "aapcs"; 627 } 628 } 629